JP7178782B2 - Electronic component mounting device and mounting method - Google Patents

Description

The present invention relates to an electronic component mounting apparatus and mounting method.

2. Description of the Related Art In recent years, attention has been paid to a semiconductor package manufacturing process called fan out-wafer level package (FO-WLP) in semiconductor package manufacturing technology. In FO-WLP, electronic components such as semiconductor chips are mounted in a matrix on a support substrate, and then the gaps between the electronic components are sealed with resin to form a pseudo-wafer. A rewiring layer is formed to provide I/O terminals in the wiring.

In addition, in the FO-WLP, there are two methods of mounting electronic components on the support substrate, namely, a face-up method and a face-down method. The face-up method is a method in which an electronic component is mounted on a support substrate with its electrode-formed surface, the so-called face surface, facing upward. On the other hand, the face-down method is a method in which an electronic component is mounted on a support substrate with the face surface facing downward.

Among them, Japanese Laid-Open Patent Publication No. 2002-100001 discloses an electronic component mounting apparatus that mounts electronic components on a support substrate by a face-down method. Here, since patterns such as wiring and electrodes are not formed on the supporting substrate unlike the interposer substrate, when electronic components are mounted, it is possible to perform position recognition for each mounting area on the supporting substrate. Can not. Therefore, such a mounting apparatus adopts a method (hereinafter referred to as a "global recognition method") of mounting electronic components in a plurality of mounting areas on the support substrate based on the recognition result of the overall position of the support substrate. there is In the global recognition method, positioning in each mounting area is not possible, so high accuracy is required for the mounting head that mounts electronic components and the stage that supports the support substrate. Since there is no need to secure time for recognition, there is an advantage that mounting efficiency can be improved.

In addition, FO-WLP is a multi-chip package (MCP) in which semiconductor chips such as RAM, flash memory, CPU, etc., and multiple types of electronic components such as diodes and capacitors are combined and mounted in one semiconductor package. It is also applicable to When mounting electronic components corresponding to such an MCP, a first electronic component as a first type of electronic component is first mounted in each mounting region of the support substrate, and then a second type of electronic component is mounted in each mounting region. Electronic components are sequentially mounted one by one on a support substrate, such as mounting a second electronic component as an electronic component. The first electronic component and the second electronic component may be of different types or may be of the same type.

However, when a plurality of types of electronic components are mounted one by one on the basis of the recognition result of the overall position of the supporting substrate by the global recognition method, each of the first electronic components and each of the second electronic components is positioned on the entire supporting substrate. Displacement due to individual variations with respect to the position. Therefore, when the first electronic component and the second electronic component mounted in the same mounting area are displaced from each other, the relative position of the first electronic component and the second electronic component is increased. In some cases, the positional relationship may be shifted beyond the permissible position within the mounting area. In such a case, the manufactured MCP becomes defective, which is not preferable because the yield decreases.

Therefore, when mounting the second electronic component, the position of the first electronic component already mounted in each mounting area is recognized each time, and the second electronic component is mounted based on the position of the first electronic component. It is possible to implement By doing so, it is possible to prevent the relative positions of the first and second electronic components from being greatly displaced in each mounting area. However, for electronic components subsequent to the second electronic component, it is necessary to recognize the position of the first electronic component for each mounting area. Therefore, every time electronic components after the second electronic component are mounted, the time required for position recognition is required, and the advantage of improving the mounting efficiency by the global recognition method is lost.

WO2017/135257

An object of the present invention is to mount each electronic component on a supporting substrate even when a second electronic component is mounted on each mounting region of a supporting substrate on which a first electronic component is mounted on a plurality of mounting regions. To provide an electronic component mounting apparatus and a mounting method capable of mounting electronic components quickly and accurately in each mounting area of the electronic component.

An electronic component mounting apparatus according to an embodiment includes a mounting unit that mounts electronic components on a plurality of mounting regions of a supporting substrate, an imaging unit that captures an image of the supporting substrate, and a control unit that controls the mounting unit and the imaging unit. and controlling the mounting unit based on the overall position of the supporting substrate obtained based on the image captured by the imaging unit to mount electronic components in a plurality of mounting regions of the supporting substrate. In the device, when mounting a second electronic component in each mounting region of a supporting substrate having the first electronic component mounted in the plurality of mounting regions, the controller controls the mounting regions of the supporting substrate. causing the imaging unit to image four or more preset first electronic components among the already mounted first electronic components, and position information of the first electronic components based on the captured image; and controlling the mounting unit to mount the second electronic component in the plurality of mounting areas based on the overall position of the supporting substrate obtained from the obtained positional information. .

The electronic component mounting method of the present embodiment is based on the overall position of the supporting substrate obtained based on the image captured by the imaging unit, and the electronic component is mounted on a plurality of mounting regions of the supporting substrate by the mounting unit. In the mounting method, when mounting a second electronic component in each mounting region of a supporting substrate having the first electronic component mounted in the plurality of mounting regions, the second electronic component is mounted in the plurality of mounting regions of the supporting substrate. positional information of the first electronic component is obtained based on captured images of four or more preset first electronic components among the first electronic components that are installed, and is obtained from the obtained positional information The second electronic component is mounted in the plurality of mounting regions based on the overall position of the supporting substrate.

According to the present invention, even when a second electronic component is mounted in each mounting region of a supporting substrate on which a first electronic component is mounted in a plurality of mounting regions, each electronic component is mounted on the supporting substrate. can be quickly and accurately mounted in each mounting area of the .

1 is a plan view showing a schematic configuration of an electronic component mounting apparatus according to an embodiment; FIG. FIG. 2 is a side view of the electronic component mounting apparatus of FIG. 1 as viewed from the left; 1 is a block diagram showing an electronic component mounting apparatus according to an embodiment; FIG. FIG. 2 is a plan view showing a support substrate on which a first electronic component (semiconductor chip) is mounted; FIG. 2 is a plan view showing a support substrate on which first and second electronic components (semiconductor chips) are mounted; FIG. 2 is a plan view showing the arrangement of first electronic components (semiconductor chips) on the support substrate used for recognizing the overall position of the support substrate; FIG. 10 is a schematic diagram for explaining evaluation processing of the recognized position of the first electronic component (semiconductor chip) used for recognizing the overall position of the support substrate; FIG. 10 is a schematic diagram for explaining evaluation processing of the recognized position of the first electronic component (semiconductor chip) used for recognizing the overall position of the support substrate; FIG. 10 is a schematic diagram for explaining evaluation processing of the recognized position of the first electronic component (semiconductor chip) used for recognizing the overall position of the support substrate;

Embodiments of the present invention (hereinafter referred to as embodiments) will be specifically described below with reference to FIGS. 1 to 3. FIG. The drawings are schematic, and the relationship between thickness and planar dimensions, the position and size of each component, etc. are merely expedient representations to make the structure easier to understand, and differ from the actual ones. Sometimes. Unless otherwise specified, the terms indicating the vertical direction in the description indicate the relative direction when the surface on which electronic components are mounted on the support substrate described later is facing up, and the terms indicating the horizontal direction are , unless otherwise specified, directions are shown with reference to the plan view of FIG. Also, with FIG. 1 as a reference, the horizontal direction is the X direction, the front-rear direction is the Y direction, and the vertical direction is the Z direction.

FIG. 1 is a plan view showing the configuration of an electronic component mounting apparatus according to an embodiment, and FIG. 2 is a side view of the mounting apparatus shown in FIG. 1 as viewed from the left. However, illustration of the transfer section and the mounting section shown on the left side in FIG. 1 is omitted. FIG. 3 is a block diagram of the mounting apparatus of the embodiment.

The mounting apparatus 1 includes a component supply unit 10 that supplies semiconductor chips t as electronic components, a stage unit 20 that has a stage 21 on which a support substrate W is placed, and a transfer unit 30 that takes out the semiconductor chips t from the component supply unit 10. , a mounting unit 40 that receives the semiconductor chip t picked up by the transfer unit and mounts it on the support substrate W placed on the stage 21, and a control unit 50 that controls the operations of the respective units 10, 20, 30, and 40 (FIG. 3). Prepare.

The component supply unit 10 is arranged in the front center of the mounting apparatus 1 . The component supply unit 10 supplies semiconductor chips t as electronic components to be mounted on the support substrate W. FIG. The semiconductor chip t is, for example, RAM, flash memory, IC, MPU, or the like. A component supply unit 10 detachably holds a wafer ring 11 holding a resin sheet S to which a semiconductor wafer T separated into individual semiconductor chips t is adhered, and an XY movement (not shown). A semiconductor chip t is taken out by a wafer ring holder 12 movable in the XY directions by a mechanism, a first camera 13 (FIG. 2) for capturing an image of the semiconductor chip t stuck on the wafer ring 11, and a transfer unit 30. A push-up mechanism (not shown) is sometimes provided to push up the semiconductor chip t to be taken out from the lower side of the wafer ring 11 .

A push-up mechanism (not shown) is fixedly arranged at a position where the transfer section 30 picks up the semiconductor chip t. Each semiconductor chip t on the wafer ring 11 is sequentially positioned at the take-out position by the movement of the wafer ring holder 12 . The first camera 13 is arranged directly above the take-out position and images the semiconductor chip t positioned at the take-out position.

The component supply unit 10 further includes a wafer ring exchange device (not shown). The exchange device consists of a storage section (also referred to as a magazine having a plurality of grooves for accommodating the wafer rings 11 in the vertical direction) provided on the front side of the wafer ring holder 12, and a space between the wafer ring holder 12 and the storage section. and a wafer ring conveying part conveyed by. The changer supplies unused wafer rings 11 onto wafer ring holders 12 . In addition, the wafer ring 11 from which the semiconductor chip t has been taken out is stored in the storage portion, and a new wafer ring 11 is supplied to the wafer ring holder 12 .

The stage unit 20 includes a stage 21 on which a support substrate W having a plurality of mounting areas is placed, and an XY movement mechanism 22 (FIG. 3) that moves the stage 21 in the XY directions. The XY moving mechanism 22 moves the stage 21 so that each mounting area E (see FIG. 4) of the support substrate W placed on the stage 21 is positioned at a fixed mounting position described later. The stage 21 is configured to be capable of sucking and holding the mounted support substrate W by means of a suction/suction mechanism (not shown). A second camera 23 for imaging the support substrate W is arranged above the stage 21 . The second camera 23 is for recognizing the overall position of the support substrate W by capturing an image of a global mark for position detection provided on the support substrate W, for example. The overall position of the support substrate W may be recognized by imaging the outer shape of the support substrate W with the second camera 23 .

The support substrate W placed on the stage 21 is a substrate used for forming a pseudo-wafer applied to manufacture of FO-WLP, for example, and a silicon substrate, a glass substrate, a metal substrate such as stainless steel, or the like is used. A pseudo-wafer is a state in which a plurality of individualized electronic components such as semiconductor chips t are arranged in a plane and formed into a single plate by sealing the electronic components between them with resin. be. Therefore, the shape of the support substrate W used for forming the pseudo-wafer is not limited to a circle, but may be a rectangle, other polygons, an ellipse, or the like, and the shape is not limited.

The support substrate W, as shown in FIG. 4, has a plurality of mounting areas E on which electronic components such as semiconductor chips t are mounted. However, the plurality of mounting regions E are virtually set on the support substrate W, and marks, patterns, etc. indicating the respective mounting regions E are not actually formed. The support substrate W may have global marks for recognizing the overall position of the substrate, but does not have alignment marks for indicating the positions of individual mounting regions E. FIG.

The transfer section 30 includes a pair of left and right transfer sections 30A and 30B. These transfer sections 30A and 30B have the same configuration and are arranged in a state in which the component supply section 10 is sandwiched between them. be. Only the configuration of the left transfer section 30A will be described below, and the configuration of the right transfer section 30B will be omitted.

The transfer unit 30A includes a suction nozzle (transfer nozzle) 31 (FIG. 2) that sucks and holds the semiconductor chip t, an arm body 33 that is elongated in the X direction and supports the suction nozzle 31 via a reversing mechanism 32, An X-direction moving device 34 that supports the arm body 33 so as to be movable in the X direction, a lifting device 35 that supports the X-direction moving device 34 so that it can move up and down, and a Y direction that supports the lifting device 35 so that it can move in the Y direction. a mobile device 36; The elevating mechanism 35 includes a rotary motor 37 and vertically moves the X-direction moving device 34, and more specifically the arm body 33 and the suction nozzle 31 supported by it, via a ball screw mechanism (not shown).

The reversing mechanism 32 is fixed to the front side of the device at the tip of the arm body 33, and includes a rotary drive portion 38 provided with a rotating shaft 38a extending to the rear side of the device along the Y direction and passing through the arm body 33. , and a reversing arm 39 connected to the rotating shaft 38 a of the rotary drive unit 38 . The reversing arm 39 reverses 180° on a trajectory that draws an arc upward between a horizontal state in which its tip faces rightward and a horizontal state in which its tip faces leftward. The suction nozzle 31 is attached to the reversing arm 39 so that the suction surface for vacuum-sucking the semiconductor chip t faces downward while the reversing arm 39 faces rightward. The transfer section 30B on the right side also has the same configuration except that the arrangement is horizontally reversed.

When the suction nozzles 31 of the left and right transfer sections 30A and 30B are positioned at the pick-up position at the same time, the suction nozzles 31 (reversing arms 39) interfere with each other. Therefore, the suction nozzles 31 are controlled to alternately move to the take-out position.

As with the transfer section 30, the mounting section 40 is a pair of mounting sections 40A and 40B having the same configuration arranged in a left-right reversed state with the stage section 20 interposed therebetween. As for the configuration of the mounting section 40, the description of the configuration of the right mounting section 40B is also omitted.

The mounting portion 40A includes a support frame 41 having a gate shape in a side view (viewed from the direction of FIG. 2), an X-direction moving block 42 supported on the support frame 41 so as to be movable along the X direction, A Y-direction moving device 43 provided on the right side surface of the X-direction moving block 42, a movable body 44 provided on the Y-direction moving device 43 so as to be movable in the Y direction, and the movable body 44 being movable in the vertical direction. and a mounting head 45 provided. At the lower end of the mounting head 45, a mounting tool 46 (FIG. 2) having a lower surface for holding the semiconductor chip t is provided.

The X-direction moving block 42 is mounted on the support frame 41 via an X-direction guide member 42a, and is movable in the X direction by a ball screw mechanism (not shown) driven by a motor. The Y-direction moving device 43 includes a Y-direction guide member 43a that supports the movable body 44 so as to be movable in the Y direction, and a ball screw mechanism (not shown) driven by a motor, and moves the movable body 44 in the Y direction. It is possible. The mounting section 40A includes a moving device (not shown) that moves the mounting head 45 in the vertical direction (Z direction). The mounting head 45 also includes a correction mechanism for the rotation direction (θ direction) (not shown). The mounting portion 40B on the right side also has the same configuration except that the arrangement of each portion is horizontally reversed.

Further, the mounting section 40 includes an intermediate stage 47 shared by the pair of mounting sections 40A and 40B. The intermediate stage 47 is arranged between the component supply section 10 and the stage section 20 and is a stage on which the semiconductor chip t taken out from the component supply section 10 by the transfer section 30 is temporarily placed. Directly above the intermediate stage 47, a third camera 48 (FIG. 2) used for recognizing the position of the semiconductor chip t is arranged. The intermediate stage 47 is used when the semiconductor chip t taken out from the component supply unit 10 is mounted as it is, in other words, when it is mounted on the support substrate W without being turned upside down. Since the semiconductor chip t is normally arranged in the component supply unit 10 with its face up, in this case, the mounting is performed by the face-up method. On the other hand, the intermediate stage 47 is not used in face-down mounting in which the semiconductor chip t is turned upside down. After the semiconductor chip t is reversed using the reversing mechanisms 32 of the transfer sections 30A and 30B, it is directly transferred to the mounting tools 46 of the mounting sections 40A and 40B. It should be noted that the operation of this embodiment, which will be described later, will be explained using an example of the face-up method.

The mounting units 40A and 40B mount the received semiconductor chip t on the support substrate W placed on the stage 21, regardless of whether the method is face-up or face-down. At this time, the mounting position where the mounting tool 46 mounts the semiconductor chip t on the support substrate W on the stage 21 is set to a fixed position common to the left and right mounting portions 40A and 40B. For this reason, the stage 21 is movement-controlled so that each mounting region E on the support substrate W is sequentially positioned at the mounting position. In this embodiment, the fixed position (mounting position) is set at the center of the movable range of the stage 21 . Since the mounting position is common to the left and right mounting sections 40A and 40B, the left and right mounting sections 40A and 40B alternately mount the semiconductor chip t on the mounting position. The aforementioned second camera 23 is arranged directly above the mounting position.

The mounting apparatus 1 includes a control section 50 as shown in FIG. Based on the information stored in the storage unit 51, the control unit 50 controls the operations of the component supply unit 10, the stage unit 20 (XY moving mechanism 22), the transfer units 30A and 30B, and the mounting units 40A and 40B. An electronic component including a semiconductor chip t is sequentially mounted on each mounting region E of the support substrate W. As shown in FIG.

Here, during mounting by the face-down method, the mounting tools 46 of the left and right mounting sections 40A and 40B receive the semiconductor chip t from the suction nozzles 31 of the transfer sections 30A and 30B, and then move to the mounting position. A camera (fourth camera) (not shown) that takes an image of the semiconductor chip t sucked and held by the mounting tool 46 from below is arranged below each. The fourth camera is arranged at a height position below the movement path of the mounting tool 47 and above the wafer ring holder 12 .

Next, a process of mounting an electronic component such as a semiconductor chip t using the mounting apparatus 1 of the embodiment will be described. In each mounting region E, two types of semiconductor chips t, that is, one first semiconductor chip ta and one second semiconductor chip tb are mounted. The first semiconductor chip ta and the second semiconductor chip tb are simply referred to as semiconductor chips t when they are not distinguished from each other.

The mounting apparatus 1 supplies the wafer ring 11 and the support substrate W prior to mounting the semiconductor chips t. That is, an unused wafer ring 11 is carried into the wafer ring holder 12 of the component supply section 10 by a transport means (not shown), and the wafer ring 11 is set in the wafer ring holder 12 . A first semiconductor chip ta of one type is attached to the wafer ring 11 . Further, the support substrate W is placed on the stage 21 by a transport means (not shown) that transports the support substrate W, and the support substrate W is held on the stage 21 . In this embodiment, the support substrate W is a patternless wafer having only a plurality of alignment marks (global marks) for recognizing the overall position of the support substrate W formed on its outer edge. However, the support substrate W is not limited to a wafer, and may be a plate-shaped member such as stainless steel or glass, and its shape is not limited to circular, and may be polygonal such as rectangular.

When the support substrate W is held on the stage 21 , the global mark of the support substrate W is imaged by the camera 23 . At this time, since the camera 23 is fixedly arranged, the stage 21 is moved so that each global mark is positioned within the imaging field of the camera 23 . Based on the image of the global marks captured by the camera 23, the control unit 50 recognizes the position of each global mark using an image recognition technique such as a known pattern matching technique, and determines the position of the support substrate W on the stage 21. Ask. Then, based on the obtained position, the mounting area E on which the semiconductor chip t is to be mounted first among the mounting areas E on the support substrate W is positioned at the mounting position. For example, in FIG. 4, the mounting area E located at the left end of the top row is assumed to be the mounting area E0 where the semiconductor chip t is first mounted. Thereafter, the mounting area E located on the right side of the same row is sequentially moved to be positioned at the mounting position, and when the end of the row is reached, the mounting area E at the right end of the row below by one row is positioned at the mounting position. After that, the mounting area E located on the left side of the same row is moved so as to be sequentially positioned at the mounting position E this time. The individual mounting areas E are sequentially positioned at the mounting positions along such a turning locus.

On the other hand, in the component supply section 10, the semiconductor chip t to be taken out first from the wafer ring 11 set on the wafer stage 12 is positioned at the take-out position. In the case of the semiconductor chips t as well, the semiconductor chips t arranged in a matrix on the wafer ring 11 are sequentially positioned at the take-out position from the left end of the uppermost row, following the trajectory.

When the semiconductor chip t is positioned at the removal position, the semiconductor chip t is imaged by the camera 13, and the control unit 50 uses a known image recognition technique based on the image of the semiconductor chip t imaged by the camera 13. The position of the semiconductor chip t is recognized. As a result of this position recognition, if the position of the semiconductor chip t is misaligned with respect to the take-out position, the wafer ring holder 12 is moved to correct the misalignment.

When the positioning of the semiconductor chip t with respect to the take-out position is completed, on the other hand, for example, the suction nozzle 31 of the left transfer section 30A is moved to right above the take-out position, and the semiconductor chip t is taken out. At this time, a push-up mechanism (not shown) is operated in accordance with the pickup of the semiconductor chip t by the suction nozzle 31 to assist the peeling of the semiconductor chip t from the resin sheet S.

After the suction nozzle 31 picks up the semiconductor chip t, the suction nozzle 31 is moved to the intermediate stage 47 and the picked semiconductor chip t is placed on the intermediate stage 47 . When the semiconductor chip t is placed on the intermediate stage 47 , the semiconductor chip t is imaged by the third camera 48 . The control unit 50 recognizes the position of the semiconductor chip t based on the image captured by the third camera 48 using a known image recognition technique. Note that the suction nozzle 31 that has finished placing the semiconductor chip t on the intermediate stage 47 enters a standby state in preparation for the next extraction.

Next, the mounting tool 46 of the left mounting section 40A is moved onto the intermediate stage 47, and the semiconductor chip t on the intermediate stage 47 is received. At this time, the mounting tool 46 is rotated to the center of the mounting tool 46 in a correct positional relationship with respect to the mounting tool 46 based on the positional information of the semiconductor chip t recognized by the control unit 50 . The positions in the X, Y, and .theta.

After the mounting tool 46 receives the semiconductor chip t, the mounting tool 46 is moved toward the mounting position and mounts the semiconductor chip t on the mounting area E of the support substrate W. FIG. At this time, the mounting area E is positioned at the mounting position based on the recognized position of the support substrate W, and the mounting tool 46 has a correct positional relationship based on the position information of the semiconductor chip t recognized using the third camera 48. , the semiconductor chip t is held. Therefore, by moving the mounting tool 46 to a preset movement position with respect to the mounting position, the semiconductor chip t can be mounted on the mounting area E with desired accuracy.

In parallel with the mounting of the semiconductor chip t by the left mounting section 40A, the transfer section 30B on the right side picks up the next semiconductor chip t from the component supply section 10 and places the picked semiconductor chip t on the intermediate stage 47. Place. Also, the right mounting section 40B receives the semiconductor chip t placed on the intermediate stage 47 .

After completing the mounting of the semiconductor chip t, the mounting tool 46 of the left mounting section 40A moves toward the intermediate stage 47 and waits until the semiconductor chip t is placed on the intermediate stage 47 by the transfer section 30A. On the other hand, the mounting tool 46 of the right mounting section 40B moves toward the mounting position. In addition, the stage 21 moves between the mounting tool 46 of the left (one) mounting section 40A leaving the mounting position and the mounting tool 46 of the right (the other) mounting section 40B being positioned at the mounting position. It is moved so as to position the mounting area E in which the semiconductor chip t is mounted to the mounting position.

The semiconductor chips t are mounted on all the mounting regions E of the support substrate W while alternately repeating such operations between the left transfer section 30A and the mounting section 40A and the right transfer section 30B and the mounting section 40B. go. FIG. 4 shows a plan view of the support substrate W on which the first semiconductor chips ta have been completely mounted on all the mounting areas E. As shown in FIG.

After the mounting of the first semiconductor chip ta is completed in this way, next, the second semiconductor chip tb as the second item is mounted by the same operation as described above. When the second semiconductor chip tb is mounted, the wafer ring 11 to which the second semiconductor chip tb is attached is supplied to the component supply unit 10, and the stage 21 is provided with the support substrate on which the first semiconductor chip ta is already mounted. W will be supplied sequentially. FIG. 5 is a plan view showing the support substrate W on which the first and second semiconductor chips ta and tb have been completely mounted on all the mounting regions E. FIG. Switching to the second type is generally performed in units of lots of semiconductor chips t, but may be performed in units of wafer rings 11, for example.

Here, in the embodiment of the present invention, the position recognition method (global recognition method) of the support substrate W when starting the mounting of the second semiconductor chip tb is the same as when mounting the first semiconductor chip ta. are different. The position recognition operation of the support substrate W when mounting the second semiconductor chip tb will be described in detail below.

When mounting the second semiconductor chip tb, the first semiconductor chip ta mounted on the support substrate W is used without using the global mark for position recognition of the support substrate W. FIG. That is, as shown in FIG. 6, among the first semiconductor chips ta mounted on the support substrate W, the support substrate W is determined based on the positions of eight semiconductor chips ta1 to ta8 located at predetermined locations. recognize the overall position of The positions of the eight semiconductor chips ta1 to ta8 are set based on the trajectory of a rectangle D including a square that is inscribed in a circle (concentric circle) C that is set to have a center common to the circular support substrate W. More specifically, four mounting areas E1 to E4 located at or near the four vertices of rectangle D, and located at the midpoints of the four sides of rectangle D, Alternatively, the semiconductor chips ta1 to ta8 are mounted in four mounting regions E5 to E8 positioned close to each midpoint.

Here, it is preferable that the eight semiconductor chips ta1 to ta8 are separated from each other. Therefore, the concentric circle C should be set as large as possible with respect to the area where the mounting area E is arranged. For example, the diameter of the concentric circle C is preferably set to 1/2 or more of the diameter of the support substrate W, that is, set to be equal to or greater than the radius. good. Also, it is preferable that the lengths of the sides of the rectangle D are as far apart as possible. For example, it is preferable to separate them by the radius of the support substrate W or more. The eight semiconductor chips ta1 to ta8 are divided into a line segment M1 (FIG. 7) connecting the centers of the semiconductor chips ta1 and ta2, and a line segment M2 (FIG. 7) connecting the centers of the semiconductor chips ta4 and ta3. ), and a line segment M3 (FIG. 7) connecting the centers of the semiconductor chip ta8 and the semiconductor chip ta6 preferably have the same direction and the same length. In this embodiment, the concentric circle C is set to pass over the mounting area E located on the outermost periphery on the support substrate W, and the rectangle D has a vertex of the mounting area E located on the outermost periphery on the support substrate W. set to the top. As a result, the diameter of the concentric circle C and the length of each side of the rectangle D are equal to or greater than the radius of the support substrate W. FIG.

When recognizing the overall position of the support substrate W, first, the second camera 23 is used to sequentially image these eight semiconductor chips ta1 to ta8. Positional information of the mounting regions E1 to E8 on the support substrate W is known from design data or the like. Therefore, the control unit 50 controls the XY movement mechanism 22 so as to sequentially position the semiconductor chips ta1 to ta8 within the field of view of the camera 23 based on these positional information. The control unit 50 recognizes the positions of the semiconductor chips ta1 to ta8 based on the images captured by the second camera 23. FIG. The positions of the semiconductor chips ta1 to ta8 can be determined by recognizing the positions of patterns such as electrodes provided on the semiconductor chip t using a known image recognition technique.

Once the positions of the eight semiconductor chips ta1 to ta8 have been recognized, the overall position of the support substrate W, in other words, the arrangement position of the mounting area E can be grasped based on the positional information of these semiconductor chips ta1 to ta8. , the second semiconductor chip tb is sequentially mounted in each mounting area E by the same operation as that for mounting the first semiconductor chip ta.

Here, the overall position of the support substrate W can be obtained by comparing the reference position information pre-stored in the storage unit 51 with the obtained position information of the semiconductor chips ta1 to ta8, and based on the deviation therebetween. The reference position information refers to each of the semiconductor chips ta1 to ta8 when the support substrate W on which the eight semiconductor chips ta1 to ta8 are mounted in the mounting area E in the correct positional relationship is placed on the stage 21 in the correct positional relationship. location information.

The positional deviation in the XY directions is determined based on the reference position information for each of the semiconductor chips ta1 to ta8, such as the difference between the reference position information of the semiconductor chip ta1 and the acquired position information, and the difference between the reference position information of the semiconductor chip ta2 and the acquired position information. It can be obtained by calculating the difference between the position information and the acquired position information and taking the average value of these. Further, the positional deviation in the direction of rotation (θ) is, as shown in FIG. , the angular difference between the line segment M1′ connecting the semiconductor chip ta1 and the semiconductor chip ta2 obtained from the acquired position information, and the line segment M2 and the line segment M2′ connecting the semiconductor chip ta4 and the semiconductor chip ta3. and the angular difference between the line segment M3 and the line segment M3' connecting the semiconductor chip ta8 and the semiconductor chip ta6, and the average value of these.

Once the overall position of the support substrate W on which the first semiconductor chip ta is mounted can be recognized in this manner, the second semiconductor chip tb is mounted in the same manner as the first semiconductor chip ta.

Among the eight semiconductor chips ta1 to ta8, there are some that are suddenly and greatly displaced for some reason, and the patterns used for position recognition such as alignment marks are defective such as defects and stains. It is also possible that the The recognition position of the semiconductor chip t, which is suddenly displaced, is greatly deviated from its original position. Moreover, the position of the semiconductor chip t having a problem in the pattern may not be correctly recognized. In any case, the recognized position includes a large positional deviation. Therefore, if such a semiconductor chip t exists among the eight semiconductor chips ta1 to ta8, the result of recognizing the overall position of the support substrate W will be affected by the semiconductor chip t with a large positional deviation. There is a risk that the overall position cannot be recognized.

Therefore, in consideration of the existence of such a semiconductor chip t, evaluation processing may be performed to evaluate whether the positional information of the recognized eight semiconductor chips ta1 to ta8 is appropriate. As shown in FIG. 8, this evaluation process is based on the obtained positional information of the eight semiconductor chips ta1 to ta8, the lengths and angles of the three line segments M1′, M2′, and M3′ described above, and the semiconductor chip ta1 and a line segment M4' connecting the centers of the semiconductor chips ta4, a line segment M5' connecting the centers of the semiconductor chips ta2 and the semiconductor chips ta3, and a line segment M6' connecting the centers of the semiconductor chips ta5 and ta7. This can be done by comparing each angle with the angle.

That is, regarding the three line segments M1', M2', and M3', for each combination of the line segment M1' and the line segment M2', the line segment M1' and the line segment M3', and the line segment M2' and the line segment M3', It is determined whether or not the length and the angle match within an allowable range preset in the storage unit 51 . Similar determinations are made for the three line segments M4', M5', and M6'.

If none of the eight semiconductor chips ta1 to ta8 has a semiconductor chip t that has undergone a sudden positional shift or the like, any combination of the line segments M1′, M2′, and M3′ will have the length and the angle match within an allowable range, and lengths and angles match within an allowable range whichever of the line segments M4', M5', and M6' are combined.

As a result of the comparison, if any combination of line segments M1′, M2′, and M3′ results in a combination exceeding the allowable range, or any combination of line segments M4′, M5′, and M6′ is acceptable. If there is only a combination that exceeds the range, the controller 50 outputs an error, assuming that the entire position of the support substrate W cannot be recognized. For example, the control unit 50 displays an error message on a display unit (not shown) or the like.

As a result of the comparison, there is a match within the allowable value in a combination of one or more sets of line segments M1′, M2′ and M3′, and one or more sets of line segments M4′, M5′ and M6′ If there is a match within the allowable value in the combination, it is determined that the overall position of the support substrate W can be recognized, and the controller 50 calculates the overall position of the support substrate W. FIG.

Note that when calculating the overall position of the support substrate W, the position information of the semiconductor chip t corresponding to the line segment whose length and angle differ beyond the allowable value is excluded. For example, as shown in FIG. 8, it is assumed that the length and angle of any combination of line segments M1', M2', and M3' are within the allowable range. On the other hand, regarding the line segments M4', M5', and M6', the combination of the line segment M4' and the line segment M5' was within the allowable range, but the combination of the line segment M4' and the line segment M6' and the line segment 5 It is assumed that the combination of ' and line segment 6' is out of the allowable range. In this case, there is a possibility that the semiconductor chips ta5 and ta7 corresponding to the line segment M6' are suddenly misaligned. Therefore, the positional information of the semiconductor chips ta5 and ta7 is eliminated, and the overall position of the support substrate W is calculated based on the positional information of the remaining six semiconductor chips ta1 to ta4, ta6 and ta8.

In addition to comparing the lengths and angles of the three line segments M1', M2', M3' and the lengths and angles of the three line segments M4', M5', M6', the three line segments M1' , M2′ and M3′ and the average values of the angles of the three line segments M4′, M5′ and M6′ may be compared. More specifically, the difference between the average value of the angles of the three line segments M1′, M2′, M3′ and the average value of the angles of the three line segments M4′, M5′, M6′ is Then, it is determined whether or not they match within an allowable range preset in the storage unit 51 . If the allowable range is exceeded, even if the lengths and angles of the line segments M1′, M2′ and M3′ and the lengths and angles of the line segments M4′, M5′ and M6′ match, an error will occur. I judge. By doing so, it is possible to eliminate the state in which the eight semiconductor chips ta1 to ta8 are arranged in a parallelogram (not including a rectangle) as shown in FIG.

By doing so, the second semiconductor chip tb can be mounted more accurately.

Here, the line segments M1′, M2′, M3′ and the line segments M4′, M5′, M6′ used in the evaluation process described above are the same line segments used for recognizing the overall position of the support substrate W. However, the set of two semiconductor chips t forming the line segments M1', M2', M3' and the line segments M4', M5', M6' can be selected as follows.

In the selection, two or more sets of two semiconductor chips ta are selected so that two or more line segments along the X direction and two or more line segments along the Y direction are formed. In this embodiment, as a set of semiconductor chips ta forming a line segment along the X direction, a set of a semiconductor chip ta1 and a semiconductor chip ta2 positioned at the upper two vertices of the rectangle D, and Three pairs of a pair of semiconductor chips ta4 and ta3 located and a pair of semiconductor chips ta8 and semiconductor chips ta6 located at the midpoints of the two vertical sides of the rectangle D were selected. Also, as a set of semiconductor chips ta forming a line segment along the Y direction, a set of the semiconductor chip ta1 and the semiconductor chip ta4 located at the two vertices on the left side of the rectangle D, and a semiconductor chip located at the two vertices on the right side of the rectangle D. Three pairs of the pair of the semiconductor chip ta2 and the semiconductor chip ta3, and the pair of the semiconductor chip ta5 and the semiconductor chip ta7 located at the midpoint of the two horizontal sides of the rectangle D were selected. The combination of the selected semiconductor chips ta1 to ta8 is stored in the storage unit 51. FIG.

The setting of the eight semiconductor chips ta1 to ta8 and the selection of the combination of the semiconductor chips ta1 to ta8 described above may be performed by an operator, or may be performed by the control unit 50 by calculation or the like. When the controller 50 performs the operation, the information such as the shape and dimensions of the support substrate W and the layout information of the mounting area E on the support substrate W are known from the design data. A program defining conditions for setting the inscribed rectangle D may be set in the control unit 50 .

As described above, according to the mounting apparatus 1 of the present embodiment, when mounting the second semiconductor chip tb on the support substrate W on which the first semiconductor chip ta has already been mounted and is set again on the stage 21, Based on the position information of the semiconductor chips ta1 to ta8 mounted in preset eight mounting regions E1 to E8 among the first semiconductor chips ta already mounted in each mounting region E of the support substrate W , the entire position of the support substrate W is recognized.

In this manner, the second semiconductor chip tb is mounted on the support substrate W having the first semiconductor chips ta mounted in the plurality of mounting regions E of the support substrate W, and the entire position of the support substrate W is used as a reference. In the case of mounting as such, it is possible to mount each mounting region E with a desired positional relationship with the first semiconductor chip ta with high accuracy.

That is, the support substrate W on which the first semiconductor chip ta is mounted in each mounting area E is once unloaded from the stage 21, and is again supplied and placed on the stage 21 when mounting the second semiconductor chip tb. . The support substrate W is supplied to the stage 21 by transport means such as a transport robot. At this time, a placement position error of the support substrate W with respect to the stage 21 occurs due to the mechanical accuracy of the transport means or the like. As a result, when the second semiconductor chip tb is mounted, the mounting position of the support substrate W relative to the stage 21 is shifted from when the first semiconductor chip ta is mounted. Therefore, when mounting the second semiconductor chip tb, the position of the support substrate W is recognized again.

When the positions of marks such as global marks on the support substrate W are image-recognized, not a little recognition error occurs. This also occurs when mounting the first semiconductor chip ta. If both recognition errors occur in the same direction and by the same amount, there is no problem, but recognition errors usually occur randomly. Therefore, for example, when mounting the first semiconductor chip ta, a recognition error of 1 μm occurs on the − (minus) side in the X direction, and when mounting the second semiconductor chip tb, a recognition error of 1 μm occurs on the + (plus) side in the X direction. Suppose an error occurs. As a result, the recognition result of the overall position of the support substrate W is deviated by 2 μm from the time when the first semiconductor chip ta is mounted. When the second semiconductor chip tb is mounted based on such a recognition result, considering the mounting error of the semiconductor chip t, in each mounting region E, the relative relationship between the first semiconductor chip ta and the second semiconductor chip tb is It is conceivable that a deviation of 3 μm or more occurs in the relative positional relationship. In the FO-WLP in which a rewiring process for forming a rewiring layer is performed after the process of mounting the semiconductor chip t, this misalignment may greatly affect the yield.

In contrast, in this embodiment, when mounting the second semiconductor chip tb, the overall position of the support substrate W is recognized based on the position of the first semiconductor chip ta already mounted on the support substrate W. do. Therefore, even if a recognition error occurs when recognizing the position of the first semiconductor chip ta, the recognition error is with respect to the arrangement positions of the plurality of first semiconductor chips ta mounted on the support substrate W. It is not for the substrate W itself, ie for the global marks on the support substrate W. FIG. Therefore, it is possible to prevent the recognition error of the overall position of the support substrate W when mounting the first semiconductor chip ta from being added to the recognition error of the overall position of the support substrate W when mounting the second semiconductor chip tb. As a result, it is possible to prevent the recognition error of the entire position of the support substrate W from increasing. Therefore, the second semiconductor chip tb can be accurately mounted in the correct positional relationship with respect to each mounting region E of the support substrate W with respect to the first semiconductor chip ta mounted in each mounting region E. becomes. Moreover, since the second semiconductor chip tb can be mounted by the global recognition method, it is possible to maintain the same mounting efficiency as when mounting the first semiconductor chip ta. As a result, it is possible to improve both the quality and yield of the manufactured semiconductor package and to improve productivity.

In recognizing the overall position of the support substrate W based on the position information of the eight semiconductor chips ta1 to ta8 selected in advance, the appropriateness of the position information of the recognized eight semiconductor chips ta1 to ta8 is evaluated. made it More specifically, a plurality of sets of two semiconductor chips t positioned on the same coordinate in each of the X direction and the Y direction are selected from among the eight semiconductor chips ta1 to ta8. Then, the lengths and angles of line segments (M1′, M2′, M3′ and M4′, M5′, M6′) connecting the preselected sets of semiconductor chips t are obtained, and the line segments (M1′, M2′) are obtained. . That is, if it is within the allowable range, it is judged to be "suitable", and if it is outside the allowable range, it is judged to be "unsuitable". Then, the recognized position of the semiconductor chip t determined as “unsuitable” is excluded from the position information for recognizing the overall position of the support substrate W. FIG.

By doing so, among the selected eight semiconductor chips ta1 to ta8, the semiconductor chip t that has suddenly been misaligned, and the marks used for position recognition, such as alignment marks, are missing or dirty. Even if there is a semiconductor chip t unsuitable for recognizing the entire position of the support substrate W, such as a semiconductor chip t whose position cannot be recognized, the support substrate is not affected by such a semiconductor chip t. The overall position of W, in other words, the arrangement state of the first semiconductor chip ta on the support substrate W can be recognized with high accuracy. This also allows the second semiconductor chip tb to be accurately mounted in each mounting region E of the support substrate W in a correct positional relationship with respect to the first semiconductor chip ta already mounted in each mounting region E. .

In addition, as the semiconductor chips t used for recognizing the overall position of the support substrate W, a total of eight semiconductor chips ta1 to ta8 located at each vertex on the trajectory of the rectangle D including the square and at the midpoints of each side were selected. . By doing so, three line segments (line segments M1′, M2′, M3′ and line segments M4′, M5′, M6′) can be set for each of the X direction and the Y direction. . This makes it possible to compare the lengths and angles of line segments in two or more pairs in both the X and Y directions. If any of the other sets are within the allowable range, recognition of the overall position of the support substrate W can be continued without error. Therefore, it is possible to reduce the frequency of stopping the mounting apparatus 1 due to an error, and to improve productivity.

Further, when selecting the eight semiconductor chips ta1 to ta8, the diameter of the concentric circle C virtually set with respect to the support substrate W and the length of each side of the rectangle inscribed in this concentric circle C are both The length was set to be longer than the radius of the supporting substrate W. By doing so, the length of each of the line segments M1' to M6' can be made as long as possible. Therefore, it is possible to improve the angle resolution and angle recognition accuracy of each of the line segments M1′ to M6′, improve the recognition accuracy of the entire position of the support substrate W, and improve the mounting accuracy of the second semiconductor chip tb. It is possible to

Further, according to the mounting apparatus 1 of the present embodiment, when mounting the semiconductor chip t on the support substrate W, a certain mounting position is set, and each mounting area E of the support substrate W is positioned at this mounting position. By moving the stage 21 and moving the mounting tools 46 of the mounting sections 40A and 40B, the semiconductor chips t are mounted in the respective mounting regions E at fixed mounting positions. By doing so, the mounting accuracy can be easily improved compared to the case where the position of the support substrate W is fixed at a fixed position and the mounting tool 46 is moved to each mounting area E to mount the semiconductor chip t. can be done.

That is, the movement of the mounting tools 46 and the like of the mounting sections 40A and 40B includes movement errors caused by the mechanical processing accuracy of the moving devices in the X, Y, and Z directions including the Y-axis moving device 43 . This movement error varies irregularly in magnitude and direction for each movement position. Therefore, correcting the movement error at all the movement positions of the mounting tool 46 takes an enormous amount of time, and is difficult to handle.

On the other hand, the movement of the mounting tool 46 and the like has a very high reproducibility with respect to movement to a fixed position. Therefore, in the present embodiment, the mounting position is set at a fixed position, so that the mounting accuracy of the semiconductor chip t in the mounting area E of the support substrate W is improved.

Moreover, in the mounting apparatus 1 of the present embodiment, the mounting positions by the mounting tools 46 of the left and right mounting portions 40A and 40B are also the same. As a result, even when the two mounting tools 46 are used to mount the semiconductor chips t on the same support substrate W, the mounting efficiency is improved while ensuring the mounting accuracy.

Note that the present embodiment described above is an example, and the present invention is not limited to this embodiment. For example, although the semiconductor chip t has been described as an example of an electronic component, it is not limited to this, and may be an electronic component such as a diode or a capacitor. Also, the configuration example of the MCP is not limited to the semiconductor chips t, and may be a combination of the semiconductor chip t and a diode, a capacitor, or the like.

Further, the configuration of the MCP is not limited to mounting two types of electronic components in one mounting area E, and three or more types of electronic components may be mounted. In this case, the plurality of electronic components to be mounted in one mounting area E may be a combination of electronic components of different types or a combination of electronic components of the same type. Further, when three or more types of electronic components are mounted, the recognition of the overall position of the support substrate W when mounting the third and subsequent types may be performed based on the position of the first type (first) electronic component. Alternatively, it may be performed based on the positions of the electronic components of the second and subsequent items. However, when mounting electronic components of the second and subsequent types, it is considered that relative positional accuracy will be improved if the position of the same electronic component is used as a reference. It is preferable to know the global position of W.

Moreover, although the supporting substrate W has been described as an example having a circular shape, the supporting substrate W may have another shape, for example, a rectangular shape. If the support substrate W is rectangular, it is conceivable that the mounting areas E are also arranged in a rectangular shape. Therefore, the eight semiconductor chips ta1 to ta8 used for recognizing the overall position of the support substrate W are positioned corresponding to the four mounting areas E corresponding to the vertices of the rectangular arrangement and the midpoints between the respective vertices. It is sufficient to select the first semiconductor chips ta mounted in the four mounting regions E that are the same.

Further, when mounting the first semiconductor chip ta on the support substrate W, the selected eight semiconductor chips ta1 to ta8 may be mounted first. In this case, while the first semiconductor chip ta is being mounted on the support substrate W, the mounting of the semiconductor chip t may be interrupted for some reason, and the support substrate W may be unloaded from the stage 21. However, when the problem is resolved and the support substrate W is resupplied onto the stage 21, the overall position of the support substrate W can be recognized based on the positions of the eight semiconductor chips ta1 to ta8 already mounted. can.

Further, when an error is found in the evaluation of the position information of the eight semiconductor chips ta1 to ta8, the semiconductor chip t to be recognized may be changed and recognized again. For example, semiconductor chips ta1' to ta8' (see FIG. 6) for re-recognition may be set in advance, and the positions of these semiconductor chips ta1' to ta8' may be recognized when an error occurs. The semiconductor chips ta1' to ta8' for re-recognition may be set based on a rectangle D' different from the rectangle D and inscribed in the concentric circle C, and set based on this rectangle D'.

Also, the eight semiconductor chips ta1 to ta8 may be indexed based on the positions of the global marks on the support substrate W. FIG. That is, the positional information of the mounting area E on which the eight semiconductor chips ta1 to ta8 are mounted on the support substrate W is known from the design data or the like, and the support substrate W is within the range of transportation error caused by transportation means (not shown) or the like. 8 semiconductor chips ta1 to ta8 can be positioned within the imaging field of view of the second camera 23 based on this positional information. However, in order to further improve reliability, it may be determined based on the positions of the global marks on the support substrate W. FIG.

Further, although the example in which the semiconductor chip t is mounted face-up on the support substrate W has been described, the present invention is not limited to this, and may be mounted face-down. In the case of face-down mounting, the pick-up semiconductor chip t is reversed by reversing the suction nozzle 31 using the reversing mechanism 32 of the transfer sections 30A and 30B, and the reversed semiconductor chip t is mounted from the suction nozzle 31. Deliver directly to tool 46 . A fourth camera (not shown) is used to recognize the position of the semiconductor chip t sucked and held by the mounting tool 46 while the mounting tool 46 is being moved to the mounting position, and the semiconductor chip t is mounted on the mounting area E of the support substrate W. You should do it like this. When the semiconductor chip t is mounted face down, the face surface of the semiconductor chip t faces the support substrate W, and therefore the face surface cannot be imaged after mounting. Therefore, when the position of the semiconductor chip t sucked and held by the mounting tool 46 is recognized using a fourth camera (not shown), the outer shape of the semiconductor chip t is also recognized, and alignment marks of the semiconductor chip t are recognized. The positional relationship with the outer shape is recognized and stored in the storage unit 51 . When recognizing the positions of the eight semiconductor chips ta1 to ta8 mounted on the support substrate W, the outer shapes of the semiconductor chips ta1 to ta8 are recognized, and the positional relationship between the outer shape positions stored in the storage unit 51 and the alignment marks. , the positions of the semiconductor chips ta1 to ta8 can be recognized. At this time, the surfaces of the semiconductor chips ta1 to ta8 that are imaged by the fourth camera (not shown) and by the second camera 23 are reversed. Needless to say, the positional relationship is reversed. Further, the positional relationship between the outer shape position of the semiconductor chip t and the alignment marks may be stored in the storage unit 51 for at least eight semiconductor chips ta1 to ta8.

In the evaluation process, the lengths and angles of three line segments M1', M2' and M3' along the X direction and three line segments M4', M5' and M6' along the Y direction are compared. However, this evaluation may be performed in only one of the X direction and the Y direction. That is, when the arrangement of the first semiconductor chips ta mounted on the support substrate W is rarely arranged in a parallelogram as shown in FIG. 9, it is judged that there is no problem if only one side is evaluated. If possible, only one of them may be evaluated.

Further, the entire position of the support substrate W is recognized based on the positional information of the eight semiconductor chips ta1 to ta8, but the number of the semiconductor chips t is not limited to this, and the number of the semiconductor chips t is not limited to four or more. good.

Also, the explanation is given assuming that the single mounting apparatus 1 is used to mount the first semiconductor chip ta (first electronic component) and the second semiconductor chip tb (second electronic component) on the support substrate W. However, it is not limited to this. For example, two mounting apparatuses 1 are prepared, one mounting apparatus 1 mounts the first semiconductor chip ta on the support substrate W, and another mounting apparatus 1 mounts the first semiconductor chip ta. Even in the case of mounting the second semiconductor chip tb on the support substrate W, the present invention can be applied to another mounting apparatus 1 .

1 mounting device 10 component supply unit 20 stage unit 21 stage 23 second camera 30, 30A, 30B transfer unit 31 suction nozzle 34 X-direction moving device 35 lifting device 36 Y-direction moving device 40, 40A, 40B mounting unit 45 mounting Head 46 Mounting tool 47 Intermediate stage 48 Third camera 50 Control unit 51 Storage unit W Support substrate E Mounting area C Concentric circle D Inscribed rectangle t Semiconductor chip

Claims (8)

An image captured by the imaging unit, comprising: a mounting unit for mounting electronic components in a plurality of mounting areas of a supporting substrate; an imaging unit for imaging the supporting substrate; and a control unit for controlling the mounting unit and the imaging unit. An electronic component mounting apparatus for mounting electronic components in a plurality of mounting areas of the supporting substrate by controlling the mounting unit based on the overall position of the supporting substrate obtained based on
When the second electronic component is mounted in each mounting region of the supporting substrate having the first electronic component mounted in the plurality of mounting regions, the control unit has already mounted the second electronic component in the plurality of mounting regions of the supporting substrate. causing the imaging unit to image four or more preset first electronic components among the first electronic components, and acquiring position information of the first electronic component based on the captured image; and controlling the mounting unit to mount the second electronic component on the plurality of mounting areas based on the overall position of the supporting substrate obtained from the positional information. . 2. The electronic component mounting apparatus according to claim 1, wherein said control unit evaluates whether the positional information of said first electronic component obtained based on the captured image of said imaging unit is appropriate. The control unit determines whether or not the position information of the first electronic components obtained based on the captured image of the imaging unit is appropriate, by two or more sets selected in advance from the four or more first electronic components. , in a set consisting of two electronic components, a line segment connecting the first electronic components obtained from reference position information stored in advance for each set, and the first electronic component obtained from the obtained position information Obtaining the angle formed by the line segment connecting the components and the length of the line segment connecting the first electronic components obtained from the acquired position information, and comparing the length and angle of these line segments. 3. The electronic component mounting apparatus according to claim 1, wherein the evaluation is performed by: The support substrate is a circular support substrate,
The control unit selects a first electronic component to be imaged by the imaging unit within the support substrate based on a rectangle inscribed in the concentric circle on the support substrate having a diameter equal to or larger than the radius of the support substrate. 4. The electronic component mounting apparatus according to any one of claims 1 to 3, wherein the electronic component mounting apparatus is set as follows. 5. The method according to claim 4, wherein the control unit sets the first electronic component to be imaged by the imaging unit based on four vertices and four midpoints of a rectangle inscribed in the concentric circle. Mounting equipment for electronic components. The support substrate is a rectangular support substrate,
2. The control unit sets the first electronic component to be imaged by the imaging unit based on a rectangular layout of a plurality of rectangular mounting areas within the support substrate. 4. The electronic component mounting apparatus according to any one of 1 to 3. 7. The control unit sets the first electronic component to be imaged by the imaging unit based on four vertexes and midpoints of four sides of the rectangular arrangement of the mounting area. mounting equipment for electronic components. An electronic component mounting method for mounting electronic components in a plurality of mounting regions of a support substrate by a mounting unit based on the overall position of the support substrate obtained based on an image captured by an imaging unit, comprising:
When mounting the second electronic component in each mounting region of the supporting substrate having the first electronic component mounted in the plurality of mounting regions, the first electronic component already mounted in the plurality of mounting regions of the supporting substrate is mounted. positional information of the first electronic component is obtained based on captured images of four or more preset first electronic components among the electronic components, and the entire support substrate obtained from the obtained positional information An electronic component mounting method, wherein the second electronic component is mounted in the plurality of mounting regions based on the position.

Images