JP7172022B2 - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

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JP7172022B2
JP7172022B2 JP2017153249A JP2017153249A JP7172022B2 JP 7172022 B2 JP7172022 B2 JP 7172022B2 JP 2017153249 A JP2017153249 A JP 2017153249A JP 2017153249 A JP2017153249 A JP 2017153249A JP 7172022 B2 JP7172022 B2 JP 7172022B2
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semiconductor device
resin layer
manufacturing
base material
metal foil
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JP2019033175A (en
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正明 竹越
希 高野
直也 鈴木
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Showa Denko Materials Co Ltd
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Hitachi Chemical Co Ltd
Showa Denko Materials Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting

Description

本発明は、各種電子機器に搭載される半導体装置の製造方法に関する。 The present invention relates to a method of manufacturing a semiconductor device mounted on various electronic equipment.

一般的な電子機器に搭載される半導体装置は、これまで半導体を金属のリードフレームに実装し封止したリードフレームパッケージ及び有機基板に実装したパッケージが主流であった。一方、電子機器の小型化・高性能化に伴い、搭載するパッケージも小型化が進み、半導体素子のバンプ面に基板と接続するバンプを直接形成するウエハレベルパッケージが増加している。さらに、バンプ数の増加及び配線の微細化が進行しており、半導体素子サイズよりも大きな絶縁層に配線を引き出すファンアウトのウエハレベルパッケージの需要が高まっている。 Semiconductor devices mounted on general electronic equipment have hitherto been mainly lead frame packages in which a semiconductor is mounted on a metal lead frame and sealed, and packages mounted on an organic substrate. On the other hand, along with the miniaturization and high performance of electronic equipment, the size of the package to be mounted is also progressing, and the wafer level package in which bumps to be connected to the substrate are directly formed on the bump surface of the semiconductor element is increasing. Furthermore, the number of bumps is increasing and wiring is becoming finer, and there is a growing demand for fan-out wafer-level packages in which wiring is drawn out to an insulating layer larger than the size of a semiconductor element.

ファンアウトのウエハレベルパッケージの製造方法は多岐に渡っているが、微細配線を複数層形成する1つの方法として、キャリアに形成された接着層の上に半導体素子のバンプ面が上になるように半導体素子を実装した後に半導体素子を封止する、チップファースト/フェイスアップのプロセスがある。ここで使われる接着層は、仮固定材料として、半導体素子の封止、封止材の研削、配線層の形成等のいくつかの工程を経てから剥離されるのが一般的である。この場合、接着層は、幾つかの高温プロセスに対応する優れた耐熱性が必要になるだけでなく、接着層となる仮固定材料を剥離した後に半導体素子の裏面が露出するため、必要に応じてチップ保護等の目的で裏面保護材料を形成する必要がある。 There are various methods for manufacturing fan-out wafer level packages, but one method for forming multiple layers of fine wiring is to place the bump surface of the semiconductor element on top of the adhesive layer formed on the carrier. There is a chip-first/face-up process in which the semiconductor element is sealed after being mounted. The adhesive layer used here is used as a temporary fixing material and is generally peeled off after going through several processes such as encapsulation of the semiconductor element, grinding of the encapsulant, and formation of the wiring layer. In this case, the adhesive layer not only needs to have excellent heat resistance to withstand several high-temperature processes, but also the back surface of the semiconductor element is exposed after the temporary fixing material that becomes the adhesive layer is peeled off. It is necessary to form a back surface protective material for the purpose of chip protection and the like.

半導体素子を実装した接着層を剥離する方法はいくつか提案されており、例えば特許文献1に記載の加熱剥離方式が代表的である。また半導体素子の裏面保護に関しては、特許文献2に記載のウエハ裏面に予め形成した後に半導体素子を個片化する方法が一般的である。 Several methods have been proposed for peeling off the adhesive layer on which the semiconductor element is mounted. As for the protection of the back surface of the semiconductor element, a method of preliminarily forming the semiconductor element on the back surface of the wafer described in Patent Document 2 and then singulating the semiconductor element is generally used.

特許3594853号公報Japanese Patent No. 3594853 特許5814487号公報Japanese Patent No. 5814487

ファンアウトのウエハレベルパッケージを製造する場合は、基材102上に接着層103が配置された仮固定材料の接着層101に、既に個片化された半導体素子104を間隔を開けて実装し(図5(a)(b)参照)、その後、半導体素子104を封止材105で封止する(図5(c)参照)。このため、接着層103から半導体素子104を剥離した後には、半導体素子104の裏面だけでなく封止材105の面も同時に露出することになる(図5(d)参照)。そのため、それらの面を保護するためには、接着層103から半導体素子104を剥離した後にさらに保護層106を形成するか、個片化したパッケージの個々に保護層106を形成する必要がある(図5(e)参照)。そして、封止材を研削後、再配線層107を形成する(図5(f)参照)。 In the case of manufacturing a fan-out wafer level package, semiconductor elements 104 that have already been separated into individual pieces are mounted on an adhesive layer 101 of a temporary fixing material in which an adhesive layer 103 is arranged on a substrate 102 ( 5A and 5B), and then the semiconductor element 104 is sealed with a sealing material 105 (see FIG. 5C). Therefore, after peeling the semiconductor element 104 from the adhesive layer 103, not only the back surface of the semiconductor element 104 but also the surface of the sealing material 105 are exposed at the same time (see FIG. 5D). Therefore, in order to protect those surfaces, it is necessary to further form a protective layer 106 after peeling the semiconductor element 104 from the adhesive layer 103, or to form a protective layer 106 for each individual package ( See FIG. 5(e)). After grinding the sealing material, a rewiring layer 107 is formed (see FIG. 5F).

しかし、接着層からの剥離と保護層の形成を別々に実施することは生産性の観点から好ましくなく、半導体装置製造プロセスを更に簡略化する必要がある。 However, separating from the adhesive layer and forming the protective layer separately is not preferable from the viewpoint of productivity, and it is necessary to further simplify the semiconductor device manufacturing process.

本発明は、上記事情に鑑みてなされたものであり、半導体装置製造プロセスの簡略化を可能とする半導体装置の製造方法を提供することを目的とする。 SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of manufacturing a semiconductor device that enables simplification of the semiconductor device manufacturing process.

本発明者らは鋭意検討の結果、上記課題を解決しうる半導体装置の製造方法を見出し、本発明を完成させるに至った。すなわち、本発明は下記の態様を有することを特徴とする。 As a result of intensive studies, the inventors of the present invention found a method of manufacturing a semiconductor device capable of solving the above problems, and completed the present invention. That is, the present invention is characterized by having the following aspects.

[請求項1]樹脂層と前記樹脂層に対して剥離可能な基材とが一体となったフィルムの前記樹脂層に、バンプ面が上となるように半導体素子を搭載することを特徴とする半導体装置の製造方法。 [Claim 1] A semiconductor element is mounted on the resin layer of a film in which a resin layer and a base material that can be peeled off from the resin layer are integrated so that the bump surface faces upward. A method of manufacturing a semiconductor device.

[請求項2]前記樹脂層に個片化した前記半導体素子を搭載することを特徴とする請求項1に記載の半導体装置の製造方法。 [Claim 2] The method of manufacturing a semiconductor device according to Claim 1, wherein the semiconductor elements separated into individual pieces are mounted on the resin layer.

[請求項3]前記樹脂層が接着性を有することを特徴とする請求項1又は2に記載の半導体装置の製造方法。 [Claim 3] The method of manufacturing a semiconductor device according to claim 1 or 2, wherein the resin layer has adhesiveness.

[請求項4]前記樹脂層に搭載した前記半導体素子を封止材で封止した後、前記樹脂層から前記基材を剥離することを特徴とする請求項1~3の何れか一項に記載の半導体装置の製造方法。 [Claim 4] The method according to any one of claims 1 to 3, characterized in that after the semiconductor element mounted on the resin layer is sealed with a sealing material, the base material is peeled off from the resin layer. A method of manufacturing the semiconductor device described.

[請求項5]前記樹脂層から前記基材を剥離した後、一つ又は複数の半導体装置単位に個片化することを特徴とする請求項1~4の何れか一項に記載の半導体装置の製造方法。 [Claim 5] The semiconductor device according to any one of Claims 1 to 4, wherein after the base material is separated from the resin layer, the semiconductor device is singulated into one or a plurality of semiconductor device units. manufacturing method.

[請求項6]前記基材が剥離可能な2枚以上の金属箔を片面もしくは両面に配置した積層体であり、少なくとも前記基材の前記樹脂層と接する側に前記金属箔を配置することを特徴とする請求項1~5の何れか一項に記載の半導体装置の製造方法。 [Claim 6] The base material is a laminate in which two or more peelable metal foils are arranged on one side or both sides, and the metal foil is arranged at least on the side of the base material that is in contact with the resin layer. 6. The method of manufacturing a semiconductor device according to claim 1.

[請求項7]前記樹脂層から基材を剥離する際に、前記金属箔の1枚を前記樹脂層に残すことを特徴とする請求項6に記載の半導体装置の製造方法。 [Claim 7] The method of manufacturing a semiconductor device according to Claim 6, wherein one sheet of the metal foil is left on the resin layer when the base material is peeled off from the resin layer.

[請求項8]前記積層体の前記金属箔以外の部分が有機材料であることを特徴とする請求項6又は7に記載の半導体装置の製造方法。 [8] The method of manufacturing a semiconductor device according to [6] or [7], wherein the portion of the laminate other than the metal foil is made of an organic material.

[請求項9]前記積層体がガラス布を有することを特徴とする請求項6~8の何れか一項に記載の半導体装置の製造方法。 [9] The method of manufacturing a semiconductor device according to any one of [6] to [8], wherein the laminated body has a glass cloth.

[請求項10]前記積層体のガラス転移点が、120℃~300℃であることを特徴とする請求項6~9の何れか一項に記載の半導体装置の製造方法。 [10] The method of manufacturing a semiconductor device according to any one of [6] to [9], wherein the laminated body has a glass transition point of 120°C to 300°C.

[請求項11]前記積層体の前記金属箔以外の部分のガラス転移点以下の熱膨張率が、1×10-6/℃~20×10-6/℃であることを特徴とする請求項6~10の何れか一項に記載の半導体装置の製造方法。 [Claim 11] A claim characterized in that the coefficient of thermal expansion below the glass transition point of the portion other than the metal foil of the laminate is 1×10 -6 /°C to 20×10 -6 /°C. 11. The method of manufacturing a semiconductor device according to any one of 6 to 10.

[請求項12]前記積層体の前記金属箔以外の部分の厚さが、0.015mm~2.00mmであることを特徴とする請求項6~11の何れか一項に記載の半導体装置の製造方法。 [Claim 12] The semiconductor device according to any one of Claims 6 to 11, wherein the thickness of the portion of the laminate other than the metal foil is 0.015 mm to 2.00 mm. Production method.

[請求項13]前記樹脂層と接する前記金属箔に予め回路が形成されていることを特徴とする請求項6~12の何れか一項に記載の半導体装置の製造方法。 [13] The method of manufacturing a semiconductor device according to any one of [6] to [12], wherein a circuit is formed in advance on the metal foil in contact with the resin layer.

[請求項14]前記樹脂層として、グリシジルアクリレートを含有するアクリル重合体を用いることを特徴とする請求項1~13の何れか一項に記載の半導体装置の製造方法。 [14] The method of manufacturing a semiconductor device according to any one of [1] to [13], wherein an acrylic polymer containing glycidyl acrylate is used as the resin layer.

[請求項15]前記樹脂層は、エポキシ樹脂、フェノール樹脂、硬化促進剤及び無機充填剤を含有することを特徴とする請求項1~14の何れか一項に記載の半導体装置の製造方法。 [15] The method of manufacturing a semiconductor device according to any one of [1] to [14], wherein the resin layer contains an epoxy resin, a phenol resin, a curing accelerator, and an inorganic filler.

[請求項16]前記樹脂層がガラス布を含有することを特徴とする請求項1~15の何れか一項に記載の半導体装置の製造方法。 [16] The method of manufacturing a semiconductor device according to any one of [1] to [15], wherein the resin layer contains a glass cloth.

本発明の半導体装置の製造方法によれば、樹脂層と樹脂層に対して剥離可能な基材とが一体となったフィルムの樹脂層に、バンプ面が上となるように半導体素子を搭載し、半導体素子を封止するため、基材から樹脂層を剥離しても、予め半導体素子の裏面が保護された状態で、封止材表面の研磨、再配線層の形成等のファンアウトウエハレベルパッケージ製造プロセスを実施することができる。 According to the method of manufacturing a semiconductor device of the present invention, the semiconductor element is mounted on the resin layer of the film in which the resin layer and the base material that can be separated from the resin layer are integrated with the bump surface facing upward. , In order to seal the semiconductor element, even if the resin layer is peeled off from the base material, the back surface of the semiconductor element is protected in advance. A package manufacturing process can be implemented.

本発明によれば、半導体実装プロセスの簡略化を可能とする半導体装置の製造方法を提供することができる。 According to the present invention, it is possible to provide a method of manufacturing a semiconductor device that enables simplification of the semiconductor packaging process.

本発明により得られる半導体装置は、高機能化・多機能化が進むスマートフォン及びタブレット端末等の電子機器に好適である。 A semiconductor device obtained by the present invention is suitable for electronic devices such as smartphones and tablet terminals that are becoming increasingly sophisticated and multi-functional.

樹脂層と樹脂層に対して剥離可能な基材が一体となったフィルムを用いた半導体装置の製造方法を説明するための断面図である。図1(a)はフィルムの断面図、図1(b)はフィルムに半導体素子を搭載した状態を示す断面図、図1(c)は半導体素子を封止材で封止した状態を示す断面図、図1(d)は剥離可能な基材を剥離した状態を示す断面図、図1(e)は剥離可能な基材を剥離した後、封止材の研削、再配線層の形成及びはんだバンプの搭載を実施し、半導体装置単位で個片化した状態を示す断面図である。FIG. 10 is a cross-sectional view for explaining a method of manufacturing a semiconductor device using a film in which a resin layer and a base material that can be separated from the resin layer are integrated; 1(a) is a cross-sectional view of the film, FIG. 1(b) is a cross-sectional view showing a state in which a semiconductor element is mounted on the film, and FIG. 1(c) is a cross-sectional view showing a state in which the semiconductor element is sealed with a sealing material. FIG. 1(d) is a cross-sectional view showing a state in which the peelable base material is peeled off; FIG. FIG. 4 is a cross-sectional view showing a state in which solder bumps are mounted and separated into individual semiconductor devices; 剥離可能な基材が剥離可能な2枚以上の金属箔を片面に配置した積層体である場合の半導体装置の製造方法を説明するための断面図である。図2(a)はフィルムの断面図、図2(b)はフィルムに半導体素子を搭載した状態を示す断面図、図2(c)は半導体素子を封止材で封止した状態を示す断面図、図2(d)は剥離可能な基材を剥離した状態を示す断面図、図2(e)は剥離可能な基材を剥離した後、封止材の研削、再配線層の形成及びはんだバンプの搭載を実施し、半導体装置単位で個片化した状態を示す断面図である。FIG. 11 is a cross-sectional view for explaining a method of manufacturing a semiconductor device when the peelable base material is a laminate having two or more peelable metal foils arranged on one side thereof; 2(a) is a cross-sectional view of the film, FIG. 2(b) is a cross-sectional view showing a state in which a semiconductor element is mounted on the film, and FIG. 2(c) is a cross-sectional view showing a state in which the semiconductor element is sealed with a sealing material. FIG. 2(d) is a cross-sectional view showing the state in which the peelable base material is peeled off; FIG. FIG. 4 is a cross-sectional view showing a state in which solder bumps are mounted and separated into individual semiconductor devices; 樹脂層と接する側の金属箔に予め回路を形成した場合の半導体装置の製造方法を説明するための断面図である。図3(a)はフィルムの断面図、図3(b)はフィルムに半導体素子を搭載した状態を示す断面図、図3(c)は半導体素子を封止材で封止した状態を示す断面図、図3(d)は剥離可能な基材を剥離した状態を示す断面図、図3(e)は剥離可能な基材を剥離した後、封止材の研削、再配線層の形成及びはんだバンプの搭載を実施し、半導体装置単位で個片化した状態を示す断面図である。FIG. 10 is a cross-sectional view for explaining a method of manufacturing a semiconductor device when a circuit is formed in advance on the metal foil on the side contacting the resin layer; 3(a) is a cross-sectional view of the film, FIG. 3(b) is a cross-sectional view showing a state in which a semiconductor element is mounted on the film, and FIG. 3(c) is a cross-sectional view showing a state in which the semiconductor element is sealed with a sealing material. FIG. 3(d) is a cross-sectional view showing a state in which the peelable base material is peeled off; FIG. FIG. 4 is a cross-sectional view showing a state in which solder bumps are mounted and separated into individual semiconductor devices; 樹脂層と樹脂層に対して剥離可能な基材が一体となったフィルムを用いた半導体装置の製造方法を説明するための断面図である。図4(a)はフィルムの断面図、図4(b)はフィルムに半導体素子を搭載した状態を示す断面図、図4(c)は半導体素子を封止材で封止した後、封止材を研削している状態を示す断面図、図4(d)は再配線層の形成及びはんだバンプの搭載を実施した状態を示す断面図、図4(e)は剥離可能な基材を剥離した状態を示す断面図、図4(f)半導体装置単位で個片化した状態を示す断面図である。FIG. 10 is a cross-sectional view for explaining a method of manufacturing a semiconductor device using a film in which a resin layer and a base material that can be separated from the resin layer are integrated; FIG. 4(a) is a cross-sectional view of the film, FIG. 4(b) is a cross-sectional view showing a state where the semiconductor element is mounted on the film, and FIG. 4(c) is a semiconductor element sealed with a sealing material. A cross-sectional view showing a state in which the material is ground, FIG. 4D is a cross-sectional view showing a state in which a rewiring layer is formed and solder bumps are mounted, and FIG. FIG. 4F is a cross-sectional view showing a state in which semiconductor devices are separated into individual pieces; 接着層からの剥離と保護層の形成を別々に実施する場合の半導体装置の製造方法を説明するための断面図である。図5(a)はフィルムの断面図、図5(b)はフィルムに半導体素子を搭載した状態を示す断面図、図5(c)は半導体素子を封止材で封止した状態を示す断面図、図5(d)は基材を剥離した状態を示す断面図、図5(e)は封止材を研削している状態を示す断面図、図5(f)は再配線層を形成した状態を示す断面図である。FIG. 10 is a cross-sectional view for explaining a method of manufacturing a semiconductor device in which peeling from an adhesive layer and formation of a protective layer are performed separately; 5(a) is a cross-sectional view of the film, FIG. 5(b) is a cross-sectional view showing a state in which a semiconductor element is mounted on the film, and FIG. 5(c) is a cross-sectional view showing a state in which the semiconductor element is sealed with a sealing material. FIG. 5(d) is a cross-sectional view showing the state in which the base material is peeled off, FIG. 5(e) is a cross-sectional view showing the state in which the sealing material is being ground, and FIG. 5(f) is a rewiring layer formed FIG. 3 is a cross-sectional view showing a state in which

以下、必要に応じて図面を参照しつつ、本発明を実施するための形態について詳細に説明する。ただし、本発明は以下の実施形態に限定されるものではない。また、図面の寸法比率は図示した比率に限られるものではない。また、本明細書において「~」を用いて示された数値範囲は、「~」の前後に記載される数値をそれぞれ最小値及び最大値として含む範囲を示す。 EMBODIMENT OF THE INVENTION Hereinafter, the form for implementing this invention is demonstrated in detail, referring drawings as needed. However, the present invention is not limited to the following embodiments. Also, the dimensional ratios of the drawings are not limited to the illustrated ratios. Further, in this specification, a numerical range indicated using "to" indicates a range including the numerical values before and after "to" as the minimum and maximum values, respectively.

本実施形態に係る半導体装置の製造方法では、樹脂層1と、樹脂層1に対して剥離可能な基材2と、が一体となったフィルム3を用いる(図1(a)参照)。フィルム3の形状、大きさに関しては特に限定するものではなく、例えば直径が12インチのウエハ状としてもよく、600mm×600mmのパネル状としてもよい。 In the method of manufacturing a semiconductor device according to this embodiment, a film 3 is used in which a resin layer 1 and a substrate 2 that can be separated from the resin layer 1 are integrated (see FIG. 1A). The shape and size of the film 3 are not particularly limited, and may be, for example, a wafer shape with a diameter of 12 inches or a panel shape of 600 mm×600 mm.

樹脂層1としては特に限定するものではなく、任意の樹脂を適用することができるが、例えば、半導体素子の裏面との接着性に優れるグリシジルアクリレートを含有するアクリル重合体、又はエポキシ樹脂、フェノール樹脂、硬化促進剤及び無機充填剤を含有する樹脂を用いることが好ましい。また、樹脂層1としては、剛性と低熱膨張性を付与するため、例えば、ガラス布を含有する樹脂を用いることが好ましい。 The resin layer 1 is not particularly limited, and any resin can be applied. , a curing accelerator and an inorganic filler are preferably used. As the resin layer 1, it is preferable to use a resin containing glass cloth, for example, in order to impart rigidity and low thermal expansion.

グリシジルアクリレートを含有するアクリル重合体としては、従来公知のものを特に制限なく用いることができる。 As the acrylic polymer containing glycidyl acrylate, conventionally known ones can be used without particular limitation.

また、エポキシ樹脂、フェノール樹脂、硬化促進剤及び無機充填剤を含有する樹脂としては、従来公知のものを特に制限なく等を好適に用いることができる。 As the resin containing epoxy resin, phenol resin, curing accelerator and inorganic filler, conventionally known resins can be suitably used without particular limitation.

さらにガラス布としては、従来公知のものを特に制限なく用いることができる。また、その際の樹脂としては特に限定するものではない。 Further, as the glass cloth, conventionally known ones can be used without particular limitation. In addition, the resin in that case is not particularly limited.

剥離可能な基材2としては特に限定するものではなく、機械剥離、レーザー剥離、UV剥離、熱剥離等の方式で剥離可能な剥離層5を備えた任意の基材を用いることができる(図1(a)参照)。剥離工程が簡便かつ樹脂層1に金属箔層を提供できる点から、剥離層5として、剥離可能な2枚以上の金属箔51,52を片面もしくは両面に配置した積層体であることが好ましい(図2(a)参照)。この場合、少なくとも基材2の樹脂層1と接する側に金属箔51,52を配置することが好ましい。 The peelable substrate 2 is not particularly limited, and any substrate having a peelable layer 5 that can be peeled off by a method such as mechanical peeling, laser peeling, UV peeling, or thermal peeling can be used (Fig. 1(a)). From the viewpoint that the peeling process is simple and the metal foil layer can be provided on the resin layer 1, it is preferable that the peeling layer 5 is a laminate in which two or more peelable metal foils 51 and 52 are arranged on one side or both sides ( See FIG. 2(a)). In this case, it is preferable to arrange the metal foils 51 and 52 at least on the side of the substrate 2 that is in contact with the resin layer 1 .

剥離可能な2枚以上の金属箔51,52としては、特に限定するものではない。 The two or more peelable metal foils 51 and 52 are not particularly limited.

このとき、金属箔51,52を有する積層体の金属箔51,52以外の部分4は特に限定するものではなく、有機材料、ガラス、シリコンウエハ、金属板等の任意の材料を適用することができるが、物性のコントロールがしやすく、ウエハレベルパッケージの製造プロセス中で割れにくく、様々な形状に加工しやすいことから、有機材料であることが好ましい。
上記有機材料としては、特に限定されるものではない。
At this time, the portion 4 of the laminate having the metal foils 51 and 52 other than the metal foils 51 and 52 is not particularly limited, and any material such as organic material, glass, silicon wafer, metal plate, etc. can be applied. However, organic materials are preferable because they are easy to control physical properties, are not easily cracked during the wafer level package manufacturing process, and are easy to process into various shapes.
The organic material is not particularly limited.

また、剛性と低熱膨張性を付与するため、金属箔51,52を有する積層体がガラス布を有することが好ましい。 Further, it is preferable that the laminate having the metal foils 51 and 52 has a glass cloth in order to impart rigidity and low thermal expansion.

上記ガラス布としては、特に限定されるものではない。 The glass cloth is not particularly limited.

剥離可能な基材2の作製方法については特に限定するものではないが、上記有機材料、ガラス布及び金属箔を用いる場合、以下のような工程を経ることができる。各工程の条件は、適用する樹脂にあわせて任意に設定することができる。
(I)ワニス状とした有機材料を塗工機でガラスクロスに含浸させる、あるいはPETフィルムにダムコートした有機材料を、ガラスクロスの両側からラミネートし含浸させる
(II)加熱乾燥してBステージ(半硬化)状態とする
(III)その片面あるいは両面に剥離可能な2枚以上の金属箔51,52を配し、プレスする
(IV)有機材料を硬化する
The method for producing the peelable base material 2 is not particularly limited, but when using the above organic material, glass cloth, and metal foil, the following steps can be performed. The conditions of each step can be arbitrarily set according to the resin to be applied.
(I) Impregnate a glass cloth with a varnish-like organic material using a coating machine, or laminate and impregnate a PET film with an organic material dam-coated from both sides of the glass cloth (II) Heat dry and B stage (half) (III) Two or more metal foils 51 and 52 that can be peeled off are placed on one or both sides of the material and pressed (IV) The organic material is cured.

また、金属箔51,52を有する積層体のTg(ガラス転移点)を120℃~300℃とすることで、ウエハレベルパッケージ製造プロセス中の加熱工程における寸法安定性を確保することができ好ましい。 Further, by setting the Tg (glass transition point) of the laminate having the metal foils 51 and 52 to 120° C. to 300° C., it is possible to ensure dimensional stability in the heating step during the wafer level package manufacturing process, which is preferable.

Tgが120℃を下回ると、ウエハレベルパッケージ製造プロセス中の乾燥工程のたびにゴム領域となるため、基板内部にひずみを生じやすく好ましくない。また、Tgが300℃を上回ると、積層体自体の硬化反応に必要な温度が高くなる傾向にあり、積層体の硬化時に基板内部にひずみを生じやすくなるため好ましくない。 If the Tg is less than 120° C., it becomes a rubber region every time a drying step is performed during the wafer level package manufacturing process, which is not preferable because it tends to cause distortion inside the substrate. On the other hand, if the Tg exceeds 300° C., the temperature required for the curing reaction of the laminate itself tends to be high, and distortion tends to occur inside the substrate during curing of the laminate, which is not preferable.

また、金属箔51,52を有する積層体の金属箔51,52以外の部分4のTg以下の熱膨張率を、1×10-6/℃~20×10-6/℃とすることで、半導体素子6を搭載して封止材8で封止した際の反りを低く抑えやすいため好ましい。封止材8としては特に限定するものではなく、半導体装置の目的に合わせた任意の封止樹脂を適用することができる。例えば、直径が5~20μm程度のシリカを5~80wt%の範囲で含有したエポキシ系樹脂等が適用できる。半導体素子6は熱膨張係数が3.5×10-6/℃近辺であり、封止材8は5.0×10-6/℃~25.0×10-6/℃程度であるため、熱膨張係数が上記範囲内にあると、半導体素子6のサイズ、封止材8の厚さ等で最適化しやすい。 Further, by setting the thermal expansion coefficient below Tg of the portion 4 other than the metal foils 51 and 52 of the laminate having the metal foils 51 and 52 to 1×10 −6 /° C. to 20×10 −6 /° C., This is preferable because warping when the semiconductor element 6 is mounted and sealed with the sealing material 8 can be easily suppressed. The sealing material 8 is not particularly limited, and any sealing resin suitable for the purpose of the semiconductor device can be applied. For example, an epoxy resin or the like containing silica having a diameter of about 5 to 20 μm in a range of 5 to 80 wt % can be applied. The thermal expansion coefficient of the semiconductor element 6 is around 3.5×10 −6 /° C., and the sealing material 8 is around 5.0×10 −6 /° C. to 25.0×10 −6 /° C., When the coefficient of thermal expansion is within the above range, it is easy to optimize the size of the semiconductor element 6, the thickness of the encapsulant 8, and the like.

半導体素子6を搭載して封止材8で封止した際に、金属箔51,52を有する積層体の金属箔51,52以外の部分のTg以下の熱膨張率が1×10-6/℃を下回ると、封止材8を上面にしてスマイル形状(封止材8側が凹となってフィルム3側が凸となる湾曲形状)に反りやすくなり、20×10-6/℃を上回ると、封止材8を上面にしてクライ形状(封止材8側が凸となってフィルム3側が凹となる湾曲形状)に反りやすくなり、剥離可能な基材2の剥離工程の支障となりやすくなるため好ましくない。 When the semiconductor element 6 is mounted and sealed with the sealing material 8, the thermal expansion coefficient below Tg of the portion other than the metal foils 51 and 52 of the laminate having the metal foils 51 and 52 is 1×10 −6 / When the temperature is below 20×10 −6 /° C., it tends to warp into a smile shape (a curved shape in which the sealing material 8 side is concave and the film 3 side is convex) with the sealing material 8 facing upward. It is preferable because it tends to warp into a cry shape (a curved shape in which the sealing material 8 side is convex and the film 3 side is concave) with the sealing material 8 facing upward, and it tends to interfere with the peeling process of the peelable base material 2. do not have.

また、金属箔51,52を有する積層体の金属箔51,52以外の部分4の厚さを、0.015mm~2.00mmとすることで、ウエハレベルパッケージ製造プロセス中の反りと、製造しやすさを両立できるため好ましい。 In addition, by setting the thickness of the portion 4 other than the metal foils 51 and 52 of the laminate having the metal foils 51 and 52 to 0.015 mm to 2.00 mm, warping during the wafer level package manufacturing process and manufacturing It is preferable because it is compatible with ease of use.

積層体の金属箔51,52以外の部分4の厚さが0.015mmを下回ると、剥離可能な基材2の剛性が低下し、また、熱膨張係数を低く抑えることが難しくなるため好ましくなく、2.00mmを上回ると、装置の搬送系及び封止金型が対応しにくくなり、また、剥離可能な基材2の製造コスト増となるため好ましくない。 If the thickness of the portion 4 other than the metal foils 51 and 52 of the laminate is less than 0.015 mm, the rigidity of the base material 2 that can be peeled off decreases, and it becomes difficult to keep the coefficient of thermal expansion low, which is not preferable. , 2.00 mm, it is not preferable because it becomes difficult for the conveying system of the apparatus and the sealing mold to cope with it, and the production cost of the peelable base material 2 increases.

樹脂層1を剥離可能な基材2上に設けるには、樹脂層1をラミネート、スピンコート、ダムコート、ダイコート、プレス等任意の方法で形成することができ、その方法を特に限定するものではない。 In order to provide the resin layer 1 on the peelable base material 2, the resin layer 1 can be formed by any method such as lamination, spin coating, dam coating, die coating, pressing, etc., and the method is not particularly limited. .

例えば、樹脂層1としてグリシジルアクリレートを含有するアクリル重合体を用いる場合、以下のような工程をとることができる。各工程の条件は、適用する樹脂にあわせ任意に設定することができる。
(I)ワニス状とした樹脂をPETフィルムにダムコートする
(II)加熱乾燥してBステージ(半硬化)状態とする
(III)剥離可能な基材2上にラミネートする
(IV)樹脂を硬化する
For example, when an acrylic polymer containing glycidyl acrylate is used as the resin layer 1, the following steps can be taken. Conditions for each step can be arbitrarily set according to the resin to be applied.
(I) Dam-coating a varnish-like resin on a PET film (II) B-stage (semi-cured) by heating and drying (III) Laminating on a peelable substrate 2 (IV) Curing the resin

例えば、樹脂層1としてガラス布を含有する樹脂を用いる場合、以下のような工程を経ることができる。各工程の条件は、適用する樹脂にあわせ任意に設定することができる。
(I)ワニス状とした樹脂を塗工機でガラスクロスに含浸させる、あるいはPETフィルムにダムコートした樹脂を、ガラスクロスの両側からラミネートし含浸させる
(II)加熱乾燥してBステージ(半硬化)状態とする
(III)剥離可能な基材2上にプレスする
(IV)樹脂を硬化する
For example, when a resin containing glass cloth is used as the resin layer 1, the following steps can be performed. Conditions for each step can be arbitrarily set according to the resin to be applied.
(I) Impregnate a glass cloth with a varnish-like resin using a coating machine, or laminate and impregnate a PET film with a resin dam-coated from both sides of the glass cloth (II) B stage (semi-cured) by heating and drying (III) Pressing onto the peelable substrate 2 (IV) Curing the resin

上記工程における加熱乾燥、ラミネート、プレス及び硬化条件等を調整することで、樹脂層1を半硬化状態に維持し、接着性を持たせてもよい。 The resin layer 1 may be maintained in a semi-cured state and have adhesiveness by adjusting heat drying, lamination, pressing, curing conditions, and the like in the above steps.

また、本実施形態に係る半導体装置の製造方法では、樹脂層1に半導体素子6を搭載する(図1(b)、図2(b)参照)。この場合、樹脂層1に個片化した半導体素子6を搭載することが好ましい。 In addition, in the method of manufacturing a semiconductor device according to this embodiment, the semiconductor element 6 is mounted on the resin layer 1 (see FIGS. 1B and 2B). In this case, it is preferable to mount individualized semiconductor elements 6 on the resin layer 1 .

半導体素子6の個数、大きさ、厚さ、材質、付着物、機能等に関しては特に限定するものではなく、あらゆる種類の半導体素子を適用することができる。また、半導体素子6の搭載方法に関しても特に限定するものではなく、半導体後工程で広く適用されているダイボンダ等、あらゆる装置及び方法を適用することができる。半導体素子搭載時の条件についても一切の限定はなく、温度、圧力、それらの印加時間等、任意に設定できる。 The number, size, thickness, material, attachments, functions, etc. of the semiconductor elements 6 are not particularly limited, and all kinds of semiconductor elements can be applied. Also, the method of mounting the semiconductor element 6 is not particularly limited, and any device and method such as a die bonder widely used in the post-process of semiconductors can be applied. The conditions for mounting the semiconductor element are not limited at all, and the temperature, pressure, application time thereof, and the like can be arbitrarily set.

半導体素子6の接着のため、ダイボンドフィルム及びアンダフィル材を始めとするあらゆる接着剤を用いることができるが、前述したように樹脂層1が接着性を有してあると、それら接着剤の供給工程が不要となり、工程の簡略化となるため好ましい。 Any type of adhesive, including a die bond film and an underfill material, can be used for bonding the semiconductor element 6. However, if the resin layer 1 has adhesiveness as described above, the supply of these adhesives will be difficult. This is preferable because it eliminates the need for a process and simplifies the process.

また、本実施形態に係る半導体装置の製造方法では、樹脂層1に、バンプ面が上となるように半導体素子6を搭載する。バンプ面は、半導体素子6のバンプ7が形成された面である。搭載の際に半導体素子のバンプ面を保護するシート状の部材を適用してもよく、それを後からはがす工程があってもよい。 Further, in the method of manufacturing a semiconductor device according to the present embodiment, the semiconductor element 6 is mounted on the resin layer 1 so that the bump surface faces upward. The bump surface is the surface on which the bumps 7 of the semiconductor element 6 are formed. A sheet-like member may be applied to protect the bump surfaces of the semiconductor element during mounting, and a step of removing it later may be included.

また、本実施形態に係る半導体装置の製造方法では、樹脂層1に搭載した半導体素子6を封止材8で封止した後(図1(c)、図2(c)参照)、樹脂層1から剥離可能な基材2を剥離する(図1(d)、図2(d)参照)。封止方法については特に限定するものではなく、コンプレッションモールド方式、トランスファモールド方式、フィルムラミネート方式、ディスペンス方式等あらゆる方法を任意の封止条件で適用することができる。 Further, in the method for manufacturing a semiconductor device according to the present embodiment, after sealing the semiconductor element 6 mounted on the resin layer 1 with the sealing material 8 (see FIGS. 1(c) and 2(c)), the resin layer A peelable base material 2 is peeled off from 1 (see FIG. 1(d) and FIG. 2(d)). The sealing method is not particularly limited, and any method such as a compression mold method, a transfer mold method, a film lamination method, or a dispensing method can be applied under arbitrary sealing conditions.

また、本実施形態に係る半導体装置の製造方法では、剥離可能な基材2を剥離した後、必要ならば所望する組立プロセスを通した後、一つ又は複数の半導体装置単位に個片化する(図1(e)、図2(e)参照)。該当する組立プロセスとしては、特に限定するものではないが、封止材8の研削、再配線層9の形成、はんだバンプ10の搭載、封止材8への導電ビア11の形成(図3(e)参照)等が挙げられる。半導体装置単位への個片化はダイサ(ダイシングマシン)を始めとする様々な装置を用いて実施することができ、特に限定するものではない。 In addition, in the method of manufacturing a semiconductor device according to the present embodiment, after peeling off the peelable base material 2, after passing through a desired assembly process if necessary, the semiconductor device is singulated into one or a plurality of semiconductor device units. (See FIG. 1(e) and FIG. 2(e)). The applicable assembly process is not particularly limited, but includes grinding of the sealing material 8, formation of the rewiring layer 9, mounting of the solder bumps 10, and formation of the conductive vias 11 in the sealing material 8 (FIG. 3 ( e) see) and the like. Dividing into semiconductor device units can be performed using various devices including a dicer (dicing machine), and is not particularly limited.

このとき、剥離可能な基材2として、剥離可能な2枚以上の金属箔51,52を有する積層体を用いた場合、1枚の金属箔51を樹脂層1に残すと、半導体素子6の裏面に樹脂層1を介して金属箔51が残るため、半導体素子6の発熱をパッケージ外部に逃がしやすくなり好ましい(図2(d)(e)参照)。 At this time, when a laminate having two or more peelable metal foils 51 and 52 is used as the peelable base material 2 , if one sheet of the metal foil 51 is left on the resin layer 1 , the semiconductor element 6 will be damaged. Since the metal foil 51 remains on the back surface through the resin layer 1, the heat generated by the semiconductor element 6 can easily escape to the outside of the package, which is preferable (see FIGS. 2(d) and 2(e)).

さらに、樹脂層1と接する側の金属箔51に予め回路53を形成しておくことで、樹脂層1の表面を基板同様の回路面として適用することができ好ましい(図3(a)~(e)参照)。回路53の形成方法は特に限定するものでなく、サブトラクティブ法、セミアディティブ法、アディティブ法等の任意の方法を用いることができる。図3(e)には剥離可能な基材2を剥離した後に、封止材8の研削、封止材8への導電ビア11の形成、再配線層9の形成、はんだバンプ10の搭載、個片化を実施した様子を示す。金属箔51に予め回路53を形成しておくことで、より高機能な半導体装置を製造することができる。 Furthermore, by forming a circuit 53 in advance on the metal foil 51 on the side that contacts the resin layer 1, the surface of the resin layer 1 can be applied as a circuit surface similar to the substrate, which is preferable (FIGS. 3A to 3D). e) see). A method of forming the circuit 53 is not particularly limited, and any method such as a subtractive method, a semi-additive method, or an additive method can be used. In FIG. 3(e), after peeling off the peelable base material 2, the sealing material 8 is ground, the conductive vias 11 are formed in the sealing material 8, the rewiring layer 9 is formed, the solder bumps 10 are mounted, A state in which singulation is performed is shown. By forming the circuit 53 on the metal foil 51 in advance, a semiconductor device with higher functionality can be manufactured.

なお、剥離可能な機材を剥離するタイミングは、特に限定されるものではない。例えば、図4(a)~(f)に示すように、封止材8の研削(図4(c)参照)を実施し、再配線層9の形成及びはんだバンプ10の搭載(図4(d)参照)を実施し、その後に、剥離可能な基材2を剥離し(図4(e)参照)、半導体装置単位で個片化してもよい(図4(f)参照)。 The timing of peeling off the peelable material is not particularly limited. For example, as shown in FIGS. 4(a) to 4(f), the sealing material 8 is ground (see FIG. 4(c)), the rewiring layer 9 is formed, and the solder bumps 10 are mounted (see FIG. 4 ( d)) may be carried out, after which the peelable base material 2 may be peeled off (see FIG. 4(e)) and separated into individual semiconductor devices (see FIG. 4(f)).

以上、本発明によって、接着層からの剥離と保護層の形成を別々に実施する必要がなくなり、半導体装置製造プロセスの簡略化が図れる。当該半導体装置は、薄型かつ高機能な半導体装置に好適であり、産業上の利用価値は非常に大きい。 As described above, according to the present invention, it is no longer necessary to separate the separation from the adhesive layer and the formation of the protective layer, thereby simplifying the semiconductor device manufacturing process. The semiconductor device is suitable for a thin and highly functional semiconductor device, and has a very large industrial utility value.

1…樹脂層、2…基材、3…フィルム、4…積層体の金属箔以外の部分、5…剥離層、6…半導体素子、7…バンプ、8…封止材、9…再配線層、10…はんだバンプ、11…導電ビア、51,52…金属箔、53…回路、101…接着層、102…基材、103…接着層、104…半導体素子、105…封止材、106…保護層、107…再配線層。
DESCRIPTION OF SYMBOLS 1... Resin layer, 2... Base material, 3... Film, 4... Part other than metal foil of laminated body, 5... Release layer, 6... Semiconductor element, 7... Bump, 8... Sealing material, 9... Rewiring layer , 10... Solder bump 11... Conductive via 51, 52... Metal foil 53... Circuit 101... Adhesive layer 102... Base material 103... Adhesive layer 104... Semiconductor element 105... Sealing material 106... Protective layer, 107... Rewiring layer.

Claims (14)

樹脂層と前記樹脂層に対して剥離可能な基材とが一体となったフィルムの前記樹脂層に、バンプ面が上となるように半導体素子を搭載し、
前記樹脂層に搭載した前記半導体素子を封止材で封止した後、前記樹脂層から前記基材を剥離し、その後、前記封止材を研削し、
前記樹脂層として、グリシジルアクリレートを含有するアクリル重合体を用いることを特徴とする半導体装置の製造方法。
A semiconductor element is mounted on the resin layer of a film in which a resin layer and a base material that can be separated from the resin layer are integrated with the bump surface facing upward,
After sealing the semiconductor element mounted on the resin layer with a sealing material, the base material is peeled off from the resin layer, and then the sealing material is ground ,
A method of manufacturing a semiconductor device, wherein an acrylic polymer containing glycidyl acrylate is used as the resin layer .
前記樹脂層に個片化した前記半導体素子を搭載することを特徴とする請求項1に記載の半導体装置の製造方法。 2. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor elements separated into individual pieces are mounted on the resin layer. 前記樹脂層が接着性を有することを特徴とする請求項1又は2に記載の半導体装置の製造方法。 3. The method of manufacturing a semiconductor device according to claim 1, wherein said resin layer has adhesiveness. 前記樹脂層から前記基材を剥離した後、一つ又は複数の半導体装置単位に個片化することを特徴とする請求項1~3の何れか一項に記載の半導体装置の製造方法。 4. The method of manufacturing a semiconductor device according to claim 1, wherein after the base material is separated from the resin layer, the substrate is separated into one or a plurality of semiconductor device units. 前記フィルムは、剥離可能な2枚以上の金属箔が前記基材の片面もしくは両面に配置された積層体を有し、
少なくとも前記基材の前記樹脂層と接する側に前記金属箔を配置することを特徴とする請求項1~4の何れか一項に記載の半導体装置の製造方法。
The film has a laminate in which two or more peelable metal foils are arranged on one side or both sides of the base material,
5. The method of manufacturing a semiconductor device according to claim 1, wherein the metal foil is arranged at least on a side of the base material that is in contact with the resin layer.
前記樹脂層から基材を剥離する際に、前記金属箔の1枚を前記樹脂層に残すことを特徴とする請求項5に記載の半導体装置の製造方法。 6. The method of manufacturing a semiconductor device according to claim 5, wherein one sheet of the metal foil is left on the resin layer when the base material is peeled off from the resin layer. 前記積層体の前記金属箔以外の部分が有機材料であることを特徴とする請求項5又は6に記載の半導体装置の製造方法。 7. The method of manufacturing a semiconductor device according to claim 5, wherein a portion of said laminate other than said metal foil is made of an organic material. 前記積層体がガラス布を有することを特徴とする請求項5又は6に記載の半導体装置の製造方法。 7. The method of manufacturing a semiconductor device according to claim 5, wherein said laminate comprises glass cloth. 前記積層体のガラス転移点が、120℃~300℃であることを特徴とする請求項5~8の何れか一項に記載の半導体装置の製造方法。 9. The method of manufacturing a semiconductor device according to claim 5, wherein the laminated body has a glass transition point of 120.degree. C. to 300.degree. 前記積層体の前記金属箔以外の部分のガラス転移点以下の熱膨張率が、1×10-6/℃~20×10-6/℃であることを特徴とする請求項5~9の何れか一項に記載の半導体装置の製造方法。 10. The thermal expansion coefficient below the glass transition point of the portion other than the metal foil of the laminate is 1×10−6/° C. to 20×10−6/° C., according to any one of claims 5 to 9. 1. A method of manufacturing a semiconductor device according to claim 1. 前記積層体の前記金属箔以外の部分の厚さが、0.015mm~2.00mmであることを特徴とする請求項5~10の何れか一項に記載の半導体装置の製造方法。 11. The method of manufacturing a semiconductor device according to claim 5, wherein the thickness of the portion of the laminate other than the metal foil is 0.015 mm to 2.00 mm. 前記樹脂層と接する前記金属箔に予め回路が形成されていることを特徴とする請求項6~11の何れか一項に記載の半導体装置の製造方法。 12. The method of manufacturing a semiconductor device according to claim 6, wherein a circuit is formed in advance on said metal foil in contact with said resin layer. 前記樹脂層は、エポキシ樹脂、フェノール樹脂、硬化促進剤及び無機充填剤を含有することを特徴とする請求項1~12の何れか一項に記載の半導体装置の製造方法。 13. The method of manufacturing a semiconductor device according to claim 1 , wherein the resin layer contains an epoxy resin, a phenol resin, a curing accelerator and an inorganic filler. 前記樹脂層がガラス布を含有することを特徴とする請求項1~13の何れか一項に記載の半導体装置の製造方法。 14. The method of manufacturing a semiconductor device according to claim 1 , wherein the resin layer contains glass cloth.
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