JP7157220B2 - inverter circuit - Google Patents

Description

Application of Article 30, Paragraph 2 of the Patent Act Date of sale January 27, 2020 Place of sale Ryoei Metals Co., Ltd. (1230 Kamideya, Okegawa City, Saitama Prefecture) Publisher Shimada Rika Kogyo Co., Ltd.

The present invention relates to an inverter circuit. More particularly, the present invention relates to inverter circuits suitable for use in the field of power electronics.

2. Description of the Related Art Conventionally, inverter devices are known as power supply devices connected to loads such as series resonant loads and parallel resonant loads.

Examples of the load include an induction heating circuit, which is a series resonance circuit configured by connecting a heating coil for induction heating and a resonance capacitor in series.

Generally, in such an inverter device, as an inverter control unit for controlling an inverter unit having an inverter circuit, an inverter control unit configured by a phase locked loop (PLL) circuit or a pulse width modulation (PWM) circuit is used. ), an inverter control unit or the like that operates according to a control system is used, and the inverter unit is controlled by such an inverter control unit.

Here, a conventionally known inverter device controlled by the inverter control section described above will be described with reference to FIG.

FIG. 1 shows a configuration explanatory diagram schematically showing the overall configuration of a conventional inverter device controlled by an inverter control section and connected to a load.

As shown in FIG. 1, the inverter device 100 converts alternating current (AC) power supplied from an alternating current (AC) power supply 102 into high frequency alternating current power of a desired voltage, and converts it into a load on the side of an external load such as an induction heating circuit. 200.

For example, a commercial AC power supply can be used as the AC power supply 102 . In this case, the inverter device 100 converts the commercial AC voltage into a desired high-frequency AC voltage and supplies it to the load 200 .

More specifically, the inverter device 100 receives an AC voltage supplied from an AC power supply 102 and converts it forward into a DC voltage (plus DC voltage (+DC voltage) and minus DC voltage (−DC voltage)). and a converter unit 104 having a converter circuit that outputs a DC voltage output from the converter unit 104, and an output signal (non-inverted An inverter unit 106 having an inverter circuit that outputs an output signal Q and an inverted output signal NQ), an output sensor 108 that detects an output signal from the inverter unit 106 and outputs the detection result as an output sensor signal, and an inverter from the outside. Converter control unit 110 feedback-controls the DC voltage forward-converted by converter unit 104 based on an output setting signal, which is a signal for setting the output of unit 106, and an output sensor signal output from output sensor 108; and an inverter control section 112 that feedback-controls the operation of the inverter section 106 based on the outputted output sensor signal.

Here, the converter circuit of the converter section 104 is configured by, for example, a thyristor rectifier circuit, a chopper circuit, or the like. When supplied with an AC voltage from the AC power supply 102 , the converter unit 104 controls forward conversion of the AC voltage to a DC voltage according to a signal output from the converter control unit 110 .

The inverter unit 106 includes an inverter circuit composed of semiconductor elements such as transistors, for example. The inverter unit 106 receives the DC voltage output from the converter unit 104, reverse-converts the input DC voltage to a high-frequency AC voltage by switching ON/OFF of the transistor, and outputs the voltage. control.

Here, as the inverter circuits constituting the inverter section 106, for example, as will be described later with reference to FIG. An inverter circuit having inverter blocks of 3 stages) is used.

Output sensor 108 provided at the output stage of inverter section 106 outputs the detection result to converter control section 110 and inverter control section 112 as an output sensor signal.

As a result, in inverter device 100, the DC voltage value output from converter section 104 is variably controlled so that the output of inverter section 106 reaches the set level indicated by the output setting signal.

Inverter control unit 112 outputs a rectangular-wave inverter drive signal (non-inverted rectangular-wave inverter drive signal Q and inverted rectangular-wave inverter drive signal NQ) that is an inverter drive signal for driving inverter unit 106, and outputs the output of inverter unit 106. is automatically controlled to the resonance frequency of the load 200 .

2, reference numeral 106a denotes an output synthesizing unit (non-inverting output Reference numeral 106b synthesizes the inverted output signal NQ from each inverter block constituting the inverter unit 106 and outputs the result to the load 200. It is an inverted output signal synthesizing terminal which is an output signal synthesizing terminal as an output synthesizing section (inverted output synthesizing section).

FIG. 2 shows a circuit configuration explanatory diagram schematically showing the configuration of a conventional inverter circuit that constitutes the inverter section 106. As shown in FIG.

In FIG. 2, the inverter circuit that constitutes the inverter unit 106 inversely converts the input DC voltage into a high-frequency AC voltage and then outputs output signals (non-inverted output signals Q and Only the configuration of the output section (output stage) that outputs the inverted output signal NQ) is illustrated, and in the inverter circuit, the DC voltage (plus DC voltage (+ DC voltage) and negative DC voltage ( The other components including the input section (input stage) for inputting the DC voltage) are appropriately omitted from the drawing because they are conventionally known techniques.

In the following, referring to FIG. 2, the inverter circuit forming the inverter unit 106 reversely converts the input DC voltage to a high-frequency AC voltage, and then outputs an output signal (non-inverted signal) for supplying power to the load 200 . Only the configuration of the output section (output stage) that outputs the output signal Q and the inverted output signal NQ) will be described in detail. ) and an input section (input stage) for inputting a negative DC voltage (-DC voltage)) are conventionally well-known techniques, and therefore descriptions thereof will be omitted as appropriate.

Here, the inverter circuit forming the inverter section 106 includes three inverter blocks (first inverter block 302A, It has a second inverter block 302B and a third inverter block 302C).

In other words, each of the three inverter blocks, ie, the first inverter block 302A, the second inverter block 302B, and the third inverter block 302C, that is, each inverter block outputs opposite polarity output signals (non-inverted output signals Q and Each is composed of a pair of inverters for generating an inverted output signal NQ).

In the inverter section 106, output terminals serving as output sections (non-inverted output section) of the non-inverted output signal Q in each of the three inverter blocks, namely, the first inverter block 302A, the second inverter block 302B, and the third inverter block 302C. and an output portion (inverted output portion) of the inverted output signal NQ in each of the first inverter block 302A, the second inverter block 302B, and the third inverter block 302C, which are three inverter blocks. Inverted output signal output terminals, which are output terminals, are connected in parallel, and output synthesizing sections (non-inverted output synthesizing section (non-inverted output signal synthesizing terminal 106a) and inverted output synthesizing section (inverted output signal synthesizing terminal 106b)) A large current is generated by combining the currents, and is output as an output signal (non-inverted output signal Q and inverted output signal NQ) from non-inverted output signal combining terminal 106a and non-inverting output signal combining terminal 106b to load 200. .

More specifically, the first inverter block 302A, the second inverter block 302B, and the third inverter block 302C, which are the three inverter blocks, are arranged in the vertical direction (vertical direction) which is the Y direction on the paper surface (XY plane) of FIG. , and the non-inverted output signal output terminal and the inverted output signal output terminal are connected in parallel as described below.

Here, the first inverter block 302A located in the upper stage in the vertical direction generates a non-inverted output signal Q as a pair of inverters for generating output signals of opposite polarities (a non-inverted output signal Q and an inverted output signal NQ). It is composed of a first non-inverted output inverter 302A-1 and a first inverted output inverter 302A-2 for generating an inverted output signal NQ.

Similarly, the second inverter block 302B positioned in the middle in the vertical direction generates a non-inverted output signal Q as a pair of inverters for generating output signals of opposite polarities (a non-inverted output signal Q and an inverted output signal NQ). It is composed of a second non-inverted output inverter 302B-1 and a second inverted output inverter 302B-2 that generates an inverted output signal NQ.

Similarly, the third inverter block 302C located in the lower row in the vertical direction generates a non-inverted output signal Q as a pair of inverters for generating output signals of opposite polarities (a non-inverted output signal Q and an inverted output signal NQ). It is composed of a third non-inverted output inverter 302C-1 and a third inverted output inverter 302C-2 for generating an inverted output signal NQ.

The first non-inverted output inverter 302A-1, the second non-inverted output inverter 302B-1, and the third non-inverted output inverter 302C-1 have the same configuration. 2. The second inverted output inverter 302B-2 and the third inverted output inverter 302C-2 have the same configuration. The second inverter block 302B and the third inverter block 302C have the same configuration.

Here, reference numeral 304 denotes a first non-inverted output signal output terminal 302A-1-1, which is the output portion (non-inverted output portion) of the first non-inverted output inverter 302A-1, and a second non-inverted output inverter 302B-1. The second non-inverted output signal output terminal 302B-1-1 which is the output portion (non-inverted output portion) of the third non-inverted output signal output terminal 302B-1-1 and the third non-inverted output which is the output portion (non-inverted output portion) of the third non-inverted output inverter 302C-1 A non-inverting output combining portion copper plate which is a conductor for current combining the non-inverting output signals Q output from the signal output terminals 302C-1-1.

The non-inverting output signal synthesizing section copper plate 304 is a rectangular linear plate-like body extending along the vertical direction (vertical direction), which is the Y direction on the XY plane. is formed.

Reference numeral 306 denotes a first inverted output signal output terminal 302A-2-2, which is the output portion (inverted output portion) of the first inverted output inverter 302A-2, and an output portion (inverted output portion) of the second inverted output inverter 302B-2. from the second inverted output signal output terminal 302B-2-2 which is the output section) and the third inverted output signal output terminal 302C-2-2 which is the output section (inverted output section) of the third inverted output inverter 302C-2. This is an inverted output synthesizing portion copper plate which is a conductor for current synthesizing the output inverted output signal NQ.

The inverted output synthesizing copper plate 306 extends along the vertical direction (vertical direction), which is the Y direction, on the XY plane, and is substantially parallel to the non-inverting output synthesizing copper plate 304 in the lateral direction (horizontal direction), which is the X direction. It is a rectangular linear plate-like body arranged in the vertical direction, and an inverted output signal synthesizing terminal 106b is formed in a substantially central portion in the vertical direction.

Reference numeral 308 connects the first non-inverted output signal output terminal 302A-1-1 of the first non-inverted output inverter 302A-1 and the first non-inverted output signal input terminal 304A-1 of the non-inverted output combining section copper plate 304. a first non-inverting output connection copper plate which is a conductor for

The first non-inverting output connection copper plate 308 is a rectangular straight plate-like body extending along the horizontal direction (horizontal direction), which is the X direction on the XY plane, and the extension direction thereof is the extension of the non-inverting output combining section copper plate 304. It is arranged perpendicular to the direction.

Reference numeral 310 denotes a conductor that connects the first inverted output signal output terminal 302A-2-2 of the first inverted output inverter 302A-2 and the first inverted output signal input terminal 306A-1 of the inverted output synthesis section copper plate 306. A first inverting output connection copper plate.

The first inverting output connection copper plate 310 is a rectangular straight plate-like body extending along the lateral direction (horizontal direction), which is the X direction in the XY plane, and its extending direction is the same as the extending direction of the inverting output synthesizing portion copper plate 306 . arranged orthogonally.

Reference numeral 312 connects the second non-inverted output signal output terminal 302B-1-1 of the second non-inverted output inverter 302B-1 and the second non-inverted output signal input terminal 304B-1 of the non-inverted output synthesis section copper plate 304. a second non-inverting output connection copper plate which is a conductor for

The second non-inverted output connection copper plate 312 is a rectangular straight plate-like body extending along the lateral direction (horizontal direction) which is the X direction in the XY plane, and the extension direction thereof is the extension of the non-inverted output combining section copper plate 304. It is arranged perpendicular to the direction.

Reference numeral 314 is a conductor that connects the second inverted output signal output terminal 302B-2-2 of the second inverted output inverter 302B-2 and the second inverted output signal input terminal 306B-1 of the inverted output synthesis section copper plate 306. A second inverting output connection copper plate.

The second inverting output connection copper plate 314 is a rectangular straight plate-like body extending along the lateral direction (horizontal direction), which is the X direction in the XY plane, and its extending direction coincides with the extending direction of the inverting output synthesizing portion copper plate 306 . arranged orthogonally.

Reference numeral 316 connects the third non-inverted output signal output terminal 302C-1-1 of the third non-inverted output inverter 302C-1 and the third non-inverted output signal input terminal 304C-1 of the non-inverted output synthesizing section copper plate 304. a third non-inverting output connection copper plate which is a conductor for

The third non-inverting output connection copper plate 316 is a rectangular straight plate-like body extending along the horizontal direction (horizontal direction), which is the X direction on the XY plane, and its extending direction is the extension of the non-inverting output combining section copper plate 304. It is arranged perpendicular to the direction.

Reference numeral 318 denotes a conductor that connects the third inverted output signal output terminal 302C-2-2 of the third inverted output inverter 302C-2 and the third inverted output signal input terminal 306C-1 of the inverted output synthesizing section copper plate 306. A third inverting output connection copper plate.

The third inverting output connection copper plate 318 is a rectangular linear plate-like body extending along the lateral direction (horizontal direction), which is the X direction in the XY plane, and its extending direction coincides with the extending direction of the inverting output synthesizing portion copper plate 306 . arranged orthogonally.

In the above configuration, according to the inverter device 100, in the inverter section 106, the first non-inverted output signal output terminal 302A-1-1 of the first inverter block 302A and the second non-inverted output signal output terminal of the second inverter block 302B The terminal 302B-1-1 and the third non-inverted output signal output terminal 302C-1-1 of the third inverter block 302C are connected in parallel to the non-inverted output synthesizing section copper plate 304, and the first The inverted output signal output terminal 302A-2-2, the second inverted output signal output terminal 302B-2-2 of the second inverter block 302B and the third inverted output signal output terminal 302C-2-2 of the third inverter block 302C are connected. The non-inverted output signal synthesis terminal 106 a of the non-inverted output synthesis section copper plate 304 and the non-inverted output signal synthesis of the inverted output synthesis section copper plate 306 are combined by connecting in parallel to the inverted output synthesis section copper plate 306 and combining currents to generate a large current. Output signals (non-inverted output signal Q and inverted output signal NQ) resulting from current synthesis can be output to load 200 from terminal 106b.

By the way, according to the inverter circuit of the conventional inverter section 106 described above, the non-inverted output synthesis section copper plates 304 are rectangular straight plates extending in the Y direction and arranged in parallel with each other in the X direction. A first non-inverted output connection copper plate 308 and a first inverted output, each of which is a rectangular linear plate-like body extending in the X direction and arranged with a shift parallel to the Y direction with respect to the inverted output synthesizing portion copper plate 306 A connection copper plate 310, a second non-inverted output connection copper plate 312, a second inversion output connection copper plate 314, a third non-inversion output connection copper plate 314, and a third inversion output connection copper plate 316 are connected in a mutually orthogonal positional relationship. By doing so, a conductor that connects the output section to the output combining section in each inverter block (in this specification and the scope of claims, a conductor that connects the output section to the output combining section is referred to as a "conductor between output sections"). In addition, in this specification and the scope of claims, the length of the conductor between the output parts, in other words, the length of the high-frequency alternating current flowing in the conductor between the output parts is referred to as the "effective length" as appropriate. ) is configured.

Therefore, in the inverter circuit of the conventional inverter section 106, in each inverter block, a conductor between output sections that outputs a non-inverted output signal Q (in this specification and the scope of claims, a "non-inverted output signal The inter-output conductor that outputs Q” is appropriately referred to as the “non-inverted output signal inter-output conductor”.) and the inter-output conductor that outputs the inverted signal NQ (in this specification and the scope of claims, "The conductor between the output section that outputs the inverted output signal NQ" is appropriately called the "Conductor between the inverted output signal output section"). not equal.

Specifically, for the first inverter block 302A, for example, the effective length of the conductor between the non-inverted output signal output sections formed by the non-inverted output synthesizing copper plate 304 and the first non-inverted output connection copper plate 308 is shown. The distance between the first non-inverted output signal output terminal 302A-1-1 and the non-inverted output signal synthesizing terminal 106a is the inverting output signal composed of the inverting output synthesizing section copper plate 306 and the first inverting output connection copper plate 310. It is different from the distance between the first inverted output signal output terminal 302A-2-2 and the inverted output signal synthesizing terminal 106b, which indicates the running length of the inter-output conductor.

That is, in the first inverter block 302A, the effective length of the conductor between non-inverted output signal output sections and the effective length of the conductor between inverted output signal output sections are different and not equal.

Similarly, for the second inverter block 302B and the third inverter block 302C, as in the case of the first inverter block 302A, the effective length of the conductor between the non-inverted output signal output section and the inverted output signal output section in each inverter block The effective lengths of the interconductors are different and unequal.

In addition, the effective lengths of the conductors between the output portions are different and unequal between the inverter blocks of the first inverter block 302A, the second inverter block 302B, and the third inverter block 302C.

Specifically, for example, when the first inverter block 302A and the second inverter block 302B are compared, the effective length of the conductor between the non-inverted output signal output sections and the effective length of the conductor between the inverted output signal output sections are both The first inverter block 302A is longer than the second inverter block 302B.

Similarly, when comparing the second inverter block 302B and the third inverter block 302C, the effective length of the conductor between the non-inverted output signal output sections and the effective length of the conductor between the inverted output signal output sections are both 302C is longer than the second inverter block 302B.

That is, in the above-described conventional inverter circuit in which a plurality of inverter blocks are connected in parallel, the distance between the output section of each inverter block and the output synthesizing section (in this specification and the scope of claims, "from the output section (In this specification and the scope of claims, "the distance from the output section to the output synthesis section" is referred to as the "output ), that is, the effective length of the conductors between the output sections (the conductors between the non-inverted output signal output sections and the conductors between the inverted output signal output sections) are different. , the inductance does not match due to the difference in the effective length of the conductor between the non-inverted output signal output section and the conductor between the inverted output signal output section. are not uniform, the influence of different inductances in each inverter block and between each inverter block causes current variations in each inverter block and between each inverter block, making it impossible to combine currents with uniform currents. There was a problem that it would become

Further, in the above-described conventional inverter circuit in which a plurality of inverter blocks are connected in parallel, each inverter block is affected by the inductance of the adjacent inverter block, forming a pseudo inverter, which will be described later. There is also a problem that current variations occur between them, making it impossible to synthesize currents with uniform currents. Such a problem will be described with reference to FIG.

Here, FIG. 3 is a circuit configuration explanatory diagram schematically showing the configuration of a conventional inverter circuit in which a plurality of inverter blocks are connected in parallel. ing. Also, in FIG. 3, the shape illustrated by the dashed-dotted line indicates the conductor between the non-inverted output signal output portions that outputs the non-inverted output signal Q, and the shape illustrated by the two-dotted chain line indicates the inverted output signal that outputs the inverted output signal NQ. Inter-output conductors are shown.

In the following description, the same or similar configurations and actions as those described with reference to FIGS. , the detailed description of the configuration and operation thereof will be omitted as appropriate.

The inverter circuit includes n ("n" is a positive integer) inverter blocks, and in the example shown in FIG. 400 is shown.

Here, the five inverter blocks are aligned in five vertical stages so as to be aligned along the vertical direction (vertical direction), which is the Y direction, on the paper surface (XY plane) of FIG. An inverted output signal output terminal and an inverted output signal output terminal are connected in parallel as described below.

More specifically, the three inverter blocks downward from the top are the same as the first inverter block 302A, the second inverter block 302B, and the third inverter block 302C, which are the three inverter blocks described above. is.

A fourth inverter block 302D is provided below the third inverter block 302C, and a fifth inverter block 302E is provided below the fourth inverter block 302D.

The fourth inverter block 302D and the fifth inverter block 302E have the same configuration as the first inverter block 302A, the second inverter block 302B, and the third inverter block 302C, which are the three upper inverter blocks. there is

Here, reference numeral 302D-1-1 denotes a fourth non-inverted output signal output terminal that is a non-inverted output signal output terminal that is an output section (non-inverted output section) of the non-inverted output signal Q in the fourth inverter block 302D. Reference numeral 302D-2-2 denotes an inverted output signal output terminal, which is an output terminal (inverted output section) of the inverted output signal NQ in the fourth inverter block 302D.

Similarly, reference numeral 302E-1-1 denotes a fifth non-inverted output signal output terminal that is a non-inverted output signal output terminal that is an output section (non-inverted output section) of the non-inverted output signal Q in the fifth inverter block 302E. Reference numeral 302E-2-2 denotes an inverted output signal output terminal that is an output terminal (inverted output section) of the inverted output signal NQ in the fifth inverter block 302E.

In the inverter circuit 400 described above, for each of the adjacent inverter blocks, the spacing between the conductors between the output sections of the adjacent inverter blocks ("the spacing between the conductors between the output sections of the adjacent inverter blocks" Specifically, "the space L1 between the conductor between the inverted output signal output section of the first inverter block 302A and the conductor between the non-inverted signal output section of the second inverter block 302B", "the inverted output of the second inverter block 302B The distance L2 between the inter-signal output section conductor and the non-inverted signal output section conductor of the third inverter block 302C", "the inverted output signal output section conductor of the third inverter block 302C and the non-inverted signal output section conductor of the fourth inverter block 302D and the distance L4 between the conductor between the inverted output signal outputs of the fourth inverter block 302D and the conductor between the non-inverted signal outputs of the fifth inverter block 302E.) is narrow, the inductance between the output section conductors of the adjacent inverter blocks affects each other, the coupling between the output sections of the adjacent inverter blocks increases, and the adjacent inverter blocks are affected by each other's currents. Therefore, a pseudo inverter block is formed between adjacent inverter blocks.

Specifically, a first pseudo inverter block 400A having a first inverted output signal output terminal 302A-2-2 and a second non-inverted output signal output terminal 302B-1-1 is formed, and a second inverted output signal output A second pseudo inverter block 400B having a terminal 302B-2-2 and a third non-inverted output signal output terminal 302C-1-1 is formed, and a third inverted output signal output terminal 302C-2-2 and a fourth non-inverted output terminal 302C-2-2 are formed. A third pseudo inverter block 400C having an output signal output terminal 302D-1-1 is formed, and a fourth inverted output signal output terminal 302D-2-2 and a fifth non-inverted output signal output terminal 302E-1-1 are connected. A fourth pseudo inverter block 400D is formed.

That is, according to the above-described conventional inverter circuit in which a plurality of inverter blocks are connected in parallel, since the distance between the conductors between the output portions of adjacent inverter blocks is narrow, each inverter block is affected by the inductance of the adjacent inverter block. As a result, a pseudo inverter is formed, and there is a problem that current variations occur between the inverter blocks, and current synthesis cannot be performed with uniform currents.

The prior art known to the applicant at the time of filing the patent application is not an invention related to inventions publicly known in the literature, so there is no prior art document information to be described in the specification of the present application.

SUMMARY OF THE INVENTION The present invention has been made in view of the various problems in the prior art as described above. An object of the present invention is to provide an inverter circuit capable of suppressing current variations among inverter blocks and performing current synthesis with more uniform currents.

In order to achieve the above object, the present invention suppresses the influence of inductance between each inverter block and each inverter block in an inverter circuit in which a plurality of inverter blocks are connected in parallel.

For this reason, the present invention (first invention) provides an inverter circuit in which a plurality of inverter blocks are connected in parallel. an inverter circuit for combining and outputting by an inverted output synthesizing unit and an inverted output synthesizing unit), and for each inverter block, a non-inverting output signal, which is the output of each inverter block, is conducted to the non-inverting output synthesizing unit. The effective length of the conductor between the inverted output signal output section and the effective length of the conductor between the inverted output signal output section that conducts the inverted output signal that is the output of each inverter block to the inverted output synthesizing section are made approximately equal. is.

Therefore, according to the present invention (the first invention), the effective length of the conductor between the non-inverted output signal output portions and the effective length of the conductor between the inverted output signal output portions are substantially equal for each inverter block. , the inductances of the conductors between the non-inverted output signal output sections and the conductors between the inverted output signal output sections in each inverter block are aligned, the influence of the inductance in each inverter block is suppressed, and the current in each inverter block is Variation is suppressed, and current synthesis can be performed using uniform currents.

Further, according to the present invention (second invention), in an inverter circuit in which a plurality of inverter blocks are connected in parallel, outputs from output units of the respective inverter blocks are synthesized by an output synthesizing unit and output, wherein each The effective lengths of the conductors between the output sections that conduct electricity from the output sections of the inverter blocks to the output synthesizing section are made substantially equal among the inverter blocks.

Therefore, according to the present invention (second invention) described above, since the effective length of the conductor between the output portions is substantially equal between the inverter blocks, the inductance is uniform between the inverter blocks, and the inductance between the inverter blocks is equalized. The influence of the inductance is suppressed, the current variation among the inverter blocks is suppressed, and current synthesis can be performed with a uniform current.

Further, according to the present invention (third invention), in an inverter circuit in which a plurality of inverter blocks are connected in parallel, outputs from output units of the respective inverter blocks are synthesized by an output synthesizing unit for output, Regarding the inter-output conductors that conduct electricity from the output section of the inverter block to the output synthesizing section, the spacing between the inter-output section conductors in adjacent inverter blocks is not affected by the inductance of the inter-output section conductors of the adjacent inverter blocks. It is designed to extend the distance.

Therefore, according to the present invention (the third invention) described above, since the influence of the inductance of the adjacent inverter block is suppressed and is not affected, a pseudo inverter is not formed. , current variations among the inverter blocks are suppressed, and current synthesis with uniform currents can be performed.

The present invention (fourth invention) provides an inverter circuit in which a plurality of inverter blocks are connected in parallel. output synthesizing unit and inverted output synthesizing unit), and for each inverter block, the non-inverted output signal that is the output of each inverter block is passed to the non-inverted output synthesizing unit. A non-inverted output signal output section in which a conductor between output signal output sections and a conductor between inverted output signal output sections for conducting an inverted output signal, which is an output of each inverter block, to an inverted output synthesizing section are arranged substantially parallel and close to each other. The distance between the inter-conductor and the inter-inverted output signal output section conductor is narrowed.

Therefore, according to the present invention (fourth invention), since the distance between the conductor between the non-inverted output signal output portions and the conductor between the inverted output signal output portions is narrow, the inductance can be reduced. The influence of the inductance in the inverter blocks is suppressed, the current variations among the inverter blocks are suppressed, and currents can be combined with uniform currents.

As described above, according to the present invention, it is possible to equalize the output currents of the switching semiconductor elements constituting the inverter circuit by suppressing the current variation in each inverter block and between the inverter blocks. Since the number of semiconductor elements constituting the circuit can be reduced, the size of the entire device can be reduced and the cost can be reduced.

That is, according to the present invention, a plurality of inverter blocks are connected in parallel, non-inverted output signals outputted from non-inverted output portions of the plurality of inverter blocks are synthesized in a non-inverted output synthesizing portion, and the plurality of inverter blocks are combined. In an inverter circuit that combines and outputs inverted output signals output from the respective inverted output units in the inverted output synthesizing unit, for each of the plurality of inverter blocks, a non-inverted output output from the non-inverted output unit of the inverter block The effective length of the conductor between the non-inverted output signal output sections that conducts the signal to the non-inverted output synthesizing section, and the inverted output signal output section that conducts the inverted output signal output from the inverted output section of the inverter block to the inverted output synthesizing section. It is formed so that the effective length of the intermediate conductor is almost equal to that of the intermediate conductor.

Further, according to the present invention, there is provided an inverter circuit in which a plurality of inverter blocks are connected in parallel, and output signals output from respective output sections of the plurality of inverter blocks are synthesized by an output synthesizing section and output. The effective lengths of the inter-output conductors that conduct electricity from the output section of each inverter block to the output synthesizing section are formed so as to be substantially equal between the inverter blocks.

Further, according to the present invention, there is provided an inverter circuit in which a plurality of inverter blocks are connected in parallel, and output signals output from respective output sections of the plurality of inverter blocks are synthesized by an output synthesizing section and output. The inter-output conductors that conduct electricity from the output section of each inverter block to the output synthesizing section are arranged at a wide first interval, which is the interval between the inter-output conductors of adjacent inverter blocks.

Further, according to the present invention, a plurality of inverter blocks are connected in parallel, non-inverted output signals outputted from non-inverted output units of the plurality of inverter blocks are synthesized in a non-inverted output synthesizing unit, and the plurality of inverter blocks are combined. In an inverter circuit that combines and outputs inverted output signals output from the respective inverted output units in the inverted output synthesizing unit, for each of the plurality of inverter blocks, a non-inverted output output from the non-inverted output unit of the inverter block a conductor between the non-inverted output signal output section that conducts the signal to the non-inverted output synthesizing section, and a conductor between the inverted output signal output section that conducts the inverted output signal outputted from the inverting output section of the inverter block to the inverted output synthesizing section; are arranged substantially parallel and close to each other so as to narrow the second distance between the conductor between the non-inverted output signal output sections and the conductor between the inverted output signal output sections. be.

Further, according to the present invention, a plurality of inverter blocks are connected in parallel, non-inverted output signals outputted from non-inverted output units of the plurality of inverter blocks are synthesized in a non-inverted output synthesizing unit, and the plurality of inverter blocks are combined. In an inverter circuit that combines and outputs inverted output signals output from the respective inverted output units in the inverted output synthesizing unit, for each of the plurality of inverter blocks, a non-inverted output output from the non-inverted output unit of the inverter block a first effective length of the conductor between the non-inverted output signal output sections for conducting the signal to the non-inverted output synthesis section; and an inverted output for conducting the inverted output signal output from the inverted output section of the inverter block to the inverted output synthesis section. The second effective length of the inter-signal-output section conductor is formed to be substantially equal, and the first effective length and the second effective length are respectively formed between the inverter blocks of the plurality of inverter blocks. The conductors between the non-inverted output signal output sections and the conductors between the inverted output signal output sections in each of the inverter blocks are arranged substantially parallel and close to each other for each of the plurality of inverter blocks. The second gap between the conductor between the non-inverted output signal output sections and the conductor between the inverted output signal output sections is narrowed.

Further, according to the present invention, in the above-described invention, the conductor between the non-inverted output signal output sections and the conductor between the inverted output signal output sections in each inverter block are arranged between the non-inverted output signal output sections of adjacent inverter blocks. The conductor and the conductor between the inverted output signal output portions are arranged at a wide first interval.

Further, according to the present invention, in the above-described present invention, the first spacing is such that the inductance between the conductors between the output sections of the adjacent inverter blocks is three times or more the inductance of the conductors between the output sections of each of the inverter blocks. It is designed to be a distance of

Further, in the present invention, in the above-described present invention, the second distance is a distance having an inductance of ⅓ or less of the inductance between the conductors between the output portions of the adjacent inverter blocks. It is what I did.

Further, according to the present invention, a plurality of inverter blocks are connected in parallel, non-inverted output signals outputted from non-inverted output units of the plurality of inverter blocks are synthesized in a non-inverted output synthesizing unit, and the plurality of inverter blocks are combined. in an inverter circuit for synthesizing and outputting inverted output signals output from respective inverting output units of a plurality of inverter blocks in an inverting output synthesizing unit, wherein non-inverted output signals output from respective non-inverting output units of a plurality of inverter blocks are non-inverted a first plate-shaped conductor that conducts electricity to the output synthesizing section; and a second plate-shaped conductor that conducts the inverted output signal output from each of the inverted output sections of the plurality of inverter blocks to the inverted output synthesizing section. , the first plate-shaped conductor and the second plate-shaped conductor are each formed with a long hole.

Further, according to the present invention, in the above-described present invention, the elongated hole is formed to be longer than the length of the inverter block located in the middle part of the inverter block row from the plurality of inverter blocks.

Further, according to the present invention, a plurality of inverter blocks are connected in parallel, non-inverted output signals outputted from non-inverted output units of the plurality of inverter blocks are synthesized in a non-inverted output synthesizing unit, and the plurality of inverter blocks are combined. in an inverter circuit for synthesizing and outputting inverted output signals output from respective inverting output units of a plurality of inverter blocks in an inverting output synthesizing unit, wherein non-inverted output signals output from respective non-inverting output units of a plurality of inverter blocks are non-inverted a first plate-shaped conductor that conducts electricity to the output synthesizing section; and a second plate-shaped conductor that conducts the inverted output signal output from each of the inverted output sections of the plurality of inverter blocks to the inverted output synthesizing section. , the first plate-like conductor and the second plate-like conductor are each formed with a notch.

Further, according to the present invention, in the above-described present invention, the notch is formed in the vicinity of the inverter block located in the intermediate part of the row of inverter blocks from the plurality of inverter blocks.

Further, according to the present invention, in the above-described present invention, the first plate-shaped conductor and the second plate-shaped conductor are formed to have substantially the same shape, and the first plate-shaped conductor and the second plate-shaped conductor The conductors are closely spaced.

Further, according to the present invention, in the above-described present invention, the first plate-shaped conductor and the second plate-shaped conductor are notched in the vicinity of the output portions of the inverter blocks located at both ends of the row of inverter blocks. is formed.

Since the present invention is configured as described above, in an inverter circuit in which a plurality of inverter blocks are connected in parallel, variations in current between each inverter block and each inverter block are suppressed, resulting in a more uniform current. This has the excellent effect of making it possible to perform synthesis.

FIG. 1 is a configuration explanatory diagram schematically showing the overall configuration of a conventional inverter device controlled by an inverter control section and connected to a load. FIG. 2 is a circuit configuration explanatory diagram schematically showing the configuration of a conventional inverter circuit that constitutes the inverter section. FIG. 3 is a circuit configuration explanatory diagram schematically showing the configuration of a conventional inverter circuit in which a plurality of inverter blocks are connected in parallel, and is a circuit configuration explanatory diagram of the configuration corresponding to FIG. Also, in FIG. 3, the shape illustrated by the dashed-dotted line indicates the conductor between the non-inverted output signal output portions that outputs the non-inverted output signal Q, and the shape illustrated by the two-dotted chain line indicates the inverted output signal that outputs the inverted output signal NQ. Inter-output conductors are shown. FIG. 4 is a circuit configuration explanatory diagram schematically showing the configuration of an inverter circuit according to an embodiment (first embodiment) of the present invention, and is a circuit configuration explanatory diagram of a configuration corresponding to FIG. is. Also, in FIG. 4, the shape illustrated with a one-dot chain line indicates a conductor between non-inverted output signal output portions that outputs a non-inverted output signal Q, and the shape illustrated with a two-dot chain line indicates an inverted output signal that outputs an inverted output signal NQ. Inter-output conductors are shown. FIG. 5 is a circuit configuration explanatory diagram schematically showing the configuration of an inverter circuit according to an embodiment (second embodiment) of the present invention, and is a circuit configuration explanatory diagram of a configuration corresponding to FIG. is. FIG. 6(a) is a circuit configuration explanatory diagram schematically showing a connection relation portion of the inverter circuit shown in FIG. FIG. 6(b) is a circuit configuration explanatory diagram schematically showing the connection relation part of the lower conductor, which is the conductor between the inverted output signal output sections, of the inverter circuit shown in FIG. FIG. 7 is a circuit configuration explanatory diagram schematically showing the configuration of an inverter circuit according to an embodiment (third embodiment) of the present invention, and is a circuit configuration explanatory diagram of a configuration corresponding to FIG. is. FIG. 8(a) is a circuit configuration explanatory diagram schematically showing the connection relation part of the upper conductor, which is the conductor between the non-inverted output signal output sections, of the inverter circuit shown in FIG. FIG. 8(b) is a schematic diagram of the circuit configuration of the inverter circuit shown in FIG. 7, showing the connection relationship between the lower conductors serving as the conductors between the inverted output signal output sections. FIG. 9 is a circuit configuration explanatory diagram schematically showing the configuration of an inverter circuit according to an embodiment (fourth embodiment) of the present invention, and is a circuit configuration explanatory diagram of a configuration corresponding to FIG. is. FIG. 10(a) is a circuit configuration explanatory diagram schematically showing the connection relation part of the upper conductor, which is the conductor between the non-inverted output signal output sections, of the inverter circuit shown in FIG. FIG. 10(b) is a circuit configuration explanatory diagram schematically showing the connection relation part of the lower conductor, which is the conductor between the inverted output signal output sections, of the inverter circuit shown in FIG. FIG. 11 is a circuit configuration explanatory diagram schematically showing the configuration of an inverter circuit according to an embodiment (fifth embodiment) of the present invention, and is a circuit configuration explanatory diagram of a configuration corresponding to FIG. is. FIG. 12(a) is a circuit configuration explanatory diagram schematically showing the connection relation part of the upper conductor, which is the conductor between the non-inverted output signal output sections, of the inverter circuit shown in FIG. FIG. 12(b) is a schematic diagram of the circuit configuration of the inverter circuit shown in FIG. 11, showing the connection relationship between the lower conductors serving as the conductors between the inverted output signal output sections.

An example of an embodiment of an inverter circuit according to the present invention will be described in detail below with reference to the accompanying drawings.

In addition, in the description of the following "Modes for Carrying Out the Invention" section, the configuration and operation described above with reference to FIGS. 1 to 3 or FIG. 4 and subsequent figures are assigned to the same or corresponding configurations and actions, and detailed descriptions of the configurations and actions will be provided. omitted.

(I) First embodiment

First, an inverter circuit according to the first embodiment of the present invention will be described with reference to FIG.

Here, FIG. 4 is a circuit configuration explanatory diagram schematically showing the configuration of the inverter circuit according to one example of the embodiment (first embodiment) of the present invention, which corresponds to the configuration shown in FIG. A circuit configuration explanatory diagram is shown. Also, in FIG. 4, the shape illustrated with a one-dot chain line indicates a conductor between non-inverted output signal output portions that outputs a non-inverted output signal Q, and the shape illustrated with a two-dot chain line indicates an inverted output signal that outputs an inverted output signal NQ. Inter-output conductors are shown.

The inverter circuit 10 according to the first embodiment shown in FIG. 4 differs from the inverter circuit of the conventional inverter section 106 described above in that the configuration of the conductors between the output sections is different.

That is, in the inverter circuit of the conventional inverter section 106 described above, the non-inverted output synthesis section copper plate which is a rectangular straight plate-like body extending in the Y direction and arranged with a parallel shift in the X direction. 304 and the inverted output synthesizing section copper plate 306, a first non-inverted output connection copper plate 308, a first inverted output connection copper plate 308, each of which is a rectangular straight plate-like body extending in the X direction and arranged with a shift parallel to the Y direction. The output connection copper plate 310, the second non-inverted output connection copper plate 312, the second inverted output connection copper plate 314, the third non-inverted output connection copper plate 314, and the third inverted output connection copper plate 316 are arranged in a positional relationship such that they are orthogonal to each other. The connection constitutes an inter-output conductor, which is a conductor that connects the output section to the output synthesizing section in each inverter block.

On the other hand, in the inverter circuit 10 according to the first embodiment shown in FIG. Inter-output conductors in the inverter block are configured in a straight line shape or a bent line graph shape.

More specifically, the first non-inverted output signal inter-output section conductor 12 connecting the first non-inverted output signal output terminal 302A-1-1 of the first inverter block 302A and the non-inverted output signal synthesizing terminal 106a is a straight line. formed into a shape.

Further, the conductor 14 between the first inverted output signal output section connecting the first inverted output signal output terminal 302A-2-2 of the first inverter block 302A and the inverted output signal synthesizing terminal 106b has two bent portions 14a, 14b is formed in a line graph shape.

Here, the first non-inverted output signal inter-output conductor 12 and the first inverted output signal inter-output conductor 14 are formed in a straight line shape and a broken line graph shape, respectively, so that their effective lengths are substantially equal. is configured as

The effective length of the conductor 12 between the first non-inverted output signal output section and the conductor 14 between the first inverted output signal output section is collectively referred to as the first effective length.

Further, the first inter-non-inverted output signal output conductor 12 and the first inverted output signal inter-output conductor 14 are arranged substantially parallel and close to each other so that the first non-inverted output signal inter-output conductor 12 and the first inter-inverted output signal output conductor 14 are arranged in close proximity to each other. The interval (interval in the XY directions) W1 between the 1-inverted output signal output portion inter-conductor 14 is narrowed.

Specifically, the first non-inverted output signal inter-output conductor 12 and the first inverted output signal inter-output conductor 14, which are the inter-output conductors of the first inverter block 302A, are the same as those of the adjacent second inverter block 302B. Compared to the inductance between the output section conductors (second non-inverted output signal output section conductor 16 and second inverted output signal output section conductor 18), the inductance is, for example, 1/3 or less, It is preferable to arrange them in parallel and close to each other so that the distance W1 is narrow.

Next, the second non-inverted output signal inter-output section conductor 16 connecting the second non-inverted output signal output terminal 302B-1-1 of the second inverter block 302B and the non-inverted output signal synthesizing terminal 106a is provided at two locations. It is formed in a line graph shape with bent portions 16a and 16b.

Further, the conductor 18 between the second inverted output signal output section connecting the second inverted output signal output terminal 302B-2-2 of the second inverter block 302B and the inverted output signal synthesizing terminal 106b has four bent portions 18a, It is formed in a line graph shape with 18b, 18c and 18d.

Here, the conductor 16 between the second non-inverted output signal output section and the conductor 18 between the second inverted output signal output section have a polygonal line graph shape with two bends and a polygonal line with four bends, respectively. By forming them into graph shapes, they are configured so that their effective lengths are substantially equal.

The effective lengths of the conductor 16 between the second non-inverted output signal output section and the conductor 18 between the second inverted output signal output section are collectively referred to as the second effective length.

Here, the above-described second effective length is set to be approximately equal to the above-described first effective length.

In addition, the conductor 16 between the second non-inverted output signal output section and the conductor 18 between the second inverted output signal output section are arranged substantially parallel and close to each other so that the conductor 16 between the second non-inverted output signal output section and the second conductor 18 between the non-inverted output signal output section The interval (interval in the XY direction) W2 between the two-inverted output signal output section conductor 18 is narrowed.

Specifically, the second non-inverted output signal inter-output conductor 16 and the second inverted output signal inter-output conductor 18, which are the inter-output conductors of the second inverter block 302B, are the same as those of the adjacent third inverter block 302C. Compared to the inductance between the conductors between the output sections (the third conductor between the non-inverted output signal output section 20 and the third conductor between the inverted output signal output section 22), the inductance is, for example, ⅓ or less, It is preferable to arrange them in parallel and close to each other so that the distance W2 is narrow.

Further, in the second inverter block 302B, the second non-inverted output signal inter-output conductor 16 and the first inverted output signal inter-output conductor 14 are arranged at a wide distance G1.

Here, the distance G1 is such that the inductance between the first inverter block 302A and the second inverter block 302B is equal to the conductor 16 between the second non-inverted output signal output section and the second inverted output signal output section of the second inverter block 302B. It is preferable to set a wide interval such that the inductance is, for example, three times or more the inductance between the intermediate conductors 18 .

Next, the third non-inverted output signal inter-output section conductor 20 connecting the third non-inverted output signal output terminal 302C-1-1 of the third inverter block 302C and the non-inverted output signal synthesizing terminal 106a has three It is formed in a line graph shape with bent portions 20a, 20b, and 20c.

Further, the conductor 22 between the third inverted output signal output section connecting the third inverted output signal output terminal 302C-2-2 of the third inverter block 302C and the inverted output signal synthesizing terminal 106b has four bent portions 22a, It is formed in a line graph shape with 22b, 22c and 22d.

Here, the third inter-non-inverted output signal output section conductor 20 and the third inter-inverted output signal output section conductor 22 are formed in a polygonal line graph shape with three bends and a polygonal line with four bends, respectively. By forming them into graph shapes, they are configured so that their effective lengths are substantially equal.

The effective lengths of the third inter-non-inverted output signal output conductor 20 and the third inter-inverted output signal output conductor 22 are collectively referred to as the third effective length.

Here, the above-described third effective length is set to be approximately equal to the above-described first and second effective lengths.

Further, the third inter-non-inverted output signal output section conductor 20 and the third inter-inverted output signal output section conductor 22 are arranged substantially parallel and close to each other so that the third inter-non-inverted output signal output section conductor 20 and the third inter-inverted output signal output section conductor 20 The interval (interval in the XY direction) W3 between the 3-inverted output signal output section conductor 22 is narrowed.

Specifically, the third non-inverted output signal inter-output conductor 20 and the third inverted output signal inter-output conductor 22, which are the inter-output conductors of the third inverter block 302C, are the same as those of the adjacent fourth inverter block 302D. Compared to the inductance between the conductors between the output sections (the fourth conductor between the non-inverted output signal output sections 24 and the fourth conductor between the inverted output signal output sections 26), for example, so that the inductance is ⅓ or less, It is preferable to arrange them in parallel and close to each other so that the distance W3 is narrow.

Further, in the third inverter block 302C, the third non-inverted output signal inter-output conductor 20 and the second inverting conductor 20 are arranged so that a pseudo inverter is not formed under the influence of the inductance of the inter-output conductor of the second inverter block 302B. It is arranged with a distance G2 as a wide gap from the conductor 18 between the output signal output portions.

Here, the distance G2 is such that the inductance between the second inverter block 302B and the third inverter block 302C is equal to the distance between the conductor 20 between the third non-inverted output signal output section and the third inverted output signal output section of the third inverter block 302C. It is preferable to set a wide interval such that the inductance is, for example, three times or more the inductance between the intermediate conductors 22 .

Next, the conductor 24 between the fourth non-inverted output signal output section connecting the fourth non-inverted output signal output terminal 302D-1-1 of the fourth inverter block 302D and the non-inverted output signal synthesizing terminal 106a has three It is formed in a line graph shape with bent portions 24a, 24b, and 24c.

Further, the conductor 26 between the fourth inverted output signal output section connecting the fourth inverted output signal output terminal 302D-2-2 of the fourth inverter block 302D and the inverted output signal synthesizing terminal 106b has five bent portions 26a, It is formed in a line graph shape with 26b, 26c, 26d and 26e.

Here, the fourth inter-non-inverted output signal output portion conductor 24 and the fourth inter-inverted output signal output portion conductor 26 are formed in a polygonal line graph shape with three bends and a polygonal line with five bends, respectively. By forming them into graph shapes, they are configured so that their effective lengths are substantially equal.

The effective lengths of the fourth inter-non-inverted output signal output section conductor 24 and the fourth inter-inverted output signal output section conductor 26 are collectively referred to as the fourth effective length.

Here, the above-described fourth effective length is set to be substantially equal to the above-described first effective length, second effective length and third effective length.

In addition, the fourth inter-non-inverted output signal output section conductor 24 and the fourth inter-inverted output signal output section conductor 26 are arranged substantially parallel and close to each other so that the fourth inter-inverted output signal output section conductor 24 and the third inter-inverted output signal output section conductor 24 are arranged in close proximity. The interval (interval in the XY directions) W4 between the conductor 26 between the inverted output signal output portions is narrowed.

Specifically, the fourth non-inverted output signal inter-output conductor 24 and the fourth inverted output signal inter-output conductor 26, which are the inter-output conductors of the fourth inverter block 302D, are connected to the adjacent fifth inverter block 302E. Compared to the inductance between the output section conductors (fifth non-inverted output signal output section conductor 28 and fifth inverted output signal output section conductor 30), for example, so that the inductance is ⅓ or less, It is preferable to arrange them in parallel and close to each other so that the distance W4 is narrow.

Furthermore, in the fourth inverter block 302D, the fourth non-inverted output signal inter-output conductor 24 and the third inverting conductor 24 are arranged so that a pseudo inverter is not formed under the influence of the inductance of the inter-output conductor of the third inverter block 302C. It is arranged with a distance G3 as a wide interval from the conductor 22 between the output signal output portions.

Here, the distance G3 is such that the inductance between the third inverter block 302C and the fourth inverter block 302D is equal to the conductor 24 between the fourth non-inverted output signal output section and the fourth inverted output signal output section of the fourth inverter block 302D. It is preferable to set a wide interval such that the inductance is, for example, three times or more the inductance between the intermediate conductors 28 .

Next, the fifth non-inverted output signal inter-output conductor 28 connecting the fifth non-inverted output signal output terminal 302E-1-1 of the fifth inverter block 302E and the non-inverted output signal synthesizing terminal 106a has three It is formed in a line graph shape with bent portions 28a, 28b, and 28c.

In addition, the fifth inverted output signal inter-output section conductor 30 connecting the fifth inverted output signal output terminal 302E-2-2 of the fifth inverter block 302E and the inverted output signal synthesizing terminal 106b has one bent portion 30a. It is formed in a line graph shape.

Here, the fifth inter-non-inverted output signal output section conductor 28 and the fifth inter-inverted output signal output section conductor 30 are in the form of a line graph with three bends and a line graph with one bend. By forming them into graph shapes, they are configured so that their effective lengths are substantially equal.

The effective lengths of the fifth inter-non-inverted output signal output conductor 28 and the fifth inter-inverted output signal output conductor 30 are collectively referred to as the fifth effective length.

Here, the above-described fifth effective length is set to be substantially equal to the above-described first effective length, second effective length, third effective length, and fourth effective length.

Further, the fifth inter-non-inverted output signal output section conductor 28 and the fifth inter-inverted output signal output section conductor 30 are arranged substantially parallel and close to each other, and the fifth inter-inverted output signal output section conductor 28 and the fifth inter-inverted output signal output section conductor 28 are arranged in close proximity. The interval (interval in the XY directions) W5 between the conductor 30 between the inverted output signal output portions is narrowed.

Specifically, the fifth non-inverted output signal inter-output conductor 28 and the fifth inverted output signal inter-output conductor 30, which are the inter-output conductors of the fifth inverter block 302E, are connected to the adjacent fourth inverter block 302D. Compared to the inductance between the conductors between the output sections (the fourth conductor between the non-inverted output signal output sections 24 and the fourth conductor between the inverted output signal output sections 26), for example, so that the inductance is ⅓ or less, It is preferable to arrange them in parallel and close to each other so that the distance W5 is narrow.

Furthermore, in the fifth inverter block 302E, the fifth non-inverted output signal inter-output conductor 28 and the fourth inverting conductor 28 are arranged so that a pseudo inverter is not formed under the influence of the inductance of the inter-output conductor of the fourth inverter block 302D. It is arranged with a distance G4 as a wide interval from the conductor 26 between the output signal output portions.

Here, the distance G4 is such that the inductance between the fourth inverter block 302D and the fifth inverter block 302E is equal to the conductor 28 between the fifth non-inverted output signal output section and the fifth inverted output signal output section of the fifth inverter block 302E. It is preferable to set a wide interval such that the inductance is, for example, three times or more the inductance between the intermediate conductors 30 .

Further, as described above, in the inverter circuit 10, for each inverter block, the effective length of the conductor between the non-inverted output signal output portions and the effective length of the conductor between the inverted output signal output portions are substantially equal. is formed in

Specifically, the first inverter block 302A is formed such that the effective length of the conductor 12 between the first non-inverted output signal output section and the effective length of the conductor 14 between the first inverted output signal output section are substantially equal, The second inverter block 302B is formed so that the effective length of the conductor 16 between the second non-inverted output signal output section and the effective length of the conductor 18 between the second inverted output signal output section are substantially equal, and the third inverter block 302C is formed. is formed so that the effective length of the conductor 20 between the third non-inverted output signal output section and the effective length of the conductor 22 between the third inverted output signal output section are substantially equal. The effective length of the conductor 24 between the inverted output signal output section and the effective length of the conductor 26 between the fourth inverted output signal output section are formed to be substantially equal. The effective length of the intermediate conductor 28 and the effective length of the fifth inverted output signal output portion intermediate conductor 30 are formed to be substantially equal.

Here, when forming the effective length of the conductor between the non-inverted output signal output portions and the effective length of the conductor between the inverted output signal output portions to be substantially equal, for example, the effective length of the conductor between the non-inverted output signal output portions and the effective length of the conductor between the non-inverted output signal output portions The difference between the effective length of the conductor between the output signal output parts is within 30% of the average value of the effective length of the conductor between the non-inverted output signal output part and the effective length of the conductor between the inverted output signal output part. preferably formed.

Specifically, assuming that the effective length of the conductor between the non-inverted output signal output portions is "α" and the effective length of the conductor between the inverted output signal output portions is "β", "(α+β)÷2×0.3≧ It is preferable that the effective length of the conductor between the non-inverted output signal output portions and the effective length of the conductor between the inverted output signal output portions are substantially equal so that |α−β|

As described above, in the inverter circuit 10, each inverter block of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E The effective length of the conductor between the non-inverted output signal output portions and the effective length of the conductor between the inverted output signal output portions are set substantially equal.

Therefore, in the inverter circuit 10, between the non-inverted output signal output portions of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E. The inductances of the conductors and the conductors between the inverted output signal output sections are aligned, so that the influence of the inductances in each inverter block is suppressed.

In the inverter circuit 10, the effective length of each of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E, that is, the first effective length The length, the second effective length, the third effective length, the fourth effective length and the fifth effective length are set substantially equal.

Therefore, in the inverter circuit 10, the inductance is uniform among the inverter blocks of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E. , the influence of the inductance between the inverter blocks is suppressed.

Furthermore, in the inverter circuit 10, for each of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E, the interval between adjacent inverter blocks is Inter-output conductors are formed at wide intervals of distance G1, distance G2, distance G3 and distance G4.

Therefore, in the inverter circuit 10, for each of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E, the inverter blocks adjacent to each other The influence of the inductance is suppressed, the influence is not received, and a pseudo inverter is not formed.

Furthermore, in the inverter circuit 10, the respective non-inverted output signals of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E are The inter-output conductors and the inter-inverted output signal output conductors are arranged substantially parallel and close to each other, and the distance between the respective non-inverted output signal inter-output conductors and the inverted output signal inter-output conductors W1, spacing W2, spacing W3, spacing W4 and spacing W5 are narrowly set.

Therefore, in the inverter circuit 10, the inductance is reduced in each of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E. , and the influence of the inductance in each inverter block is suppressed.

Therefore, according to the inverter circuit 10, each of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E and between the inverter blocks Current variations are suppressed, and current synthesis can be performed using more uniform currents.

As a result, the output currents of the switching semiconductor elements forming the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E in the inverter circuit 10 are made uniform. Since the number of semiconductor elements constituting the inverter circuit 10 can be reduced, the size of the entire device can be reduced and the cost can be reduced.

(II) Second embodiment

Next, an inverter circuit according to a second embodiment of the present invention will be described with reference to FIGS. 5 and 6(a) and (b).

Here, FIG. 5 is a circuit configuration explanatory diagram schematically showing the configuration of an inverter circuit according to an example of the embodiment (second embodiment) of the present invention, which corresponds to the configuration shown in FIG. A circuit configuration explanatory diagram is shown.

Further, FIG. 6(a) shows a schematic diagram of the circuit configuration of the inverter circuit shown in FIG. 5, extracting and schematically showing the connection relation portion related to the upper conductor, which is the conductor between the non-inverted output signal output portions. there is Further, FIG. 6(b) shows a schematic diagram of the circuit configuration of the inverter circuit shown in FIG. 5 by extracting and schematically showing the connection relationship between the lower conductors serving as the conductors between the inverted output signal output sections. there is

The inverter circuit 40 according to the second embodiment shown in FIGS. They are different in that they are different.

That is, in the inverter circuit 10 according to the first embodiment, the outputs of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E are Inter-section conductors are configured in a linear shape or a bent line graph shape.

On the other hand, in the inverter circuit 40 according to the second embodiment shown in FIGS. The conductors between the non-inverted output signal output sections that conduct the non-inverted output signals Q output from 302D are each formed of a thin plate-shaped copper plate, which is a plate-shaped conductor. A conductor between the inverted output signal output portions that conducts the inverted output signal NQ output from the block 302B, the third inverter block 302C, and the fourth inverter block 302D is formed of a sheet-shaped copper plate, which is a sheet-shaped conductor. .

Here, in the inverter circuit 40, the thin plate-shaped copper plate, which is a single plate-shaped conductor, which is a conductor between the non-inverted output signal output sections that output the non-inverted output signal Q, outputs the inverted output signal NQ. The non-inverted output that outputs the non-inverted output signal Q is located above the thin plate-shaped copper plate, which is a plate-shaped conductor that is a conductor between the output parts, in the Z-axis direction. A thin plate-shaped copper plate that is a plate-shaped conductor that is a conductor between signal output sections is referred to as an upper conductor 42, and a plate-shaped conductor that is a conductor between the inverted output signal output sections that outputs the inverted output signal NQ. One sheet-like copper plate is referred to as the lower conductor 44 .

First, the upper conductor 42 will be described with reference to FIG. 6(a). The upper conductor 42 has a substantially trapezoidal shape extending in the Y direction. Of the bases that are two parallel opposite sides extending in the Y direction in the substantially trapezoidal shape, the shorter base (short base) 42a is located on the right side in the X direction, and the longer base (long base) 42b is located on the right side in the X direction. It is located on the left side in the X direction.

A rectangular elongated hole 42c extending along the Y-axis direction is bored in the substantially central portion of the upper conductor 42 .

More specifically, the elongated hole 42c is formed in the first inverter block 302A located at both ends of the inverter block row consisting of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C and the fourth inverter block 302D. and the fourth inverter block 302D.

A short base projection 42d is formed at substantially the center of the short base 42a of the upper conductor 42 in the Y-axis direction. is formed.

On the other hand, on the long base 42b of the upper conductor 42, a first non-inverted output signal output terminal 302A-1-1, a second non-inverted output signal output terminal 302B-1-1, a third non-inverted output signal output terminal 302C- A first protrusion 42e, a second protrusion 42f, a third protrusion 42g and a fourth protrusion 42h are formed at positions corresponding to the output terminals 302D-1-1 and 302D-1-1, respectively. ing.

The first protrusion 42e is connected to the first non-inverted output signal output terminal 302A-1-1, and the second protrusion 42f is connected to the second non-inverted output signal output terminal 302B-1-1. Also, the third protrusion 42g and the third non-inverted output signal output terminal 302C-1-1 are connected, and the fourth protrusion 42h and the fourth non-inverted output signal output terminal 302D-1-1 are connected. is connected.

Next, the lower conductor 44 will be described with reference to FIG. 6(b). The lower conductor 44 has substantially the same shape as the upper conductor 42, and has a substantially trapezoidal shape extending in the Y direction. On the paper surface of FIG. 6 (XY plane), the short base (short base) 44a of the bases that are two parallel opposite sides extending in the Y direction in the substantially trapezoidal shape is on the right side in the X direction. The longer base (long base) 44b is positioned on the left side in the X direction.

A rectangular long hole 44c extending along the Y-axis direction is bored in the substantially central portion of the lower conductor 44. As shown in FIG.

More specifically, the elongated hole 44c is formed in the first inverter block 302A positioned at both ends of the inverter block row consisting of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, and the fourth inverter block 302D. and the fourth inverter block 302D.

A short base projection 44d is formed at substantially the center of the short base 42a of the lower conductor 44 in the Y-axis direction. formed.

On the other hand, on the long base 44b of the lower conductor 44, a first inverted output signal output terminal 302A-2-2, a second inverted output signal output terminal 302B-2-2, and a third inverted output signal output terminal 302C-2- 2 and the fourth inverted output signal output terminal 302D-2-2, a first protrusion 44e, a second protrusion 44f, a third protrusion 44g and a fourth protrusion 44h are formed.

The first projecting portion 44e and the first inverted output signal output terminal 302A-2-2 are connected, and the second projecting portion 44f and the second inverted output signal output terminal 302B-2-2 are connected, Also, the third protrusion 44g and the third inverted output signal output terminal 302C-2-2 are connected, and the fourth protrusion 44h and the fourth inverted output signal output terminal 302D-2-2 are connected. there is

When the upper conductor 42 and the lower conductor 44 are connected to the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, and the fourth inverter block 302D in the connection relationship described above, FIG. As shown, the upper conductor 42 and the lower conductor 44 are arranged so as to overlap substantially vertically in the Z-axis direction.

In addition, the upper conductor 42 and the lower conductor 44 are set to be arranged close to each other, and the interval (distance in the Z-axis direction) between the upper conductor 42 and the lower conductor 44 is narrowed. are placed.

Here, the elongated holes 42c and 44c correspond to the inverted output signal output terminal of the inverter block positioned at one end of the inverter block row and the non-inverted output terminal of the inverter block positioned at the one end and the adjacent inverter block. The non-inverted output signal output terminal of the inverter block located at the other end of the inverter block row and the inverted output signal of the inverter block located at the other end of the inverter block row from approximately the middle position between the output signal output terminals. It is preferable to form so as to extend to a substantially intermediate position between the output terminals.

Specifically, in this inverter circuit 40, the long holes 42c and 44c are connected to the first inverted output signal output terminal 302A-2-2 of the first inverter block 302A located at one end of the inverter block row. and the second non-inverted output signal output terminal 302B-1-1 of the second inverter block 302B adjacent to the first inverter block 302A. Between the fourth non-inverted output signal output terminal 302D-1-1 of the fourth inverter block 302D and the third inverted output signal output terminal 302C-2-2 of the third inverter block 302C adjacent to the fourth inverter block 302D It is formed so as to extend to a substantially intermediate position.

In the above configuration, the second inverter block 302B and the third inverter block 302C are sandwiched between the first inverter block 302A located in the uppermost stage and the fourth inverter block 302D located in the lowermost stage in the Y-axis direction. is closer to the non-inverted output signal synthesizing terminal 106a and the inverted output signal synthesizing terminal 106b in the XY plane than the first inverter block 302A and the fourth inverter block 302D.

Here, in the inverter circuit 40, the upper conductor 42 and the lower conductor 44 are formed in substantially the same trapezoidal shape, and elongated holes 42c and 44c extending in the Y-axis direction are formed in each of them. It is

Therefore, the non-inverted output signal Q output from the second inverter block 302B and the third inverter block 302C circumvents the elongated hole 42 and bends around due to the presence of the elongated hole 42c in the upper conductor 42. It will be output to the inverted output signal synthesizing terminal 106a (see FIG. 6(a)).

On the other hand, the non-inverted output signal Q output from the first inverter block 302A and the fourth inverter block 302D is not affected by the elongated hole 42c of the upper conductor 42, and the non-inverted output signal Q is almost straight without detouring. It will be output to the signal synthesizing terminal 106a (see FIG. 6(a)).

Therefore, in the inverter circuit 40, the non-inverted output signal Q that is output from the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, and the fourth inverter block 302D and conducts the upper conductor 42 is effective. All the lengths are substantially equal, and the inductances are uniform, so that the influence of the inductances between the inverter blocks is suppressed.

Similarly, the inverted output signal NQ that is output from the second inverter block 302B and the third inverter block 302C circumvents the elongated hole 44c due to the existence of the elongated hole 44c on the lower side conductor 44 while curving. It will be output to the inverted output signal synthesizing terminal 106b (see FIG. 6(b)).

On the other hand, the inverted output signal NQ output from the first inverter block 302A and the fourth inverter block 302D is not affected by the elongated hole 44c of the lower conductor 44, and the inverted output signal NQ is almost linear without detouring. It will be output to the combining terminal 106b (see FIG. 6(b)).

Therefore, in the inverter circuit 40, the inverted output signal NQ that is output from the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, and the fourth inverter block 302D and that conducts the lower conductor 44 is effective. All the lengths are substantially equal, and the inductances are uniform, so that the influence of the inductances between the inverter blocks is suppressed.

In addition, since the upper conductor 42 and the lower conductor 44 are formed to have substantially the same shape, the effective length of the upper conductor 42 and the effective length of the lower conductor 44 are substantially equal, and the inductance of each inverter block is are aligned, the influence of the inductance in each inverter block is suppressed.

Furthermore, the upper conductor 42 and the lower conductor 44 are arranged close to each other, and the interval (distance in the Z-axis direction) between the upper conductor 42 and the lower conductor 44 is narrowed. A reduction in inductance is achieved, and the influence of inductance in each inverter block is suppressed.

Therefore, according to the inverter circuit 40, the current variation between each of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, and the fourth inverter block 302D and between the inverter blocks is suppressed. It becomes possible to combine currents with more uniform currents.

(III) Third Embodiment

Next, an inverter circuit according to a third embodiment of the present invention will be described with reference to FIGS. 7 and 8(a)(b).

Here, FIG. 7 is a circuit configuration explanatory diagram schematically showing the configuration of an inverter circuit according to an example of the embodiment (third embodiment) of the present invention, which corresponds to the configuration shown in FIG. A circuit configuration explanatory diagram is shown.

Further, FIG. 8(a) shows a schematic diagram of the circuit configuration of the inverter circuit shown in FIG. 7 by extracting and schematically showing the connection relation portion related to the upper conductor, which is the conductor between the non-inverted output signal output portions. there is Further, FIG. 8(b) shows a schematic diagram of the circuit configuration of the inverter circuit shown in FIG. 7 by extracting and schematically showing the connection relation portion related to the lower conductor serving as the conductor between the inverted output signal output portions. there is

When the inverter circuit 50 according to the third embodiment shown in FIGS. 7 to 8A and 8B is compared with the inverter circuit 40 according to the second embodiment described above, the output section is as follows. Both are different in that the structure of the intermediate conductor is different.

That is, in the inverter circuit 40 according to the second embodiment, the upper conductor 42 is formed with one elongated hole 42c and the lower conductor 44 is formed with one elongated hole 44c. On the other hand, in the inverter circuit 50 according to the third embodiment, the upper conductor 52 is formed with three rectangular notches 52a, 52b, 52c instead of the long hole 42c, and the upper conductor 52 is substantially the same as the upper conductor 52. Both are different only in that the lower conductor 54 having a rectangular shape has three rectangular cutouts 54a, 54b, 54c instead of the elongated hole 44c.

Here, the three notches 52a, 52b, and 52c in the upper conductor 52 and the three rectangular notches 54a, 54b, and 54c in the lower conductor 54 are the first inverter block 302A and the second inverter block 302A. 302B, a third inverter block 302C, a fourth inverter block 302D and a fifth inverter block 302E. In the vicinity of the second inverter block 302B, the third inverter block 302C, and the fourth inverter block 302D, they are formed at positions overlapping each other on the XY plane when viewed along the Z-axis direction.

Reference numeral 42i denotes a fifth protrusion of the upper conductor 52 connected to the fifth non-inverted output signal output terminal 304E-1-1, and reference numeral 44i denotes the fifth inverted output signal output terminal 304E-2. -2 is the fifth protrusion of the lower conductor 54 that is connected.

In the above configuration, the cutouts 52a, 52b, 52c of the upper conductor 52 act in the same manner as one elongated hole 42c of the upper conductor 42, and the second inverter block 302B, the third inverter block 302C and the fourth inverter block 302B Due to the existence of the cutouts 52a, 52b, 52c of the upper conductor 52, the non-inverted output signal Q from each inverter block of the block 302D makes a large turn while curving around the cutouts 52a, 52b, 52c. It will be output to the output signal synthesizing terminal 106a (see FIG. 8(a)).

On the other hand, the non-inverted output signals Q from the first inverter block 302B and the fifth inverter block 302E are not affected by the cutouts 52a, 52b, 52c of the upper conductor 52, and are non-inverted substantially linearly without detours. It will be output to the inverted output signal synthesizing terminal 106a (see FIG. 8(a)).

For this reason, in the inverter circuit 50, the non-inductive currents output from the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E, and the upper conductors 52 are electrically connected. The effective lengths of the inverted output signals Q are all substantially equal and the inductances are aligned, thereby suppressing the influence of the inductances between the inverter blocks.

Similarly, the notches 54a, 54b, 54c in the lower conductors 54 act similarly to the single slot 44c in the lower conductors 44 to provide the second inverter block 302B, the third inverter block 302C and the fourth inverter block 302B. Due to the presence of the cutouts 54a, 54b, and 54c of the lower conductor 54, the inverted output signal NQ from each inverter block of the block 302D makes a round trip while curving around the cutouts 54a, 54b, and 54c. It will be output to the signal synthesizing terminal 106b (see FIG. 8(b)).

On the other hand, the inverted output signals NQ from the first inverter block 302B and the fifth inverter block 302E are almost linearly inverted without detours, without being affected by the cutouts 54a, 54b, 54c of the lower conductor 54. It will be output to the output signal synthesizing terminal 106b (see FIG. 8(a)).

Therefore, in the inverter circuit 50, the signals are output from the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E, and the lower conductors 54 are made conductive. The effective lengths of the inverted output signals NQ are all substantially equal, and the inductances are aligned, thereby suppressing the influence of the inductances between the inverter blocks.

In addition, since the upper conductor 52 and the lower conductor 54 are formed in substantially the same shape, the effective length of the upper conductor 52 and the effective length of the lower conductor 54 are substantially equal, and the inductance of each inverter block is are aligned, the influence of the inductance in each inverter block is suppressed.

Furthermore, the upper conductor 52 and the lower conductor 54 are arranged close to each other, and the interval (distance in the Z-axis direction) between the upper conductor 52 and the lower conductor 54 is narrowed. A reduction in inductance is achieved, and the influence of inductance in each inverter block is suppressed.

Therefore, according to the inverter circuit 50, each of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E and between the inverter blocks Current variations are suppressed, and current synthesis can be performed using more uniform currents.

(IV) Fourth embodiment

Next, an inverter circuit according to a fourth embodiment of the present invention will be described with reference to FIGS. 9 and 10(a)(b).

Here, FIG. 9 is a circuit configuration explanatory diagram schematically showing the configuration of an inverter circuit according to an example of the embodiment (fourth embodiment) of the present invention, which corresponds to the configuration shown in FIG. A circuit configuration explanatory diagram is shown.

Further, FIG. 10(a) shows a schematic diagram of the circuit configuration of the inverter circuit shown in FIG. 9 by extracting and schematically showing the connection relation portion related to the upper conductor, which is the conductor between the non-inverted output signal output portions. there is Further, FIG. 10(b) shows a schematic diagram of the circuit configuration of the inverter circuit shown in FIG. 9 by extracting and schematically showing the connection relation portion of the lower conductor serving as the conductor between the inverted output signal output portions. there is

Compared with the inverter circuit 40 according to the second embodiment described above, the inverter circuit 60 according to the fourth embodiment shown in FIGS. The only difference is that the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E are arranged in different positions.

For each of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E, for example, as shown in the inverter circuit 60, the inverter blocks are arranged diagonally in the XY plane. It may be arranged, and the arrangement position is not particularly limited.

That is, the positions of the first inverter block 302A, the second inverter block 302B, the third inverter block 302C, the fourth inverter block 302D, and the fifth inverter block 302E are not subject to any particular restrictions. The size of the entire apparatus may be reduced by arranging it at an appropriate position according to design conditions.

(V) Fifth embodiment

Next, an inverter circuit according to a fifth embodiment of the present invention will be described with reference to FIGS. 11 and 12(a) and (b).

Here, FIG. 11 is a circuit configuration explanatory diagram schematically showing the configuration of an inverter circuit according to an example of the embodiment (fifth embodiment) of the present invention, which corresponds to the configuration shown in FIG. A circuit configuration explanatory diagram is shown.

Further, FIG. 12(a) shows a schematic diagram of the circuit configuration of the inverter circuit shown in FIG. 11, extracting and schematically showing the connection relation portion related to the upper conductor, which is the conductor between the non-inverted output signal output portions. there is Further, FIG. 12(b) shows a schematic diagram of the circuit configuration of the inverter circuit shown in FIG. 11, extracting and schematically showing the connection relation portion related to the lower conductor serving as the conductor between the inverted output signal output portions. .

In the inverter circuit 70 according to the fifth embodiment shown in FIGS. 11 to 12(a) and (b), the long base of the upper conductor 72 is larger than that of the inverter circuit 40 according to the second embodiment described above. The only difference is that substantially triangular cutouts 72a and 72b are formed in 42b, and substantially triangular cutouts 74a and 74b are formed in the long base 44b of the lower conductor 74. FIG.

More specifically, on the long bottom side 42b of the upper conductor 72 in the inverter circuit 70, there is a gap between the first protrusion 42e located at the uppermost stage and the second protrusion 42f adjacent to the first protrusion 42e. A position adjacent to the first protrusion 42e, that is, a first inverter block row positioned at one end of an inverter block row composed of a first inverter block 302A, a second inverter block 302B, a third inverter block 302C, and a fourth inverter block 302D. A notch 72a is formed at a position adjacent to the first non-inverted output signal output terminal 302A-1-1 of the inverter block 302A. The fourth non-inverted output signal of the fourth inverter block 302D located between the matching third projections 42g and adjacent to the fourth projections 42h, that is, the other end of the inverter block row. A notch 72b is formed adjacent to the output terminal 302D-1-1.

Similarly, on the long base 44b of the lower conductor 74 in the inverter circuit 70, between the first protrusion 44e positioned at the uppermost stage and the second protrusion 44f adjacent to the first protrusion 44e, A notch 74a is located adjacent to the first protrusion 44e, that is, adjacent to the first inverted output signal output terminal 302A-2-2 of the first inverter block 302A located at one end of the inverter block row. is formed, and a position adjacent to the fourth protrusion 44h between the fourth protrusion 44h located at the bottom and the third protrusion 44g adjacent to the fourth protrusion 44h, that is, A notch 74b is formed at a position adjacent to the fourth inverted output signal output terminal 302D-2-2 of the fourth inverter block 302D located at the other end of the inverter block row.

In the inverter circuit 70, notches 72a and 72b of the upper conductor 72 and notches 74a and 74b of the lower conductor 74 are provided so that the first inverter block 304A positioned at the top and the fourth inverter block 304A positioned at the bottom are arranged. For each inverter block 304D, the inductance between the adjacent inverter blocks (first inverter block 304A and adjacent second inverter block 304B, fourth inverter block 304D and adjacent third inverter block 304C) is increased to achieve current balance. can be improved.

(VI) Description of other embodiments and modifications

It should be noted that the above-described embodiment is merely an example, and the present invention can be implemented in various other forms. That is, the present invention is not limited to the above-described embodiments, and various omissions, replacements, and modifications can be made without departing from the scope of the present invention.

For example, the above embodiment may be modified as shown in (VI-1) to (VI-11) below.

(V1-1) In each of the above-described embodiments, one sheet of thin copper plate serving as a conductor between non-inverted output signal output sections for outputting the non-inverted output signal Q is referred to as upper conductors 42, 52, and 72; , and one sheet of thin copper plate, which is a conductor between the inverted output signal output sections for outputting the inverted output signal NQ, is used as the lower conductors 44, 54, and 74, but the vertical relationship of these is for the sake of convenience in simplifying the explanation. It goes without saying that the vertical relationship between the two may be reversed.

(V1-2) In each of the above-described embodiments, the number of inverter blocks is 4 and 5, but the number of inverter blocks is of course not limited to these. . The present invention can be applied to an inverter circuit comprising a plurality of inverter blocks of 2 or more, more preferably 3 or more.

(V1-3) In the above-described first embodiment, the conductors between the output sections are formed in a straight line shape or a bent line graph shape, but it is of course not limited to these, and the output section The intermediate conductor may be configured in a curvilinear shape.

(V1-4) In each of the above-described embodiments, detailed descriptions of the width, thickness, material, etc. of each output conductor are omitted, but the width, thickness, material, etc. are for each output conductor. It is preferable to make them the same.

(V1-5) In the second embodiment described above, the upper conductor 42 is provided with one elongated hole 42c and the lower conductor 44 is provided with one elongated hole 44c. Of course, the number of elongated holes is not limited to this. may be different.

(V1-6) In the second embodiment described above, the upper conductor 42 is provided with the rectangular elongated hole 42c and the lower conductor 44 is provided with the rectangular elongated hole 44c. Of course, the shape of the long hole is not limited to a rectangular shape formed by straight lines. It may have an appropriate shape depending on the conditions.

(V1-7) In the above-described third embodiment, the upper conductor 52 is formed with three notches 52a, 52b, and 52c, and the lower conductor 54 is formed with three notches 54a, 54b, and 54c. However, the number of cutouts is not limited to this, and one or two or four or more cutouts are provided in each of the upper conductor and the lower conductor. Alternatively, the number of cutouts may be different between the upper conductor and the lower conductor.

(V1-8) In the third embodiment described above, the upper conductor 52 is formed with rectangular cutouts 52a, 52b, and 52c, and the lower conductor 54 is formed with rectangular cutouts 54a, 54b, and 54c. is formed, but the shape of the notch is of course not limited to a rectangular shape formed by straight lines. It may be formed in an appropriate shape according to design conditions and the like.

(V1-9) In the fifth embodiment, substantially triangular cutouts 72a and 72b are formed in the long base 42b of the upper conductor 72, and substantially triangular cutouts are formed in the long base 44b of the lower conductor 74. Although the case where the cutouts 74a and 74b are formed has been described, the shape of the cutouts is of course not limited to a substantially triangular shape. It may have an appropriate shape according to design conditions, such as one formed by

(V1-10) In the above embodiments, the upper conductor 42, the lower conductor 44, the upper conductor 52, the lower conductor 54, the upper conductor 72, and the lower conductor 74 are substantially trapezoidal. Of course, the shape is not limited to this. For example, a shape formed by a curve such as a rectangular shape, a rectangular shape with rounded corners, or an elliptical shape may be used.

(VI-11) It goes without saying that each of the above-described embodiments and each of the above-described embodiments (VI-1) to (VI-10) may be combined as appropriate.

INDUSTRIAL APPLICABILITY The present invention can be applied to inverter devices used in various technologies that use high power, such as various motors, contactless power supply, induction heating, and the like.

REFERENCE SIGNS LIST 10 inverter circuit 12 conductor between first non-inverted output signal output portions 14 conductor between first inverted output signal output portions 14 a bent portion 14 b bent portion 16 conductor between second non-inverted output signal output portions 16 a bent portion 16 b bent portion 18 second second Conductor between inverted output signal output portions 18a Bent portion 18b Bent portion 18c Bent portion 18d Bent portion 20 Conductor between third non-inverted output signal output portions 20a Bent portion 20b Bent portion 20c Bent portion 22 Conductor between third inverted output signal output portions 22a Bending portion 22b Bending portion 22c Bending portion 22d Bending portion 24 Conductor between fourth non-inverted output signal output portions 24a Bending portion 24b Bending portion 24c Bending portion 26 Conductor between fourth inverting output signal output portions 26a Bending portion 26b Bending portion 26c Bending portion 26d bent portion 26e bent portion 28 conductor between fifth non-inverted output signal output portions 28a bent portion 28b bent portion 28c bent portion 30 conductor between fifth inverted output signal output portions 30a bent portion 40 inverter circuit 42 upper conductor (first plate conductor)
42a Short base 42b Long base 42c Long hole 42d Short base projection 42e First projection 42f Second projection 42g Third projection 42h Fourth projection 42i Fifth projection 44 Lower conductor (second plate conductor )
44a short bottom side 44b long bottom side 44c long hole 44d short bottom side protrusion 44e first protrusion 44f second protrusion 44g third protrusion 44h fourth protrusion 44i fifth protrusion 50 inverter circuit 52 upper conductor (first plate conductor)
52a Notch 52b Notch 52c Notch 54 Lower conductor (second plate conductor)
54a Notch 54b Notch 54c Notch 60 Inverter circuit 70 Inverter circuit 72 Upper conductor (first plate conductor)
72a Notch 72b Notch 74 Lower conductor (second plate conductor)
74a notch 74b notch 100 inverter device 102 alternating current (AC) power supply 104 converter section 106 inverter section 106a non-inverted output signal synthesis terminal 106b inversion output signal synthesis terminal 108 output sensor 110 converter control section 112 inverter control section 200 load 302A first Inverter block 302A-1 First non-inverted output inverter 302A-1-1 First non-inverted output signal output terminal 302A-2 First inverted output inverter 302A-2-2 First inverted output signal output terminal 302B Second inverter block 302B -1 Second non-inverted output inverter 302B-1-1 Second non-inverted output signal output terminal 302B-2 Second inverted output inverter 302B-2-2 Second inverted output signal output terminal 302C Third inverter block 302C-1 Third 3 non-inverted output inverter 302C-1-1 3rd non-inverted output signal output terminal 302C-2 3rd inverted output inverter 302C-2-2 3rd inverted output signal output terminal 302D 4th inverter block 302D-1-1 4th Non-inverted output signal output terminal 302D-2-2 Fourth inverted output signal output terminal 302E Fifth inverter block 302E-1-1 Fifth non-inverted output signal output terminal 302E-2-2 Fifth inverted output signal output terminal 304 Non Inverted output synthesis copper plate 304A-1 First non-inverted output signal input terminal 304B-1 Second non-inverted output signal input terminal 304C-1 Third non-inverted output signal input terminal 306 Inverted output synthesis copper plate 306A-1 First non-inverted output signal input terminal Inverted output signal input terminal 306B-1 Second non-inverted output signal input terminal 306C-1 Third non-inverted output signal input terminal 308 First non-inverted output connection copper plate 310 First inverted output connection copper plate 312 Second non-inverted output connection copper plate 314 Second inverting output connection copper plate 316 Third non-inverting output connection copper plate 318 Third inverting output connection copper plate 400 Inverter circuit 400A First pseudo inverter block 400B Second pseudo inverter block 400C Third pseudo inverter block 400D Fourth pseudo inverter block

Claims (4)

A plurality of inverter blocks are connected in parallel, non-inverted output signals outputted from non-inverted output terminals of the plurality of inverter blocks are combined at a non-inverted output synthesis terminal , and inverted output terminals of the plurality of inverter blocks. In an inverter circuit that synthesizes and outputs the inverted output signal output from the inverted output synthesis terminal ,
a first plate-shaped conductor that conducts a non-inverted output signal output from each non-inverted output terminal of the plurality of inverter blocks to a non-inverted output combining terminal ;
a second plate-shaped conductor that conducts an inverted output signal output from each of the inverted output terminals of the plurality of inverter blocks to an inverted output synthesis terminal ;
One long hole is formed in each of the first plate-shaped conductor and the second plate-shaped conductor
an inverter circuit,
The first plate-shaped conductor has a substantially trapezoidal shape, and the non-inverted output combining terminal is formed substantially at the center of the short base of the two parallel bases of the substantially trapezoidal shape. and corresponding to the non-inverted output signal output terminals of the plurality of inverter blocks on the longer base of the two parallel bases of the substantially trapezoidal shape. a plurality of protrusions respectively connected to the non-inverted output signal output terminals are formed at positions;
The second plate-shaped conductor has a substantially trapezoidal shape equivalent to that of the first plate-shaped conductor, and is substantially at the center of the short base of the two parallel bases of the substantially trapezoidal shape. , a short base protrusion having the inverted output combining terminal formed therein is formed, and each of the plurality of inverter blocks is inverted on the longer long base of the two parallel bases of the substantially trapezoidal shape. a plurality of projections respectively connected to the inverted output signal output terminals are formed at positions respectively corresponding to the output signal output terminals;
the first plate-shaped conductor and the second plate-shaped conductor are arranged close to each other with a predetermined gap therebetween so that the substantially trapezoidal shapes overlap;
the plurality of inverter blocks are aligned along the long bottom sides of the first plate-shaped conductor and the second plate-shaped conductor;
The elongated holes respectively formed in the first plate-shaped conductor and the second plate-shaped conductor are aligned between the short base and the long base of the substantially trapezoidal shape. The mutually adjacent non-inverted output signal output terminals or the inverted output signals of the inverter block positioned at one end of the row of the plurality of inverter blocks and the inverter block adjacent to the inverter block positioned at the one end The non-inverted output signal output terminal of the inverter block located at the other end of the column and the inverter block adjacent to the inverter block located at the other end from approximately the middle position between the output terminal, or the The first plate-shaped conductor and the second plate-shaped conductor are formed to extend along the long base direction to a substantially intermediate position between the inverted output signal output terminal and the substantially trapezoidal shape of the first plate-shaped conductor and the second plate-shaped conductor. formed at a position where a part of the elongated hole overlaps when placed close to each other with a predetermined interval so that the
An inverter circuit characterized by: A plurality of inverter blocks are connected in parallel, non-inverted output signals outputted from non-inverted output terminals of the plurality of inverter blocks are combined at a non-inverted output synthesis terminal, and inverted output terminals of the plurality of inverter blocks. In an inverter circuit that synthesizes and outputs the inverted output signal output from the inverted output synthesis terminal,
a first plate-shaped conductor that conducts a non-inverted output signal output from each non-inverted output terminal of the plurality of inverter blocks to a non-inverted output combining terminal;
a second plate-shaped conductor that conducts an inverted output signal output from each of the inverted output terminals of the plurality of inverter blocks to an inverted output synthesis terminal;
has
A plurality of cutouts are formed in each of the first plate-shaped conductor and the second plate-shaped conductor
an inverter circuit,
The first plate-shaped conductor has a substantially trapezoidal shape, and the non-inverted output combining terminal is formed substantially at the center of the short base of the two parallel bases of the substantially trapezoidal shape. and corresponding to the non-inverted output signal output terminals of the plurality of inverter blocks on the longer base of the two parallel bases of the substantially trapezoidal shape. a plurality of protrusions respectively connected to the non-inverted output signal output terminals are formed at positions;
The second plate-shaped conductor has a substantially trapezoidal shape equivalent to that of the first plate-shaped conductor, and is substantially at the center of the short base of the two parallel bases of the substantially trapezoidal shape. , a short base protrusion having the inverted output combining terminal formed therein is formed, and each of the plurality of inverter blocks is inverted on the longer long base of the two parallel bases of the substantially trapezoidal shape. a plurality of projections respectively connected to the inverted output signal output terminals are formed at positions respectively corresponding to the output signal output terminals;
the first plate-shaped conductor and the second plate-shaped conductor are arranged close to each other with a predetermined gap therebetween so that the substantially trapezoidal shapes overlap;
the plurality of inverter blocks are aligned along the long bottom sides of the first plate-shaped conductor and the second plate-shaped conductor;
Each of the plurality of notches formed in each of the first plate-shaped conductor and the second plate-shaped conductor is cut out from the long base of the substantially trapezoidal shape and extends along the long base direction. Each of the inverter blocks is cut out to have an elongated rectangular shape, and is arranged in the vicinity of the inverter blocks positioned between the inverter blocks positioned at both ends of the row of the plurality of inverter blocks arranged in line, When the first plate-shaped conductor and the second plate-shaped conductor are arranged close to each other with a predetermined gap so that the substantially trapezoidal shapes overlap each other, the notch is formed at a position where a part of the notch overlaps. An inverter circuit characterized by: In the inverter circuit according to any one of claims 1 or 2,
The first plate-shaped conductor and the second plate-shaped conductor are composed of a projection located at one end and a projection located at one end of the plurality of projections formed on the long base. a second notch formed at a position adjacent to the projection located at the one end between the portion and the adjacent projection, and the plurality of projections formed at the long bottom side A second projection formed at a position adjacent to the projection located at the other end between the projection located at the other end and the projection located at the other end and the adjacent projection 3 notches and
An inverter circuit comprising: In the inverter circuit according to claim 3,
The second notch is a substantially triangular notch,
The inverter circuit , wherein the third notch is a substantially triangular notch .

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