JP7145067B2 - Wiring board and its manufacturing method - Google Patents

Description

The present invention relates to a wiring board and its manufacturing method.

In order to suppress ion migration between adjacent conductor patterns, a wiring board has been proposed in which recesses are formed between these conductor patterns (Patent Document 1).

JP 2016-51834 A

However, in a wiring board in which recesses are formed between conductor patterns, connection failure may occur.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a wiring board and a method of manufacturing the wiring board that can reduce connection failures.

According to one aspect of the present disclosure, a step of forming a first pattern including a plurality of first grooves extending parallel to each other and a second pattern including a second groove surrounding a protrusion in an insulating layer. and forming a metal layer in the plurality of first grooves and in the second grooves to form a plurality of wirings extending parallel to each other in the first pattern, and forming the second pattern. and forming a degas hole having the convex portion as an opening therein.

According to the present disclosure, poor connection can be reduced.

1 is a diagram showing the layout of a wiring board according to the first embodiment; FIG. 2 is an enlarged view of a fine wiring region and its vicinity in FIG. 1; FIG. 1 is a cross-sectional view showing an outline of a wiring board according to a first embodiment; FIG. 1 is a cross-sectional view (part 1) showing details of a thin film layer; FIG. FIG. 2 is a cross-sectional view (part 2) showing details of a thin film layer; FIG. 11 is a cross-sectional view (part 1) showing the method of manufacturing the wiring board according to the second embodiment; FIG. 11 is a cross-sectional view (part 2) showing the method of manufacturing the wiring board according to the second embodiment; FIG. 11 is a cross-sectional view (No. 3) showing the method of manufacturing the wiring board according to the second embodiment; FIG. 14 is a cross-sectional view (part 4) showing the method of manufacturing the wiring board according to the second embodiment; FIG. 11 is a cross-sectional view (No. 5) showing the method of manufacturing the wiring board according to the second embodiment; FIG. 16 is a cross-sectional view (No. 6) showing the method of manufacturing the wiring board according to the second embodiment; FIG. 10 is a cross-sectional view (No. 7) showing the method of manufacturing the wiring board according to the second embodiment; FIG. 11 is a cross-sectional view (No. 8) showing the method of manufacturing the wiring board according to the second embodiment; FIG. 10 is a cross-sectional view (No. 9) showing the method of manufacturing the wiring board according to the second embodiment; 10 is a cross-sectional view (No. 10) showing the method for manufacturing the wiring board according to the second embodiment; FIG. 11A and 11B are cross-sectional views (No. 11) showing the method for manufacturing the wiring board according to the second embodiment; FIG. 12 is a cross-sectional view (No. 12) showing the method of manufacturing the wiring board according to the second embodiment; 13 is a cross-sectional view (No. 13) showing the method for manufacturing the wiring board according to the second embodiment; FIG. 14 is a cross-sectional view (No. 14) showing the method for manufacturing the wiring board according to the second embodiment; FIG. FIG. 15 is a cross-sectional view (No. 15) showing the method of manufacturing the wiring board according to the second embodiment; 16 is a cross-sectional view (No. 16) showing the method for manufacturing the wiring board according to the second embodiment; FIG. 17 is a cross-sectional view (No. 17) showing the method for manufacturing the wiring board according to the second embodiment; FIG. FIG. 11 is a cross-sectional view (part 1) showing a modification of the second embodiment; FIG. 11 is a cross-sectional view (part 2) showing a modification of the second embodiment; FIG. 11 is a cross-sectional view (part 3) showing a modification of the second embodiment; FIG. 4 is a cross-sectional view showing another example of a photoresist layer; FIG. 10 is a cross-sectional view showing still another example of a photoresist layer;

The inventors have made extensive studies to find out the cause of the poor connection. As a result, it was found that voids were present in the vicinity of the degassing holes provided around the conductor pattern, and peeling was caused by these voids. In addition, as a cause of void generation, a fine groove is formed between conductor patterns, and a groove is also formed inside the degas hole at the same time as the fine groove. It turned out that it was not formed.

Hereinafter, embodiments will be specifically described with reference to the accompanying drawings. In the present specification and drawings, constituent elements having substantially the same functional configuration may be denoted by the same reference numerals, thereby omitting redundant description.

(First embodiment)
A first embodiment will be described. A first embodiment relates to a wiring board. FIG. 1 is a diagram showing the layout of a wiring board according to the first embodiment. FIG. 2 is an enlarged view of the fine wiring region and its vicinity in FIG.

As shown in FIG. 1, a wiring board 1 according to the first embodiment includes a first area 2 on which a semiconductor integrated circuit chip such as an application specific integrated circuit (ASIC) is mounted, It has a second region 3A, 3B, 3C and 3D in which semiconductor memory chips such as high bandwidth memory (HBM) are mounted. The first region 2 has a rectangular planar shape, the second regions 3A and 3B are arranged side by side along one side 5 of the first region 2, and the second regions 3A and 3B are arranged along a side 6 parallel to the side 5. Regions 3C and 3D are arranged side by side. Hereinafter, the direction in which the sides 5 and 6 extend is defined as the Y direction, and the direction orthogonal to the Y direction within a plane parallel to the main surface of the wiring board 1 is defined as the X direction.

A fine wiring region 4A is provided between the first region 2 and the second region 3A. The fine wiring region 4A has a plurality of fine wirings that connect the semiconductor integrated circuit chips mounted in the first region 2 and the semiconductor memory chips mounted in the second region 3A. A fine wiring region 4B is provided between the first region 2 and the second region 3B. The fine wiring region 4B has a plurality of fine wirings that connect the semiconductor integrated circuit chips mounted in the first region 2 and the semiconductor memory chips mounted in the second region 3B. A fine wiring region 4C is provided between the first region 2 and the second region 3C. The fine wiring region 4C has a plurality of fine wirings that connect the semiconductor integrated circuit chips mounted in the first region 2 and the semiconductor memory chips mounted in the second region 3C. A fine wiring region 4D is provided between the first region 2 and the second region 3D. The fine wiring region 4D has a plurality of fine wirings that connect the semiconductor integrated circuit chips mounted in the first region 2 and the semiconductor memory chips mounted in the second region 3D.

FIG. 2 shows the fine wiring region 4A and its vicinity as an example of the fine wiring regions 4A to 4D. As shown in FIG. 2, the fine wiring region 4A has a plurality of fine wirings 21 extending in the X direction. The plurality of fine wirings 21 are formed in a line and space (L/S) pattern with line widths and space widths of 1 μm to 5 μm, for example.

A ground region 7 is provided around the first region 2, the second regions 3A to 3D, and the fine wiring regions 4A to 4D. The ground region 7 is provided with a plurality of grounded metal layers, three here, a plurality of degas holes 31A are formed in one metal layer, and a plurality of degas holes 31B are formed in another metal layer. and a plurality of degas holes 31C are formed in another metal layer. An anchor via pad 32A is provided at the center of the degas hole 31A, an anchor via pad 32B is provided at the center of the degas hole 31B, and an anchor via pad 32C is provided at the center of the degas hole 31C. In plan view, the degas hole 31A and the degas hole 31C overlap, and the anchor via pad 32A and the anchor via pad 32C overlap. In plan view, the degas hole 31B is separated from the degas holes 31A and 31C, and the anchor via pad 32B is separated from the anchor via pads 32A and 32C. For example, the degas holes 31A to 31C have a diameter of 50 μm to 150 μm, and the anchor via pads 32A to 32C have a diameter of 20 μm to 40 μm.

Next, the cross-sectional structure of the wiring board will be described. FIG. 3 is a cross-sectional view showing an outline of the wiring board according to the first embodiment. 4 and 5 are cross-sectional views showing details of the thin film layers. 4 corresponds to a cross-sectional view taken along line II in FIG. 2, and FIG. 5 corresponds to a cross-sectional view taken along line II-II in FIG.

As shown in FIG. 3 , the wiring board 1 has a buildup board 11 and a thin film layer 12 formed on one surface of the buildup board 11 . The fine wiring 21 is formed on the thin film layer 12 . Hereinafter, the side of the buildup substrate 11 on which the thin film layer 12 is formed is sometimes called the mounting side, and the opposite side is sometimes called the non-mounting side.

As shown in FIG. 4 , the thin film layer 12 has a third insulating layer 130 formed on the buildup substrate 11 and a first fine wiring layer 51 formed on the third insulating layer 130 . The first fine wiring layer 51 includes a seed layer 121 and a metal plating layer 122 . For example, the seed layer 121 has a titanium film and a copper film thereon, and the metal plating layer 122 is a copper plating layer. The first fine wiring layer 51 has a fine wiring 21A, a degas hole 31A and an anchor via pad 32A. The fine wiring 21A is formed in the fine wiring regions 4A to 4D, and the degas hole 31A and the anchor via pad 32A are formed in the ground region . The fine wiring 21A is part of the fine wiring 21. FIG. The upper surface of the fine wiring 21A is located below the upper surface of the third insulating layer 130. As shown in FIG.

The third insulating layer 130 is formed with a plurality of fine grooves 151, grooves 251 surrounding the projections 33A serving as openings of the degas holes 31A, and grooves 351 for the anchor via pads 32A inside the projections 33A. It is The fine wirings 21 A are formed in a plurality of fine grooves 151 , and the anchor via pads 32 A are formed in the grooves 351 . The fine groove 151 is formed in the line portion of the L/S pattern including the fine wiring 21A. For example, the planar shape of the degas hole 31A and the anchor via pad 32A is circular. The metal plating layer 122 is an example of a metal layer, the patterns in the fine wiring regions 4A to 4D of the third insulating layer 130 are examples of the first pattern, and the patterns in the ground region 7 of the third insulating layer 130 are examples of the first pattern. A pattern is an example of a second pattern. The fine wire 21A is an example of a wire, the fine groove 151 is an example of a first groove, the groove 251 is an example of a second groove, and the groove 351 is an example of a third groove.

The thin film layer 12 has a fourth insulating layer 140 formed on the third insulating layer 130 and a second fine wiring layer 52 formed on the fourth insulating layer 140 . The second fine wiring layer 52 includes a seed layer 131 and a metal plating layer 132 . For example, the seed layer 131 has a titanium film and a copper film thereon, and the metal plating layer 132 is a copper plating layer. The second fine wiring layer 52 has fine wirings 21B, degas holes 31B and anchor via pads 32B (see FIG. 2). The fine wiring 21B is formed in the fine wiring regions 4A to 4D, and the degas hole 31B and the anchor via pad 32B are formed in the ground region . The fine wiring 21B is a part of the fine wiring 21. FIG. The upper surface of the fine wiring 21B is located below the upper surface of the fourth insulating layer 140. As shown in FIG.

The fourth insulating layer 140 has a plurality of fine grooves 152, a groove 252 surrounding a projection (not shown) that serves as an opening of the degas hole 31A, and a groove (not shown) for the anchor via pad 32B inside the projection. (not shown) are formed. The fine wirings 21B are formed in a plurality of fine grooves 152, and the anchor via pads 32B are formed in the grooves for the anchor via pads 32B inside the projections. The fine groove 152 is formed in the line portion of the L/S pattern including the fine wiring 21B. For example, the planar shape of the degas hole 31B and the anchor via pad 32B is circular. The metal plating layer 132 is an example of a metal layer, the patterns in the fine wiring regions 4A to 4D of the fourth insulating layer 140 are examples of the first pattern, and the patterns in the ground region 7 of the fourth insulating layer 140 are examples of the first pattern. A pattern is an example of a second pattern. The fine wiring 21A is an example of a wiring, the fine groove 151 is an example of a first groove, the groove 252 is an example of a second groove, and the groove for the anchor via pad 32B is an example of a third groove. is.

The thin film layer 12 has a fifth insulating layer 150 formed on the buildup substrate 11 and a third fine wiring layer 53 formed on the fifth insulating layer 150 . A third fine wiring layer 53 includes a seed layer 141 and a metal plating layer 142 . For example, the seed layer 141 has a titanium film and a copper film thereon, and the metal plating layer 142 is a copper plating layer. The third fine wiring layer 53 has a fine wiring 21C, a degas hole 31C and an anchor via pad 32C. The fine wiring 21C is formed in the fine wiring regions 4A to 4D, and the degas hole 31C and the anchor via pad 32C are formed in the ground region . Fine wiring 21C is part of fine wiring 21 . The upper surface of the fine wiring 21C is located below the upper surface of the fifth insulating layer 150. As shown in FIG.

The fourth insulating layer 140 is formed with a plurality of fine grooves 153, grooves 253 surrounding the projections 33C serving as openings of the degas holes 31C, and grooves 353 for the anchor via pads 32C inside the projections 33C. It is The fine wires 21C are formed in a plurality of fine grooves 153, and the anchor via pads 32C are formed in the grooves 353. As shown in FIG. The fine groove 153 is formed in the line portion of the L/S pattern including the fine wiring 21C. For example, the planar shape of the degas hole 31C and the anchor via pad 32C is circular. The metal plating layer 142 is an example of a metal layer, the patterns in the fine wiring regions 4A to 4D of the fifth insulating layer 150 are examples of the first pattern, and the patterns in the ground region 7 of the fifth insulating layer 150 are examples of the first pattern. A pattern is an example of a second pattern. The fine wiring 21C is an example of wiring, the fine groove 153 is an example of a first groove, the groove 253 is an example of a second groove, and the groove 353 is an example of a third groove.

A micro via hole 150A is formed in the fifth insulating layer 150, and the anchor via pad 32C is metal-bonded to the second fine wiring layer 52 through the micro via hole 150A. Further, a micro via hole 140A is formed in the fourth insulating layer 140 (see FIG. 5), and the anchor via pad 32B is metal-bonded to the first fine wiring layer 51 through the micro via hole 140A in the ground region 7. ing. Therefore, the first fine wiring layer 51 , the second fine wiring layer 52 and the third fine wiring layer 53 are metal-bonded to each other within the ground region 7 . Therefore, strong joint strength can be obtained by the anchor effect.

As shown in FIG. 5, the thin film layer 12 is formed on the third fine wiring layer 53 and the fifth insulating layer 150, and on a part of the third fine wiring layer 53, a sixth via hole 160A is provided. of insulation layer 160 . The thin film layer 12 further has connection terminals 61 , 62 and 63 that are connected to the ends of the fine wires 21 and protrude from the fifth insulating layer 150 . The connection terminal 61 is electrically connected to the fine wiring 21A of the first fine wiring layer 51, the connection terminal 62 is electrically connected to the fine wiring 21B of the second fine wiring layer 52, and the connection terminal 63 is electrically connected to the third wiring. is electrically connected to the fine wiring 21C of the fine wiring layer 53 of . The connection terminals 61-63 include a seed layer 161 and a metal plating layer 162. As shown in FIG. For example, the seed layer 161 has a titanium film and a copper film thereon, and the metal plating layer 162 is a copper plating layer.

According to the wiring board 1, since the protrusion separating the fine groove 151 exists between the adjacent fine wirings 21A, it is possible to suppress ion migration between the adjacent fine wirings 21A. Similarly, there is a protrusion separating the fine groove 152 between the adjacent fine wirings 21B, and a protrusion separating the fine groove 153 is present between the adjacent fine wirings 21C. Ion migration between adjacent fine wirings 21C can be suppressed.

In addition, voids are less likely to occur in the third insulating layer 130, the fourth insulating layer 140, and the fifth insulating layer 150, since grooves are not formed inside the degas holes 31A to 31C. Therefore, it is possible to suppress the peeling in the thin film layer 12 and suppress the connection failure due to the peeling.

(Second embodiment)
A second embodiment will be described. The second embodiment relates to a wiring board manufacturing method. 6 to 22 are cross-sectional views showing the method of manufacturing the wiring board according to the second embodiment. In the second embodiment, the buildup substrate 11 is formed first, and then the thin film layer 12 is formed on the buildup substrate 11 . 6 to 8 are cross-sectional views showing a method of forming a buildup board. 9 to 22 are cross-sectional views showing a method of forming thin film layers. 9(a) to 22(a) show a portion corresponding to a cross-sectional view taken along line II in FIG. 2, and FIGS. A portion corresponding to a cross-sectional view taken along line II-II in the figure is shown.

First, as shown in FIG. 6A, a core wiring board 101 is prepared as a support. A core wiring board 101 includes a core board 102 and a first wiring layer 104 . A through hole 103A is formed through the core substrate 102 in the thickness direction, and a through conductor 103 is provided in the through hole 103A. For example, the through-hole 103A can be formed by processing using a drill or laser, and the through conductor 103 and the first wiring layer 104 can be formed by plating, photolithography, or the like. As the core wiring board 101, a large-sized board from which a plurality of wiring boards 1 can be obtained is used. That is, the core wiring board 101 has a plurality of regions in which structures corresponding to the wiring board 1 are formed.

Next, as shown in FIG. 6B, uncured resin films are attached to both sides of the core substrate 102 and cured by heat treatment to form the first insulating layer 105 . The first insulating layer 105 is made of insulating resin such as epoxy resin or polyimide resin. The first insulating layer 105 may be formed by applying a liquid resin. After that, by processing the first insulating layer 105 on both sides of the core substrate 102 with a laser, a via hole 106 reaching the connecting portion of the first wiring layer 104 is formed in the first insulating layer 105 .

Subsequently, as shown in FIG. 7A, on both sides of the core substrate 102, the second wiring layer 107 connected to the first wiring layer 104 through the via conductors in the via holes 106 is subjected to the first insulation. It is formed on layer 105 . The second wiring layer 107 can be formed by a semi-additive method.

After the formation of the second wiring layer 107, via holes 109 are formed on the first insulating layer 105 and on the connecting portion of the second wiring layer 107 on both sides of the core substrate 102, as shown in FIG. 7B. A provided second insulating layer 108 is formed. The second insulating layer 108 can be formed by a method similar to that of the first insulating layer 105 .

Further, as shown in FIG. 7B, on both sides of the core substrate 102, the third wiring layer 110 connected to the second wiring layer 107 through the via conductors in the via holes 109 is placed in the second insulation. Formed on layer 108 . The third wiring layer 110 can be formed by a semi-additive method in the same manner as the second wiring layer 107 . However, on the mounting side of the core substrate 102 , the third wiring layer 110 can be formed in a solid shape without forming a wiring pattern on the third wiring layer 110 on the second insulating layer 108 .

Next, as shown in FIG. 8, a solder resist layer 111 is formed on the second insulating layer 108 on the non-mounting side of the core substrate 102 . After that, an opening 112 is formed in the solder resist layer 111 to reach the connecting portion of the third wiring layer 110 .

The solder resist layer 111 is made of insulating resin such as photosensitive epoxy resin or acrylic resin. The solder resist layer 111 may be formed by attaching a resin film or applying a liquid resin. The opening 112 can be formed by exposure and development. An insulating resin such as a non-photosensitive epoxy resin or polyimide resin may be used for the solder resist layer 111 . In this case, the opening 112 can be formed by laser machining or blasting.

Thus, the buildup substrate 11 can be formed.

Next, as shown in FIGS. 9A and 9B, the mounting side surface of the buildup substrate 11 is polished by chemical mechanical polishing to expose the second insulating layer 108 .

After that, as shown in FIGS. 10A and 10B, a third insulating layer 130 is formed on the third wiring layer 110 and the second insulating layer 108 . The third insulating layer 130 is made of insulating resin such as photosensitive epoxy resin.

Subsequently, as shown in FIGS. 11A and 11B, a photoresist layer 191 is formed on the third insulating layer 130 so as to have openings at portions where the first fine wiring layers 51 are to be formed. . The photoresist layer 191 has a constricted portion 191A near the interface with the third insulating layer 130 . For example, the photoresist layer 191 has openings in the portion where the fine wiring 21A is formed and the portion where the anchor via pad 32A is formed, and covers the portion where the degas hole 31A is formed.

Next, as shown in FIGS. 12A and 12B, the third insulating layer 130 is etched using the photoresist layer 191 as a mask. As a result, a fine groove 151 is formed in the third insulating layer 130 in the line portion of the L/S pattern including the region for forming the fine wiring 21A. Further, grooves 251 are formed in the third insulating layer 130 in areas where the anchor via pads 32A are to be formed.

After that, as shown in FIGS. 13A and 13B, a seed layer 121 is formed in the fine grooves 151 and 251 by sputtering. The seed layer 121 is also formed on the top and side surfaces of the photoresist layer 191, but not on the constricted portion 191A. In forming the seed layer 121, for example, a titanium film and a copper film are sequentially formed.

Subsequently, as shown in FIGS. 14A and 14B, the photoresist layer 191 is removed together with the seed layer 121 formed on its upper surface and side surfaces.

Next, as shown in FIGS. 15A and 15B, a metal plating layer 122 made of copper or the like is formed on the seed layer 121 by electroless plating. A fine wire 21A, a degas hole 31A and an anchor via pad 32A are formed in the first fine wire layer 51. As shown in FIG.

After that, as shown in FIGS. 16A and 16B, a micro via hole 140A is provided on the first fine wiring layer 51 and the third insulating layer 130 and on a part of the first fine wiring layer 51. A fourth insulating layer 140 is formed. The fourth insulating layer 140 is made of insulating resin such as photosensitive epoxy resin. The microvia hole 140A is formed by photolithography, for example.

Subsequently, as shown in FIGS. 17A and 17B, a photoresist layer 192 is formed on the fourth insulating layer 140 so as to have openings at the portions where the second fine wiring layers 52 are to be formed. . The photoresist layer 192 has a constricted portion 192A near the interface with the fourth insulating layer 140 . For example, the photoresist layer 192 has openings in a portion for forming the fine wiring 21B and a portion for forming the anchor via pad 32B, and covers a portion for forming the degas hole 31B.

Then, using the photoresist layer 192 as a mask, the fourth insulating layer 140 is etched. As a result, a fine groove 152 is formed in the fourth insulating layer 140 in the line portion of the L/S pattern including the region for forming the fine wiring 21B. Further, grooves 252 are formed in the fourth insulating layer 140 in regions where the anchor via pads 32B are to be formed.

After that, as shown in FIGS. 18A and 18B, a seed layer 131 is formed in the fine grooves 152 and 252 by sputtering. The seed layer 131 is also formed on the top and side surfaces of the photoresist layer 192, but not on the constricted portion 192A. Subsequently, the photoresist layer 192 is removed together with the seed layer 131 formed on its top and side surfaces. Next, a metal plating layer 132 made of copper or the like is formed on the seed layer 131 by electroless plating. A fine wire 21B, a degas hole 31B and an anchor via pad 32B are formed in the second fine wire layer 52 (see FIG. 2).

Subsequently, as shown in FIGS. 19A and 19B, micro via holes 150A are formed on the second fine wiring layer 52 and the fourth insulating layer 140, and on part of the second fine wiring layer 52. A provided fifth insulating layer 150 is formed. The fifth insulating layer 150 is made of insulating resin such as photosensitive epoxy resin. The microvia hole 150A is formed by photolithography, for example.

Next, as shown in FIGS. 20A and 20B, a photoresist layer 193 is formed on the fifth insulating layer 150 so that openings are provided at portions where the third fine wiring layer 53 is to be formed. The photoresist layer 193 has a constricted portion 193 A near the interface with the fifth insulating layer 150 . For example, the photoresist layer 193 has openings in a portion for forming the fine wiring 21C and a portion for forming the anchor via pad 32C, and covers a portion for forming the degas hole 31C.

After that, the fifth insulating layer 150 is etched using the photoresist layer 193 as a mask. As a result, a fine groove 153 is formed in the fifth insulating layer 150 in the line portion of the L/S pattern including the region for forming the fine wiring 21C. In addition, grooves 253 are formed in the fifth insulating layer 150 in regions where the anchor via pads 32C are to be formed.

Subsequently, as shown in FIGS. 21A and 21B, a seed layer 141 is formed in the fine grooves 153 and 253 by sputtering. The seed layer 141 is also formed on the top and side surfaces of the photoresist layer 193, but not on the constricted portion 193A. The photoresist layer 193 is then removed together with the seed layer 141 formed on its top and side surfaces. Thereafter, a metal plating layer 142 made of copper or the like is formed on the seed layer 141 by electroless plating. A fine wire 21C, a degas hole 31C, and an anchor via pad 32C are formed in the third fine wire layer 53 .

Subsequently, as shown in FIGS. 22A and 22B, micro via holes 160A are formed on the third fine wiring layer 53 and the fifth insulating layer 150, and on part of the third fine wiring layer 53. A provided sixth insulating layer 160 is formed. The sixth insulating layer 160 is made of insulating resin such as photosensitive epoxy resin. The microvia hole 160A is formed by photolithography, for example.

Next, connection terminals 61 to 63 are formed to be connected to the third fine wiring layer 53 through via conductors in the micro via holes 160A. The connection terminals 61 - 63 can be formed by a semi-additive method and include a seed layer 161 and a metal plating layer 162 .

After that, the structure shown in FIGS. 22A and 22B is cut by a slicer or the like along cutting lines (not shown). As a result, the structures corresponding to the wiring boards 1 are individualized, and a plurality of wiring boards 1 according to the first embodiment are obtained from the large-sized core wiring board 101 . Thus, the wiring board 1 according to the first embodiment can be manufactured.

In this manufacturing method, the degas holes 31A and the anchor via pads 32A are formed by forming the seed layer 121 and the metal plating layer 122 in the grooves 251. Therefore, the first method can be manufactured without forming grooves that cause voids. Ion migration in the fine wiring layer 51 can be suppressed. Since the degas holes 31B and the anchor via pads 32B are formed by forming the seed layer 131 and the metal plating layer 132 in the grooves 252, the second fine wiring layer 52 can be formed without forming grooves that cause voids. Ion migration can be suppressed. Since the degas holes 31C and the anchor via pads 32C are formed by forming the seed layer 141 and the metal plating layer 142 in the grooves 253, the third fine wiring layer 53 can be formed without forming grooves that cause voids. Ion migration can be suppressed. Therefore, it is possible to suppress peeling and poor connection caused by voids.

As shown in FIGS. 23A and 23B, the seed layer 121 may be formed not only on the bottom surfaces of the fine grooves 151, 251, and 351, but also on the side surfaces. In this case, as shown in FIGS. 24(a) and 24(b), the process up to the formation of the metal plating layer 122 is performed, and then, as shown in FIGS. Of these, it is preferable to remove the portion located above the upper surface of the metal plating layer 122 . In other words, it is preferable to perform the treatment so that the upper surface of the metal plating layer 122 is located below the upper surface of the third insulating layer 130 . This is for more reliably suppressing ion migration. The same is true for seed layers 131 and 141 .

Moreover, the cross-sectional shape of the photoresist layer 191 is not particularly limited. For example, as shown in FIG. 26, the cross-sectional shape of the photoresist layer 191 may have an inverse tapered shape in which the dimensions become smaller as the third insulating layer 130 is approached. In this case, since the side surfaces of the fine groove 151 are hidden by the upper surface of the photoresist layer 191 , the seed layer 121 is less likely to be formed on the side surfaces of the fine groove 151 . Moreover, as shown in FIG. 27, the cross-sectional shape of the photoresist layer 191 may be rectangular. In this case, when forming the fine grooves 151 , it is preferable to select etching conditions such that the side surfaces of the fine grooves 151 are hidden by the upper surface of the photoresist layer 191 . When the seed layer 121 is formed on the side surface of the fine groove 151, it is preferable to remove the portion above the upper surface of the metal plating layer 122 after forming the metal plating layer 122, as described above. The same is true for photoresist layers 192 and 193 .

Although the preferred embodiments and the like have been described in detail above, the present invention is not limited to the above-described embodiments and the like, and various modifications can be made to the above-described embodiments and the like without departing from the scope of the claims. Modifications and substitutions can be made. For example, although the buildup substrate is used in the above-described embodiments, a support substrate may be used instead of the buildup substrate.

1 wiring board 4A, 4B, 4C, 4D fine wiring area 7 grounding area 11 build-up board 12 thin film layer 21, 21A, 21B, 21C, 21D fine wiring 31A, 31B, 31C degas hole 32A, 32B, 32C pad for anchor via 33A , 33C: Projections 51, 52, 53 Fine wiring layers 61, 62, 63 Connection terminals 151, 152, 153 Fine grooves 251, 252, 253, 351, 353 Grooves

Claims (9)

forming a first pattern including a plurality of first grooves extending parallel to each other and a second pattern including a second groove surrounding the protrusion in the insulating layer;
forming a plurality of wirings extending parallel to each other in the first pattern by forming a metal layer in the plurality of first trenches and in the second trenches; a step of forming a degas hole having the convex portion as an opening;
A method for manufacturing a wiring board, comprising: 2. The method of manufacturing a wiring board according to claim 1, wherein the plurality of wirings are formed in a line-and-space pattern having a line width and a space width of 1 μm to 5 μm . 3. The method of manufacturing a wiring board according to claim 1, wherein the top surface of the metal layer is positioned below the top surface of the insulating layer. 4. The method of manufacturing a wiring board according to claim 1, wherein the planar shape of the degas hole is circular. In the step of forming the first pattern and the second pattern, forming a third groove inside the convex portion,
2. A pad is formed in said third groove by forming said metal layer also in said third groove in the step of forming said plurality of wirings and said degas hole. 5. The method for manufacturing a wiring board according to any one of items 1 to 4. an insulating layer including a first pattern including a plurality of first grooves extending parallel to each other and a second pattern including a second groove surrounding the protrusion;
a metal layer including wiring formed in the plurality of first grooves and degas holes formed in the second pattern and having openings corresponding to the protrusions;
A wiring board characterized by comprising: 7. The wiring board according to claim 6, wherein the wiring formed in the plurality of first grooves is formed in a line-and-space pattern with a line width and a space width of 1 μm to 5 μm . 8. The wiring board according to claim 6, wherein the upper surface of the metal layer is positioned below the upper surface of the insulating layer. The wiring formed in the plurality of first grooves,
a seed layer;
a metal plating layer formed on the seed layer;
has
9. The wiring board according to claim 6, wherein the seed layer is in contact with bottoms of the plurality of first grooves.

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