JP2017103350A - Printed-wiring board and method for manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a printed-wiring board capable of improving connection reliability by suppressing void generation and keeping uniformity of a plating film, and a method for manufacturing the same.SOLUTION: A printed-wiring board 1 comprises: a conductor layer 11 including a conductor pad 110; an insulating layer 12 covering the conductor layer 11; a conductor layer 13 formed on the insulating layer 12; an insulating layer 14 laminated on the insulating layer 12 so as to surround the conductor layer 13; and a conductor member 15 integrally formed over the inside of the insulating layers 12 and 14. The conductor member 15 is formed of a metal seed layer and an electroless plating layer. The conductor member 15 comprises a first portion 150 penetrating through the insulating layer 12 and electrically connected to the conductor pad 110, and a second portion 151 penetrating through the insulating layer 14 and juxtaposed in the conductor layer 13. An upper surface 151a of the second portion 151 is exposed to the outside.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a printed wiring board and a manufacturing method thereof.

  Conventionally, as a technique in such a field, for example, there are those described in the following patent documents. The printed wiring board described in Patent Document 1 includes a core substrate having a first conductor layer, and an insulating layer formed on the core substrate and having first and second openings. Of the first and second openings, the second opening is disposed closest to the core substrate and exposes a portion of the first conductor layer. On the other hand, the first opening is disposed outside the second opening (the side away from the core substrate) and communicates with the second opening. A second conductor layer is formed in the first opening, and a via conductor that electrically connects the first conductor layer and the second conductor layer is formed in the second opening.

JP 2007-221089 A

  However, in the above printed wiring board, since the electroplating method is used when forming the second conductor layer and the via conductor, voids are formed inside the first and second openings due to variations in current density distribution and the like. It is easy to generate | occur | produce and it is thought that the plating film formed may become non-uniform | heterogenous. And it is estimated that the connection reliability of a printed wiring board is impaired by generation | occurrence | production of a void and the nonuniformity of a plating film.

  The printed wiring board of the present invention that solves the above problems is a printed wiring board having a plurality of conductor layers and insulating layers, and covers a first conductor layer including a first conductor pad and the first conductor layer. A first insulating layer laminated on the first conductor layer; a second conductor layer formed on the first insulating layer and including a second conductor pad; and the second conductor layer so as to surround the second conductor layer. A second insulating layer laminated on the first insulating layer; and a conductor member integrally formed across the first insulating layer and the second insulating layer, the conductor member comprising: The conductive member is formed of a metal seed layer and an electroless plating layer, and the conductor member penetrates the first insulating layer and is electrically connected to the first conductor pad, and the second insulating layer. And a second portion juxtaposed with the second conductor layer, and over the second portion Surface is exposed to the outside.

  The method for manufacturing a printed wiring board according to the present invention includes a step of forming a first insulating layer made of an insulating material, a through-hole penetrating the first insulating layer, a surface of the first insulating layer, and Forming a metal seed layer on the inner wall surface of the through hole; forming a resist layer on the metal seed layer; and exposing and developing the resist layer to cover the resist pattern and the through hole A resist post, a step of removing the metal seed layer in a portion where the resist pattern and the resist post are not formed, and the resist pattern and the resist post on the first insulating layer. A step of laminating a second insulating layer covering the substrate, and exposing the surface of the second insulating layer to plasma to expose the resist pattern and the resist post. A step of removing the resist pattern and the resist post by plasma irradiation; and a step of forming an electroless plating layer on the metal seed layer exposed by removing the resist pattern and the resist post. Prepare.

  According to the present invention, connection reliability can be improved by suppressing the generation of voids and maintaining the uniformity of the plating film.

It is a schematic sectional drawing which shows the printed wiring board which concerns on 1st Embodiment. It is process drawing explaining the manufacturing method of a printed wiring board. It is process drawing explaining the manufacturing method of a printed wiring board. It is process drawing explaining the manufacturing method of a printed wiring board. It is process drawing explaining the manufacturing method of a printed wiring board. It is process drawing explaining the manufacturing method of a printed wiring board. It is process drawing explaining the manufacturing method of a printed wiring board. It is process drawing explaining the manufacturing method of a printed wiring board. It is process drawing explaining the manufacturing method of a printed wiring board. It is process drawing explaining the manufacturing method of a printed wiring board. It is process drawing explaining the manufacturing method of a printed wiring board. It is process drawing explaining the manufacturing method of a printed wiring board. It is process drawing explaining the manufacturing method of a printed wiring board. It is process drawing explaining the manufacturing method of a printed wiring board. It is process drawing explaining the manufacturing method of a printed wiring board. It is explanatory drawing which shows the semiconductor package of the POP structure using a printed wiring board. It is a schematic sectional drawing which shows the printed wiring board which concerns on 2nd Embodiment. It is explanatory drawing which shows the semiconductor package of the POP structure using a printed wiring board. It is explanatory drawing which shows the semiconductor package of the POP structure using a printed wiring board. It is a schematic sectional drawing which shows the printed wiring board which concerns on 3rd Embodiment. It is a schematic sectional drawing which shows the printed wiring board which concerns on 4th Embodiment. It is a schematic sectional drawing which shows the printed wiring board which concerns on 5th Embodiment.

  Embodiments of a printed wiring board and a manufacturing method thereof according to the present invention will be described below with reference to the drawings. In the description of the drawings, the same elements are denoted by the same reference numerals, and redundant description is omitted.

<First Embodiment>
FIG. 1 is a schematic cross-sectional view showing a printed wiring board according to the first embodiment. The printed wiring board 1 according to the present embodiment has a build-up structure in which a plurality of conductor layers and insulating layers are alternately stacked, and includes three insulating layers 10, 12, 14 and two conductive layers. 11 and 13. The insulating layer 10, the insulating layer 12, and the insulating layer 14 are interlayer insulating layers, which are formed of, for example, a photosensitive resin and have a thickness of 5 to 25 μm. The insulating layer 10 is disposed on the lowermost side of the printed wiring board 1, the insulating layer 14 is disposed on the uppermost side of the printed wiring board 1, and the insulating layer 12 is disposed therebetween.

  A conductor layer 11 is formed on the insulating layer 10. The conductor layer of the present invention is a wiring layer constituting a conductor circuit, and may include a conductor pad and a wiring depending on the arrangement position thereof, or may include only a conductor pad. The conductor layer 11 corresponds to a “first conductor layer” recited in the claims, and a plurality of conductor pads (first conductor pads) 110 and a plurality of conductor pads 110 disposed between the conductor pads 110. The wiring 111 is included.

  The conductor pad 110 and the wiring 111 are formed of a metal seed layer 11a and an electroless plating layer 11b, respectively. The metal seed layer 11a is a Cu seed layer, for example, and is disposed on the side adjacent to the insulating layer 10, and the electroless plating layer 11b is disposed thereon. A plurality of through holes 16 penetrating the insulating layer 10 are formed in the insulating layer 10. The through hole 16 has a truncated cone shape, and its diameter extends in a direction from the insulating layer 10 toward the insulating layer 12.

  An electrode 17 is formed inside the through hole 16. The electrode 17 is formed of a metal seed layer 11 a and an electroless plating layer 11 b as in the case of the conductor layer 11, and has a diameter increased in a direction from the insulating layer 10 toward the insulating layer 12. The upper end of the electrode 17 is formed integrally with the conductor pad 110, and the lower end is exposed to the outside. The lower surface 17 a exposed to the outside of the electrode 17 is located on the same plane as the lower surface 10 a of the insulating layer 10.

  An insulating layer 12 is laminated on the conductor layer 11 so as to cover the conductor layer 11. The insulating layer 12 corresponds to a “first insulating layer” recited in the claims, and a conductor layer 13 is formed thereon. The conductor layer 13 corresponds to a “second conductor layer” recited in the claims, and includes a plurality of conductor pads (second conductor pads) 130. Further, an insulating layer 14 is laminated on the insulating layer 12. The insulating layer 14 corresponds to a “second insulating layer” recited in the claims, and surrounds the conductor layer 13 formed on the insulating layer 12. The conductor layer 13 is formed of a metal seed layer 13a and an electroless plating layer 13b.

  As shown in FIG. 1, the printed wiring board 1 further includes a plurality of conductor members 15. The conductor member 15 is integrally formed over the insulating layer 12 and the insulating layer 14, and includes a first portion 150 that penetrates the insulating layer 12, and a second portion 151 that penetrates the insulating layer 14. Have The first portion 150 is provided inside the through hole 18 formed in the insulating layer 12, has a truncated cone shape, and has a diameter expanded in a direction from the insulating layer 12 toward the insulating layer 14. The first portion 150 includes a metal seed layer 13a formed along the inner wall surface of the through hole 18, and an electroless plating layer 13b disposed inside the metal seed layer 13a so as to be surrounded by the metal seed layer 13a. Is formed by.

  On the other hand, the 2nd part 151 is arrange | positioned above the 1st part 150, and is formed in the column shape. The second portion 151 is juxtaposed with the conductor layer 13 and is surrounded by the insulating layer 14. The second portion 151 is formed by a metal seed layer 13 a formed on the surface of the insulating layer 12 and an electroless plating layer 13 b disposed on the metal seed layer 13 a and the first portion 150.

  The lower end of the first portion 150 is electrically connected to the conductor pad 110 of the conductor layer 11, and the upper end of the second portion 151 (that is, the upper surface 151a of the second portion 151) is exposed to the outside. The conductor member 15 and the electrode 17 disposed below the conductor member 15 are stacked in a straight line along the stacking direction of the insulating layers 10, 12, and 14 to form a stack structure. As shown in FIG. 1, the upper surface 151 a of the second portion 151 is located in the same plane as the upper surface 14 a of the insulating layer 14. Further, the upper surface 130 a of the conductor pad 130 is located in the same plane as the upper surface 14 a of the insulating layer 14.

  In the printed wiring board 1 having the above structure, the upper surface 151a of the second portion 151 of the conductor member 15 is exposed to the outside, and the first portion 150 is electrically connected to the conductor pad 110. Therefore, since the conductor member 15 can be used as a mounting pad for mounting with an external electronic component, the external electronic component can be easily mounted on the printed wiring board 1.

  Moreover, since the conductor layer 11, the conductor layer 13, the electrode 17, and the conductor member 15 are formed by the metal seed layers 11a and 13a and the electroless plating layers 11b and 13b, compared with the case where the conventional electrolytic plating method is used. The generation of voids can be suppressed, and the formed plating film can be kept uniform. Thereby, the connection reliability of the printed wiring board 1 can be improved. Furthermore, as long as the generation of voids can be suppressed and the uniformity of the plating film can be maintained, the designed wiring width and wiring spacing can be obtained. Accordingly, fine wiring and high-density conductor circuits can be easily formed, and the conductor circuits of the printed wiring board 1 can be easily miniaturized.

  Furthermore, since the upper surface 151a of the second portion 151 of the conductor member 15, the upper surface 130a of the conductor pad 130, and the upper surface 14a of the insulating layer 14 are located on the same plane, the flatness of these upper surfaces should be maintained. Can do. Therefore, when mounting with other electronic components via these upper surfaces, the effect of improving mountability can also be expected.

  In the present embodiment, the conductor layer 11, the conductor layer 13, the electrode 17, and the conductor member 15 are all formed of a metal seed layer and an electroless plating layer, but are not limited thereto. For example, when miniaturization or the like of the conductor circuit is not so required, the conductor layer 13 and the conductor member 15 are formed of the metal seed layer and the electroless plating layer, and the conductor layer 11 and the electrode 17 are the seed layer. It may be formed by an electrolytic plating layer. Or in the same conductor layer, you may use properly so that the part formed by a seed layer and an electroplating layer and the part formed by a seed layer and an electroless-plating layer may be mixed.

<Method for Manufacturing Printed Wiring Board 1>
Hereinafter, a method of manufacturing the printed wiring board 1 will be described with reference to FIGS. 2A to 4E. First, the support plate 20 is prepared. For the support plate 20, for example, a flat glass plate having a low coefficient of thermal expansion is used. In addition to a glass plate, Si, a metal plate, a copper clad laminated substrate, etc. may be used. Subsequently, a release layer 21 is formed on the support plate 20 (see FIG. 2A). Examples of the release agent used for the release layer 21 include Wafer Bond from Brewer Science.

  Next, an insulating layer 10 is formed by applying an interlayer insulating material made of a photosensitive polyimide resin on the release layer 21. Subsequently, the release layer 21 and the insulating layer 10 are bonded together by heat treatment. Thereafter, an exposure process is performed at a predetermined position of the insulating layer 10 using a mask, and further a developing process is performed to form a plurality of frustoconical through holes 16 in the insulating layer 10 (see FIG. 2B). The formed through-hole 16 is expanded in the direction from the support plate 20 toward the insulating layer 10 (that is, the direction from the insulating layer 10 to the insulating layer 12 shown in FIG. 1). The depth of the through hole 16 reaches the surface of the release layer 21.

  Subsequently, a catalyst such as palladium is applied to the upper surface of the insulating layer 10, the inner wall surface of the through-hole 16 and the release layer 21 exposed by the through-hole 16, and 5 to 60 is applied to the electroless plating solution having hypophosphorous acid. By soaking for a minute, a metal seed layer 11a having a thickness of 0.1 to 1 μm is formed in these places (see FIG. 2C).

  Next, a resist layer is applied on the metal seed layer 11a, a photomask film is placed on the resist layer and exposed, and then developed with sodium carbonate to form a predetermined resist pattern 22. Subsequently, an electroless plating layer 11b is formed on the metal seed layer 11a on which the resist pattern 22 is not formed by using an electroless plating method (see FIG. 2D). At this time, the inside of the through hole 16 is filled with the electroless plating layer 11b.

  Next, the resist pattern 22 is removed with a solution containing monoethanolamine, and the metal seed layer 11a exposed by the removal is removed by an etching process. Then, the metal seed layer 11a and the electroless plating layer 11b left on the insulating layer 10 form a conductor layer 11, and the metal seed layer 11a and the electroless plating layer 11b left inside the through hole 16 provide an electrode 17. Form (see FIG. 2E).

  Next, the insulating layer 12 is formed on the conductor layer 11 and the insulating layer 10 so as to cover them (see FIG. 3A). As with the insulating layer 10, the insulating layer 12 is formed by applying an interlayer insulating material made of a photosensitive polyimide resin. Subsequently, a plurality of frustoconical through holes 18 are formed by performing exposure and development processing at positions corresponding to the electrodes 17 of the insulating layer 12 (see FIG. 3B). The through hole 18 is expanded in the direction from the insulating layer 10 toward the insulating layer 12, similarly to the above-described through hole 16.

  Next, a catalyst is applied to the upper surface of the insulating layer 12 and the inner wall surface of the through hole 18 by the above-described method, and the conductor exposed by the upper surface of the insulating layer 12 and the inner wall surface of the through hole 18 and the through hole 18. A metal seed layer 13a having a thickness of 0.1 to 1 μm is formed on the layer 11 (see FIG. 3C).

  Subsequently, a resist layer 23 is formed on the metal seed layer 13a (see FIG. 3D). Here, for example, the resist layer 23 is formed by laminating a resist film on the metal seed layer 13a. Subsequently, the resist layer 23 is exposed and developed by the above-described method, whereby a predetermined resist pattern 24 is formed on the metal seed layer 13a, and a resist post 27 that covers the through hole 18 above the through hole 18; (See FIG. 4A).

  Next, the metal seed layer 13a where the resist pattern 24 and the resist post 27 are not formed is removed by etching (see FIG. 4B). Subsequently, the insulating layer 14 covering the resist pattern 24 and the resist post 27 is formed on the insulating layer 12 (see FIG. 4C).

Next, the resist pattern 24 and the resist post 27 embedded in the insulating layer 14 are exposed by irradiating the surface of the insulating layer 14 with plasma. At this time, it is necessary to perform plasma irradiation so that the upper surface 14a of the insulating layer 14 to be formed is positioned on the same plane as the upper surfaces of the resist pattern 24 and the resist post 27. Thereafter, only the resist pattern 24 and the resist post 27 are further removed by plasma irradiation (see FIG. 4D). As a result, the metal seed layer 13a formed on the inner wall surface of the insulating layer 12 and the through hole 18 is exposed again. Note that O ₂ plasma or H ₂ plasma is used for plasma irradiation.

  As shown in FIG. 4D, by removing the resist pattern 24, a plurality of spaces S1 in which the metal seed layer 13a is exposed are formed in the insulating layer. On the other hand, a plurality of spaces S2 exposing the metal seed layer 13a are formed in the insulating layer 14 by removing the resist posts 27. These spaces S1 and S2 are substantially cylindrical. Further, the through hole 18 is exposed again by removing the resist post 27.

  Next, electroless plating is performed on the space S1 and the space S2 formed inside the insulating layer 14 and the inside of the through hole 18, that is, on the metal seed layer 13a exposed by removing the resist pattern 24 and the resist post 27. The electroless plating layer 13b is formed using a method. At this time, the electroless plating layer 13b is formed so that the upper surface of the formed electroless plating layer 13b and the upper surface 14a of the insulating layer 14 are aligned on the same plane (see FIG. 4E). The electroless plating layer 13b formed in the space S1 and the metal seed layer 13a below the electroless plating layer 13b form a conductor layer 13. On the other hand, the electroless plating layer 13b formed inside the space S2 and the through hole 18 and the metal seed layer 13a below the electroless plating layer 13a form the conductor member 15.

  In addition, before forming the electroless plating layer 13b, a roughening process may be performed on the peripheral walls of the space S1 and the space S2 formed in the insulating layer 14. If it does in this way, the adhesiveness of the formed electroless-plating layer 13b and the insulating layer 14 can be improved.

  Next, the support plate 20 and the release layer 21 are heated to soften the release layer 21 and remove the support plate 20 from the printed wiring board 1. And if the peeling layer 21 which remained on the printed wiring board 1 is removed cleanly after removing the support board 20, the printed wiring board 1 shown in FIG. 1 will be obtained.

  In the above manufacturing method, since the electroless plating layers 11b and 13b are formed on the metal seed layers 11a and 13a by the electroless plating method, generation of voids can be suppressed as compared with the conventional electrolytic plating method. At the same time, the formed plating film can be kept uniform. For this reason, the connection reliability of the printed wiring board 1 can be improved.

  Further, when the conductor layer 13 and the conductor member 15 are formed, the metal seed layer 13a where the resist pattern 24 and the resist post 27 are not present is first removed by etching, and then the electroless plating layer 13b is formed. In this case, damage to the conductor layer due to the etching process can be reduced as compared with the case where the electroless plating layer is formed first and then the unnecessary metal seed layer is removed by etching. Therefore, the designed wiring circuit can be secured and the conductor circuit can be miniaturized.

  Furthermore, in the above-described manufacturing method, partial removal of the insulating layer 14 and removal of the resist pattern 24 and the resist post 27 are performed using plasma irradiation, so that the work efficiency is increased compared to the case of using a conventional solution. It is possible to improve productivity.

  The printed wiring board 1 produced in this way can be used as a single unit or in combination with other substrates. FIG. 5 shows an example in which the printed wiring board 1 is used in a semiconductor package having a POP (package on package) structure.

  The semiconductor package shown in FIG. 5 includes a printed wiring board 1, a semiconductor chip 3 mounted on the printed wiring board 1, and another printed wiring board 4. The semiconductor chip 3 and the other printed wiring board 4 are arranged so as to be stacked in the vertical direction (that is, the stacking direction of the insulating layers 10, 12, and 14). The terminals or electrodes of the semiconductor chip 3 are electrically connected to a part of the conductor member 15 of the printed wiring board 1 (the conductor member 15 located at the center of the insulating layer 14 in FIG. 5) via the solder bumps 28. Has been.

  On the other hand, the other printed wiring board 4 is arranged above the semiconductor chip 3 so as to straddle the semiconductor chip 3, and another part of the conductor member 15 of the printed wiring board 1 via the solder bumps 29 (in FIG. 5). , And electrically connected to the conductor member 15) located at the outer edge of the insulating layer 14. The conductor member 15 for electrical connection with the semiconductor chip 3 and the conductor member 15 for electrical connection with another printed wiring board 4 may have the same arrangement pitch and area. Different arrangement pitches and areas may be used in accordance with the positions and sizes of the terminals and electrodes of the chip 3 and other printed wiring boards 4.

Second Embodiment
FIG. 6 is a schematic sectional view showing a printed wiring board according to the second embodiment. The difference between the printed wiring board 2 according to this embodiment and the first embodiment is that the electrode 17 is not formed on the insulating layer 10. The printed wiring board 2 can obtain the same effects as those of the first embodiment.

  When the printed wiring board 2 having such a structure is used in a semiconductor package having a POP structure, since the electrode 17 is not provided on the insulating layer 10, a device for conducting with the outside is required. For example, as shown in FIG. 7, the insulating layer 10 has a plurality of openings 25 for exposing the conductor pads 110. Then, when electrically connecting to an external electronic component, terminals and electrodes of the external electronic component inserted into the opening 25 may be connected to the conductor pad 110 via solder bumps.

  Alternatively, as shown in FIG. 8, after the opening 25 is formed in the insulating layer 10, the inner surface of the opening 25 and the lower surface 10 a of the insulating layer 10 are formed using, for example, a semi-additive process (SAP). An electrode 26 composed of an electroless plating layer and an electrolytic plating layer may be further formed and electrically connected to terminals and electrodes of external electronic components via the electrode 26.

<Third Embodiment>
FIG. 9 is a schematic sectional view showing a printed wiring board according to the third embodiment. The difference between the printed wiring board 5 according to the present embodiment and the first embodiment is that the upper surface 151a of the second portion 151 of the conductor member 15 and the upper surface 130a of the conductor pad 130 are lower than the upper surface 14a of the insulating layer 14. Is to be formed. The upper surface 151a of the second part 151 and the upper surface 130a of the conductor pad 130 are located on the same plane.

  The printed wiring board 5 having such a structure can obtain the same effects as those of the first embodiment, and further the following effects. That is, since the upper surface 151a of the second portion 151 and the upper surface 130a of the conductor pad 130 are lower than the upper surface 14a of the insulating layer 14, the insulating layer 14 serves as a solder resist layer, and the upper surfaces 130a, 151a can be protected. Further, since the upper surface 151a of the second portion 151 is lower than the upper surface 14a of the insulating layer 14, a step is formed between these upper surfaces. When the solder bump is formed on the upper surface 151a of the second portion 151, this step restricts the solder bump from flowing to the periphery and prevents an electrical short circuit between the adjacent conductor pads 130. can do.

<Fourth embodiment>
FIG. 10 is a schematic cross-sectional view showing a printed wiring board according to the fourth embodiment. The printed wiring board 6 according to the present embodiment is disposed below the first buildup layer 6A and the first buildup layer 6A, and is formed integrally with the first buildup layer 6A. And an up layer 6B. The first buildup layer 6A has a structure similar to that of the printed wiring board 1 described above.

  The second buildup layer 6B is a buildup wiring board in which conductor layers 61 and insulating layers 62 are alternately laminated on both sides of the core substrate 60 so as to sandwich the core substrate 60 disposed in the middle. . A through-hole conductor 66 that penetrates the core substrate 60 is provided inside the core substrate 60.

  The conductor layer 61 is formed to include a plurality of conductor pads 63 and wirings 64 disposed between the conductor pads 63. A plurality of via conductors 65 for electrically connecting the conductor pads 63 adjacent in the stacking direction are formed in the insulating layer 62. The conductor layer 61 and the via conductor 65 are formed of an electroless plating layer 61a and an electrolytic plating layer 61b, respectively. In this case, the conductor layer 61 and the via conductor 65 may be formed of a metal seed layer and an electroless plating layer in the same manner as the conductor member 15 described above. On the other hand, the insulating layer 62 is formed of, for example, a curable resin.

  The first buildup layer 6A is stacked on the insulating layer 62 positioned at the uppermost layer of the second buildup layer 6B. The conductor pads 110 of the first buildup layer 6A are electrically connected to the conductor pads 63 located at the uppermost layer of the second buildup layer 6B via the via conductors 19 formed inside the insulating layer 10. Yes.

  In the stacking direction, the conductor member 15 and via conductor 19 of the first buildup layer 6A and the via conductor 65 of the second buildup layer 6B are stacked in a straight line to form a stack structure. In the present embodiment, the conductor member 15 and the via conductors 19 and 65 all have a stack structure, but in order to avoid stress concentration, for example, the positions of the conductor member 15 and the via conductors 19 and 65 are aligned along the stacking direction. The offset structure may be formed by stacking while shifting, or a part may be a stack structure and the other part may be an offset structure.

  In the present embodiment, the first buildup layer 6A has a conductor circuit with a higher density than the second buildup layer 6B. Specifically, the width (L) and interval (S) of the wiring 111 of the first buildup layer 6A are smaller than L and S of the wiring 64 of the second buildup layer 6B. Preferably, L / S of the wiring 111 of the first buildup layer 6A is 1 μm / 1 μm to 10 μm / 10 μm.

  Since the printed wiring board 6 configured in this way has the same structure as the above-described printed wiring board 1 in the first buildup layer 6A, the same effects as those of the first embodiment can be obtained. In addition, the printed wiring board 6 of this embodiment is produced by the following method, for example. That is, the core substrate 60 is prepared first, and the second buildup layer 6B is produced by laminating the insulating layer 62 and the conductor layer 61 on the upper and lower main surfaces of the core substrate 60 by a semi-additive method. Next, using the produced second buildup layer 6B as a support plate, the first buildup layer 6A is produced on the second buildup layer 6B by the same method as the printed wiring board 1 described above.

<Fifth Embodiment>
FIG. 11 is a schematic sectional view showing a printed wiring board according to the fifth embodiment. The printed wiring board 7 according to the present embodiment is arranged below the first buildup layer 7A and the first buildup layer 7A, and the second build formed integrally with the first buildup layer 7A. And an up layer 7B. The first buildup layer 7A has the same structure as the printed wiring board 1 described above.

  The second buildup layer 7B is a coreless substrate having no so-called core substrate, and is formed by alternately laminating a plurality of conductor layers 71 and insulating layers 72 in one direction. The conductor layer 71 is formed to include a plurality of conductor pads 73 and wirings 74 disposed between the conductor pads 73. A plurality of via conductors 75 are formed in the insulating layer 72 to electrically connect the conductor pads 73 adjacent to each other in the stacking direction of the insulating layer 72. The conductor layer 71 and the via conductor 75 are formed of an electroless plating layer 71a and an electrolytic plating layer 71b, respectively. In this case, the conductor layer 71 and the via conductor 75 may be formed of a metal seed layer and an electroless plating layer in the same manner as the conductor member 15 described above. On the other hand, the insulating layer 72 is made of, for example, a curable resin.

  The first buildup layer 7A is stacked on the insulating layer 72 located at the uppermost layer of the second buildup layer 7B. The conductor pad 110 of the first buildup layer 7A is electrically connected to the conductor pad 73 located at the uppermost layer of the second buildup layer 7B via the via conductor 19 formed in the insulating layer 10. Yes.

  In the stacking direction, the conductor member 15 and via conductor 19 of the first buildup layer 7A and the via conductor 75 of the second buildup layer 7B are stacked in a straight line to form a stack structure. In order to avoid stress concentration, the conductor member 15 and the via conductors 19 and 75 may have an offset structure. In the present embodiment, the first buildup layer 7A has a conductor circuit with a higher density than the second buildup layer 7B. L and S of the wiring 111 of the first buildup layer 7A are smaller than those of the second buildup layer 7B. Preferably, L / S of the wiring 111 of the first buildup layer 7A is 1 μm / 1 μm to 10 μm / 10 μm.

  The printed wiring board 7 configured in this way has the same structure and effect as the first embodiment because the first buildup layer 7A has the same structure as the printed wiring board 1 described above. In addition, the printed wiring board 7 of this embodiment is produced by the following method, for example. That is, the second buildup layer 7B is first produced on a plate-like support member by a semi-additive method, and the produced second buildup layer 7B is used as a support plate, which is the same as the printed wiring board 1 described above. The first buildup layer 7A is produced on the second buildup layer 7B by the method, and finally the support member is peeled off.

  Although the embodiments of the present invention have been described in detail above, the present invention is not limited to the above-described embodiments, and various designs can be made without departing from the spirit of the present invention described in the claims. It can be changed. For example, the metal seed layers 11a and 13a may be formed by a sputtering method in addition to the electroless plating method described above.

1, 2, 5, 6, 7 Printed wiring board 10 Insulating layer 11 Conductor layer (first conductor layer)
11a, 13a Metal seed layers 11b, 13b Electroless plating layer 12 Insulating layer (first insulating layer)
13 Conductor layer (second conductor layer)
14 Insulating layer (second insulating layer)
14a Upper surface 15 Conductive member 16, 18 Through hole 17 Electrode 20 Support plate 21 Peeling layer 22, 24 Resist pattern 23 Resist layer 27 Resist post 110 Conductor pad (first conductor pad)
130 Conductor pad (second conductor pad)
150 First portion 151 Second portion 151a Upper surface S1, S2 space

Claims (11)

A printed wiring board having a plurality of conductor layers and insulating layers,
A first conductor layer including a first conductor pad;
A first insulating layer laminated on the first conductor layer so as to cover the first conductor layer;
A second conductor layer formed on the first insulating layer and including a second conductor pad;
A second insulating layer laminated on the first insulating layer so as to surround the second conductor layer;
A conductor member formed integrally over the first insulating layer and the second insulating layer;
With
The conductor member is formed of a metal seed layer and an electroless plating layer,
The conductor member penetrates the first insulating layer, and is electrically connected to the first conductor pad; the conductor member penetrates the second insulating layer; and is juxtaposed with the second conductor layer. A second part,
The upper surface of the second part is exposed to the outside. In the printed wiring board of Claim 1,
The upper surface of the second portion of the conductor member is located in the same plane as the upper surface of the second insulating layer. In the printed wiring board of Claim 1,
The upper surface of the second portion of the conductor member is lower than the upper surface of the second insulating layer. In the printed wiring board as described in any one of Claims 1-3,
The first conductor layer is formed of a metal seed layer and an electroless plating layer. In the printed wiring board as described in any one of Claims 1-3,
The first conductor layer is formed of a seed layer and an electrolytic plating layer. In the printed wiring board as described in any one of Claims 1-5,
The second insulating layer is an interlayer insulating layer. A method of manufacturing a printed wiring board,
Forming a first insulating layer made of an insulating material;
Forming a through hole penetrating the first insulating layer, and forming a metal seed layer on a surface of the first insulating layer and an inner wall surface of the through hole;
Forming a resist layer on the metal seed layer and subjecting the resist layer to exposure and development to form a resist pattern and a resist post that covers the through hole;
Removing the metal seed layer in portions where the resist pattern and the resist post are not formed;
Laminating a second insulating layer covering the resist pattern and the resist post on the first insulating layer;
Exposing the resist pattern and the resist post by irradiating the surface of the second insulating layer with plasma, and further removing the resist pattern and the resist post by plasma irradiation;
Forming an electroless plating layer on the metal seed layer exposed by removing the resist pattern and the resist post;
Is provided. In the manufacturing method of the printed wiring board according to claim 7,
Before the step of forming the electroless plating layer, the method further includes a step of roughening a peripheral wall of a space formed in the second insulating layer by removing the resist pattern and the resist post. In the manufacturing method of the printed wiring board according to claim 7 or 8,
In the step of forming the electroless plating layer, the electroless plating layer is formed so that the upper surface of the formed electroless plating layer and the upper surface of the second insulating layer are aligned on the same plane. In the manufacturing method of the printed wiring board as described in any one of Claims 7-9,
For the plasma irradiation, O ₂ plasma or H ₂ plasma is used. In the manufacturing method of the printed wiring board as described in any one of Claims 7-10,
The metal seed layer is formed by an electroless plating method or a sputtering method.

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