JP7132799B2 - Imaging device, imaging device, and imaging method - Google Patents

Description

The present invention relates to an imaging element, an imaging apparatus, and an imaging method.

CCD image sensors and CMOS image sensors are widely known as image sensors using semiconductors. A CCD image sensor and a CMOS image sensor convert light incident on a pixel during an exposure period into an electric charge using a photodiode, and output a signal corresponding to the electric charge.

In recent years, there has been proposed a photon counting type image sensor that counts the number of photons incident on a photodiode during an exposure period and outputs the photon count value as a signal value. For example, Patent Literature 1 discloses a solid-state imaging device using an avalanche photodiode and a counter. When a reverse bias voltage higher than the breakdown voltage is applied to the avalanche photodiode, carriers generated by incident single photons cause avalanche multiplication and a large current flows through the avalanche photodiode. A signal corresponding to the number of single photons can be obtained by counting the pulse signal corresponding to the incident single photons with a counter. Since the photon counting type image sensor uses the number of photons incident on the photodiode as a signal value as it is, it is less susceptible to noise than the CCD image sensor and the CMOS image sensor. Therefore, the photon-counting image sensor can obtain a good image even in a weak light environment.

JP-A-61-152176

However, there is a concern that the proposed technique does not always provide an image with good gradation.

SUMMARY OF THE INVENTION An object of the present invention is to provide an imaging element, an imaging apparatus, and an imaging method capable of obtaining an image with good gradation.

According to one aspect of the embodiment, a plurality of pixels each provided with a sensor section that emits pulses at a frequency corresponding to the frequency of photon reception and a counter that counts the number of pulses of the signal emitted from the sensor section. a detection unit for detecting whether the count value of the counter provided in one of the plurality of pixels reaches a first threshold value; and the detection unit provided in one of the plurality of pixels. an integrator that integrates a signal based on the count value for each of the plurality of pixels when it is detected that the count value of the counter reaches the first threshold value. An imaging device is provided.

According to the present invention, it is possible to provide an imaging element, an imaging apparatus, and an imaging method capable of obtaining an image with good gradation.

1 is a block diagram showing an imaging device according to a first embodiment; FIG. It is a figure which shows the solid-state image sensor by 1st Embodiment. It is a figure which shows the unit pixel with which the solid-state image sensor by 1st Embodiment was equipped. It is a figure which shows operation|movement of a sensor part. It is a figure which shows the example of the layout of the solid-state image sensor by 1st Embodiment. 4 is a timing chart showing an example of operation of the solid-state imaging device according to the first embodiment; It is a figure which shows the solid-state image sensor by 2nd Embodiment. It is a figure which shows the unit pixel with which the solid-state image sensor by 2nd Embodiment was equipped. 9 is a timing chart showing an example of operation of the solid-state imaging device according to the second embodiment; It is a figure which shows the solid-state image sensor by 3rd Embodiment. It is a figure which shows the unit pixel with which the solid-state image sensor by 3rd Embodiment was equipped. It is a figure which shows the unit pixel with which the solid-state image sensor by 4th Embodiment was equipped. FIG. 12 is a block diagram showing an imaging device according to a fifth embodiment; FIG. It is a figure which shows the solid-state image sensor by 5th Embodiment. FIG. 11 is a diagram showing an example of a photometry area of a photometry unit according to the fifth embodiment; FIG. 12 is a diagram showing an example of an image acquired by a solid-state imaging device according to the fifth embodiment; FIG. FIG. 16 is a flow chart showing the flow of control of the imaging device according to the fifth embodiment; FIG. FIG. 16 is a flow chart showing another control flow of the imaging device according to the fifth embodiment; FIG. FIG. 12 is a block diagram showing an imaging device according to a sixth embodiment; FIG. FIG. 16 is a flow chart showing the flow of control of the imaging device according to the sixth embodiment; FIG. FIG. 16 is a flow chart showing another control flow of the imaging device according to the sixth embodiment; FIG. FIG. 16 is a flowchart showing yet another control flow of the imaging device according to the sixth embodiment; FIG. FIG. 12 is a block diagram showing an imaging device according to a seventh embodiment; FIG. FIG. 16 is a flow chart showing the flow of control of the imaging device according to the seventh embodiment; FIG. FIG. 12 is a block diagram showing an imaging device according to an eighth embodiment; FIG. FIG. 16 is a flow chart showing the flow of control of the imaging device according to the eighth embodiment; FIG.

An embodiment of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited to the following embodiments, and can be modified as appropriate. Also, the embodiments shown below may be combined as appropriate.

[First embodiment]
A solid-state imaging device, an imaging apparatus, and an imaging method according to the first embodiment will be described with reference to FIGS. 1 to 6. FIG. FIG. 1 is a block diagram showing an imaging device according to this embodiment. As shown in FIG. 1, an imaging device 120 according to this embodiment includes a solid-state imaging device 100, a signal processing unit 101, a lens driving unit 103, a control unit 104, a memory unit 105, a display unit 106, and a recording unit. A unit 107 and an operation unit 108 are provided. The imaging device 120 also includes a photographing lens (imaging optical system, lens unit) 102 . The imaging lens 102 may be detachable from the body (main body) of the imaging device 120, or may be non-detachable.

The solid-state imaging device 100 generates an imaging signal by photoelectrically converting an optical image of a subject formed by the imaging lens 102, and outputs the generated imaging signal. A unit pixel 201 (see FIG. 2) provided in the solid-state imaging device 100 is provided with a photodiode 303 (see FIG. 3) and a counter 306 (see FIG. 3) to count the number of incident photons. can be output as a signal value. Also, in this embodiment, the count value of the counter 306 is not saturated during the exposure period. Details of this point will be described later with reference to FIGS.

The imaging lens 102 forms an optical image of a subject on the imaging surface of the solid-state imaging device 100 . A lens drive unit 103 drives the photographing lens 102, and performs zoom control, focus control, aperture control, and the like. The photographing lens 102 forms an optical image of a subject and causes the formed optical image to enter the imaging surface of the solid-state imaging device 100 .

The signal processing unit 101 performs predetermined signal processing (image processing) such as correction processing on an image signal (image data) output from the solid-state imaging device 100 .

A control unit (overall control/calculation unit, control means) 104 controls the entire imaging device 120 and performs predetermined calculation processing and the like. The control unit 104 outputs control signals for driving each functional block of the imaging device 120, control data for controlling the solid-state imaging device 100, and the like. The control unit 104 performs predetermined signal processing (image processing) such as development and compression on the imaging signal that has been subjected to signal processing by the signal processing unit 101 .

A memory unit 105 temporarily stores image data and the like.

A display unit 106 displays an imaging signal subjected to signal processing by the control unit 104, various setting information of the imaging apparatus 120, and the like.

A recording unit (recording control unit) 107 is provided with a recording medium (not shown). Such a recording medium may be removable from the recording unit 107 or may be non-removable. A recording unit 107 records an imaging signal or the like subjected to signal processing or the like by the control unit 104 on a recording medium. Examples of such recording media include semiconductor memories such as flash memories.

An operation unit 108 is used to set an imaging mode, an accumulation period, and the like, and accepts operation inputs from the user. The operation unit 108 is composed of buttons, dials, and the like, for example. Note that when the display unit 106 is a touch panel, the touch panel also corresponds to the operation unit 108 .

FIG. 2 is a diagram showing a solid-state imaging device according to this embodiment. As shown in FIG. 2, the solid-state imaging device 100 includes a pixel array 200, a vertical control circuit 202, a horizontal control circuit 203, a timing generator (TG) 204, a saturation detection section 205, a frame memory 206, an addition circuit 207, and a digital An output unit 208 is provided.

A plurality of unit pixels (pixels) 201 are arranged in a matrix in a pixel array (pixel array region) 200 . Although the arrangement of 4×4 unit pixels 201 is shown here for the sake of simplicity of explanation, in reality, a large number of unit pixels 201 are arranged in the pixel array 200 . The unit pixel 201 can count photons incident on the unit pixel 201 and output a digital signal obtained by counting. Details of this point will be described later with reference to FIG.

The saturation detection unit 205 detects that the photon count value reaches a predetermined threshold value Cth during the exposure period in any one of the plurality of unit pixels 201 provided in the pixel array 200 . Upon detecting that the photon count value has reached the threshold value Cth in any one of the plurality of unit pixels 201 , the saturation detection unit 205 supplies information to that effect to the timing generator 204 .

The unit pixel 201 whose photon count value has reached the threshold value Cth sends a threshold reaching signal PSAT (see FIG. 3), which is a signal indicating that the photon count value has reached the threshold value Cth, to the saturation detection unit via the wiring 212 . 205. The threshold reaching signal PSAT is transmitted to the saturation detector 205 via a common wiring 212 provided for each row. A pull-up resistor 211 is connected to each wiring 212 . One end of the pull-up resistor 211 is connected to the wiring 212, and the other end of the pull-up resistor 211 is connected to the power supply voltage VDD.

Although the case where the threshold reaching signal PSAT is output to the saturation detection unit 205 via the common wiring 212 provided for each row has been described as an example, the present invention is not limited to this. For example, the threshold reaching signal PSAT may be transmitted to the saturation detection section 205 via a common wiring provided for each column. Alternatively, the threshold reaching signal PSAT may be output to the saturation detection unit 205 via a common wiring for all the unit pixels 201 .

When the threshold reaching signal PSAT is supplied to the saturation detecting unit 205 during the exposure period, the saturation detecting unit 205 detects the threshold reaching signal PSAT and transmits to the timing generator 204 a signal indicating that the threshold reaching signal PSAT has been detected. do. When the timing generator 204 receives a signal indicating that the threshold reaching signal PSAT has been detected from the saturation detection unit 205 , the timing generator 204 outputs a control signal for outputting a pixel signal from each unit pixel 201 to the vertical control circuit 202 and the horizontal control circuit 202 . It is supplied to circuit 203 . Note that the timing generator 204 supplies control signals to the frame memory 206, the adder circuit 207, and the digital output unit 208 via wiring (not shown).

The vertical control circuit 202 selects a plurality of unit pixels 201 provided in the pixel array 200 row by row using a switch 209 . Further, the vertical control circuit 202 supplies a control signal to each of the plurality of unit pixels 201 provided in the pixel array 200 via wiring (not shown). Details of the control signal will be described later with reference to FIG.

The horizontal control circuit 203 selects a plurality of unit pixels 201 provided in the pixel array 200 by a switch 210 in units of columns.

Pixel signals from the unit pixels 201 sequentially selected by the combination of the vertical control circuit 202 and the horizontal control circuit 203 are held in the frame memory 206 .

A frame memory 206 holds a digital pixel signal output from each unit pixel 201 . The frame memory 206 comprises a temporary memory area 206a and an accumulation memory area 206b.

The temporary memory area 206 a temporarily holds the digital pixel signal output from each unit pixel 201 . The accumulation memory area 206b accumulates the pixel signals held in the temporary memory area 206a during the exposure period for each same address (for each same pixel), and holds the pixel signal obtained by the accumulation. The bit width of the pixel signal (data) held in the temporary memory area 206 a can be made equal to the bit width of the digital pixel signal output from the unit pixel 201 . On the other hand, the bit width of the pixel signal held in the integration memory area 206b is sufficiently larger than the bit width of the digital pixel signal output from the unit pixel 201 .

The adder circuit 207 adds the pixel signal held in the integration memory area 206b of the frame memory 206 and the pixel signal newly held in the temporary memory area 206a of the frame memory 206 . The addition circuit 207 performs such addition processing for each same address (for each same pixel). A pixel signal obtained by the addition performed by the addition circuit 207 is held in the integration memory area 206b. Thus, the pixel signal held in the integration memory area 206b is updated.

The digital output unit 208 outputs the pixel signal (image signal, imaging signal) held in the integration memory area 206b of the frame memory 206 to the outside of the solid-state imaging device 100. FIG.

Here, the case where the frame memory 206 and the adder circuit 207 are provided in the solid-state imaging device 100 has been described as an example, but the present invention is not limited to this. The frame memory 206 and the adder circuit 207 may be provided outside the solid-state imaging device 100 .

FIG. 3 is a diagram showing a unit pixel provided in the solid-state imaging device according to this embodiment. As shown in FIG. 3 , the unit pixel 201 includes a sensor portion (light receiving portion) 301 and a counting portion 302 . The sensor section 301 includes a photodiode 303 , a quench resistor 304 and an inverting buffer 305 . Photodiode 303 is an avalanche photodiode. The anode of the photodiode 303 is connected to ground potential, and the cathode of the photodiode 303 is connected to one end of the quench resistor 304 . A bias voltage (reverse bias voltage) Vbias is applied to the other end of the quench resistor 304 . A bias voltage Vbias equal to or higher than the breakdown voltage of the photodiode 303 is applied to the photodiode 303 via the quench resistor 304 . Therefore, the photodiode 303 operates in Geiger mode. That is, when photons enter the photodiode 303, an avalanche multiplication phenomenon occurs. This causes an avalanche current and a voltage drop across quench resistor 304 . A quench resistor 304 is a resistive element for stopping the avalanche multiplication phenomenon of the photodiode 303 . The quench resistor 304 can be constructed using the resistive component of the transistor. When an avalanche current is generated in the photodiode 303 due to the avalanche multiplication phenomenon, a voltage drop occurs in the quench resistor 304 and the reverse bias voltage applied to the photodiode 303 drops. The avalanche multiplication phenomenon stops when the reverse bias voltage drops to the breakdown voltage. As a result, the avalanche current stops flowing, and the bias voltage Vbias is applied to the photodiode 303 again. An inverting buffer 305 is provided to extract the voltage change generated at the quench resistor 304 as a pulse signal PLS. When a photon is incident on the photodiode 303, the inverting buffer 305 outputs a pulse signal PLS. In this manner, the sensor unit 301 emits pulses at a frequency corresponding to the photon reception frequency.

Here, the operation of the sensor unit 301 will be described with reference to FIG. 4A and 4B are diagrams showing the operation of the sensor unit 301. FIG. FIG. 4 shows temporal changes in the cathode terminal voltage Vout when photons are incident on the photodiode 303 and temporal changes in the pulse signal PLS output from the inverting buffer 305 . The horizontal axis of FIG. 4 is time. The cathode terminal voltage Vout is also the magnitude of the reverse bias voltage applied to the photodiode 303 .

At timing t401, the photodiode 303 is applied with a bias voltage Vbias equal to or higher than the breakdown voltage Vbr. Therefore, the photodiode 303 operates in Geiger mode.

At timing t402, when photons enter the photodiode 303, carriers generated in the photodiode 303 cause an avalanche multiplication phenomenon, resulting in an avalanche current. Due to this avalanche current, the cathode terminal voltage Vout of the photodiode 303 connected to the quench resistor 304 begins to drop.

At timing t403, the cathode terminal voltage Vout of the photodiode 303 drops to the threshold Vth, and thereafter the cathode terminal voltage Vout of the photodiode 303 continues to drop. At timing t403 when the cathode terminal voltage Vout of the photodiode 303 drops to the threshold Vth, the pulse signal PLS output from the inverting buffer 305 transitions from L level to H level.

The cathode terminal voltage Vout of the photodiode 303 drops to the breakdown voltage Vbr at timing t404. When the cathode terminal voltage Vout of the photodiode 303 drops to the breakdown voltage Vbr, the avalanche multiplication phenomenon stops. Then, recharging is performed via the quench resistor 304 from the power supply supplying the bias voltage Vbias, so the cathode terminal voltage Vout of the photodiode 303 begins to rise.

At timing t405, the cathode terminal voltage Vout of the photodiode 303 rises to the threshold Vth. At timing t405 when the cathode terminal voltage Vout of the photodiode 303 reaches the threshold Vth, the pulse signal PLS output from the inverting buffer 305 transitions from H level to L level.

Thereafter, at timing t406, recharging is completed. At the stage when recharging is completed, the cathode terminal voltage Vout of the photodiode 303 has returned to the bias voltage Vbias. The time required for recharging depends on the resistance value of the quench resistor 304 and the parasitic capacitance. Thus, one pulse signal PLS having a pulse width ΔTp is output from the sensor section 301 by one incidence of photons.

As shown in FIG. 3 , the counting section 302 includes a counter (counter circuit) 306 , a pixel memory 307 and an inverting buffer 308 .

A pulse signal PLS generated by incident photons on the sensor unit 301 is input to the counter 306, and the counter 306 counts the number of times the pulse signal PLS changes from L level to H level as the number of pulses. A pulse count value by the counter 306 becomes a pixel signal. The counter 306 has an enable control terminal EN for switching between a pulse counting state and a pulse non-counting state. The counter 306 also has a reset terminal RES for resetting the counter 306 . An enable signal PEN is supplied from the vertical control circuit 202 to an enable control terminal EN of the counter 306 . A reset signal PRES is supplied from the vertical control circuit 202 to the reset terminal RES of the counter 306 . When the enable signal PEN supplied to the counter 306 is at H level and the pulse signal PLS changes from L level to H level, the count value of the counter 306 is incremented by one. When enable signal PEN is at the L level, the count value of counter 306 does not increase even if pulse signal PLS changes from the L level to the H level. Also, when the reset signal PRES supplied to the counter 306 changes from L level to H level, the count value of the counter 306 is reset to zero.

A pixel memory 307 temporarily holds a count value, which is a pixel signal counted by the counter 306 . A latch signal PLAT is supplied to the pixel memory 307 from the vertical control circuit 202 . When the latch signal PLAT changes from L level to H level, the pixel memory 307 fetches the count value of the counter 306 and holds the fetched count value. The count value taken into the pixel memory 307 is used as a pixel signal.

A count value (pixel signal) held in the pixel memory 307 of the unit pixel 201 selected by the vertical control circuit 202 and the horizontal control circuit 203 is transmitted to the frame memory 206 .

Note that in the present embodiment, the enable signal PEN, reset signal PRES, and latch signal PLAT are simultaneously supplied from the vertical control circuit 202 to all the unit pixels 201 provided in the pixel array 200 .

The counter 306 has a comparison circuit (not shown). When the count value becomes equal to or greater than a predetermined threshold value Cth, the counter 306 outputs a threshold reaching signal PSAT, which is a signal indicating that the count value has become equal to or greater than the threshold value Cth, via an open-drain output inverting buffer 308 . do. When the count value is less than the threshold value Cth, the threshold reaching signal PSAT output from the counter 306 via the inverting buffer 308 is at high level (H level). On the other hand, when the count value reaches or exceeds the threshold value Cth, the threshold reaching signal PSAT output from the counter 306 via the inverting buffer 308 becomes low level (L level). As described above, the threshold reaching signals PSAT output from the unit pixels 201 located in the same row are output via the common wiring 212 . The wiring 212 is pulled up by a pull-up resistor 211 . Therefore, the threshold reaching signals PSAT output from the respective unit pixels 201 are in a state of wired OR connection.

When the count value is less than the threshold value Cth for any of the plurality of unit pixels 201 located in the same row, the threshold reaching signal PSAT supplied to the saturation detection unit 205 via the wiring 212 is at H level. . On the other hand, when the count value of any one of the plurality of unit pixels 201 located in the same row is equal to or greater than the threshold value Cth, the threshold reaching signal PSAT supplied to the saturation detection unit 205 via the wiring 212 is L. be the level. The saturation detection unit 205 is supplied with threshold reaching signals PSAT from all rows. Therefore, the saturation detection unit 205 can detect that the count value of any one of the plurality of unit pixels 201 provided in the pixel array 200 has reached or exceeded the threshold value Cth.

FIG. 5 is a diagram showing an example layout of the solid-state imaging device 100 according to this embodiment. The solid-state imaging device 100 includes a sensor unit substrate 501 on which a plurality of sensor units 301 are arranged in a matrix, a counting unit substrate 502 on which a plurality of counting units 302 are arranged in a matrix, and a frame on which a frame memory 206 is arranged. It has a configuration in which the memory substrate 503 is laminated. Electrodes (not shown) provided on the sensor board 501 and electrodes (not shown) provided on the counting board 502 are electrically connected to each other. Electrodes (not shown) provided on the counting section substrate 502 and electrodes (not shown) provided on the frame memory substrate 503 are electrically connected to each other. Thus, the pulse signal PLS output from the sensor section 301 provided on the sensor section board 501 is input to the counting section 302 provided on the counting section board 502 . The counting unit board 502 is provided with a vertical control circuit 202 , a horizontal control circuit 203 , a timing generator 204 and a saturation detection unit 205 . The frame memory board 503 is provided with a frame memory 206 , an adder circuit 207 and a digital output section 208 . Since the sensor section 301 and the counting section 302 are provided on separate substrates, a large area for the sensor section 301 can be secured. Also, if the frame memory substrate 503 is manufactured in a finer process than the sensor substrate 501 and the counter substrate 502, data with a sufficiently large bit width can be recorded in the frame memory 206. FIG. Note that the configuration of the solid-state imaging device 100 is not limited to the configuration described above. For example, the sensor section 301 and the counting section 302 may be provided on the same substrate.

FIG. 6 is a timing chart showing an example of the operation of the solid-state imaging device according to this embodiment. Here, a case of obtaining an image of one frame out of a plurality of frames forming a moving image will be described as an example, but the present invention is not limited to this.

At timing t<b>601 , when the user or the like issues an instruction to start imaging via the operation unit 108 , the control unit 104 supplies a pulsed imaging start signal START to the solid-state imaging device 100 . When the imaging start signal START becomes H level, the timing generator 204 supplies the bias voltage Vbias to the sensor section 301 . When the bias voltage Vbias is supplied to the sensor unit 301, a reverse bias voltage higher than the breakdown voltage of the photodiode 303 is applied to the photodiode 303, and the photodiode 303 operates in the Geiger mode. As a result, the sensor unit 301 outputs the pulse signal PLS according to the photons incident on the photodiode 303 . FIG. 6 shows pulse signals output from the sensor units 301 of arbitrary three unit pixels 201 out of a plurality of unit pixels 201 provided in the pixel array 200, that is, the unit pixels A, B, and C, respectively. PLS_A, PLS_B, PLS_C are shown. In this example, the number of photons incident on the unit pixel A is greater than the number of photons incident on the unit pixel C, and the number of photons incident on the unit pixel C is greater than the number of photons incident on the unit pixel B. explain.

Count values COUNT_A, COUNT_B, and COUNT_C shown in FIG. 6 indicate count values obtained by the counters 306 of the unit pixels A, B, and C, respectively. The counter 306 can count from a lower count value of 0 to an upper count value of Cmax. When the count value of the counter 306 reaches or exceeds the threshold Cth, the threshold reaching signal PSAT output from the unit pixel 201 including the counter 306 whose count value reaches or exceeds the threshold Cth changes from H level to L level. As a result, the potential of the wiring 212 provided in the row where the unit pixel 201 is located changes from H level to Low level. Threshold reaching signal PSAT that has changed from H level to L level is detected by saturation detection section 205 . Threshold reaching signals PSAT_A, PSAT_B, and PSAT_C indicate the threshold reaching signals PSAT in the rows in which the respective unit pixels A, B, and C are provided.

At timing t601, the reset signal PRES is at H level. Also, the counter 306 of each unit pixel 201 is reset to 0 at timing t601.

At timing t602, the timing generator 204 simultaneously supplies the L-level reset signal PRES to all the rows of the pixel array 200. FIG. As a result, resetting of the counters 306 of all the unit pixels 201 provided in the pixel array 200 is released. Also, the timing generator 204 supplies an H-level enable signal PEN to all the rows of the pixel array 200 . As a result, the counters 306 of all the unit pixels 201 provided in the pixel array 200 are enabled, and the counter 306 of each unit pixel 201 increases the count value according to the input pulse signal PLS. . In this way, imaging of one frame out of a plurality of frames forming a moving image is started. After that, counting in the frame continues until timing t608 when the enable signal PEN changes to L level. Therefore, the period from timing t602 to timing t608 corresponds to the exposure period. Since the unit pixel A has the highest incidence of photons, the increase rate of the count value COUNT_A is the highest.

At timing t603, when the count value COUNT_A reaches the threshold Cth, the threshold reaching signal PSAT_A of the row in which the unit pixel A is provided becomes L level. When saturation detection section 205 detects that threshold attainment signal PSAT of any row has changed to L level, saturation detection section 205 transmits a signal indicating that threshold attainment signal PSAT has been detected to timing generator 204 . When timing generator 204 receives a signal indicating that threshold reached signal PSAT has been detected, timing generator 204 operates as follows. That is, the timing generator 204 supplies a control signal to the vertical control circuit 202 so that the latch signal PLAT supplied from the vertical control circuit 202 to all the unit pixels 201 becomes H level all at once. Thereby, the count value of the counter 306 provided for each unit pixel 201 is held in the pixel memory 307 corresponding to each counter 306 .

At timing t604, when the reset signal PRES becomes H level, the count value of the counter 306 of each unit pixel 201 is reset to zero. Then, when the reset signal PRES returns to L level, the reset of the counter 306 is released, and the counter 306 of each unit pixel 201 starts counting according to incident photons again. Also, since the count value of the unit pixel A is reset to 0, the threshold reaching signal PSAT_A returns from L level to H level.

At timing t<b>605 , the timing generator 204 starts supplying the signal VCLK to the vertical control circuit 202 . Each time the signal VCLK becomes H level, the switches 209 in each row are sequentially turned on, and the vertical control circuit 202 selects the plurality of unit pixels 201 provided in the pixel array 200 row by row. When an arbitrary row is selected by the vertical control circuit 202, a signal HCLK is supplied from the timing generator 204 to the horizontal control circuit 203 to sequentially turn on the switches 210 of each column. As a result, the count values (pixel signals) held in the pixel memory 307 of the unit pixels 201 in the selected row are sequentially stored in the temporary memory area 206 a of the frame memory 206 . The adder circuit 207 adds the pixel signal held in the temporary memory area 206a of the frame memory 206 and the pixel signal of the same address held in the integration memory area 206b of the frame memory 206 . Then, the addition circuit 207 stores the pixel signal obtained by the addition again in the integration memory area 206b. Note that addition processing is performed by the addition circuit 207 in parallel with holding of the pixel signal by the frame memory 206 . No pixel signal is held in the integration memory area 206b of the frame memory 206 in the addition processing performed at timings t605 to t606, that is, in the first addition processing. Therefore, the pixel signal output from each unit pixel 201 and stored in the temporary memory area 206a is held as it is in the integration memory area 206b.

At timing t607, when the count value COUNT_A reaches the threshold Cth again, the threshold reaching signal PSAT_A becomes L level. Then, the pixel signal of each unit pixel 201 is stored in the temporary memory area 206a of the frame memory 206 in the same manner as during timings t603 to t606. Then, the pixel signal stored in the temporary memory area 206a and the pixel signal held in the integration memory area 206b are added, and the pixel signal obtained by the addition is stored in the integration memory area 206b. After that, the same processing as described above is repeated each time the count value of any unit pixel 201 reaches the threshold value Cth during the exposure period.

In this manner, the count values (pixel signals) held in the pixel memory 307 of each unit pixel 201 are sequentially stored in the temporary memory area 206a of the frame memory 206 between timings t605 and t606. The process of storing the count value held in the pixel memory 307 of each unit pixel 201 in the temporary memory area 206a of the frame memory 206 is completed before the timing t607 when the count value of the unit pixel 201 reaches the threshold value Cth again. preferably. Assuming that the pulse width of the pulse signal PLS is ΔTp, the shortest time required for the count value to reach the threshold value Cth from 0 is ΔTp×Cth. Therefore, the frequencies of the signals VCLK and HCLK can be set so that the process of storing the count value of each unit pixel 201 in the temporary memory area 206a of the frame memory 206 is completed in a time shorter than (ΔTp×Cth). preferable. Also, the threshold value Cth of the counter 306 is set so that (ΔTp×Cth) is longer than the time required to store the count value of each unit pixel 201 in the temporary memory area 206a of the frame memory 206. good too.

At timing t608, when the exposure period ends, the enable signal PEN becomes L level. As a result, the counter 306 of each unit pixel 201 is disabled, and even if the pulse signal PLS is input to the counter 306, the count value does not increase. Further, the bias voltage Vbias is no longer supplied to the sensor section 301, and the sensor section 301 no longer outputs the pulse signal PLS.

After that, the timing generator 204 performs the following processing to store the count value of the counter 306 at the end of exposure in the frame memory 206 . That is, the timing generator 204 changes the latch signal PLAT from L level to H level at timing t609. When the latch signal PLAT changes from L level to H level, the pixel memory 307 fetches the count value of the counter 306 and holds the fetched count value. After that, the latch signal PLAT supplied from the timing generator 204 is returned from H level to L level. The timing generator 204 also sets the reset signal PRES to H level and resets the count value of the counter 306 to zero.

At timings t610 to t611, the pixel signal of each unit pixel 201 is held in the temporary memory area 206a of the frame memory 206, as at timings t605 to t606. Then, the pixel signal added by the adder circuit 207 is held in the accumulation memory area 206b of the frame memory 206. FIG. The pixel signal held in the integration memory area 206b is a signal obtained by integrating the pixel signal acquired from the pixel memory 307 by the addition circuit 207 during the exposure period from timing t602 to t608. The pixel signal thus obtained is a signal corresponding to the number of incident photons during the exposure period. Thus, according to this embodiment, it is possible to prevent the count value of the counter 306 from saturating during the exposure period.

It should be noted that while the pixel signals held in the pixel memory 307 are being sequentially transmitted to the temporary memory area 206a of the frame memory 206, the exposure end timing t608 may come. In such a case, after the pixel signal held in the pixel memory 307 of each unit pixel 201 is stored in the temporary memory area 206a of the frame memory 206, the count value of the counter 306 at the end of exposure is changed to the pixel. It may be stored in the memory 307 .

The control signal OUTCLK is supplied from the timing generator 204 to the digital output section 208 at timings t612 to t613. As a result, the pixel signals held in the integration memory area 206b of the frame memory 206, that is, the pixel signals integrated during the exposure period are sequentially output to the outside of the solid-state imaging device 100 via the digital output unit 208. When the output of the pixel signal to the outside of the solid-state imaging device 100 is completed, the pixel signal held in the integration memory area 206b of the frame memory 206 is reset to zero.

Thus, in the present embodiment, each time the count value of the counter 306 of each unit pixel 201 reaches the threshold value Cth, the count value acquisition and reset operation are performed. Therefore, according to this embodiment, it is possible to prevent the count value from saturating during the exposure period, and to obtain an image with good gradation.

As described above, when the latch signal PLAT becomes H level at timing t603, the count value of the counter 306 is held in the pixel memory 307. FIG. Then, at timing t604, the reset signal PRES changes from L level to H level, and the counter 306 is reset. Then, when the reset signal PRES returns from H level to L level, the reset of the counter 306 is released. In this manner, the number of pulse signals PLS cannot be counted by the counter 306 during the period from the timing t603 when the latch signal PLAT becomes H level to the timing when the reset of the counter 306 is released. This corresponds to shortening the exposure period by the period. Therefore, the exposure period may be extended by this period.

Further, the solid-state imaging device 100 may be driven in a drive mode (second drive mode) different from the drive mode (first drive mode) shown in FIG. In the second drive mode, for example, the operation of the saturation detector 205 is disabled. In the second drive mode, the count value counted by the counter 306 during the exposure period is not output to the frame memory 206 during the exposure period. In the second driving mode, the count value by the counter 306 is output to the frame memory 206 after the exposure period ends. For example, the solid-state imaging device 100 may be driven in the first drive mode under high-illuminance environments, and the solid-state imaging device 100 may be driven in the second drive mode under low-illuminance environments.

[Second embodiment]
A solid-state imaging device, an imaging apparatus, and an imaging method according to the second embodiment will be described with reference to FIGS. 7 to 9. FIG. The same components as those of the solid-state imaging device according to the first embodiment shown in FIGS. 1 to 6 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

In the solid-state imaging device according to this embodiment, the pixel memory 307 (see FIG. 3) is not provided in the counting section 801 of each unit pixel 701 .

FIG. 7 is a diagram showing a solid-state imaging device 100 according to the second embodiment. The pixel array 200 has a plurality of unit pixels 701 . The vertical control circuit 202 selects a plurality of unit pixels 701 provided in the pixel array 200 row by row using the switch 209 . The switch 209 is controlled row by row by a row selection signal PSEL supplied from the vertical control circuit 202 via the wiring 703 .

A column memory 702 is provided between the pixel array 200 and the horizontal control circuit 203 . The column memory 702 temporarily holds the pixel signal of each column output from the unit pixels 701 selected in units of rows by the vertical control circuit 202 .

FIG. 8 is a diagram showing a unit pixel 701 provided in the solid-state imaging device according to this embodiment. As shown in FIG. 8, the unit pixel 701 includes a sensor section 301 and a counting section 801 . The counting unit 801 includes a counter 306 and an inverting buffer 308 . The counting unit 801 is not provided with the pixel memory 307 (see FIG. 3). Since the counting unit 801 is not provided with the pixel memory 307 , in this embodiment, the count value of the counter 306 is held in the column memory 702 on a row-by-row basis without going through the pixel memory 307 .

A reset signal PRES is supplied from the vertical control circuit 202 to a reset terminal RES of the counter 306 on a row-by-row basis. Therefore, the count value of the counter 306 is reset row by row.

FIG. 9 is a timing chart showing the operation of the solid-state imaging device according to this embodiment. Here, a case of obtaining an image of one frame out of a plurality of frames forming a moving image will be described as an example, but the present invention is not limited to this.

FIG. 9 shows two arbitrary unit pixels 701 out of a plurality of unit pixels 701 provided in the pixel array 200, that is, the pulse signals PLS_D output from the sensor units 301 of the unit pixels D and E, respectively. PLS_E is shown. The unit pixel D is arranged in the first row of the pixel array 200 and is read out first when the pixel signal is output. On the other hand, the unit pixel E is arranged in the last row of the pixel array 200 and is read last when the pixel signal is output. Here, the case where the number of photons incident on the unit pixel E is the largest will be described as an example.

Count values COUNT_D and COUNT_E shown in FIG. 9 indicate count values obtained by the counters 306 of the unit pixels D and E, respectively. The counter 306 can count from a lower count value of 0 to an upper count value of Cmax. When the count value of the counter 306 reaches or exceeds the threshold Cth, the threshold reaching signal PSAT output from the unit pixel 701 including the counter 306 whose count value reaches or exceeds the threshold Cth changes from H level to L level. As a result, the potential of the wiring 212 provided in the row where the unit pixel 701 is located changes from H level to Low level. Threshold reaching signal PSAT that has changed from H level to L level is detected by saturation detection section 205 . Threshold reaching signals PSAT_D and PSAT_E indicate the threshold reaching signals PSAT in the rows in which the respective unit pixels D and E are provided. A row selection signal PSEL_D is supplied to the row in which the unit pixels D are arranged, that is, the first row of the pixel array 200 . A row selection signal PSEL_E is supplied to the row in which the unit pixels E are arranged, that is, the last row of the pixel array 200 . When row selection signal PSEL attains H level, switch 209 in the corresponding row is turned on. When the switch 209 is turned on, the count value of the counter 306 of the unit pixel 701 corresponding to the switch 209 is output to the column memory 702 and held by the column memory 702 . The reset signal PRES_D is supplied to the row in which the unit pixels D are arranged, that is, the first row of the pixel array 200 . The reset signal PRES_E is supplied to the row where the unit pixels E are arranged, that is, the last row of the pixel array 200 . When reset signal PRES goes high, the count value of counter 306 in the corresponding row is reset to zero.

The output start signal PVST is a signal for starting outputting the count value obtained in each unit pixel 701 to the column memory 702 and is supplied from the timing generator 204 to the vertical control circuit 202 . When the output start signal PVST changes from L level to H level, the operation of outputting the count value obtained by the counter 306 to the column memory 702 and the operation of resetting the counter 306 are performed in the first row of the pixel array 200. It is done line by line in order from .

At timing t<b>901 , when the user or the like issues an instruction to start imaging via the operation unit 108 , the control unit 104 supplies a pulsed imaging start signal START to the solid-state imaging device 100 . When the imaging start signal START becomes H level, the timing generator 204 supplies the bias voltage Vbias to the sensor section 301 . When the bias voltage Vbias is supplied to the sensor unit 301, a bias voltage higher than the breakdown voltage of the photodiode 303 is applied to the photodiode 303, and the photodiode 303 operates in the Geiger mode. As a result, the sensor unit 301 outputs the pulse signal PLS according to the photons incident on the photodiode 303 .

At timing t901, the reset signal PRES is at H level. Also, the counter 306 of each unit pixel 701 is reset to 0 at timing t901.

At timing t902, the timing generator 204 simultaneously supplies the L-level reset signal PRES to all the rows of the pixel array 200. FIG. As a result, resetting of the counters 306 of all the unit pixels 701 provided in the pixel array 200 is released. Also, the timing generator 204 supplies an H-level enable signal PEN to all the rows of the pixel array 200 . As a result, the counters 306 of all the unit pixels 701 provided in the pixel array 200 are enabled, and the counter 306 of each unit pixel 701 increases the count value according to the input pulse signal PLS. . After that, counting in the frame continues until timing t909 when the enable signal PEN changes to L level. Therefore, the period from timing t902 to timing t909 corresponds to the exposure period. Since the unit pixel E has the highest incidence of photons, the increase rate of the count value COUNT_E is the highest.

At timing t903, when the count value COUNT_E reaches the threshold Cth, the threshold reaching signal PSAT_E of the row in which the unit pixel E is provided becomes L level. When the saturation detection unit 205 detects that the threshold reaching signal PSAT of any row has changed to the L level, it outputs a pulse-shaped output start signal PVST, thereby starting the operation of reading out pixel signals.

At timing t904, when the pulse-shaped row selection signal PSEL_D is supplied to the first row of the pixel array 200, each unit pixel arranged in the first row, which is the row in which the unit pixel D is arranged, is selected. The count value of 701 is output to column memory 702 . Then, when the pulse-like reset signal PRES_D is supplied to the first row of the pixel array 200, each unit pixel 701 arranged in the first row, which is the row in which the unit pixel D is arranged, is counted. The value is reset to 0. In parallel with this operation, the signal HCLK is supplied from the timing generator 204 to the horizontal control circuit 203 to sequentially turn on the switches 210 in each column. As a result, the count value held in the column memory 702, that is, the pixel signal acquired by the unit pixel 701 located in the first row is sequentially output to the frame memory 206, and the pixel signal is output to the frame memory 206. is held in the temporary memory area 206a.

When all the pixel signals obtained by the unit pixels 701 located in the first row are transferred from the column memory 702 to the frame memory 206, the pulse-like row selection signal PSEL is applied to the second row of the pixel array 200. After that, the same operations as described above are sequentially performed. That is, an operation of outputting the count value obtained by the counter 306 to the column memory 702 and an operation of resetting the counter 306 are sequentially performed. Such operations are repeated until the last row of the pixel array 200 . In parallel with storing the pixel signal in the frame memory 206, the addition circuit 207 performs the following processing. That is, the adding circuit 207 performs addition processing of the pixel signal held in the temporary memory area 206a of the frame memory 206 and the pixel signal of the same address held in the integration memory area 206b of the frame memory 206. FIG. The pixel signal obtained by the addition by the adder circuit 207 is held in the accumulation memory area 206b of the frame memory 206. FIG.

At timing t905, when the pulse-like row selection signal PSEL_E is supplied to the last row of the pixel array 200, the count value of each unit pixel 701 arranged in the last row, which is the row in which the unit pixel E is arranged, is displayed in the column. Output to memory 702 . Then, at timing t906, when the pulse-like reset signal PRES_E is supplied to the last row of the pixel array 200, the count value of each unit pixel 701 arranged in the last row, which is the row in which the unit pixel E is arranged, is changed to Reset to 0. At timing t906, the threshold reaching signal PSAT_E of the last row, which is the row in which the unit pixel E is arranged, returns from L level to H level.

At timing t<b>907 , pixel signals output from the unit pixels 701 located in the last row of the pixel array 200 are stored in the frame memory 206 . When the adding circuit 207 completes the addition processing of the pixel signals output from the unit pixels 701 located in the last row of the pixel array 200, the pixel signals output from all the unit pixels 701 of the pixel array 200 are stored in the frame memory 206. Storing to is completed.

During the period from timing t903 to t907, the pixel signal output from the unit pixel 701 is not completely stored in the frame memory 206, so the timing generator 204 sends a new output start signal PVST to the vertical control circuit 202. do not supply.

In addition processing performed at timings t904 to t907, that is, in the first addition processing, the integration memory area 206b of the frame memory 206 does not hold pixel signals. Therefore, the pixel signal output from each unit pixel 701 and stored in the temporary memory area 206a is held as it is in the integration memory area 206b.

At timing t908, when the count value COUNT_E reaches the threshold Cth again, the threshold reaching signal PSAT_E for the row in which the unit pixel E is provided becomes L level. Then, the pixel signal of each unit pixel 701 is stored in the temporary memory area 206a of the frame memory 206 in the same manner as the processing at timings t903 to t907. Then, the pixel signal stored in the temporary memory area 206a and the pixel signal held in the integration memory area 206b are added by the addition circuit 207, and the pixel signal obtained by the addition is stored in the integration memory area 206b. After that, the same processing as described above is repeated every time the count value of any unit pixel 701 reaches the threshold value Cth during the exposure period.

Note that the count value COUNT_E of the unit pixels E arranged in the last row of the pixel array 200 continues to increase until timing t906 according to the number of incident photons even after reaching the threshold value Cth at timing t903. That is, the count value of the counter 306 increases until the pixel signal output from the unit pixel 701 arranged in the last row of the pixel array 200 is completely stored in the frame memory 206 and the counter 306 is reset. Before the pixel signals of all the unit pixels 701 provided in the pixel array 200 are completely stored in the frame memory 206, the count value of the unit pixels 701 in the last row does not reach the count upper limit value Cmax. The threshold Cth is set so as to satisfy the following formula (1).

Cth<Cmax−Trd/ΔTp (1)

Here, Trd corresponds to the period from timing t903 to timing t906. That is, Trd is a period from the timing when the output start signal PVST is supplied until the reset signal PRES_E is supplied to the unit pixels 701 located in the last row of the pixel array 200 . ΔTp is the minimum pulse width of pulse signal PLS output from sensor section 301 .

Although the threshold value Cth is uniformly set in (1) above, the present invention is not limited to this. For example, the threshold value Cth may be different for each row, as shown in Equation (2) below.

Cth(n)<Cmax−T1h×n/ΔTp (2)

Here, n indicates the nth row. Cth(n) indicates the threshold value Cth of the nth row. T1h indicates the time required to transfer the pixel signals for one row to the frame memory 206. FIG. That is, T1h corresponds to the time from when the row selection signal PSEL for a certain row goes high to when the row selection signal PSEL for the next row goes high.

At timing t909, when the exposure period ends, the enable signal PEN becomes L level. As a result, the count value of each unit pixel 701 does not increase even when photons enter the unit pixel 701 . At timing t909, the bias voltage Vbias is no longer supplied to the sensor unit 301, and the sensor unit 301 no longer outputs the pulse signal PLS.

After that, the timing generator 204 performs the following processing to store the count value of the counter 306 at the end of exposure in the frame memory 206 . That is, the timing generator 204 outputs the pulse-like output start signal PVST at timing t910. As a result, the pixel signal of each unit pixel 701 is held in the temporary memory area 206a of the frame memory 206 in the same manner as timings t903 to t907. Then, the pixel signal added by the adder circuit 207 is held in the accumulation memory area 206b of the frame memory 206. FIG.

The pixel signal held in the integration memory area 206b is a signal obtained by integrating the pixel signal obtained from the counter 306 by the addition circuit 207 during the exposure period from timings t902 to t909. The pixel signal thus obtained is a signal corresponding to the number of incident photons during the exposure period. Thus, this embodiment can also prevent the count value of the counter 306 from saturating during the exposure period.

The control signal OUTCLK is supplied from the timing generator 204 to the digital output section 208 at timings t911 to t912. As a result, the pixel signals held in the integration memory area 206b of the frame memory 206, that is, the pixel signals integrated during the exposure period are sequentially output to the outside of the solid-state imaging device 100 via the digital output unit 208. When the output of the pixel signal to the outside of the solid-state imaging device 100 is completed, the pixel signal held in the integration memory area 206b of the frame memory 206 is reset to zero.

Thus, in this embodiment as well, the count value acquisition and reset operation are performed each time the count value of the counter 306 of each unit pixel 201 reaches the threshold Cth. Therefore, also in this embodiment, it is possible to prevent the count value from saturating during the exposure period, and to obtain an image with good gradation.

[Third embodiment]
A solid-state imaging device, an imaging apparatus, and an imaging method according to the third embodiment will be described with reference to FIGS. 10 and 11. FIG. The same components as those of the solid-state imaging device according to the first or second embodiment shown in FIGS. 1 to 9 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

The solid-state imaging device according to the present embodiment includes a saturation detector 1104, an adder circuit 1105, and an integration memory 1106 in a unit pixel 1101. FIG.

FIG. 10 is a diagram showing a solid-state imaging device 100 according to this embodiment. A plurality of unit pixels 1101 are arranged in a matrix in the pixel array 200 .

FIG. 11 is a diagram showing a unit pixel 1101 provided in the solid-state imaging device according to this embodiment.

A unit pixel 1101 includes a sensor section 301 , a counting section 1102 , and an integrating section 1103 .

The counting unit 1102 includes a counter 306 , a pixel memory 307 and a saturation detection unit 1104 . When the count value of the counter 306 reaches a predetermined threshold value Cth during the exposure period, the threshold reaching signal PSAT changes from L level to H level. A threshold reaching signal PSAT output from the counter 306 is supplied to the saturation detection section 1104 . The saturation detection unit 1104 supplies the latch signal PLAT to the pixel memory 307 when the threshold reaching signal PSAT changes from the L level to the H level. When the latch signal PLAT is supplied from the saturation detection unit 1104 to the pixel memory 307 , the count value acquired by the counter 306 is held by the pixel memory 307 . After that, saturation detector 1104 supplies a reset signal to one input terminal of OR gate 1107 . As a result, the reset signal output from the saturation detector 1104 is supplied to the reset terminal RES of the counter 306 via the OR gate 1107 . When a reset signal is supplied from the saturation detector 1104 to the counter 306 via the OR gate 1107, the counter 306 resets the count value. A reset signal PRES supplied from the vertical control circuit 202 is supplied to the other input terminal of the OR gate 1107 . A reset signal PRES output from the vertical control circuit 202 is also input to the reset terminal RES of the counter 306 via the OR gate 1107 . Therefore, the counter 306 is reset by the reset signal supplied from the saturation detection section 1104 and is also reset by the reset signal PRES supplied from the vertical control circuit 202 .

The integrating section 1103 includes an adding circuit 1105 and an integrating memory 1106 . Adder circuit 1105 corresponds to adder circuit 207 described above with reference to FIG. The integration memory 1106 corresponds to the integration memory area 206b of the frame memory 206 described above with reference to FIG. The integration memory 1106 integrates and retains the pixel signals held in the pixel memory 307 during the exposure period. The bit width of the integration memory 1106 is sufficiently large with respect to the bit width of the counter 306 and also sufficiently large with respect to the bit width of the pixel memory 307 .

After supplying the latch signal PLAT to the pixel memory 307 , the saturation detection unit 1104 supplies the addition control signal PADD to the addition circuit 1105 . When the addition control signal PADD is supplied from the saturation detection unit 1104 to the addition circuit 1105 , the addition circuit 1105 adds the pixel signal held in the pixel memory 307 and the pixel signal held in the integration memory 1106 . Then, the addition circuit 1105 holds the pixel signal obtained by the addition in the integration memory 1106 .

The pixel signals held in the integration memory 1106 of each unit pixel 1101 are sequentially output to the digital output section 208 under the control of the vertical control circuit 202 and the horizontal control circuit 203 after the exposure period ends. Since such operations are the same as those in the first embodiment, detailed description thereof will be omitted.

In this way, each unit pixel 1101 may be provided with the saturation detector 1104, the adder circuit 1105, and the integration memory 1106. FIG. Also in this embodiment, it is possible to prevent the count value from saturating during the exposure period, and to obtain an image with good gradation.

[Fourth embodiment]
A solid-state imaging device, an imaging apparatus, and an imaging method according to the fourth embodiment will be described with reference to FIG. The same components as those of the solid-state imaging devices and the like according to the first to third embodiments shown in FIGS.

The solid-state imaging device according to this embodiment can prevent a defective pixel, which is a defective unit pixel, from outputting an unfavorable threshold reaching signal PSAT.

If there is a crystal defect in the photodiode 303, a dark current is generated due to the crystal defect, and an avalanche multiplication phenomenon may occur in the photodiode 303 even though no photons are incident on the photodiode 303. . In the sensor unit 301 including the photodiode 303 with crystal defects, the pulse signal PLS can be output with high frequency even though no photons are incident on the photodiode 303 . A unit pixel with such a defective photodiode 303 is called a defective pixel.

FIG. 12A is a diagram showing a unit pixel 1201 provided in the solid-state imaging device according to this embodiment. A plurality of unit pixels 1201 are arranged in a matrix in the pixel array 200 . The configuration of the solid-state imaging device according to this embodiment is the same as that of the solid-state imaging device according to the first embodiment except for the unit pixel 1201 .

A unit pixel 1201 includes a sensor section 301 and a counting section 1202 . The counting unit 1202 includes a counter 306, a pixel memory 307, a defect control unit 1203, and an inverting buffer 1204 with an enable terminal. A threshold reaching signal PSAT output from counter 306 is output via inverting buffer 1204 . When the enable signal supplied from the defect control unit 1203 to the inverting buffer 1204 is at L level, the inverting buffer 1204 is turned off. When the inverting buffer 1204 is in an off state, the output of the inverting buffer 1204 is always at high impedance, and the threshold reaching signal PSAT is not output from the inverting buffer 1204 . On the other hand, when the enable signal supplied from the defect control unit 1203 to the inverting buffer 1204 is at H level, the inverting buffer 1204 is turned on. When inverting buffer 1204 is on, it may operate similarly to inverting buffer 308 described above with reference to FIG.

The defect control unit 1203 supplies an enable signal to the inverting buffer 1204 based on defect information indicating whether each unit pixel 1201 is defective. When a certain unit pixel 1201 is a defective pixel, the enable signal supplied from the defect control unit 1203 to the inverting buffer 1204 in the unit pixel 1201 is at L level, and the inverting buffer 1204 is turned off. On the other hand, when the unit pixel 1201 is not a defective pixel, in the unit pixel 1201, the enable signal supplied from the defect control unit 1203 to the inverting buffer 1204 becomes H level, and the inverting buffer 1204 is turned on. Defect information indicating whether or not the unit pixel 1201 is a defective pixel is supplied in advance to the defect control section 1203 of each unit pixel 1201 using the vertical control circuit 202 and the horizontal control circuit 203. are held in the defect control unit 1203 of each. The defect control unit 1203 and the inverting buffer 1204 can function as output preventing means for preventing the output of a signal indicating that the count value of the counter 306 provided in the unit pixel 1201 has reached the threshold.

A pixel signal output from a unit pixel 1201 that is a defective pixel is subjected to correction processing by the signal processing unit 101 or the control unit 104 .

Although the case where the inverting buffer 1204 with an enable terminal is provided in the counting unit 1202 has been described as an example, the present invention is not limited to this. FIG. 12B is a diagram showing another example of the unit pixel 1201 provided in the solid-state imaging device according to this embodiment. As shown in FIG. 12B, the sensor section 301 includes a photodiode 303, a quench resistor 304, and an inverting buffer 1205 with an enable terminal. The counting section 1202 includes a counter 306 , a pixel memory 307 , a defect control section 1203 and an inversion buffer 1206 . An enable signal output from the defect control unit 1203 provided in the counting unit 1202 is input to an enable terminal of an inverting buffer 1205 with an enable terminal provided in the sensor unit 301 . As described above, the inverting buffer 1205 with an enable terminal may be provided in the sensor section 301 . The defect control unit 1203 and the inverting buffer 1205 can function as output preventing means for preventing the output of pulses from the sensor unit 301 provided in the unit pixel 1201 .

According to this embodiment, it is possible to prevent the threshold reaching signal PSAT from being output from the defective pixel. Therefore, according to the present embodiment, it is possible to prevent the transfer of pixel signals to the frame memory 206 from occurring frequently due to defective pixels.

[Fifth embodiment]
A solid-state imaging device, an imaging apparatus, and an imaging method according to the fifth embodiment will be described with reference to FIGS. 13 to 18. FIG. The same components as those of the solid-state imaging devices according to the first to fourth embodiments shown in FIGS. 1 to 12 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

The imaging apparatus according to this embodiment includes a photometry unit 1303, and selectively disables the threshold reaching signal PSAT of each block 1401 of the pixel array 200 shown in FIG. can be controlled. The imaging apparatus according to this embodiment can also be controlled to selectively disable the threshold reaching signal PSAT by user operation via the operation unit 108 .

FIG. 14 is a diagram showing a solid-state imaging device 100 according to this embodiment. FIG. 14 shows the pixel array 200 and the saturation detection unit 1403 extracted. Components other than the pixel array 200 and the saturation detection unit 1403 are the same as those of the solid-state imaging device 100 in the first embodiment. In FIG. 13 , 16 unit pixels 201 arranged in 4 rows×4 columns are shown for the sake of simplicity of explanation, but in reality a large number of unit pixels 201 are provided in the pixel array 200 .

As shown in FIG. 14, one block 1401 is composed of, for example, four unit pixels 201 arranged in two rows and two columns. Wiring 1402 for transmitting threshold reaching signal PSAT is shared by each block 1401 . A threshold reaching signal PSAT output from one of the plurality of unit pixels 201 provided in each block 1401 is supplied to a saturation detection unit 1403 via a wiring 1402 .

Returning to FIG. 13, the photometry unit 1303 includes a photometry imaging device such as a CCD or CMOS (not shown), and receives light incident through the photographing lens 102 via a movable mirror (not shown) or the like. The photometry unit 1303 has a plurality of photometry areas 1501 as shown in FIG.

The control unit 104 includes a PSAT selection unit 1301 , a drive setting unit 1302 and a development processing unit 1304 .

A PSAT selection unit 1301 receives the photometry result from the photometry unit 1303, and determines, among the blocks 1401 of the pixel array 200, the blocks for which the threshold reaching signal PSAT is invalidated. In addition, the threshold reaching signal PSAT is enabled in blocks where the threshold reaching signal PSAT is not disabled. In addition, PSAT selection section 1301 can selectively determine blocks for which the threshold reaching signal PSAT is invalidated by user's operation via operation section 108 . Information on whether to enable or disable the threshold reaching signal PSAT of each block of the pixel array 200 (hereinafter referred to as PSAT selection information) is transmitted to the drive setting unit 1302 .

A drive setting unit 1302 transmits control signals for controlling the solid-state imaging device 100 and the signal processing unit 101 . Also, based on the PSAT selection information transmitted from the PSAT selection unit 1301 , a control signal for validating or invalidating the threshold reaching signal PSAT of each block 1401 of the pixel array 200 is transmitted to the solid-state imaging device 100 .

Based on the control signal from the drive setting unit 1302 , the saturation detection unit 1403 sets whether to enable or disable the threshold reaching signal PSAT supplied from each block 1401 . When the saturation detector 1403 is set to invalidate the threshold reaching signal PSAT output from a certain block 1401, the saturation detector 1403 operates as follows. That is, when the threshold reaching signal PSAT is supplied from the block 1401 to the saturation detecting unit 1403, the saturation detecting unit 1403 treats the threshold reaching signal PSAT as invalid. Therefore, even if the count value of the counter 306 reaches the threshold value Cth in any one of the plurality of unit pixels 201 located within the block 1401, the latch signal PLAT is output to each unit pixel 201 of the pixel array 200. not supplied to In this way, the saturation detection unit 1403 ignores that the count value of the counter 306 reaches the threshold for a predetermined unit pixel 201 out of the plurality of unit pixels 201 . On the other hand, when the saturation detector 1403 is set to validate the threshold reaching signal PSAT output from a certain block 1401, the saturation detector 1403 operates as follows. That is, when the saturation detecting section 1403 receives the threshold reaching signal PSAT from the block 1401, the saturation detecting section 1403 treats the threshold reaching signal PSAT as valid. Therefore, when the count value of the counter 306 reaches the threshold value Cth in any one of the plurality of unit pixels 201 located within the block 1401, the latch signal PLAT is supplied to each unit pixel 201 of the pixel array 200. be done.

Here, the case where the threshold reaching signal PSAT is shared in the block 1401 including the four unit pixels 201 of 2 rows×2 columns has been described as an example, but the present invention is not limited to this. For example, the number of unit pixels 201 provided in the block 1401 does not have to be four. Further, for example, the threshold reaching signal PSAT may be shared for each column.

Image data output from the solid-state imaging device 100 and subjected to various correction processes in the signal processing unit 101 is input to the development processing unit 1304 . A development processing unit 1304 performs development processing such as demosaicing on the image data. Image data that has undergone development processing is displayed on the display unit 106, for example.

FIG. 16 is a diagram showing an example of an image 1600 acquired by the imaging device according to this embodiment. Here, an example will be described in which the threshold reaching signal PSAT supplied from the block 1601 is invalidated and the threshold reaching signal PSAT supplied from other than the block 1601 is validated. Block 1601 corresponds to the sun. Since the threshold reaching signal PSAT supplied from the block 1601 is disabled, an image signal with good gradation cannot be obtained for the block 1601 . Since the threshold reaching signal PSAT supplied from blocks other than block 1601 is valid, image signals with good gradation can be obtained from blocks other than block 1601 . Note that there is no particular problem even if the pixel signal corresponding to the sun is saturated.

FIG. 17 is a flow chart showing a flow of photographing by selectively invalidating the threshold attainment signal PSAT based on the photometry result from the photometry unit 1303 .

First, in S<b>1701 , the photometry unit 1303 performs photometry to measure subject brightness for each of a plurality of photometry areas 1501 . The photometry result is sent to PSAT selection section 1301 .

Next, in step S<b>1702 , the PSAT selection unit 1301 determines a block for invalidating the threshold reaching signal PSAT from among the blocks 1401 of the pixel array 200 based on the photometry result from the photometry unit 1303 . Here, the threshold reaching signal PSAT of the block 1401 corresponding to the photometry area 1501 where the subject brightness is equal to or higher than a certain threshold is invalidated. This makes it possible to invalidate the threshold reaching signal PSAT for a block with an extremely bright subject such as the sun. Information (PSAT selection information) as to whether to validate or invalidate the threshold reaching signal PSAT of each block is transmitted to drive setting section 1302 .

In S<b>1703 , the drive setting unit 1302 transmits a control signal for imaging to the solid-state imaging device 100 and signal processing unit 101 . Also, based on the PSAT selection information transmitted from the PSAT selection unit 1301 , a control signal for validating or invalidating the threshold reaching signal PSAT of each block 1401 of the pixel array 200 is transmitted to the solid-state imaging device 100 .

In S1704, the solid-state imaging device 100 performs imaging as described above. Image data output from the solid-state imaging device 100 undergoes various correction processes in the signal processing unit 101 and is sent to the control unit 104 . After that, development processing is performed in the development processing unit 1304 and displayed on the display unit 106 .

As described above, according to this embodiment, the threshold attainment signal PSAT can be selectively invalidated based on the photometry result of the photometry unit 1303 . For example, it is possible to selectively disable the threshold reaching signal PSAT emitted from the unit pixel 201 corresponding to the sun or the like. Therefore, according to this embodiment, it is possible to obtain an image with good gradation for areas other than the area corresponding to the sun, for example.

Alternatively, the user may switch between enabling and disabling the threshold reaching signal PSAT via the operation unit 108 .

FIG. 18 is a flow chart showing the flow of photographing by selectively disabling the threshold attainment signal PSAT by user operation via the operation unit 108 .

First, in S1801, the image captured by the solid-state imaging device 100 is subjected to various correction processing in the signal processing unit 101 and development processing in the development processing unit 1304. The image is displayed as a live view image on the display unit 106. .

Next, in step S<b>1802 , based on the live view image displayed on the display unit 106 , the user selects a region where the threshold reaching signal PSAT is to be disabled via the operation unit 108 . Information on the selected area is input to PSAT selection section 1301 . Also, when the display unit 106 is a touch panel, the display unit 106 functions as the operation unit 108 . Information (PSAT selection information) as to whether to enable or disable the threshold reaching signal PSAT of each block selected by the user's operation is transmitted from PSAT selection section 1301 to drive setting section 1302 .

In S<b>1803 , the drive setting unit 1302 transmits a control signal for imaging to the solid-state imaging device 100 and signal processing unit 101 . Also, based on the PSAT selection information transmitted from the PSAT selection unit 1301 , a control signal for validating or invalidating the threshold reaching signal PSAT of each block 1401 of the pixel array 200 is transmitted to the solid-state imaging device 100 .

In S1804, the solid-state imaging device 100 performs imaging as described above. Image data output from the solid-state imaging device 100 undergoes various correction processes in the signal processing unit 101 and is sent to the control unit 104 . After that, development processing is performed in the development processing unit 1304 and displayed on the display unit 106 .

As described above, according to the present embodiment, the threshold reaching signal PSAT can be selectively disabled by user's operation via the operation unit 108 . For example, it is possible to selectively disable the threshold reaching signal PSAT emitted from the unit pixel 201 corresponding to the sun or the like. Therefore, according to this embodiment, it is possible to obtain an image with good gradation for areas other than the area corresponding to the sun, for example.

It should be noted that when shooting for live view image display is performed in S1801, the process of selectively disabling the threshold reaching signal PSAT need not be performed. Alternatively, if PSAT selection information has been set in imaging prior to S1801, the threshold reaching signal PSAT may be selectively disabled based on that information for imaging.

[Sixth embodiment]
An imaging apparatus and a control method thereof according to the sixth embodiment will be described with reference to FIGS. 19 to 22. FIG. The same constituent elements as those of the solid-state imaging devices according to the first to fifth embodiments shown in FIGS.

FIG. 19 is a block diagram of an imaging device according to this embodiment. 19 differs from the configuration shown in FIG. 1 in that it has a photometry unit 1303 and the control unit 104 has a drive setting unit 1302 and an exposure control unit 1901 .

The exposure control unit 1901 determines shooting conditions such as the exposure time, ISO sensitivity , and aperture value of the shooting lens 102 based on the photometric result from the photometry unit 1303, and transmits the information to the drive setting unit 1302 and the lens drive unit. 103. The exposure control unit 1901 can also determine shooting conditions such as exposure time, ISO sensitivity, and aperture value through user operations via the operation unit 108 .

For example, information on the exposure time set by the exposure control unit 1901 is transmitted to the drive setting unit 1302, and control data for driving the solid-state image sensor 100 with the set exposure time is transmitted from the drive setting unit 1302 to the solid-state image sensor. 100. Information on the ISO sensitivity set by the exposure control unit 1901 is transmitted to the drive setting unit 1302 . A control signal corresponding to the ISO sensitivity is sent from the drive setting unit 1302 to the signal processing unit 101 . The signal processing unit 101 multiplies the image data by a digital gain corresponding to the ISO sensitivity based on this control signal. For example, at ISO100, the signal processing unit 101 multiplies the image data by a digital gain of x1, and at ISO200, the image data is multiplied by a digital gain of x2. Information on the aperture value set by the exposure control unit 1901 is transmitted to the lens driving unit 103 and used for aperture control of the photographing lens 102 .

Further, based on the photometry result from the photometry unit 1303, the exposure control unit 1901 switches the solid-state image sensor 100 to a first drive mode in which the saturation detection unit 205 is operated, and a second drive mode in which the operation of the saturation detection unit 205 is disabled. It determines which of the two drive modes to drive.

In FIG. 20, based on the photometry result from the photometry unit 1303, the first drive mode in which the saturation detection unit 205 is operated and the second drive mode in which the operation of the saturation detection unit 205 is disabled are switched for shooting. 4 shows a flow chart representing the flow.

First, in S2001, the photometry unit 1303 performs photometry, and measures subject brightness for each of a plurality of photometry areas 1501 shown in FIG. A photometry result is transmitted to the exposure control unit 1901 .

In S2002, the exposure control unit 1901 determines shooting conditions such as exposure time, ISO sensitivity, aperture value, etc. based on the result of photometry. For example, based on the photometry result from the photometry unit 1303, shooting conditions such as exposure time, ISO sensitivity, aperture value, etc. are set so that the average of the entire image area is the appropriate exposure amount.

The exposure control unit 1901 also determines whether the solid-state imaging device 100 should be driven in the first drive mode or the second drive mode. For example, if the exposure control unit 1901 determines from the photometry result that a high-brightness subject exists in a part of the area and that the count values of some pixels are saturated during the exposure period under the set shooting conditions, 1 drive mode is selected. Otherwise, the second drive mode is selected. In this way, from the photometry results, when a high-luminance subject exists (or in a high-illuminance environment), the first drive mode is selected, and when there is no high-luminance subject (or in a low-illuminance environment) ), the second drive mode is selected.

In S<b>2002 , the drive setting unit 1302 transmits a control signal for imaging to the solid-state imaging device 100 and signal processing unit 101 . At this time, the exposure control unit 1901 transmits a control signal to the solid-state imaging device 100 to drive the solid-state imaging device 100 in the selected drive mode.

In S2003, based on the control signal sent from the drive setting unit 1302, the solid-state imaging device 100 is driven in either the first drive mode or the second drive mode to perform imaging. Since this operation is the same as that of the first embodiment, the explanation thereof is omitted. Image data output from the solid-state imaging device 100 undergoes various correction processes in the signal processing unit 101 and is sent to the control unit 104 .

As described above, according to the present embodiment, based on the photometry result of the photometry unit 1303, when there is a high-brightness subject (or in a high-illuminance environment), shooting is possible in the first drive mode. done. Therefore, it is possible to prevent the count value from saturating during the exposure period and obtain an image with good gradation.

As another control method of this embodiment, without using the photometry result of the photometry unit 1303, the first drive mode or the second drive mode can be selected according to any one of the shooting conditions such as the exposure time, ISO sensitivity, and aperture value. You may control so that a drive mode may be switched.

FIG. 21 is a flow chart showing the flow of photographing by switching between the first drive mode and the second drive mode according to the photographing conditions set by the user via the operation unit 108 .

In step S<b>2101 , the user sets shooting conditions such as exposure time, ISO sensitivity, and aperture value via the operation unit 108 . Information on the set shooting conditions is transmitted to the exposure control unit 1901 .

In S2102, the exposure control unit 1901 determines whether to drive in the first drive mode or the second drive mode based on the shooting conditions set in S2101. Here, for example, the first drive mode is selected when the ISO sensitivity is lower than a predetermined threshold, and the second drive mode is selected otherwise. As a result, by selecting the first drive mode when the ISO sensitivity is set to be low, which is generally used in a high-illuminance environment, it is possible to prevent the count value from saturating during the exposure period.

Also, the determination method in S2102 is not limited to the ISO sensitivity. For example, depending on the aperture value of the photographing lens 102, the first drive mode may be selected on the open side of the aperture value serving as a certain threshold, and the second drive mode may be selected on the small aperture side. Alternatively, depending on the exposure time, the first driving mode may be selected when the exposure time is longer than a certain threshold, and the second driving mode may be selected when the exposure time is shorter. Further, when at least one of the above-described imaging conditions corresponds to the first drive mode, the first drive mode may be used for driving.

Since the operations after S2103 are the same as the operations after S2003 in FIG. 20, the description thereof will be omitted.

Further, as another control method of the present embodiment, a standard dynamic range (SDR) mode for outputting 14-bit image data from the solid-state imaging device 100 and a high dynamic range (HDR) mode for outputting 16-bit image data are selected. An example in which the present invention is applied to an imaging apparatus having a shooting mode will be described. In this embodiment, for example, the counter 306 shown in FIG. outputs 14-bit image data. In the HDR mode, the counter 306 has only a bit width of 14 bits, but by operating in the first drive mode, the count value acquisition and reset operation are performed each time the count value of the counter 306 reaches the threshold value Cth. gradation of 14 bits or more can be obtained. Therefore, for example, the solid-state imaging device 100 outputs 16-bit image data.

FIG. 22 shows a flow chart showing the flow of shooting by switching between the first drive mode and the second drive mode according to the shooting mode (SDR mode, HDR mode) set by the user via the operation unit 108 .

In S<b>2201 , the user sets the shooting mode (SDR mode, HDR mode) via the operation unit 108 . Information about the set shooting conditions is sent to the exposure control unit 1901 .

In S2202, the exposure control unit 1901 determines whether to drive in the first drive mode or the second drive mode based on the information on the shooting conditions. Here, for example, the second drive mode is selected during the SDR mode, and the first drive mode is selected during the HDR mode.

Since the operation after S2203 is the same as the operation after S2003 in FIG. 20 , the description thereof will be omitted.

By performing the above operation in the first drive mode during the HDR mode, it is possible to prevent the count value from saturating during the exposure period and obtain a high-gradation image.

[Seventh Embodiment]
An imaging apparatus and a control method thereof according to the seventh embodiment will be described with reference to FIGS. 23 and 24. FIG. The same components as those of the solid-state imaging devices according to the first to sixth embodiments shown in FIGS. 1 to 22 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

FIG. 23 is a block diagram of an imaging device according to this embodiment. The imaging apparatus according to this embodiment shown in FIG. 23 differs from the configuration shown in FIG.

The drive switching unit 2301 receives image data output from the solid-state imaging device 100 via the signal processing unit 101, and detects whether or not there is a saturated pixel signal in the image data. In addition, a signal indicating detection of the threshold reaching signal PSAT output from the saturation detection unit 205 in FIG. Then, the drive switching unit 2301 selects the first drive mode based on the signal indicating that the threshold reaching signal PSAT has been detected and the result of detecting whether or not there is a saturated pixel signal in the input image data. or the second drive mode to drive the solid-state imaging device 100. FIG.

A drive setting unit 1302 transmits a control signal for imaging to the solid-state imaging device 100 and the signal processing unit 101 . At this time, the drive switching unit 2301 transmits a control signal to the solid-state imaging device 100 to drive the solid-state imaging device 100 in the selected drive mode.

FIG. 24 shows a flowchart representing the flow of control of the imaging apparatus according to this embodiment. When shooting starts, the drive switching unit 2301 selects the second drive mode in S2401 and the information is sent to the drive setting unit 1302 . In S<b>2402 , the drive setting unit 1302 transmits to the solid-state image sensor 100 a control signal for driving the solid-state image sensor 100 in the drive mode selected by the drive switching unit 2301 . Then, the solid-state imaging device 100 captures an image, and captured image data is input to the drive switching unit 2301 via the signal processing unit 101 .

In S2403, the drive switching unit 2301 determines whether or not the shooting in S2402 was performed in the first drive mode. In the case of the first drive mode, the process proceeds to determination 1 of S2404, and in the case of the second drive mode, the process proceeds to determination 2 of S2405.

In determination 1 of S2404, it is determined whether or not a signal indicating detection of the threshold reaching signal PSAT input via the wiring 2302 during imaging in S2402 has not been received. If the signal indicating that the threshold reaching signal PSAT has been detected has not been received (YES), the process moves to S2406, and the drive switching unit 2301 selects the second drive mode. If the signal indicating that the threshold reaching signal PSAT has been detected is received (NO), the drive mode is not switched and the process proceeds to S2408.

On the other hand, in determination 2 of S2405, the drive switching unit 2301 detects whether or not there is a saturated pixel signal in the image data input via the signal processing unit 101. FIG. If there is a saturated pixel signal (YES), the process moves to S2407, and the drive switching unit 2301 selects the first drive mode. If there is no saturated pixel signal (NO), the process proceeds to S2408 without switching the drive mode.

In S2408, it is determined whether or not to continue shooting. For example, if the user operates the operation unit 108 to end shooting, shooting ends. If shooting continues, the process returns to S2402 and shooting is performed in the drive mode selected by the drive switching unit 2301 .

By controlling as described above, it is possible to shift to the first drive mode when there is a saturated pixel signal in the captured image in the second drive mode. Further, when the signal indicating that the threshold reaching signal PSAT has been detected is not received in the first driving mode, it is possible to shift to the second driving mode.

As described above, according to the present embodiment, when there is a saturated pixel signal in the captured image, it is possible to shift to the first drive mode, so that it is possible to prevent the count value from being saturated during the exposure period. An image with good gradation can be obtained.

[Eighth Embodiment]
An imaging apparatus and a control method thereof according to the eighth embodiment will be described with reference to FIGS. 25 and 26. FIG. The same components as those of the solid-state imaging devices according to the first to seventh embodiments shown in FIGS. 1 to 24 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

FIG. 25 is a block diagram of an imaging device according to this embodiment. The imaging apparatus according to this embodiment shown in FIG. 25 differs from the configuration shown in FIG.

The solid-state imaging device 100 in this embodiment has the same configuration as the solid-state imaging device shown in FIGS. 7 and 8 in the second embodiment, and is driven as shown in the timing chart in FIG. Also, the value of the threshold value Cth of the counter 306 of the solid-state imaging device 100 according to this embodiment can be set by the drive setting unit 2502 according to the shooting mode.

A shooting mode selection unit 2501 selects a shooting mode by, for example, user operation via the operation unit 108 , and transmits information on the selected shooting mode to the drive setting unit 2502 . Examples of shooting modes include a full-screen readout mode in which signals of all pixels of the pixel array 200 are output, and a crop readout mode in which signals of some pixels of the pixel array 200 are output.

A drive setting unit 2502 transmits a control signal for driving the solid-state imaging device 100 and the signal processing unit 101 in the imaging mode selected by the imaging mode selection unit 2501 . The drive setting unit 2502 also transmits a control signal for setting the threshold value Cth of the counter 306 of each pixel of the solid-state imaging device 100 according to the shooting mode selected by the shooting mode selection unit 2501 . Here, the value of the threshold Cth set by the drive setting unit 2502 is, for example, the value shown in Equation (2) of the second embodiment. Here, n indicating the number of readout rows in equation (2) and T1h, which is the time required to transfer pixel signals for one row to the frame memory 206, are determined by the shooting mode such as full screen readout mode or crop readout mode. is used.

FIG. 26 is a flowchart showing a flow of shooting with the threshold value Cth set according to the shooting mode (full-screen reading mode, crop reading mode) set by the user via the operation unit 108 .

In S2601, the shooting mode selection unit 2501 selects a shooting mode (full screen readout mode, crop readout mode) by user operation or the like via the operation unit . Information on the selected shooting mode is transmitted to the drive setting unit 2502 .

In S2602, the drive setting unit 2502 transmits a control signal for driving the solid-state imaging device 100 and the signal processing unit 101 in the selected shooting mode. In addition, the drive setting unit 2502 sends a control signal to the solid-state image sensor 100 for setting the value of the threshold value Cth of the counter 306 of each pixel of the solid-state image sensor 100 according to the shooting mode selected by the shooting mode selection unit 2501. Send.

In S2603, the solid-state imaging device 100 performs imaging in the imaging mode selected in S2601. At this time, as the threshold Cth of the counter 306, a value corresponding to the shooting mode selected in S2601 is used.

With the above operation, the imaging apparatus according to this embodiment can change the threshold Cth of the counter 306 according to the imaging mode. Also in this embodiment, as in the second embodiment, it is possible to prevent the count value from saturating during the exposure period, and an image with good gradation can be obtained.

Although the embodiments of the present invention have been described above, the present invention is not limited to these embodiments.

The present invention supplies a program that implements one or more functions of the above-described embodiments to a system or apparatus via a network or a recording medium, and one or more processors in the computer of the system or apparatus reads and executes the program. It can also be realized by processing to It can also be implemented by a circuit (for example, ASIC) that implements one or more functions.

100: solid-state imaging device, 101: image processing unit, 104: control unit, 106: display unit, 108: operation unit, 200: pixel array, 201, 1101: unit pixel, 202: vertical control circuit, 203: horizontal control circuit 204: timing generation circuit 205, 1403: saturation detector 206: frame memory 206a: temporary memory area 206b: integration memory area 207: adder circuit 208: digital output unit 209, 210: switch 211 : pull-up resistor, 212: wiring, 306: counter, 207, 307: pixel memory, 1202: defect control unit, 1301: PSAT selection unit, 1302, 2502: drive setting unit, 1303: photometry unit, 1901: exposure control unit , 2301: drive switching unit, 2501: shooting mode selection unit

Claims (20)

a plurality of pixels each provided with a sensor unit that emits pulses at a frequency corresponding to the frequency of photon reception , and a counter that counts the number of pulses of the signal emitted from the sensor unit ;
a detection unit that detects whether the count value of the counter provided for one of the plurality of pixels has reached a first threshold ;
when the detection unit detects that the count value of the counter provided for one of the plurality of pixels has reached the first threshold value, for each of the plurality of pixels, based on the count value an integrator that integrates the signal;
An imaging device comprising : resetting the counter provided for each of the plurality of pixels when the detection unit detects that the count value of the counter provided for one of the plurality of pixels reaches the first threshold value; 2. The imaging device according to claim 1, characterized in that: further comprising a memory for holding the count value obtained by the counter for each of the plurality of pixels ;
After the count value obtained by the counter is held in the memory, the counter provided for each of the plurality of pixels is reset .
3. The imaging device according to claim 1, wherein: 4. The imaging device according to claim 3, wherein the memory is provided in each of the pixels. further comprising a memory provided outside the pixels and sequentially selecting the count values obtained by the counter and holding the count values for each of the plurality of pixels ;
resetting the counter provided for each of the plurality of pixels after reading the count value obtained by the counter ;
3. The imaging device according to claim 1, wherein: Each of the plurality of pixels is
the detection unit;
a memory that holds the count value obtained by the counter;
the integrating section;
2. The imaging device according to claim 1, comprising : Prevent output of a signal indicating that the count value obtained by the counter provided in a predetermined pixel among the plurality of pixels has reached the first threshold based on the result of detection by the detection unit 7. The imaging device according to any one of claims 1 to 6 , further comprising output preventing means for preventing the output of the image. 7. The imaging according to any one of claims 1 to 6 , further comprising output prevention means for preventing a pulse from being output from the sensor unit provided in a predetermined pixel among the plurality of pixels. element. 9. The imaging device according to claim 7 , wherein the predetermined pixels are defective pixels. 7. The detection unit according to any one of claims 1 to 6 , wherein the detection unit ignores that the count value of the counter reaches the first threshold for a predetermined pixel among the plurality of pixels. 1. The imaging device according to 1. further comprising photometric means;
11. The imaging device according to claim 10 , wherein the predetermined pixel is a pixel corresponding to a subject having a luminance equal to or higher than a second threshold as a result of photometry by the photometry device. further comprising operating means;
12. The imaging device according to claim 10 , wherein the predetermined pixels are pixels selected by the operating means. a first mode for performing detection by the detection unit;
13. The imaging device according to any one of claims 1 to 12 , wherein the imaging device is capable of operating in a second mode in which detection by the detection unit is not performed . further comprising photometric means;
If the result of photometry by the photometry means is that there is a subject having a luminance equal to or higher than the third threshold, the operation is performed in the first mode, and if there is no subject having a luminance equal to or higher than the third threshold, 14. The imaging device according to claim 13 , which operates in the second mode. further comprising setting means for setting imaging conditions;
15. The imaging device according to claim 13 , wherein switching between operation in the first mode and operation in the second mode is performed based on the photographing conditions set by the setting means. When operating in the first mode and the detection unit does not detect that the count value has reached the first threshold, switching to the second mode,
3. The mode is switched to the first mode when operating in the second mode and when there is a count value equal to or greater than a third threshold among the count values of the counter. 14. The imaging device according to 13 . a selection means for selecting one of a plurality of different shooting modes;
2. The imaging device according to claim 1 , wherein said first threshold value is changed according to the shooting mode selected by said selection means. The imaging device according to any one of Claims 1 to 17 , wherein the sensor section includes an avalanche photodiode. a plurality of pixels each provided with a sensor section that emits pulses at a frequency corresponding to the frequency of photon reception ; and a counter that counts the number of pulses of the signal emitted from the sensor section; a detection unit for detecting whether the count value of the provided counter reaches a threshold value; and the detection unit detects that the count value of the counter provided for one of the plurality of pixels has reached the threshold value. an imaging device comprising : an integrator that integrates a signal based on the count value for each of the plurality of pixels when detected ;
and a processing unit that performs predetermined processing on a signal output from the imaging device. a step of counting, by a counter , the number of pulses of a signal emitted from a sensor unit provided in each pixel of a plurality of pixels at a frequency corresponding to the frequency of photon reception;
detecting whether the count value of the counter provided for one of the plurality of pixels reaches a threshold;
and integrating a signal based on the count value for each of the plurality of pixels when detecting that the count value of the counter provided for one of the plurality of pixels has reached the threshold value. An imaging method, comprising:

Images