JP7129182B2 - Solid-state imaging device, imaging device, and imaging method - Google Patents

Description

The present invention relates to a solid-state imaging device, an imaging device, and an imaging method.

2. Description of the Related Art In recent years, imaging devices equipped with solid-state imaging devices such as CMOS image sensors have become widespread. On the other hand, a technique for detecting single photons using an avalanche photodiode has been proposed. Avalanche photodiodes that can detect single photons are called SPADs (Single Photon Avalanche Diodes). Patent Literature 1 describes an optical distance measuring device that uses an avalanche photodiode as a light receiving element to perform distance measurement based on the Time Of Flight method.

JP 2014-77658 A

If an attempt is made to configure a solid-state imaging device simply using SPADs, power consumption may increase.
SUMMARY OF THE INVENTION An object of the present invention is to provide a solid-state imaging device, an imaging apparatus, and an imaging method capable of suppressing power consumption.

According to one aspect of the embodiment, a plurality of pixels each provided with a sensor unit that includes an avalanche photodiode and emits a pulse at a frequency corresponding to the frequency of photon reception, and the number of pulses emitted from the sensor unit is counted. and when the count value of the counter is less than the threshold value, control is performed so that the transistor constituting the quench element connected to the avalanche photodiode is turned on, and the count value of the counter is set to the above A solid-state imaging device characterized by comprising a control section for controlling the transistor to be in an OFF state when a threshold value is reached.

According to another aspect of the embodiment, a plurality of pixels each provided with a sensor unit that includes an avalanche photodiode and emits a pulse at a frequency corresponding to the frequency of photon reception, and the number of pulses emitted from the sensor unit is A counter for counting, and when the count value of the counter is less than a threshold , control is performed so that a first voltage is applied to the avalanche photodiode, and the count value of the counter reaches the threshold. a control unit for controlling a second voltage lower than the first voltage to be applied to the avalanche photodiode , wherein the second voltage is a ground voltage. There is provided a solid-state imaging device characterized by:

According to the present invention, it is possible to provide a solid-state imaging device, an imaging apparatus, and an imaging method capable of suppressing power consumption.

It is a figure which shows the solid-state image sensor by 1st Embodiment. 4 is a timing chart showing an example of operation of the solid-state imaging device according to the first embodiment; It is a figure which shows the solid-state image sensor by 1st Embodiment. 1 is a block diagram showing an imaging device according to a first embodiment; FIG. It is a figure which shows the solid-state image sensor by 2nd Embodiment. 9 is a timing chart showing an example of operation of the solid-state imaging device according to the third embodiment; It is a timing chart which shows operation|movement of the solid-state image sensor by 4th Embodiment.

An embodiment of the present invention will be described below with reference to the drawings. It should be noted that the present invention is not limited to the following embodiments, and can be modified as appropriate. Also, the embodiments shown below may be combined as appropriate.

[First embodiment]
A solid-state imaging device, an imaging device, and an imaging method according to the first embodiment will be described with reference to FIGS. 1 to 4. FIG. FIG. 1 is a diagram showing a solid-state imaging device according to this embodiment.
As shown in FIG. 1 , the solid-state imaging device 100 according to this embodiment includes a vertical scanning section 101 , a timing generator (TG) 102 , a column memory section 103 and a horizontal scanning section 104 . The solid-state imaging device 100 also includes a plurality of pixels 110 arranged in a matrix, that is, in a matrix. Although four pixels 110a, 110b, 110c, and 110d are shown here for simplification of explanation, a large number of pixels 110 are actually provided in the solid-state imaging device 100. FIG. Reference numeral 110 is used when describing pixels in general, and reference numerals 110a to 110d are used when describing individual pixels.

The timing generator 102 generates a signal for controlling each part of the solid-state imaging device 100 based on a control signal or the like supplied from the processing part 404 (see FIG. 4). The timing generator 102 is supplied with the synchronization signal VD and the like from the processing unit 404 . The timing generator 102 supplies various signals and the like to the vertical scanning section 101 and column memory section 103 . The timing generator 102 also supplies a signal HCLK to the horizontal scanning section 104 . Also, the timing generator 102 supplies a control signal CTL, a transfer signal WRT, and a reset signal RES to each pixel 110, respectively. The timing generator 102 can function as a control section (control means) that controls each section of the solid-state imaging device 100 .
Each pixel 110 includes a SPAD 111, a quench element 112, an inverter 113, a counter 114, a control section 115, a transfer switch 116, a pixel memory 117, and a readout switch 118, respectively.

The SPAD 111 has an anode connected to ground voltage and a cathode connected to one end of the quench element 112 . A bias voltage Vbias is applied to the other end of the quench element 112 . A bias voltage Vbias greater than the breakdown voltage of SPAD 111 can be applied to SPAD 111 via quench element 112 . Thus, the SPAD 111 can operate in a mode of operation called Geiger mode. That is, when a photon is incident on the SPAD 111, an avalanche multiplication phenomenon occurs. This causes an avalanche current and a voltage drop across the quench element 112 . A quench element 112 is a resistance element for stopping the avalanche multiplication phenomenon of the SPAD 111 . Here, the quench element 112 is constructed using the resistance component of the MOS transistor. When an avalanche current is generated by the avalanche multiplication phenomenon, a voltage drop occurs in the quench element 112 and the bias voltage applied to the SPAD 111 drops. When the bias voltage drops below the breakdown voltage of the SPAD 111, the avalanche multiplication phenomenon stops. As a result, the avalanche current stops flowing, and the bias voltage Vbias is applied to the SPAD 111 again. The cathode of SPAD 111, one end of quench element 112, and the input terminal of inverter 113 are connected to each other at node PLSa. The output terminal of inverter 113 and the input terminal of counter 114 are connected to each other at node PLSd. When a photon is incident on the SPAD 111, the phenomenon described above occurs, causing a voltage change at the node PLSa. Inverter 113 generates pulse signal PLS according to a voltage change at node PLSa, and outputs generated pulse signal PLS to node PLSd. In this way, inverter 113 outputs pulse signal PLS whose waveform has been shaped. Thus, in the sensor unit 303 (see FIG. 3), when a photon is incident on the SPAD 111, the pulse signal PLS is output from the inverter 113 at a frequency corresponding to the photon reception frequency. More specifically, when one photon is incident on the SPAD 111, the inverter 113 outputs one pulse signal PLS. The bias voltage Vbias can be, for example, approximately +20 V, but is not limited to this. For example, the anode of SPAD 111 may be connected to a negative potential.

In the process of generating one pulse signal PLS, the following current flows in the pixel 110 . That is, an avalanche current flows in the pixel 110 due to the avalanche multiplication phenomenon. Also, a transient current flows in the pixel 110 when the potential of the node PLSa returns to Vbias after the avalanche multiplication phenomenon has stopped.

The quench element 112 is configured using the resistance component of the MOS transistor, as described above. A control signal (control pulse) CTRL output from a control section 115 to be described later is supplied to the gate terminal of the MOS transistor forming the quench element 112 . The operation of quench element 112 is controlled by control section 115 . When the control signal CTRL is at High level, the MOS transistor forming the quench element 112 is in ON state. In this case, since the bias voltage Vbias is applied to the SPAD 111, the SPAD 111 can operate in Geiger mode. On the other hand, when the control signal CTRL is at Low level, the MOS transistor forming the quench element 112 is in the OFF state. In this case, since the bias voltage Vbias is not applied to the SPAD 111, the SPAD 111 cannot operate in Geiger mode. More precisely, when the MOS transistor forming the quench element 112 is turned off, no current flows from the SPAD 111 to the power supply that supplies the bias voltage Vbias. Therefore, once the potential of the cathode of the SPAD 111 drops below the breakdown voltage Vbr, the SPAD 111 cannot return to the Geiger mode. A mode of operation of SPAD 111 that is not the Geiger mode is also referred to as the "non-Geiger mode."

Counter 114 counts the number of pulses of pulse signal PLS output from inverter 113 . The bit width of the counter 114 is 16, for example. The upper limit value that can be counted by the counter 114 with a bit width of 16, that is, the count upper limit value is 0xFFFF (65535 in decimal). A reset signal (reset pulse) RES output from the timing generator 102 is input to the counter 114 . The count value of counter 114 is reset by reset signal RES. When the reset is released, counter 114 starts counting pulse signal PLS.

A control signal CTL supplied from the timing generator 102 is input to the control section 115 . Control unit 115 outputs control signal CTRL according to the count value of counter 114 . A control signal CTRL is supplied to the gate terminal of the MOS transistor forming the quench element 112 . More specifically, when the count value is less than the threshold (predetermined value) Cref, the control unit 115 sets the control signal CTRL to High level. Further, when the count value reaches the threshold value Cref, the control unit 115 sets the control signal CTRL to Low level. When the bit width of the counter 114 is 16, the threshold Cref is set to 0xFFFF (65535 in decimal), for example. Note that the threshold Cref is not limited to 0xFFFF. The maximum value of the signal range required in the imaging device 400 (see FIG. 4) provided with the solid-state imaging device 100 may be set as the threshold value Cref. When the count value of the counter 114 increases and eventually reaches the threshold value Cref, the control unit 115 sets the control signal CTRL to Low level to turn off the MOS transistor forming the quench element 112 . By turning off the MOS transistor forming the quench element 112, the operation mode of the SPAD 111 can be changed to the non-Geiger mode. A control unit 115 is provided for each pixel 110 . Therefore, the operation mode of SPAD 111 can be switched for each pixel 110 . In the present embodiment, after the count value of the counter 114 reaches the threshold value Cref, the avalanche current does not flow to the pixel 110, so power consumption can be suppressed.

Transfer switch 116 is controlled by transfer signal WRT supplied from timing generator 102 . When the transfer signal WRT becomes High level, the transfer switch 116 is turned on, and the count value output from the counter 114 is written to the pixel memory 117 as the pixel signal value of the pixel 110 concerned.

A plurality of control lines extending in the horizontal direction are connected to the vertical scanning unit 101 . The vertical scanning unit 101 sequentially supplies readout signals READ to these control lines. When describing the read signal in general, the symbol READ is used, and when describing the individual read signals, the symbols READn and READn+1 are used. Although two control lines are shown here, in practice a large number of control lines are provided. A read signal READn is a read signal applied to the control line located in the n-th row. The read signal READn+1 is a read signal applied to the control line located in the (n+1)th row. A plurality of pixels 110 positioned in the same row are supplied with the readout signal READ through the same control line.

A plurality of signal lines (vertical signal lines, output signal lines) 105 extending in the vertical direction are connected to the column memory section 103 . Note that reference numeral 105 is used when general signal lines are described, and reference numerals 105a and 105b are used when individual signal lines are described. Although two signal lines 105 are illustrated here, a large number of signal lines 105 are actually provided. A signal output from the pixel memory 117 is output to the column memory unit 103 via the read switch 118 and the signal line 105 . The read switch 118 is turned off when the read signal READ supplied from the vertical scanning unit 101 is at Low level, and turned on when the read signal READ is at High level. Pixel signal values output from the plurality of pixels 110 located in the row selected by the read signal READ supplied from the vertical scanning unit 101 are written to the column memory unit 103 via the signal lines 105, respectively. The column memory unit 103 holds the pixel signal values read from each pixel 110 respectively. The horizontal scanning unit 104 sequentially outputs each pixel signal value held in the column memory unit 103 to the image processing unit 402 (see FIG. 4) through the output line Output.

Thus, in this embodiment, when the count value of the counter 114 is less than the threshold value Cref, the SPAD 111 provided in the pixel 110 operates in the Geiger mode. Then, when the count value of the counter 114 reaches the threshold value Cref, the control unit 115 provided in the pixel 110 performs control so that the SPAD 111 provided in the pixel 110 does not operate in the Geiger mode. Therefore, after the count value of the counter 114 reaches the threshold value Cref, the avalanche current does not flow through the pixel 110 . Therefore, according to this embodiment, power consumption can be suppressed.

FIG. 2 is a timing chart showing an example of the operation of the solid-state imaging device 100 according to this embodiment. Here, the operation of the pixel 110a among the plurality of pixels 110 will be focused on and explained. FIG. 2 shows a timing chart corresponding to two frames out of a plurality of frames forming a moving image. The period from timing t210 to timing t220 corresponds to the m-th frame FRAMEm. The period from timing t220 to timing t230 corresponds to the (m+1)th frame FRAMEm+1.

First, at timing t210, when the synchronization signal (synchronization pulse) VD becomes High level, the timing generator 102 makes the control signal CTL High level. The control signal CTL is simultaneously supplied to the control unit 115 provided for each of all the pixels 110 . When the control signal CTL becomes High level, the control section 115 makes the control signal CTRL High level. When the control signal CTRL becomes High level, the MOS transistor forming the quench element 112 is turned on, and the bias voltage Vbias is applied to the SPAD 111 . The timing generator 102 also sets the reset signal (reset pulse) RES to High level at timing t210. When the reset signal RES is set to High level, the counter 114 is reset. Thus, the bias voltage Vbias is applied to the SPADs 111 provided in all the pixels 110 all at once, and the counters 114 provided in all the pixels 110 are reset at once.

At timing t211, when the voltage of the node PLSa reaches the bias voltage Vbias, the SPAD 111 can operate in Geiger mode.
At timing t212, the timing generator 102 changes the reset signal RES to Low level. When the reset signal RES becomes Low level, the reset of the counter 114 is released, and the counter 114 starts counting the pulse signal PLS output from the inverter 113 . Thus, the counter 114 starts counting the pulse signal PLS after a predetermined time has passed since the MOS transistor forming the quench element 112 was turned on. The reason why the count of the pulse signal PLS is started after the lapse of a predetermined time after the MOS transistor constituting the quench element 112 is turned on is the margin period for allowing the SPAD 111 to stably operate in the Geiger mode. This is to ensure Therefore, during the period from timing t210 to timing t212, even if the pulse signal PLS is output from the inverter 113, the counter 114 does not count the number of the pulse signals PLS.

The period from timing t212 to timing t215 is the photon detection period of the m-th frame FRAMEm, and the number of photons detected in each pixel 110 during the photon detection period is the pixel signal in the m-th frame FRAMEm. value. Here, a case where the count value of the counter 114 reaches the threshold Cref at timing t213 will be described as an example.
At timing t213, when the count value of the counter 114 reaches the threshold Cref, the control unit 115 changes the control signal CTRL to Low level. When the control signal CTRL becomes Low level, the MOS transistor forming the quench element 112 is turned off.

At timing t214, the potential of the node PLSa becomes equal to or lower than the breakdown voltage Vbr of the SPAD111. When the potential of the node PLSa becomes equal to or lower than the breakdown voltage Vbr of the SPAD 111, the operation mode of the SPAD 111 becomes the non-Geiger mode. In the non-Geiger mode, even if a photon is incident on the SPAD 111, no avalanche current is generated. The counter 114 keeps holding the threshold Cref as the count value.

At timing t215, the timing generator 102 changes the transfer signal WRT to High level. When the transfer signal WRT becomes High level, the transfer switch 116 is turned on, and the count value of the counter 114 at timing t215 is written to the pixel memory 117. FIG. Since the count value of the counter 114 is the threshold Cref, data indicating the threshold Cref is written to the pixel memory 117 .
Here, the case where the count value of the counter 114 reaches the threshold value Cref at timing t213 before timing t215 has been described as an example. However, if the count value of the counter 114 is less than the threshold Cref even at timing t215, the following will occur. That is, in such a case, the counter 114 continues counting the pulse signal PLS until timing t215. Then, the count value of the counter 114 at timing t215 is written to the pixel memory 117 at timing t215.

During the period from timing t220 to timing t230, the (m+1)th frame FRAMEm+1 is acquired and the pixel signal values of the mth frame FRAMEm are read. Acquisition of the (m+1)th frame FRAMEm+1 is similar to acquisition of the mth frame FRAMEm. Here, the count value of the counter 114 reaches the threshold Cref at timing t225. Here, the case where the count value of the counter 114 reaches the threshold Cref at timing t225 before timing t226 has been described as an example. However, if the count value of the counter 114 is still less than the threshold Cref at timing t226, the following will occur. That is, in such a case, the counter 114 continues counting the pulse signal PLS until timing t226. Then, the count value of the counter 114 at timing t226 is written to the pixel memory 117 at timing t226. Reading of pixel signal values of the m-th frame FRAMEm is performed as follows. First, at timing t221, the vertical scanning unit 101 sets the readout signal READ0 to High level. Thereby, the pixel signal values of the plurality of pixels 110 located in the 0th row are written to the column memory section 103 via the signal line 105 . Thereafter, at timing t222 to timing t223, the horizontal scanning unit 104 sequentially outputs each pixel signal value held in the column memory unit 103 to the image processing unit 402 (see FIG. 4) via the output line Output. . In this way, the pixel signal values of the plurality of pixels 110 located in the 0th row are output. Thereafter, similarly, pixel signal values of the plurality of pixels 110 located in the first row are output. After that, pixel signal values are similarly output, and the process of outputting all pixel signal values is completed by timing t224. Thus, the image data of the m-th frame FRAMEm is output to the image processing section 402 .

As described above, in the present embodiment, when the count value of the counter 114 reaches the threshold value Cref at the timing t213 before the timing t215 or at the timing t225 before the timing t226, the control unit 115 performs the following works like That is, the control unit 115 sets the control signal CTRL supplied to the gate of the MOS transistor forming the quench element 112 to Low level, prevents the bias voltage Vbias from being supplied to the SPAD 111, and sets the operation mode of the SPAD 111 to the non-Geiger mode. Therefore, according to the present embodiment, even when a large number of photons are incident on the pixel 110, a large amount of avalanche current can be prevented from flowing, and an increase in current consumption can be prevented.

FIG. 3 is a diagram showing a solid-state imaging device according to this embodiment. FIG. 3A is a perspective view showing the solid-state imaging device according to this embodiment. As shown in FIG. 3A, the solid-state imaging device 100 is constructed by laminating two substrates (semiconductor chips) 301 and 302 . FIG. 3B shows pixels provided in the solid-state imaging device 100 according to this embodiment. In FIG. 3B, one pixel 110 out of the plurality of pixels 110 provided in the solid-state imaging device 100 is extracted and shown.

As shown in FIG. 3A, the solid-state imaging device 100 includes a substrate (upper substrate) 301 for receiving an optical image formed by an optical system (imaging optical system) (not shown), and mainly digital circuits. It is composed of a substrate (lower substrate) 302 . As shown in FIG. 3B, the pixel 110 is composed of a sensor section (light receiving section, pixel section) 303 and a counting section 304 . A sensor portion 303 of the pixel 110 is formed on the substrate 301 . A counting portion 304 of the pixel 110 is formed on the substrate 302 . A plurality of sensor units 303 are arranged in a matrix on the substrate 301 . A plurality of counting units 304 are arranged in a matrix on the substrate 302 . Each of the plurality of sensor sections 303 and each of the plurality of counting sections 304 corresponding to these sensor sections 303 are electrically connected to each other. Thus, a plurality of pixels 110 are arranged in a matrix. The sensor section 303 is provided with a SPAD 111 , a quench element 112 and an inverter 113 . Since the sensor unit 303 is provided with the inverter 113 , the waveform-shaped pulse signal PLS is transmitted from the sensor unit 303 to the counting unit 304 . Therefore, the transmission from the sensor section 303 to the counting section 304 is relatively robust. The counting section 304 includes a counter 114 , a control section 115 , a transfer switch 116 , a pixel memory 117 and a readout switch 118 . The vertical scanning section 101, the timing generator 102, the column memory section 103, and the horizontal scanning section 104 are provided in either the peripheral circuit section 305 of the substrate 301 or the peripheral circuit section 306 of the substrate 302. . Here, a case where the vertical scanning section 101, the timing generator 102, the column memory section 103, and the horizontal scanning section 104 are arranged in the peripheral circuit section 306 of the substrate 302 will be described as an example.

Thus, in this embodiment, the sensor section 303 is formed on the substrate 301 and the counting section 304 is formed on the substrate 302 . Since the counting unit 304 with a large circuit size is provided on the substrate 302 separate from the substrate 301 on which the sensor unit 303 is provided, a sufficient area for the sensor unit 303 can be secured. Therefore, the opening area of the sensor section 303 can be sufficiently secured.

Note that the structure of the solid-state imaging device 100 is not limited to the above. The structure of the solid-state imaging device 100 can be changed as appropriate according to purposes and applications. For example, the solid-state imaging device 100 may be configured by stacking three or more substrates, or the solid-state imaging device 100 may be configured by one substrate. Each of the plurality of substrates (semiconductor chips) may be manufactured according to different process rules. Further, another circuit for performing signal processing, a frame memory, or the like may be provided on the substrate 302 . For example, the substrate 302 may be provided with a signal processing circuit that performs noise reduction processing, a detection circuit that performs detection of an imaged subject, and the like.

FIG. 4 is a block diagram showing the imaging device according to this embodiment. An optical system (imaging optical system) 401 includes a focus lens, a zoom lens, an aperture, and the like. The optical system 401 forms an optical image of a subject and causes the formed optical image to enter the imaging surface of the solid-state imaging device 100 . The solid-state imaging device 100 captures an optical image formed by the optical system 401 as described above. The solid-state imaging device 100 sequentially reads pixel signal values from each of the plurality of pixels 110 and sequentially outputs the read pixel signal values to the image processing unit 402 .

The image processing unit 402 sequentially performs predetermined processing on pixel signal values output from the solid-state imaging device 100 to generate an image, that is, image data. Such an image may be a still image or a frame constituting a moving image. The image processing unit 402 can further perform signal rearrangement, defective pixel correction, noise reduction, color conversion, white balance correction, gamma correction, resolution conversion, data compression, etc. in the process of generating an image.

The memory 403 is used when the image processing unit 402 performs arithmetic processing and the like. As the memory 403, for example, a DRAM (Dynamic Random Access Memory), a flash memory, or the like can be used. The memory 403 can also be used as a buffer memory during continuous shooting. A processing unit (overall control/calculation unit) 404 controls the entire imaging apparatus 400 according to this embodiment. The processing unit 404 includes a CPU (Central Processing Unit) and the like. The processing unit 404 also outputs the image signal processed by the image processing unit 402 to the recording unit 407 and the display unit 406 . An operation unit 405 is configured by operation members such as buttons, switches, and electronic dials. When a user or the like operates the operation unit 405 , a signal corresponding to the content of the operation is supplied from the operation unit 405 to the processing unit 404 . A display unit 406 displays an image supplied from the processing unit 404 . A recording medium (not shown) is attached to the recording unit (recording control unit) 407 . For example, a memory card or the like is used as such a recording medium. A hard disk or the like may be used as the recording medium. An optical system driving unit 408 controls a focus lens, a zoom lens, an aperture, and the like provided in the optical system 401 . Note that the imaging device 400 may further include a wired or wireless communication interface for communicating with an external device. In this case, the imaging device 400 can transmit generated images and the like to an external device and receive control signals and the like from the external device via the communication interface. Also, the imaging device 400 may further include a light source device that projects light onto the subject. In this case, the light source device can emit pulsed light in synchronization with, for example, the synchronization signal VD. Further, the light source device can always emit light. Since the light source device can irradiate the subject with light, the subject can be recognized more reliably.

Thus, in this embodiment, when the count value of the counter 114 is less than the threshold, the SPAD 111 provided in the pixel 110 operates in Geiger mode. On the other hand, when the count value of the counter 114 reaches the threshold value, the SPAD 111 provided in the pixel 110 operates in a non-Geiger mode, which is an operation mode different from the Geiger mode. Therefore, according to the present embodiment, even when a large number of photons enter the pixel 110, the avalanche current in the pixel 110 can be suppressed. Therefore, according to this embodiment, power consumption can be suppressed.

[Second embodiment]
A solid-state imaging device, imaging apparatus, and imaging method according to the second embodiment will be described with reference to FIG. The same components as those of the solid-state imaging device according to the first embodiment shown in FIGS. 1 to 4 are denoted by the same reference numerals, and the description thereof is omitted or simplified.
The solid-state imaging device 500 according to this embodiment lowers the bias voltage applied to the SPAD 111 provided in the pixel when the count value of the counter 114 reaches the threshold value Cref.

FIG. 5 is a diagram showing a solid-state imaging device according to this embodiment. As shown in FIG. 5, a solid-state imaging device 500 according to this embodiment includes a vertical scanning unit 101, a timing generator 102, a column memory unit 103, a horizontal scanning unit 104, and a plurality of pixels 510 arranged in a matrix. and Although four pixels 510 a , 510 b , 510 c , and 510 d are shown here for simplification of explanation, a large number of pixels 510 are actually provided in the solid-state imaging device 500 . Further, reference numeral 510 is used when general pixels are described, and reference numerals 510a to 510d are used when specific individual pixels are described.

The pixel 510 includes a SPAD 111 , a quench element 512 , an inverter 113 , a counter 114 , a control section 515 , a transfer switch 116 , a pixel memory 117 , a readout switch 118 and a changeover switch 519 . SPAD 111 , quench element 512 and inverter 113 are provided in sensor section 303 arranged on substrate 301 . Counter 114 , control unit 515 , transfer switch 116 , pixel memory 117 , readout switch 118 , and changeover switch 519 are provided in counting unit 304 arranged on substrate 302 .

The quench element 512 is a resistive element for stopping the avalanche multiplication of the SPAD 111, like the quench element 112 described above in the first embodiment. The quench element 512 is configured using the resistance component of the MOS transistor. A predetermined voltage Vg is applied to the gate terminal of the MOS transistor forming the quench element 512, and the quench element 512 is in an ON state. A drain terminal of the MOS transistor forming the quench element 512 is connected to a changeover switch (power supply changeover switch) 519 .

The control unit 515 supplies a control signal CTRL2 to the switch 519 based on the count value of the counter 114 . The switch 519 is switched by a control signal CTRL2 supplied from the control section 515. FIG. The changeover switch 519 sets the connection destination of the drain terminal of the MOS transistor forming the quench element 512 to either the bias voltage Vbias or the voltage Vres based on the control signal CTRL2. The bias voltage Vbias is, as described above, a voltage higher than the breakdown voltage Vbr of the SPAD 111, eg +20V. On the other hand, the voltage Vres is a voltage lower than the breakdown voltage Vbr, for example +5V. When the count value of the counter 114 is less than the threshold value Cref, the control unit 515 sets the control signal CTRL2 to, for example, High level. On the other hand, when the count value of the counter 114 reaches the threshold value Cref, the control unit 515 sets the control signal CTRL2 to, for example, Low level. When the control signal CTRL2 is at High level, the bias voltage Vbias is applied to the drain terminal of the MOS transistor forming the quench element 512. FIG. Also, when the control signal CTRL2 changes from High level to Low level, the voltage Vres is applied to the drain terminal of the MOS transistor that constitutes the quench element 512 . Thus, when the count value of the counter 114 reaches the threshold value Cref, the control unit 515 changes the control signal CTRL2 from High level to Low level to switch the changeover switch 519 . As a result, the voltage applied to the SPAD 111 via the quench element 512 switches from the bias voltage Vbias to the voltage Vres. As described above, the bias voltage Vbias is greater than the SPAD 111 breakdown voltage Vbr, and the voltage Vres is less than the SPAD 111 breakdown voltage Vbr. Accordingly, the operation mode of SPAD 111 switches from the Geiger mode to the non-Geiger mode. A control unit 515 is provided for each pixel 510 . Therefore, the operation mode of the SPAD 111 is switched for each pixel 510. FIG. After the count value of the counter 114 reaches the threshold value Cref, the avalanche current does not flow to the pixel 510, so power consumption can be suppressed in this embodiment as well.

In this embodiment, even after the operation mode of the SPAD 111 is switched from the Geiger mode to the non-Geiger mode, the MOS transistor forming the quench element 512 remains ON. Thus, in this embodiment, unwanted charge generated when the SPAD 111 operates in non-Geiger mode can be discharged through the quench element 512 to the power supply supplying the voltage Vres. If such unnecessary charges cannot be discharged, the charges overflowing from the SPAD 111 may reach the pixels 510 located around the SPAD 111 and cause noise. can be discharged, which can contribute to noise reduction.

Here, the case where the voltage Vres is set to a voltage lower than the breakdown voltage Vbr of the SPAD 111, for example +5 V, has been described as an example, but the voltage Vres is not limited to this. For example, the voltage Vres may be the ground voltage (ground, 0V). In this case, the types of power supply voltages required to drive the solid-state imaging device 500 can be reduced.

As described above, in this embodiment, when the count value of the counter 114 reaches the threshold Cref, the magnitude of the bias voltage applied to the SPAD 111 provided in the pixel 510 becomes equal to or less than the breakdown voltage of the SPAD 111. . Therefore, the operation mode of the SPAD 111 provided in the pixel 510 becomes the non-Geiger mode, and the avalanche current does not flow through the pixel 510 . Therefore, also in this embodiment, an increase in power consumption can be prevented. Moreover, according to the present embodiment, unnecessary charges generated during operation in the non-Geiger mode can be discharged to the power supply that supplies a voltage lower than the breakdown voltage of the SPAD 111. Therefore, unnecessary charges overflow and other pixels 510 are discharged. can be prevented from reaching, which can contribute to noise reduction.

[Third embodiment]
A solid-state imaging device, an imaging device, and a driving method according to the third embodiment will be described with reference to FIG. The same components as those of the solid-state imaging device according to the first embodiment shown in FIGS. 1 to 5 are denoted by the same reference numerals, and the description thereof is omitted or simplified.

The configuration of the solid-state imaging device according to this embodiment can be the same as the configuration of the solid-state imaging device 100 according to the first embodiment or the configuration of the solid-state imaging device 500 according to the second embodiment. Here, a case where the configuration of the solid-state imaging device according to this embodiment is the same as that of the solid-state imaging device 100 according to the first embodiment will be described as an example. However, in this embodiment, as will be described later, the operation of the control unit 115 is different from the operations of the control units 115 and 515 in the first and second embodiments.

FIG. 6 is a timing chart showing the operation of the solid-state imaging device according to this embodiment. Here, the operation of the pixel 110a among the plurality of pixels 110 will be focused on and explained. FIG. 6 shows a timing chart corresponding to two frames out of a plurality of frames forming a moving image. The period from timing t610 to timing t620 corresponds to the m-th frame FRAMEm. The period from timing t620 to timing t630 corresponds to the (m+1)th frame FRAMEm+1.

First, at timing t610, when the synchronization signal VD becomes High level, the timing generator 102 makes the control signal CTL High level. The control signal CTL is simultaneously supplied to the control unit 115 provided for each of all the pixels 110 . When the control signal CTL becomes High level, the control section 115 makes the control signal CTRL High level. When the control signal CTRL becomes High level, the MOS transistor forming the quench element 112 is turned on, and the bias voltage Vbias is applied to the SPAD 111 . The timing generator 102 also brings the reset signal RES to a high level at timing t610. When the reset signal RES is set to High level, the counter 114 is reset.

At timing t611, when the voltage of the node PLSa reaches the bias voltage Vbias, the SPAD 111 can operate in Geiger mode.
At timing t612, the timing generator 102 changes the reset signal RES to Low level. When the reset signal RES becomes Low level, the reset of the counter 114 is released, and the counter 114 starts counting the pulse signal PLS output from the inverter 113 .
The period from timing t612 to timing t618 is the photon detection period of the m-th frame FRAMEm, and the number of photons detected in each pixel 110 during the photon detection period is the number of pixels in the m-th frame FRAMEm. signal value.

When the count value of the counter 114 is less than the threshold (reference signal) Cref, the control unit 115 maintains the control signal CTRL at High level. Control unit 115 gradually increases threshold Cref over time. The control unit 115 sets the threshold Cref to the first value during the period from the first timing to the second timing. As a result, the threshold Cref is set to Cref0 during the period from timing t610 to timing t613. The control unit 115 sets the threshold Cref to a second value larger than the first value during the period from the second timing to the third timing. As a result, the threshold Cref is set to Cref1, which is larger than Cref0, during the period from timing t613 to timing t614. The control unit 115 sets the threshold Cref to a third value larger than the second value during the period from the third timing to the fourth timing. As a result, the threshold Cref is set to Cref2, which is larger than Cref1, during the period from timing t614 to timing t615. The control unit 115 sets the threshold Cref to a fourth value larger than the third value during the period from the fourth timing to the fifth timing. As a result, the threshold Cref is set to Cref3, which is larger than Cref2, during the period from timing t615 to timing t620. Thus, the control unit 115 gradually increases the value of the threshold Cref over time. Control unit 115 can detect the passage of time by a timer (not shown) provided in control unit 115 . A signal for increasing the threshold value Cref may be supplied from the timing generator 102 to the control unit 115 instead of providing the control unit 115 with a timer. The specific values of Cref0, Cref1, and Cref2 and the timing of setting the threshold Cref to these values are determined so that the count value of the counter 114 is fully expected to reach Cref3 in the photon detection period. , respectively. If the bit width of the counter 114 is 16, for example, Cref3 is set to 0xFFFF (65535 in decimal). Note that Cref3 is not limited to 0xFFFF. Cref3 may be the maximum value of the signal range required in an imaging apparatus provided with the solid-state imaging device according to this embodiment. Here, a case where the count value of the counter 114 reaches the threshold Cref at timing t616 will be described as an example. The threshold Cref at timing t616 is Cref3.

At timing t616, when the count value of the counter 114 reaches the threshold value Cref, the control section 115 changes the control signal CTRL to Low level. When the control signal CTRL becomes Low level, the MOS transistor forming the quench element 112 is turned off.

At timing t617, the potential of the node PLSa becomes equal to or lower than the breakdown voltage Vbr of the SPAD 111. FIG. When the potential of the node PLSa becomes equal to or lower than the breakdown voltage Vbr of the SPAD 111, the operation mode of the SPAD 111 becomes the non-Geiger mode. In the non-Geiger mode, even if a photon is incident on the SPAD 111, no avalanche current is generated. Counter 114 continues to hold Cref3 as the count value.

At timing t618, the timing generator 102 changes the transfer signal WRT to High level. When the transfer signal WRT becomes High level, the transfer switch 116 is turned on, and the count value of the counter 114 at timing t618 is written to the pixel memory 117. FIG. Since the count value of the counter 114 is Cref3, data indicating Cref3 is written in the pixel memory 117 .

Here, the case where the count value of the counter 114 reaches the threshold Cref at the timing t616 before the timing t618 has been described as an example. However, if the count value of the counter 114 is less than the threshold Cref even at timing t618, the following will occur. That is, in such a case, the counter 114 continues counting the pulse signal PLS until timing t618. Then, the count value of the counter 114 at timing t618 is written to the pixel memory 117 at timing t618.

During the period from timing t620 to timing t630, the (m+1)th frame FRAMEm+1 is acquired and the pixel signal values of the mth frame FRAMEm are read. Here, a case where the count value of the counter 114 reaches the threshold Cref at timing t622 will be described as an example. Readout of the pixel signal values of the m-th frame FRAMEm is the same as in the first embodiment, so description thereof will be omitted.
During the period from timing t620 to timing t621, the control unit 115 sets the value of the threshold Cref to Cref0. Here, a case where the counter value of the counter 114 does not reach Cref0 at a stage before timing t621 will be described as an example.

At timing t621, the control unit 115 changes the threshold Cref from Cref0 to Cref1. Here, the case where the count value of the counter 114 reaches the threshold Cref at the timing t622 before the timing t623 at which the threshold Cref is switched from Cref1 to Cref2 will be described as an example.

At timing t622, when the count value of the counter 114 reaches the threshold Cref, the controller 115 operates as follows. That is, when the count value of the counter 114 reaches the threshold Cref, the control section 115 sets the control signal CTRL to Low level to turn off the MOS transistor forming the quench element 112 . Also, the control unit 115 sets the count value of the counter 114 to Cref3. Counter 114 maintains Cref3 set by control unit 115 as a count value. Then, at timing t624, the count value of the counter 114, that is, Cref3 is written to the pixel memory 117. FIG.

As described above, according to the present embodiment, since the threshold Cref is gradually increased according to the elapsed time, the counter value of the counter 114 reaches the threshold Cref at a relatively early stage in the pixel 110 where many photons are incident. and the avalanche current stops flowing. Therefore, according to the present embodiment, it is possible to further reduce power consumption.

[Fourth embodiment]
A solid-state imaging device, an imaging apparatus, and an imaging method according to the fourth embodiment will be described with reference to FIG. The same components as those of the solid-state imaging devices according to the first to third embodiments shown in FIGS.

The configuration of the solid-state imaging device according to this embodiment can be the same as the configuration of the solid-state imaging device 500 according to the second embodiment. Here, a case where the configuration of the solid-state imaging device according to the present embodiment is the same as that of the solid-state imaging device 500 (see FIG. 5) according to the second embodiment will be described as an example. However, in this embodiment, when the count value of the counter 114 reaches the threshold value Cref, the magnitude of the voltage Vres applied to the SPAD 111 provided in the pixel is set to a voltage slightly lower than the breakdown voltage Vbr of the SPAD 111. is. The breakdown voltage Vbr of the SPAD 111 can be, for example, +19 V, the bias voltage Vbias can be, for example, +20 V, and the voltage Vres can be, for example, +18 V, but they are not limited to these.

FIG. 7 is a timing chart showing the operation of the solid-state imaging device according to this embodiment. Here, the operation of the pixel 110a among the plurality of pixels 110 will be focused on and explained. FIG. 7 shows a timing chart corresponding to two frames out of a plurality of frames forming a moving image. The period from timing t710 to timing t720 corresponds to the m-th frame FRAMEm. The period from timing t720 to timing t730 corresponds to the (m+1)th frame FRAMEm+1.

First, at timing t710, when the synchronization signal (synchronization pulse) VD becomes High level, the control section 515 makes the control signal CTRL2 High level. When the control signal CTRL2 becomes High level, the bias voltage Vbias is applied to the drain terminal of the MOS transistor forming the quench element 512 . The bias voltage Vbias is, for example, +20V as described above.

At timing t711, when the voltage of the node PLSa reaches the bias voltage Vbias, the SPAD 111 can operate in Geiger mode.
At timing t712, the timing generator 102 changes the reset signal RES to Low level. When the reset signal RES becomes Low level, the reset of the counter 114 is released, and the counter 114 starts counting the pulse signal PLS output from the inverter 113 .

The period from timing t712 to timing t715 is the photon detection period of the m-th frame FRAMEm, and the number of photons detected in each pixel 110 during the photon detection period is the pixel signal in the m-th frame FRAMEm. value. Here, a case where the count value of the counter 114 reaches the threshold Cref at timing t713 will be described as an example.

At timing t713, when the count value of the counter 114 reaches the threshold Cref, the control section 515 changes the control signal CTRL2 to Low level. When the control signal CTRL2 becomes Low level, the voltage Vres is applied to the drain of the MOS transistor forming the quench element 112 . Voltage Vres is, for example, +18V as described above.

At timing t714, when the potential of the node PLSa becomes lower than the breakdown voltage Vbr of the SPAD 111, the operation mode of the SPAD 111 becomes the non-Geiger mode. In the non-Geiger mode, even if a photon is incident on the SPAD 111, no avalanche current is generated. The counter 114 keeps holding the threshold Cref as the count value.

At timing t715, the timing generator 102 changes the transfer signal WRT to High level. When the transfer signal WRT becomes High level, the transfer switch 116 is turned on, and the count value of the counter 114 at timing t715 is written to the pixel memory 117. FIG. Since the count value of the counter 114 is the threshold Cref, data indicating the threshold Cref is written to the pixel memory 117 .

Here, the case where the count value of the counter 114 reaches the threshold value Cref at timing t713 before timing t715 has been described as an example. However, if the count value of the counter 114 is less than the threshold Cref even at timing t715, the following will occur. That is, in such a case, the counter 114 continues counting the pulse signal PLS until timing t715. Then, the count value of the counter 114 at timing t715 is written to the pixel memory 117 at timing t715.

During the period from timing t720 to timing t730, the (m+1)th frame FRAMEm+1 is acquired and the pixel signal values of the mth frame FRAMEm are read. Acquisition of the (m+1)th frame FRAMEm+1 is the same as acquisition of the mth frame FRAMEm, and thus description thereof is omitted.

As described above, in the present embodiment, when the count value of the counter 114 reaches the threshold value Cref at timing t713 before timing t715, the control unit 115 sets the control signal CTRL2 to Low level. When the control signal CTRL2 becomes Low level, the voltage Vres is applied to the drain of the MOS transistor forming the quench element 112 . The voltage Vres is a voltage smaller than the breakdown voltage Vbr of the SPAD 111, as described above. Therefore, the operation mode of the SPAD 111 is the non-Geiger mode. Therefore, even when a large number of photons enter the pixel 110, a large amount of avalanche current can be prevented from flowing, and an increase in current consumption can be prevented in this embodiment as well.

Furthermore, in this embodiment, the voltage Vres applied when the SPAD 111 is set to the non-Geiger mode is set to a voltage Vres slightly lower than the breakdown voltage Vbr. Therefore, according to this embodiment, the time required for switching from the non-Geiger mode to the Geiger mode is shortened. That is, in this embodiment, the potential of the node PLSa is held at a relatively high voltage Vres at timing t710. Therefore, according to the present embodiment, the period until the voltage of the node PLSa reaches the bias voltage Vbias, that is, the period from timing t710 to timing t711 can be shortened.

Thus, according to this embodiment, it is possible to shorten the period for allowing the SPAD 111 to stably operate in the Geiger mode, that is, the period from timing t710 to timing t712.

[Modified embodiment]
Although preferred embodiments of the present invention have been described above, the present invention is not limited to these embodiments, and various modifications and changes are possible within the scope of the gist.
For example, in the above embodiment, the case where each of the plurality of pixels is provided with the counter 114, the control unit 115, the pixel memory 117, etc. has been described as an example, but the present invention is not limited to this. For example, pixels adjacent to each other may share these.
Further, in the above embodiment, the case where control is performed so that the avalanche current does not flow to the SPAD 111 when the count value of the counter 114 reaches the threshold has been described as an example, but the present invention is not limited to this. The current flowing through the SPAD 111 may be limited when the count value of the counter 114 reaches a threshold. For example, an element for limiting the current may be arranged on the anode side or the cathode side of the SPAD 111, and the element may limit the current when the count value of the counter 114 reaches the threshold value.

The present invention supplies a program that implements one or more functions of the above-described embodiments to a system or apparatus via a network or a storage medium, and one or more processors in the computer of the system or apparatus reads and executes the program. It can also be realized by processing to It can also be implemented by a circuit (for example, ASIC) that implements one or more functions.

DESCRIPTION OF SYMBOLS 100... Solid-state image sensor 102... Timing generator 110... Pixel 111... SPAD
DESCRIPTION OF SYMBOLS 112... Quench element 113... Inverter 114... Counter 115... Control part 116... Transfer switch 117... Pixel memory part 118... Read switch

Claims (13)

a plurality of pixels each provided with a sensor unit that includes an avalanche photodiode and emits a pulse at a frequency corresponding to the frequency of photon reception;
a counter that counts the number of pulses emitted from the sensor unit;
When the count value of the counter is less than the threshold value, control is performed so that the transistor constituting the quench element connected to the avalanche photodiode is turned on, and the count value of the counter reaches the threshold value. A solid-state imaging device, comprising: a controller for controlling the transistor to be in an OFF state in a case where the transistor is in an OFF state . 2. The solid-state imaging device according to claim 1, wherein said counter starts counting after a predetermined time has passed since said transistor is turned on. a plurality of pixels each provided with a sensor unit that includes an avalanche photodiode and emits a pulse at a frequency corresponding to the frequency of photon reception;
a counter that counts the number of pulses emitted from the sensor unit;
When the count value of the counter is less than the threshold value, control is performed so that a first voltage is applied to the avalanche photodiode, and when the count value of the counter reaches the threshold value, a control unit for controlling a second voltage lower than the first voltage to be applied to the avalanche photodiode;
with
A solid-state imaging device, wherein the second voltage is a ground voltage. 4. The solid-state imaging device according to claim 3, wherein said counter starts counting after a predetermined time has passed since said first voltage is applied to said avalanche photodiode. 5. The solid-state imaging device according to claim 1, wherein each of said plurality of pixels is provided with said counter. 6. The solid-state imaging device according to claim 1, wherein each of said plurality of pixels is provided with said controller. 7. The solid-state imaging device according to claim 1 , wherein said threshold value increases with time. the threshold eventually increases to a first value over time;
setting the count value of the counter to the first value when the count value of the counter reaches the threshold value in a state where the threshold value is set to a second value lower than the first value; 8. The solid-state imaging device according to claim 7 , characterized by: 9. The solid-state imaging device according to claim 1 , further comprising a memory for holding count values output from said counter. A plurality of pixels each provided with a sensor unit that includes an avalanche photodiode and emits a pulse at a frequency corresponding to the frequency of photon reception, a counter that counts the number of pulses emitted from the sensor unit, and a count value of the counter is less than the threshold, the transistor constituting the quench element connected to the avalanche photodiode is controlled to be turned on, and when the count value of the counter reaches the threshold, the A solid-state imaging device comprising a control unit that controls the transistor to be in an OFF state ;
and a processing unit that performs predetermined processing on an image output from the solid-state imaging device. A plurality of pixels each provided with a sensor unit that includes an avalanche photodiode and emits a pulse at a frequency corresponding to the frequency of photon reception, a counter that counts the number of pulses emitted from the sensor unit, and a count value of the counter is less than the threshold, control is performed to apply a first voltage to the avalanche photodiode, and when the count value of the counter reaches the threshold, the avalanche photodiode a control unit that controls so that a second voltage lower than the first voltage is applied to the
wherein the second voltage is a ground voltage, a solid-state imaging device;
and a processing unit that performs predetermined processing on an image output from the solid-state imaging device. When the count value of a counter that counts the number of pulses emitted from a sensor unit that includes an avalanche photodiode and emits pulses at a frequency corresponding to the frequency of photon reception is less than a threshold value, the counter is connected to the avalanche photodiode. a step of controlling to turn on the transistor constituting the quench element ;
and controlling the transistor to be in an OFF state when the count value of the counter reaches the threshold value. When the count value of a counter that counts the number of pulses emitted from a sensor unit that includes an avalanche photodiode and emits pulses at a frequency corresponding to the frequency of photon reception is less than a threshold value, the avalanche photodiode receives a first a step of controlling to apply a voltage of
controlling a second voltage lower than the first voltage to be applied to the avalanche photodiode when the count value of the counter reaches the threshold ;
has
the second voltage is a ground voltage
An imaging method characterized by:

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