JP2019110409A - Solid state imaging device, imaging apparatus, and imaging method - Google Patents

Abstract

To provide a solid state imaging device, an imaging apparatus, and an imaging method, capable of acquiring an image with an excellent gray scale.SOLUTION: A solid state imaging device comprises: a pixel array in which a plurality of pixels in which an optical sensor part emitting a pulse of a prescribed pulse width at a frequency in accordance with a light reception frequency of a light quantum is arranged in a matrix state; a counter counting the number of pulses emitted from the optical sensor part; and a control part capable of performing a control so that a count value is read out from the counter in a period smaller than the product of a counter upper limit value of the counter and a prescribed pulse width.SELECTED DRAWING: Figure 1

Description

  The present invention relates to a solid-state imaging device, an imaging device, and an imaging method.

  CCD image sensors and CMOS image sensors are widely known as image sensors using semiconductors. The CCD image sensor and the CMOS image sensor convert the light incident on the pixel during the exposure period into a charge by the photodiode and output a signal according to the charge.

  In recent years, a photon counting type image sensor has been proposed which counts the number of photons (photons) incident on a photodiode during an exposure period and outputs the count value of photons as a signal value. For example, Patent Document 1 discloses a solid-state imaging device in which an avalanche photodiode and a counter are used. When a reverse bias voltage greater than the breakdown voltage is applied to the avalanche photodiode, carriers generated by the incidence of single photon cause avalanche multiplication, and a large current flows in the avalanche photodiode. It is possible to obtain a signal corresponding to the number of single photons by counting pulse signals corresponding to the incidence of single photons by a counter. The image sensor of the photon counting method uses the number of photons incident on the photodiode as it is as a signal value, and thus is less susceptible to noise compared to a CCD image sensor and a CMOS image sensor. For this reason, the photon counting type image sensor can obtain a good image even in a weak light environment.

Japanese Patent Application Laid-Open No. 61-152176

  However, with the proposed technology, there is a concern that images with good gradation can not always be obtained.

  An object of the present invention is to provide a solid-state imaging device, an imaging device and an imaging method capable of acquiring an image with good gradation.

  According to one aspect of the embodiment, there is provided a pixel array in which a plurality of pixels provided in a matrix are provided with a light sensor unit that emits a pulse having a predetermined pulse width at a frequency according to the light reception frequency of photons The counter can be controlled to read out the count value from the counter in a cycle equal to or less than the product of the count upper limit value of the counter and the predetermined pulse width, and a counter that counts the number of pulses emitted from the unit. There is provided a solid-state imaging device comprising: a control unit.

  According to the present invention, it is possible to provide a solid-state imaging device, an imaging device, and an imaging method capable of acquiring an image with good gradation.

It is a timing chart which shows operation of a solid-state image sensing device by a 1st embodiment. It is a block diagram showing an imaging device by a 1st embodiment. It is a figure which shows the layout of the solid-state image sensor by 1st Embodiment. It is a figure which shows the solid-state image sensor by 1st Embodiment. It is a figure which shows operation | movement of an optical sensor part. It is a figure which shows transition of the count value of a counter. It is a figure which shows transition of the count value of a counter, and the pixel signal memorize | stored in frame memory. It is a timing chart which shows operation of a solid-state image sensing device by a modification of a 1st embodiment. It is a figure which shows the solid-state image sensor by 2nd Embodiment. Driving timing chart showing driving of solid-state imaging device according to the second embodiment It is a figure which shows transition of the count value of a counter. It is a figure which shows the solid-state image sensor by 3rd Embodiment. It is a timing chart which shows operation of a solid-state image sensing device by a 3rd embodiment.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the attached drawings.
First Embodiment
A solid-state imaging device, an imaging device, and an imaging method according to the first embodiment will be described with reference to FIGS. 1 to 7.
FIG. 2 is a block diagram showing an imaging device according to the present embodiment. As shown in FIG. 2, the imaging device 200 according to the present embodiment includes a solid-state imaging device 1, a signal processing unit 2, a lens driving unit 6, a control unit 3, a display unit 4 and a recording unit 5. ing. Further, the imaging device 200 is provided with a photographing lens (imaging optical system, lens unit) 7. The imaging lens 7 may be detachable from the body (main body) of the imaging device 200 or may not be detachable.

  The solid-state imaging device 1 generates an imaging signal by photoelectrically converting an optical image of a subject formed by the imaging lens 7, and outputs the generated imaging signal. The pixel cell (unit pixel) 10 (see FIG. 4) provided in the solid-state imaging device 1 includes a photodiode 101 (see FIG. 4) and a counter (pulse counter) 111 (see FIG. 4). The number of incident photons can be counted and output as a signal value.

  The imaging lens 7 forms an optical image of a subject on the imaging surface of the solid-state imaging device 1. The lens drive unit 6 drives the photographing lens 7 and performs zoom control, focus control, aperture control and the like. The imaging lens 7 forms an optical image of a subject, and causes the formed optical image to be incident on the imaging surface of the solid-state imaging device 1.

  The signal processing unit 2 performs predetermined signal processing (image processing) such as correction processing on an imaging signal (image data) output from the solid-state imaging device 1.

  The control unit (whole control / calculation unit, control means) 3 controls the entire imaging apparatus 200 and performs predetermined arithmetic processing and the like. The control unit 3 outputs control signals for driving each functional block of the imaging device 200, control data for controlling the solid-state imaging device 1, and the like. The control unit 3 performs predetermined signal processing (image processing) and the like such as development and compression on the imaging signal subjected to the signal processing and the like by the signal processing unit 2.

  The display unit 4 displays an imaging signal subjected to signal processing and the like by the control unit 3, various setting information of the imaging device 200, and the like.

  The recording unit (recording control unit) 5 includes a recording medium (not shown). The recording medium may or may not be detachable from the recording unit 5. The recording unit 5 records, on a recording medium, an imaging signal or the like which has been subjected to signal processing and the like by the control unit 3. As such a recording medium, for example, a semiconductor memory such as a flash memory can be mentioned.

  FIG. 3 is a view showing a layout of the solid-state imaging device 1 according to the present embodiment. The solid-state imaging device 1 includes an optical sensor unit substrate 30 in which a plurality of optical sensor units 100 are arranged in a matrix, a counting unit substrate 31 in which a plurality of counting units 110 are arranged in a matrix, and a frame memory 13. The frame memory substrate 32 is stacked.

  The light sensor unit substrate 30 includes a pixel array (imaging area) 300 in which a plurality of light sensor units (sensor units) 100 are arranged in a matrix of J rows × K columns. The detailed configuration of the light sensor unit 100 will be described later.

  The counting unit substrate 31 includes a counting area 310 in which a plurality of counting units (counting means) 110 are arranged in a matrix of J rows × K columns. The plurality of counting units 110 disposed in the counting area 310 correspond to the plurality of light sensor units 100 disposed in the pixel array 300.

  An electrode (not shown) provided on the light sensor unit substrate 30 and an electrode (not shown) provided on the counting unit substrate 31 are electrically connected to each other. Further, an electrode (not shown) provided on the counter substrate 31 and an electrode (not shown) provided on the frame memory substrate 32 are electrically connected to each other. Thus, the pulse signal Pout output from the light sensor unit 100 provided on the light sensor unit substrate 30 is input to the counting unit 110 provided on the counting unit substrate 31.

  One pixel cell 10 is configured by one light sensor unit 100 and one counting unit 110. The detailed configuration of the counting unit 110 will be described later.

  The counting unit substrate 31 includes a drive control unit 311 and a temporary storage unit 312. The drive control unit 311 controls the drive of the counting area 310. The temporary storage unit 312 includes a temporary storage unit 312 provided with a read memory 11 described later. The read memory 11 temporarily stores the count value read from the counting unit 110.

  The frame memory substrate 32 includes an adder circuit 12 and a frame memory 13. The frame memory 13 stores the count value read from each counting unit 110 as a pixel signal of each pixel. The adder circuit 12 sequentially adds the count value from each of the pixel cells 10 sequentially read out through the readout memory 11 to the pixel signal stored in the frame memory 13. The frame memory 13 stores the integrated value of the count value read from the counting unit 110. The frame memory substrate 32 further includes a memory control unit 321 and an output unit 322. The memory control unit 321 controls writing and reading of data (signal value) to the frame memory 13. The output unit 322 outputs the pixel signal (image signal, imaging signal) held in the frame memory 13 to the outside of the solid-state imaging device 1.

  Since the light sensor unit 100 and the counting unit 110 are provided on separate substrates, a large area of the light sensor unit 100 can be secured. In addition, if the frame memory substrate 32 is manufactured by a process finer than the optical sensor unit substrate 30 and the counting unit substrate 31, data with a sufficiently large bit width can be recorded in the frame memory 13. The configuration of the solid-state imaging device 1 is not limited to the above configuration. For example, the light sensor unit 100 and the counting unit 110 may be provided on the same substrate.

FIG. 4 is a diagram showing the configuration of the solid-state imaging device 1 according to the present embodiment.
The pixel cell 10 includes an optical sensor unit 100 and a counting unit 110. The light sensor unit 100 includes a photodiode (avalanche photodiode) 101, a load resistor 102, and a waveform shaping circuit 103. The anode of the photodiode 101 is grounded. The cathode of the photodiode 101 is connected to the bias voltage Vbias via the load resistor 102. The connection portion between the cathode of the photodiode 101 and the load resistor 102 is connected to the waveform shaping circuit 103.

The counting unit 110 includes a counter 111 and a selection switch 121. The pulse signal Pout output from the waveform shaping circuit 103 is input to the counter 111. The counter 111 counts the number of times the pulse signal Pout turns from low level to high level. The counter 111 can count the pulse signal Pout (2 ^N −1) times. The counter 111 is an N-bit counter capable of counting the number of pulses for N bits and storing the count value. The N-bit counter is configured, for example, by connecting N flip-flops. The count enable signal PEN for enabling the counter 111 is supplied from the drive control unit 311 to the counter 111. When the count enable signal PEN is at high level, the counter 111 can perform counting operation. When the count enable signal PEN is at low level, the counter 111 stops the counting operation and holds the count value immediately before the counting operation is stopped. A reset signal PRES for resetting the count value is supplied from the drive control unit 311 to the counter 111. When the reset signal PRES is at low level, the counter 111 performs the counting operation or the operation of holding the count value according to the count enable signal PEN. When the reset signal PRES becomes high level, the count value of the counter 111 is reset.

  The count value having a bit width of N output from the counter 111 is parallel-transmitted to the read memory 11 via the bus line 122 provided with N wirings. When a high level pixel selection signal PSEL is supplied from the drive control unit 311 to the selection switch 121, the selection switch 121 provided on the bus line 122 is turned on. When a high level memory selection signal PMEM is supplied from the drive control unit 311 to the read memory 11, the count value with a bit width N output from the counter 111 is supplied to the read memory 11. Here, in the case where the count value sequentially output from the counters 111 of the J pixel cells 10 arranged in the same column is input to the readout memory 11 via the common bus line 122 for N bits. Will be described by way of example. When the high level read signal PRD is supplied from the drive control unit 311 to the read memory 11, the count value held in the read memory 11 is output to the adder circuit 12. The adder circuit 12 sequentially adds the count value sequentially read out from the pixel cell 10 via the readout memory 11 to the pixel signal stored in the frame memory 13. More specifically, the adder circuit 12 reads out the count value output from a certain pixel cell 10 and acquires it via the memory 11. Further, the addition circuit 12 reads a pixel signal corresponding to the pixel cell 10 from the frame memory 13. Then, the adding circuit 12 adds the count value of the pixel cell 10 acquired via the readout memory 11 and the pixel signal of the pixel cell 10 read out from the frame memory 13. Then, the addition circuit 12 stores the pixel signal obtained by such addition processing in the frame memory 13 as a pixel signal of the pixel cell 10. Thus, integration processing of pixel signals is performed. The adder circuit 12 sequentially performs such processing on the count value acquired by each of the plurality of pixel cells 10 provided in the pixel array 300. The frame memory 13 can store pixel signals of M bits (M> N) per pixel.

Next, the operation of the solid-state imaging device 1 according to the present embodiment will be described.
In the present embodiment, in the count period in which photons are counted by the counter 111, the readout of the count value is repeated in a readout cycle shorter than the period required for the count value of the counter 111 to saturate. When the count value is read from the counter 111, the counter 111 is reset. After this, the counter 111 continues counting photons. In the present embodiment, the count value of the counter 111 is not saturated in one read cycle. Therefore, even when pulse signals Pout whose number exceeds the count upper limit value of the counter 111 are input during the count period, the count value acquired by the counter 111 can be reflected on the pixel signal without leakage. The count value read from the counter 111 is integrated in pixel units. Therefore, it is possible to obtain an M bit pixel signal having a bit width exceeding the bit width N of the counter 111. Therefore, it is possible to obtain pixel signals corresponding to the number of photons exceeding the count upper limit value of the counter 111.

  Here, the operation of the light sensor unit 100 will be described with reference to FIG. FIG. 5 is a diagram showing an operation of the light sensor unit 100. As shown in FIG. FIG. 5 shows a time change of the cathode terminal voltage Vout when a photon is incident on the photodiode 101 and a time change of the pulse signal Pout output from the waveform shaping circuit 103. The horizontal axis in FIG. 5 indicates time T.

  A reverse bias voltage Vbias exceeding the breakdown voltage Vbr is applied to the cathode terminal of the photodiode 101. Thus, the photodiode 101 can operate in Geiger mode. In this state, when a photon is incident on the photodiode 101, carriers generated in the photodiode 101 cause avalanche multiplication development to generate an avalanche current. Due to this avalanche current, the cathode terminal voltage Vout of the photodiode 101 connected to the load resistor 102 starts to decrease.

  The cathode terminal voltage Vout of the photodiode 101 decreases to the threshold voltage Vth, and thereafter, the cathode terminal voltage Vout of the photodiode 101 continues to further decrease. At the timing when the cathode terminal voltage Vout of the photodiode 101 falls to the threshold voltage Vth, the pulse signal Pout output from the waveform shaping circuit 103 transitions from the low level to the high level.

The cathode terminal voltage Vout of the photodiode 101 falls to the breakdown voltage Vbr. When the cathode terminal voltage Vout of the photodiode 101 falls to the breakdown voltage Vbr, avalanche multiplication development is stopped. Then, since the power supply supplying the bias voltage Vbias is recharged via the load resistor 102, the cathode terminal voltage Vout of the photodiode 101 starts to rise.
Thereafter, the cathode terminal voltage Vout of the photodiode 101 rises to the threshold voltage Vth. At the timing when the cathode terminal voltage Vout of the photodiode 101 reaches the threshold voltage Vth, the pulse signal Pout output from the waveform shaping circuit 103 transitions from high level to low level.

  After this, recharging is completed. At the stage where the recharging is completed, the cathode terminal voltage Vout of the photodiode 101 returns to the reverse bias voltage Vbias. The time required for recharging depends on the resistance value of the load resistor 102 and the parasitic capacitance. As described above, one pulse signal Pout having a pulse width ΔTp is output from the light sensor unit 100 by the incidence of one photon. As described above, the light sensor unit 100 generates the pulse signal Pout at a frequency according to the light reception frequency of the photons.

  As described above, the pulse signal Pout output from the light sensor unit 100 is at the low level in the steady state. On the other hand, while the cathode terminal voltage Vout of the photodiode 101 is lower than the threshold voltage Vth, the pulse signal Pout output from the light sensor unit 100 is at the high level. That is, the pulse signal Pout output from the light sensor unit 100 changes from the low level to the high level each time a photon is incident on the photodiode 101, and returns to the low level after a predetermined period elapses. Therefore, by counting the pulse signal Pout output from the light sensor unit 100, the number of photons incident on the photodiode 101 can be detected. The pulse width ΔTp of the pulse signal Pout corresponds to a period from when the pulse signal Pout turns to high level and then returns to low level by the incidence of one photon.

FIG. 6 is a diagram showing the transition of the count value C of the counter 111. As shown in FIG. Since the bit width of the counter 111 is N, the count upper limit, which is the maximum value that can be counted by the counter 111, is (2 ^N −1). FIG. 6 shows an example where the count value C of the counter 111 reaches the count upper limit value in the shortest time ΔTsat.

The count value C of the counter 111 is incremented each time the pulse signal Pout transitions to the high level. The interval at which the count value C is incremented does not fall below the pulse width ΔTp of the pulse signal Pout. Therefore, the shortest time ΔTsat required for the count value C of the counter 111 to reach the count upper limit value from 0 is expressed by the following equation (1).
ΔTsat = ΔTp × (2 ^N −1) (1)

  Therefore, if the reading of the count value from the counter 111 and the resetting of the counter 111 are repeated in a cycle equal to or less than the above-described shortest time ΔTsat, the pulse signal Pout is counted while preventing the counter 111 from being saturated. Can.

  FIG. 1 is a timing chart showing an example of the operation of the solid-state imaging device 1 according to the present embodiment. FIG. 1 shows an operation in which the total number of photons counted during the count period ΔTacc is acquired for each pixel, and an image signal of one frame is generated.

  At timing T100, the drive control unit 311 supplies the pulse-like reset signal PRES to the counters 111 respectively provided to all the pixel cells 10. Thereby, the counters 111 of all the pixel cells 10 are reset, and the photographing operation for one frame is started. The frame memory 13 is reset at a timing prior to the timing at which the reading of the count value from the counter 111 is started. Here, the case where the frame memory 13 is reset at timing T100 will be described as an example.

  At timing T101, the drive control unit 311 supplies the high-level count enable signal PEN to the counters 111 respectively provided to all the pixel cells 10. Thereby, the counting by the counter 111 of the pulse signal Pout output from the light sensor unit 100 is started in all the pixel cells 10.

  At timing T102, the first reading of the count value is started. The drive control unit 311 supplies a pixel selection signal PSEL of high level to the plurality of pixel cells 10 located in the first row of the pixel array 300. Thus, the plurality of pixel cells 10 located in the first row of the pixel array 300 are selected. Among the J pixel cells 10 sharing the readout memory 11, the pixel cell 10 located in the first row is selected. In addition, the drive control unit 311 reads the high level memory selection signal PMEM and supplies the read memory selection signal PMEM to the memory 11. Thus, the count value output from the counter 111 of the pixel cell 10 is stored in the readout memory 11. After this, the drive control unit 311 supplies a high level reset signal PRES to the pixel cells 10 located in the first row. As a result, the counters 111 provided in the pixel cells 10 located in the first row are reset. After the reset is performed, the counter 111 continues counting the pulse signal Pout. Thereafter, the drive control unit 311 supplies the read signal PRD to the read memory 11. Thus, the count value stored in the read memory 11 is input to the frame memory 13 via the adder circuit 12. The pixel signals acquired using the respective pixel cells 10 are sequentially stored in the frame memory 13 in this manner. A period ΔTread from the timing T101 when the counting is started to the timing T103 when the counter 111 located in the J-th row is reset is set to the above-mentioned shortest time ΔTsat or less. Since the period ΔTread is set to the shortest time ΔTsat or less, readout of the count value is completed before the counters 111 of all the pixel cells 10 reach the count upper limit value. As described above, in the present embodiment, reading of the count value from the counter 111 and resetting of the counter 111 are performed in a cycle equal to or less than the product of the count upper limit value of the counter 111 and the pulse width ΔTp of the pulse signal Pout.

  The readout of the second count value starts at timing T104 when the period ΔTread has elapsed since the first count value readout from the counter 111 provided in the pixel cell 10 positioned in the first row. Be done. Also in the second reading of the count value, the count value is sequentially read from the pixel cell 10 as in the first reading of the count value. The adder circuit 12 sequentially adds the count values sequentially read out through the readout memory 11 to the pixel signals stored in the frame memory 13. The count value of a certain pixel cell 10 located in the first row is, for example, C1 at the time of reading the first count value. The count value C1 is held in the frame memory 13 as a pixel signal of the pixel cell 10. The count value of the one pixel cell 10 is, for example, C2 at the time of reading the second count value. The adder circuit 12 obtains the addition value (C1 + C2) by adding the count value C1 and the count value C2. The addition value (C1 + C2) thus obtained by the addition circuit 12 is stored in the frame memory 13 as a pixel signal of the pixel cell 10. As described above, timing T103 is timing at which the counter 111 located in the J-th row is reset in the first reading of the count value. The timing T105 is, as described above, the timing at which the counter 111 located in the J-th row is reset in the second reading of the count value. The period ΔTread from the timing T103 to the timing T105 is also set equal to or less than the above-described shortest time ΔTsat.

  Reading of the third and subsequent count values is also performed in the same manner as reading of the second count value. Also after timing T106, the same operation as described above is repeated until the count enable signal PEN transitions to the low level.

  At timing T107 at which the count period ΔTacc has elapsed from timing T101 at which counting is started, the drive control unit 311 causes the count enable signal PEN to transition to the low level. As a result, counting of the pulse signal Pout output from the light sensor unit 100 is stopped at the counters 111 of all the pixel cells 10. The counters 111 provided in each of the plurality of pixel cells 10 provided in the pixel array 300 respectively hold count values. Thereafter, the count value is read from each pixel cell 10 in the same manner as described above. The adder circuit 12 sequentially adds the count value sequentially read from each pixel cell 10 to the pixel signal held in the frame memory 13.

  From timing T108 to timing T109, the signal value of each pixel stored in the frame memory 13 is output to the outside of the solid-state imaging device 1. Thus, the shooting operation of one frame is completed.

  FIG. 7 is a diagram showing the transition between the count value of the counter 111 and the pixel signal stored in the frame memory 13. FIG. 7 focuses on one pixel cell 10 among the plurality of pixel cells 10 provided in the pixel array 300. The count value of the counter 111 and the pixel signal stored in the frame memory 13 are shown in FIG.

  At the timing when the count period ΔTacc starts, the counter 111 and the frame memory 13 are reset. The counter 111 starts counting pulse signals. Thereafter, each time the pulse signal Pout is output, the count value of the counter 111 is incremented in the pixel cell 10.

  At the timing when a period ΔT1 shorter than the above-described shortest time ΔTsat elapses, the count value is read from the counter 111, and the count value of the counter 111 is reset. The counter 111 continues counting the pulse signal Pout even after being reset. The count value read from the counter 111 is integrated with the reset value 0 held in the frame memory 13 and stored in the frame memory 13 as a pixel signal.

  After that, at the timing when the above-mentioned period ΔTread which is shorter than the above-mentioned shortest time ΔTsat elapses, the count value is read from the counter 111, and the count value of the counter 111 is reset. The counter 111 continues counting the pulse signal Pout even after being reset. The count value read from the counter 111 is integrated with the pixel signal held in the frame memory 13, and the pixel signal obtained by the integration is stored in the frame memory 13. After this, the same operation as described above is repeated with a period of ΔTread.

  At the timing when the count period ΔTacc has elapsed, the counter 111 stops counting the pulse signal. Then, the count value is read from the counter 111. The count value read from the counter 111 is integrated with the pixel signal held in the frame memory 13, and the pixel signal obtained by the integration is stored in the frame memory 13. Thus, the pixel signals stored in the frame memory 13 correspond to the number of pulse signals Pout counted in each pixel cell 10 within the count period ΔTacc.

  As described above, according to the present embodiment, the count value counted in a period shorter than the shortest time ΔTsat required for the count value of the counter 111 to reach the count upper limit value is read, and the counter 111 is read. Reset is performed. The count values read out from the counter 111 are sequentially accumulated and held in the frame memory 13 which can hold an image signal having a bit width larger than that of the counter 111. Therefore, according to the present embodiment, it is possible to prevent the count value of the counter 111 from being saturated during the exposure period, and it is possible to obtain an image with good gradation.

(Modification 1)
Next, a solid-state imaging device 1 according to a modification of the present embodiment will be described.
The counter 111 provided in the pixel cell 10 of the solid-state imaging device 1 according to the present modification is reset to 0 at the next count when the count value is saturated, and performs the count operation repeating the count operation thereafter. The adder circuit 12 subtracts the count value Ci−1 read from the same counter 111 one time earlier than the count value Ci from the count value Ci read out from the counter 111 i. The count value Ci-1 is sent to and stored in the frame memory 13 when the count value Ci-1 is read, and sent to the addition circuit 12 when the count value Ci is read, and used for subtraction processing. The subtraction value obtained at this time is N obtained by adding 1 to the complement of count value Ci-1 and adding to count value Ci with respect to N-bit count value Ci and Ci-1 represented by binary numbers. It is a bit value. The addition circuit 12 further adds the subtraction value of the count value Ci-1 from the count value Ci to the integrated value of the subtraction values obtained from the exposure start to the i-1st count value readout. The frame memory 13 stores the integrated value for each counter 111 and the count value Ci of the subtraction value from the start of exposure. The count value Ci stored in the frame memory is updated to the latest count value for each counter 111 each time the count value is read.
In this configuration, it is not necessary to reset the counter 111 during the exposure period, and the drive control of the counter 111 is simplified.
According to the present embodiment, it is possible to obtain an image with good gradation without resetting the count value of the counter 111 during the exposure period.

(Modification 2)
Next, a solid-state imaging device 1 according to another modification of the present embodiment will be described with reference to FIG.
The solid-state imaging device 1 according to this modification can set the cycle in which the count value is read out from the counter 111 provided in the pixel cell 10 according to the luminance of the subject.

  FIG. 8 is a timing chart showing the operation of the solid-state imaging device according to the present modification. FIG. 8 shows an example of the read operation. Here, the case where the reading of the count value is not performed in the counting period ΔTacc and the reading of the count value is performed after the counting period ΔTacc ends will be described as an example. In the present modification, since the reading of the count value is not performed during the count period ΔTacc, the frequency at which the component positioned downstream of the counter 111 is driven is reduced, and power consumption is thus reduced.

  The operation at timings T800 and T801 is similar to the operation at timings T100 and T101 described above with reference to FIG.

  During the count period ΔTacc, reading of the count value from the counter 111 is not performed, and the counter 111 counts the pulse signal Pout.

  At timing T802 when the count period ΔTacc has elapsed from timing T801 of the count start, the drive control unit 311 sets the count enable signal PEN to the low level. Thereby, in all of the plurality of pixel cells 10 provided in the pixel array 300, the counting by the counter 111 of the pulse signal Pout output from the light sensor unit 100 is stopped. The count value obtained in the counter 111 of each pixel cell 10 when the counting is stopped is held by the counter 111 of each pixel cell 10 respectively. Thereafter, the count value is read from the counter 111 of each pixel cell 10, and the read pixel signal is stored in the frame memory 13.

  At timings T803 to T804, the pixel signal of each pixel stored in the frame memory 13 is output to the outside of the solid-state imaging device 1. Thus, shooting of an image corresponding to one frame is completed.

  The imaging device according to the present modification is provided with a photometric unit (not shown). The photometric means can determine the brightness of the subject. For example, a photometric sensor or the like can be used as the photometric means, but it is not limited to this. For example, the luminance of the subject may be determined based on the pixel signal acquired by the solid-state imaging device 1.

  A threshold value is set based on the luminance of the subject such that the count value of the counter 111 reaches the count upper limit value at the end of the count period ΔTacc. When the brightness of the subject is less than the threshold value, the possibility that the count value of the counter 111 reaches the count upper limit during the count period ΔTacc is low. Therefore, in the present modification, when the luminance of the subject is equal to or higher than the threshold value, the solid-state imaging device 1 is operated in the first operation mode. The first operation mode is the operation mode as described above with reference to FIGS. 1 to 7.

  On the other hand, when the luminance of the subject is equal to or higher than the threshold, the count value of the counter 111 is likely to reach the count upper limit during the count period ΔTacc. Therefore, in the present modification, when the luminance of the subject is less than the threshold value, the solid-state imaging device 1 is operated in the second operation mode. The second operation mode is the operation mode as described above with reference to FIG.

  In the above description, reading of the count value is not performed in the count period ΔTacc, and reading of the count value is performed after the count period ΔTacc is completed. Absent. For example, the cycle in which the count value is read out from the counter 111 provided in the pixel cell 10 may be set according to the luminance of the subject. For example, as the luminance of the subject decreases, the cycle in which the count value is read out from the counter 111 provided in the pixel cell 10 may be made longer.

  According to the present embodiment, the cycle in which the count value is read out from the counter 111 provided in the pixel cell 10 is set according to the luminance of the subject. For this reason, according to the present embodiment, when the luminance of the subject is low, the frequency at which the component positioned downstream of the counter 111 is driven is low, and power consumption can be reduced.

Second Embodiment
A solid-state imaging device, an imaging device, and an imaging method according to a second embodiment will be described with reference to FIGS. 9 and 10. The same members of the present embodiment as those of the solid-state imaging device, the imaging device and the imaging method according to the first embodiment shown in FIGS. 1 to 8 are represented by the same reference numbers not to repeat or to simplify their explanation.

  In the solid-state imaging device according to the present embodiment, the count value obtained by the counter 111a is read out via the bus line 122a provided with a number of wires smaller than the bit width of the counter 111a.

FIG. 9 is a view showing a solid-state imaging device 1a according to the present embodiment.
In the pixel array 300, a plurality of pixel cells 10a are arranged in a matrix. The counting unit 110a provided in the pixel cell 10a is provided with a counter 111a having a bit width of N. The counter 111 a includes an upper bit unit 112, a lower bit unit 113, and a carry memory 114. The bit width of the upper bit part 112 is L. Here, although the case where L is N / 2 is described as an example, the present invention is not limited to this. The bit width of the lower bit portion 113 is (N−L). Here, (N−L) is also N / 2 in order to explain an example where L is N / 2. The carry memory 114 acquires and holds information indicating the carry of the lower bit portion 113. The bit width of the carry memory 114 is, for example, one.

  The count enable signal PEN is supplied from the drive control unit 311 to the lower bit unit 113. When the count enable signal PEN is at the high level, the lower bit unit 113 can perform the counting operation. When the count enable signal PEN is at low level, the lower bit unit 113 stops the count operation and holds the count value immediately before the count operation is stopped.

  The upper bit enable signal PEN1 is supplied to the upper bit unit 112 from the drive control unit 311. When the upper bit enable signal PEN1 is at high level, the upper bit unit 112 can perform counting operation. When the upper bit enable signal PEN1 is at low level, the upper bit unit 112 stops the count operation and holds the count value immediately before the stop of the count operation.

  The carry memory 114 receives an inverted signal of the upper bit enable signal PEN1. In the drawing, the inverted signal of the upper bit enable signal PEN1 is shown using the symbol PEN1 with a bar, and in the specification, the upper bit enable signal PEN1 is represented using the code / PEN1. An inverted signal is shown.

The carry memory 114 performs the same counting operation as the least significant bit of the upper bit unit 112 when the upper bit enable signal PEN1 is at low level, that is, when the counting operation of the upper bit unit 112 is stopped. If the count value of the lower bit portion 113 does not exceed the count upper limit value of the lower bit portion 113, no carry information is stored in the carry memory 114. That is, in this case, for example, a low level carry signal is stored in the carry memory 114. On the other hand, when the count value of the lower bit portion 113 exceeds the count upper limit value of the lower bit portion 113, carry information is stored in the carry memory 114. That is, in this case, for example, a high level carry signal is stored in the carry memory 114. When the count value of the lower bit portion 113 returns from (2 ^N-L- 1) which is the count upper limit value to 0 which is the count lower limit value, the carry memory 114 stores a high level carry signal. As described above, the carry memory 114 indicates whether or not the count value of the upper bit part 112 exceeds the count upper limit while the count operation of the upper bit part 112 is stopped. Therefore, even when the count value of lower bit portion 113 exceeds the upper limit value of lower bit portion 113 while the count operation of upper bit portion 112 is stopped, it is stored in carry memory 114. The count information can be supplemented using the above information. For this reason, according to the present embodiment, it is possible to prevent the information related to the count value from being lost.

  The reset signal PRES1 is supplied from the drive control unit 311 to the upper bit unit 112. When the reset signal PRES1 becomes high level, the count value of the upper bit unit 112 is reset. The lower bit unit 113 is supplied with a reset signal PRES 2 from the drive control unit 311. When the reset signal PRES2 becomes high level, the count value of the lower bit portion 113 is reset. The data shift signal PDS is supplied from the drive control unit 311 to the lower bit unit 113. When the data shift signal PDS becomes high level, the count value of the lower bit part 113 is written to the upper bit part 112. The carry memory 114 is supplied with a reset signal PRES3 from the drive control unit 311. When the reset signal PRES3 becomes high level, the carry information held in the carry memory 114 is reset.

  The bus line 122 a is provided with L wirings corresponding to the bit width of the upper bit portion 112. The signal of the least significant bit of the upper bit portion 112 is output to the wiring of the least significant bit of the bus line 122 a via the selection switch 123 and the selection switch 121 a. The signal of bits other than the least significant bit of the upper bit part 112 is output to the wiring of bits other than the least significant bit of the bus line 122a through the selection switch 121a. A signal from the carry memory 114 is supplied through the selection switch 123 to the wiring to which the signal from the least significant bit of the upper bit portion 112 is supplied among the L wirings provided on the bus line 122a. . One of the signal from the least significant bit of the upper bit portion 112 and the signal from the carry memory 114 is selectively supplied by the selection switch 123 to the wiring of the least significant bit of the bus line 122 a. The pixel selection signal PSEL2 is supplied from the drive control unit 311 to the selection switch 123. The pixel selection signal PSEL1 is supplied from the drive control unit 311 to the selection switch 121a.

  The bit width of the read memory 11a is N + 1. The count value acquired by the counter 111a is stored in the N bit memory area 118 of the N + 1 bit memory area provided in the read memory 11a. Information acquired by the carry memory 114 is stored in a 1-bit memory area 117 of the (N + 1) -bit memory area provided in the read memory 11 a. The memory area 118 is provided with an upper bit portion 115 and a lower bit portion 116. The bit width of the upper bit part 115 is L. The bit width of the lower bit portion 116 is (N−L). Data of the upper bits of the count value acquired by the counter 111a is input to the upper bit unit 115 of the read memory 11a via the bus line 122a. Data of lower bits of the count value acquired by the counter 111a is input to the lower bit portion 116 of the read memory 11a through the bus line 122a. The wiring of the least significant bit of the bus line 122a is connected not only to the least significant bit of the lower bit portion 116 of the read memory 11a but also to the memory area 117.

  The memory selection signal PMEM1 is supplied from the drive control unit 311 to the upper bit unit 115 of the read memory 11a. When the memory selection signal PMEM1 becomes high level, the signal supplied from the counter 111a to the bus line 122a is written to the upper bit section 115 of the read memory 11a. The memory selection signal PMEM2 is supplied from the drive control unit 311 to the lower bit portion 116 of the read memory 11a. When the memory selection signal PMEM2 becomes high level, the signal supplied from the counter 111a to the bus line 122a is written to the lower bit portion 116 of the read memory 11. The memory selection signal PMEM3 is supplied from the drive control unit 311 to the memory area 117 of the read memory 11a. When the memory selection signal PMEM 3 becomes high level, the signal supplied from the carry memory 114 to the bus line 122 a is written to the memory area 117. The read signal PRD is supplied from the drive control unit 311 to the read memory 11 a. When the read signal PRD becomes high level, the count value held in the memory area 118 of the read memory 11a and the carry signal held in the memory area 117 of the read memory 11a are sent to the addition circuit 12. The count value and the carry signal read out from the read out memory 11a are input to the addition circuit 12 and used to calculate the pixel signal.

  The components other than the above among the components provided in the solid-state imaging device 1 according to the present embodiment are the same as the components of the solid-state imaging device 1 according to the first embodiment.

Next, the operation of the solid-state imaging device according to the present embodiment will be described with reference to FIG. FIG. 10 shows the transition of the count value of the counter 111a. Since the bit width of the counter 111a is N, the count upper limit, which is the maximum value that the counter 111a can count, is (2 ^N -1). Also in the present embodiment, as in the first embodiment, the shortest time required for the count value of the counter 111a to reach the count upper limit value is ΔTsat.

However, in the present embodiment, as described later, reading of the count value of the lower bit portion 113 of the counter 111a is not performed during the count period, and reset of the lower bit portion 113 of the counter 111a is also performed during the count period. Absent. The shortest time ΔTsat1 required for the count value of the counter 111 a to reach the count upper limit value (2 ^N −1) from (2 ^(N−L) −1) is expressed by the following equation (2).
ΔTsat1 = ΔTp × (2 ^N −2 ^(N−L) ) (2)

Note that 2 ^(N−L) −1 is the count value of the counter 111 a when the count value of the upper bit unit 112 is 0 and the count value of the lower bit unit 113 is the count upper limit value. Also, (2 ^N −1) is the count value of the counter 111a when the upper bit part 112 is the count upper limit value and the count value of the lower bit part 113 is the count upper limit value. If reading and resetting of the upper bit portion 112 of the counter 111a are performed in a cycle of the shortest time ΔTsat1 or less, the pulse signal Pout can be counted while preventing the counter 111a from being saturated.

  Further, in the present embodiment, when reading and resetting the upper bit portion 112 of the counter 111 a, a carry signal indicating a carry from the most significant bit of the lower bit portion 113 is stored in the carry memory 114. Hold by The carry signal held in the carry memory 114 is read out after the count operation of the upper bit unit 112 is resumed, and is used when calculating a pixel signal based on the count value.

  FIG. 10 is a timing chart showing the operation of the solid-state imaging device according to the present embodiment. FIG. 10A shows an operation in which the total number of photons counted during the count period ΔTacc is acquired for each pixel, and an image signal of one frame is generated.

  At timing T1000, the drive control unit 311 supplies the pulse-like reset signals PRES1, PRES2, and PRES3 to the counters 111a respectively provided to all the pixel cells 10a. As a result, the counters 111a of all the pixel cells 10a are reset, and a photographing operation for one frame is started. The frame memory 13 is reset at a timing prior to the timing at which the reading of the count value from the counter 111a is started. Here, the case where the frame memory 13 is reset at timing T1000 will be described as an example.

  The operation at timing T1001 is the same as the operation at timing T101 of the solid-state imaging device 1 according to the first embodiment described above with reference to FIG. That is, at timing T1001, the drive control unit 311 supplies the count enable signal PEN of high level to the counters 111 respectively provided to all the pixel cells 10. Thereby, the counting by the counter 111 of the pulse signal Pout output from the light sensor unit 100 is started in all the pixel cells 10a.

  At timing T1002, the first reading of the count value is started. Here, the count value is read from the upper bit section 112 of the counter 111a, and the carry signal is read from the carry memory 114.

  Here, the operation from timing T1002 to T1010 will be described with reference to FIG.

  At timing T1002, the drive control unit 311 sets the upper bit enable signal PEN1 supplied to the pixel cells 10a located in the first row of the pixel array 300 to the low level. As a result, the counting operation of the upper bit portion 112 of the pixel cell 10a located in the first row of the pixel array 300 is stopped. An inverted signal / PEN1 of the upper bit enable signal PEN1 is input to the carry memory 114 of the pixel cell 10a located in the first row of the pixel array 300. Thus, the carry memory 114 can detect a carry from the most significant bit of the lower bit portion 113. In addition, the drive control unit 311 sets the pixel selection signal PSEL1 supplied to the selection switch 121a provided in the pixel cell 10a located in the first row of the pixel array 300 to a high level. As a result, the pixel cell 10a located in the first row of the pixel array 300 is selected, and the count value of the upper bit portion 112 of the counter 111a is output via the bus line 122a.

  At timing T1003, the drive control unit 311 supplies the pulsed memory selection signal PMEM1 to the read memory 11a. As a result, the count value output from the upper bit unit 112 of the counter 111a of the pixel cell 10a is stored in the upper bit unit 115 of the readout memory 11a.

  At timing T1004, the drive control unit 311 supplies the pulse-like reset signal PRES1 to the upper bit portion 112 of the counter 111a of the pixel cell 10a located in the first row of the pixel array 300. As a result, the upper bit portion 112 of the counter 111a of the pixel cell 10a located in the first row of the pixel array 300 is reset. That is, the upper bit portion 112 of the counter 111a of the pixel cell 10a for which the output of the count value is completed is reset.

  At timing T1005, the drive control unit 311 sets the upper bit enable signal PEN1 supplied to the counters 111a of the pixel cells 10a located in the first row of the pixel array 300 to a high level. Thereby, the count operation of the upper bit portion 112 of the counter 111a of the pixel cell 10a located in the first row of the pixel array 300 is resumed. That is, the counting operation of the upper bit unit 112 of the reset counter 111a is resumed. In addition, the inverted signal / PEN1 of the upper bit enable signal PEN1 is input to the carry memory 114 of the pixel cell 10a located in the first row of the pixel array 300. Therefore, the carry memory 114 of the pixel cell 10a located in the first row of the pixel array 300 stops detecting the carry from the most significant bit of the lower bit portion 113. Further, the drive control unit 311 sets the pixel selection signal PSEL2 supplied to the selection switch 123 of the pixel cell 10a located in the first row of the pixel array 300 to the high level. As a result, the carry signal acquired by the carry memory 114 of the pixel cell 10a located in the first row of the pixel array 300 is output via the bus line 122a.

  At timing T1006, the drive control unit 311 supplies the pulsed memory selection signal PMEM3 to the read memory 11a. As a result, the carry signal output from the carry memory 114 of the pixel cell 10 a is stored in the memory area 117 of the read memory 11 a.

  At timing T1007, the drive control unit 311 sets the pixel selection signal PSEL1 supplied to the selection switch 121a of the pixel cell 10a located in the first row of the pixel array 300 to the low level. As a result, the upper bit portion 112 and the carry memory 114 provided in the counter 111a of the pixel cell 10a located in the first row of the pixel array 300 are not connected to the bus line 122a. In addition, the drive control unit 311 supplies a pulse-like reset signal PRES3 to the pixel cells 10a located in the first row of the pixel array 300. As a result, the carry memory 114 of the pixel cell 10a located in the first row of the pixel array 300 is reset. That is, the carry memory 114 which has completed the output of the carry signal is reset. Further, the drive control unit 311 sets the pixel selection signal PSEL2 supplied to the selection switch 123 of the pixel cell 10a located in the first row of the pixel array 300 to the low level. Thus, the output terminal of the least significant bit of the upper bit portion 112 of the counter 111a of the pixel cell 10a located in the first row of the pixel array 300 is connected to the selection switch 121a via the selection switch 123. Become.

  From timing T1007 to T1008, the drive control unit 311 sequentially supplies the readout signal PRD to the plurality of readout memories 11a corresponding to each of the plurality of columns of the pixel array 300. Thereby, the count value and the carry signal respectively held in the plurality of read memories 11 a are sequentially output to the adder circuit 12. The adder circuit 12 adds 1 to the count value from the upper bit unit 115 when the carry signal from the memory area 117 is, for example, high level. On the other hand, the adding circuit 12 adds, for example, 0 to the count value from the upper bit unit 115 when the carry signal from the memory area 117 is, for example, low level. Thus, addition processing is sequentially performed by the addition circuit 12. Each count value obtained by the addition processing by the addition circuit 12 is sequentially stored in the frame memory 13 as an N-bit pixel signal in which all the lower (NL) bit data is 0.

  Thereafter, the same operation as the operation from timing T1002 to T1008 is sequentially performed from the second row to the J-th row of the pixel array 300. At timing T1010, the read process for the Jth row is completed.

  Timing T1001 is timing when the count operation is started in all the pixel cells 10a included in the pixel array 300. Timing T1009 is timing when the counting operation of the upper bit portion 112 of the counter 111a of the pixel cell 10a located in the J-th row is stopped. A period ΔTread1 from the timing T1001 to the timing T1009 is set to the shortest time ΔTsat1 or less. By setting ΔTread in this manner, readout of the count value can be completed before the counters 111a of all the pixel cells 10a included in the pixel array 300 reach the count upper limit value.

  As described above, at timing T1002, the first reading of the count value is started. At timing T1011 after the period ΔTread1 has elapsed from timing T1002, the second reading of the count value is started. Also in the second reading of the count value, the count value is read from the high-order bit portion 112 of the counter 111a of the pixel cell 10a as in the first reading of the count value. The rising signal is read out. The addition circuit 12 performs addition processing similar to the addition processing performed by the addition circuit 12 at timings T1007 to T1008, and sequentially adds the count value obtained by the addition processing to the pixel signal stored in the frame memory 13. The pixel signal obtained by the addition processing by the addition circuit 12 is stored in the frame memory 13. At timing T1012, the counter operation of the upper bit portion 112 of the counter 111a of the pixel cell 10a located in the J-th row of the pixel array 300 is stopped. As described above, timing T1009 is timing at which the counter 111a located in the J-th row is stopped in the second reading of the count value. A timing T1012 is a timing at which the counter 111a located in the J-th row is stopped in the second reading of the count value. The period ΔTread1 from the timing T1009 to the timing T1012 is also set equal to or less than the above-described shortest time ΔTsat1. Thus, the second reading of the count value is performed.

  As described above, at timing T1011, the second reading of the count value is started. At timing T1013 after the period ΔTread1 has elapsed from timing T1011, the third reading of the count value is started. Also after timing T1013, the same operation as timing T1011 to T1013 is repeated until the count enable signal PEN transitions to the low level.

  At timing T1014 when the count period ΔTacc has elapsed from timing T1001 at which counting is started, the drive control unit 311 causes the count enable signal PEN to transition to the low level. As a result, counting of the pulse signal Pout output from the light sensor unit 100 is stopped at the counters 111 a of all the pixel cells 10 a. The counters 111 a provided in each of the plurality of pixel cells 10 a provided in the pixel array 300 respectively hold count values. Thereafter, the count value of the upper bit portion 112 and the count value of the lower bit portion 113 are read out from the counters 111a of the respective pixel cells 10a. That is, the count value for N bits is read out from the counter 111a of each pixel cell 10a. The adder circuit 12 adds the count value read out in this manner to the pixel signal read out from the frame memory 13. The pixel signal obtained by the addition processing by the addition circuit 12 is stored in the frame memory 13.

  Here, the operation from timing T1014 to T1020 will be described with reference to FIG.

  At timing T1014, the drive control unit 311 causes the pixel selection signal PSEL1 supplied to each of the plurality of pixel cells 10a located in the first row of the pixel array 300 to transition to the high level. Thus, the plurality of pixel cells 10a located in the first row of the pixel array 300 are selected.

  At timing T1015, the drive control unit 311 supplies a pulsed memory selection signal PMEM1 to the upper bit unit 115 of the read memory 11a. As a result, the count value of the upper bit portion 112 of the counters 111a of the plurality of pixel cells 10a located in the first row of the pixel array 300 is held in the upper bit portion 115 of the readout memory 11a.

  At timing T1016, the drive control unit 311 supplies the pulse-like data shift signal PDS to the lower bit portion 113 of the counter 111a. As a result, the count value of the lower bit portion 113 of the counter 111a is written to the upper bit portion 112 of the counter 111a. The upper bit unit 112 of the counter 111a holds the written count value.

  At timing T1017, the drive control unit 311 supplies a pulse-like memory selection signal PMEM2 to the lower bit portion 116 of the read memory 11a. As a result, the count value acquired by the lower bit portion 113 of the counters 111a of the plurality of pixel cells 10a located in the first row of the pixel array 300 is held in the lower bit portion 116 of the readout memory 11a. Thus, the count value acquired by the lower bit portion 113 of the counter 111a of the pixel cell 10a located in the first row of the pixel array 300 is read out via the upper bit portion 112 of the counter 111a. It is stored in the lower bit part 116.

  During timing T1018 to T1019, the drive control unit 311 sequentially supplies the readout signal PRD to the plurality of readout memories 11a corresponding to each of the plurality of columns of the pixel array 300. Thus, the count values respectively stored in the plurality of read memories 11 a are sequentially output to the adder circuit 12. The adder circuit 12 adds the count value read out in this manner to the pixel signal read out from the frame memory 13. The pixel signal obtained by the addition processing by the addition circuit 12 is stored in the frame memory 13. At this time, addition processing of the carry signal is not performed by the addition circuit 12. Thereafter, until timing T1020, operations similar to the operations from timing T1014 to T1019 are sequentially performed from the second row to the J-th row of the pixel array 300. At timing T1020, the read process for the Jth row is completed.

  Thereafter, as shown in FIG. 10A, at timings T1020 to T1021, the pixel signal of each pixel stored in the frame memory 13 is output from the solid-state imaging device 1a. Thus, the photographing operation of one frame is completed.

  FIG. 11 is a diagram showing the transition between the count value of the counter 111 a and the pixel signal stored in the frame memory 13. FIG. 11 focuses on one pixel cell 10 a of the plurality of pixel cells 10 a provided in the pixel array 300. FIG. 11 shows the count value of the upper bit unit 112 of the counter 111a, the count value of the lower bit unit 113 of the counter 111a, the carry signal, and the pixel signal stored in the frame memory 13.

  At the timing when the count period ΔTacc is started, the counter 111a and the frame memory 13 are reset. The counter 111a starts counting of pulse signals. After that, each time the pulse signal Pout is output, the count value of the counter 111a is incremented in the pixel cell 10a.

  At a timing when a period ΔT1 shorter than the above-described shortest time ΔTsat1 elapses, the count value acquired by the upper bit unit 112 of the counter 111a is read out, and the count value of the upper bit unit 112 of the counter 111a is reset. The counter 111a continues counting the pulse signal Pout even after being reset. Thereafter, the carry signal obtained while reading and resetting the upper bit portion 112 of the counter 111a is read from the carry memory 114. The 1-bit carry signal read from the carry memory 114 of the counter 111a is added to the count value read from the upper bit unit 112 of the counter 111a. Using the count value thus obtained, an N-bit count value is generated with the lower (NL) bit set to 0. The count value generated in this manner is integrated to the reset value 0 held in the frame memory 13 and stored in the frame memory 13 as a pixel signal.

  After that, at the timing when the period ΔTread1 shorter than the above-described shortest time ΔTsat1, the count value is read from the upper bit unit 112 of the counter 111a, and the count value of the upper bit unit 112 of the counter 111a is reset. A carry signal is read out from the carry memory 114 of the counter 111a, as in the first read. The 1-bit carry signal read from the carry memory 114 of the counter 111a is added to the count value read from the upper bit unit 112 of the counter 111a. Using the count value thus obtained, an N-bit count value is generated with the lower (NL) bit set to 0. The count value generated in this manner is integrated with the pixel signal held in the frame memory 13, and the pixel signal obtained by the integration is stored in the frame memory 13. After this, the same operation as described above is repeated in the cycle of ΔTread1.

  At the timing when the count period ΔTacc has elapsed, the counter 111a stops counting the pulse signal. Then, the count value is read out from the upper bit section 112 of the counter 111a. The count value read from the upper bit portion 112 of the counter 111 a is integrated with the pixel signal held in the frame memory 13, and the pixel signal obtained by the integration is stored in the frame memory 13. At this time, the reading process of the carry signal is not performed, and the addition process of the carry signal is not performed. Thereafter, the count value of the lower bit portion 113 of the counter 111a is written to the upper bit portion 112 of the counter 111a. Thereafter, the count value is read out from the upper bit section 112 of the counter 111a. The count value read out from the upper bit portion 112 of the counter 111a is used as data of lower (NL) bits of the pixel signal held in the frame memory 13. Thus, the count value acquired by the lower bit portion 113 of the counter 111a is used as data of lower (NL) bits of the pixel signal stored in the frame memory 13.

  Here, although the case where the bit width of the upper bit portion 112 of the counter 111a and the bit width of the lower bit portion 113 of the counter 111a are equal to each other has been described as an example, the present invention is not limited to this. If the bit width of the lower bit portion 113 of the counter 111a is larger than the bit width of the upper bit portion 112 of the counter 111a, the count value obtained by the lower bit portion 113 is divided into plural times via the upper bit portion 112. Read out.

  Thus, the pixel signals stored in the frame memory 13 correspond to the number of pulse signals out counted by each pixel cell 10 within the count period ΔTacc.

  As described above, also according to the present embodiment, the count value counted within the time shorter than the shortest time ΔTsat1 required for the count value of the counter 111a to reach the count upper limit value is read, and the counter 111a is reset. Is done. The count values read out from the counter 111 are sequentially accumulated and held in the frame memory 13 which can hold an image signal having a bit width larger than that of the counter 111. Therefore, according to the present embodiment, it is possible to prevent the count value of the counter 111 from being saturated during the exposure period, and it is possible to obtain an image with good gradation. Moreover, while the count value acquired by the upper bit unit 112 of the counter 111a is read in the cycle of ΔTread, the count value acquired by the lower bit unit 113 of the counter 111a is read only once in the count period ΔTacc. It is. Therefore, according to the present embodiment, the number of wirings provided in the bus line 122 can be reduced, and the wiring layout can be simplified.

Third Embodiment
A solid-state imaging device, an imaging device, and an imaging method according to a third embodiment will be described with reference to FIGS. 12 and 13.
The solid-state imaging device according to the present embodiment is output from the upper bit unit 112 of the counters 111b of the plurality of pixel cells 10b via a bus line provided with the same number of interconnections as the bit width of the counters 111b of the pixel cells 10b. The count value is read out simultaneously.

FIG. 12 is a view showing a solid-state imaging device 1b according to the present embodiment.
In the pixel array 300, a plurality of pixel cells 10b are arranged in a matrix. The counting unit 110 b provided in the pixel cell 10 b is provided with a counter 111 b having a bit width of N. Similar to the counter 111a described above with reference to FIG. 9, the counter 111b includes the upper bit unit 112, the lower bit unit 113, and the carry memory 114. However, the data shift signal PDS (see FIG. 9) is not supplied to the counter 111b.

  The bus line 122 b is provided with L wirings corresponding to the bit width of the counter 111 b. The signal of the least significant bit of the upper bit unit 112 can be output to the wiring of the least significant bit of the bus line 122 b through the selection switch 123 and the selection switch 121 b. The signal of bits other than the least significant bit of the upper bit portion 112 can be output to the wiring of bits other than the least significant bit of the bus line 122 b through the selection switch 121 b. The signal from the carry memory 114 is supplied to the wiring to which the signal from the least significant bit of the upper bit portion 112 is supplied among the L wirings provided on the bus line 122 b via the selection switch 123 and the selection switch 121 b. Can be supplied. The bus line 126 is provided with (N−L) wires. The signal of the least significant bit of the upper bit portion 112 can be output to the wiring of the least significant bit of the bus line 126 via the selection switch 123 and the selection switch 124. The signal of bits other than the least significant bit of the upper bit portion 112 can be output to the wiring of bits other than the least significant bit of the bus line 126 through the selection switch 124. A signal from the carry memory 114 is transmitted to the wiring to which the signal from the least significant bit of the upper bit portion 112 is supplied among the L wirings provided on the bus line 126 via the selection switch 123 and the selection switch 124. Can be supplied. The signal of each bit of the lower bit portion 113 can be output to the wiring of the bus line 126 through the selection switch 125, respectively. The pixel selection signal PSEL1 is supplied from the drive control unit 311 to the selection switch 121b. The pixel selection signal PSEL3 is supplied to the selection switch 124 from the drive control unit 311. The pixel selection signal PSEL4 is supplied to the selection switch 125 from the drive control unit 311.

  The number of bits of the read memory 11 b is N + 2. The read memory 11b includes an N / 2 bit first memory area 1201, an N / 2 bit second memory area 1202, a 1 bit third memory area 1203, and a 1 bit fourth memory. An area 1204 is provided. The count value acquired by the upper bit unit 112 of the counter 111b of the pixel cell 10b located in the Pth row of the pixel array 300 is input to the first memory area 1201 through the bus line 122b. The count value obtained by the upper bit unit 112 of the counter 111b of the pixel cell 10b located in the (P + 1) th row of the pixel array 300 is input to the second memory area 1202 via the bus line 126. The carry information output from the carry memory 114 of the pixel cell 10b located in the Pth row of the pixel array 300 is input to the third memory area 1203 via the bus line 122b. The carry information output from the carry memory 114 of the pixel cell 10 b located in the (P + 1) th row of the pixel array 300 is input to the fourth memory area 1204 via the bus line 126.

  The memory selection signal PMEM from the drive control unit 311 is supplied to the first memory area 1201 and the second memory area 1202 of the read memory 11 b. When the memory selection signal PMEM becomes high level, the signal supplied to the bus line 122b from the counter 111b of the pixel cell 10b located in the Pth row is written to the first memory area 1201 of the read memory 11b. In addition, when the memory selection signal PMEM becomes high level, the signal supplied to the bus line 126 from the counter 111b of the pixel cell 10b located in the (P + 1) th row is written to the second memory area 1202 of the read memory 11b. Be

  The memory selection signal PMEM3 is supplied from the drive control unit 311 to the third memory area 1203 and the fourth memory area 1204 of the read memory 11b. When the memory selection signal PMEM3 becomes high level, the carry signal supplied from the carry memory 114 of the pixel cell 10b located in the Pth row to the bus line 122b is the third memory area 1203 of the read memory 11b. Is written to Further, when the memory selection signal PMEM becomes high level, the carry signal supplied from the carry memory 114 of the pixel cell 10b located in the (P + 1) th row to the bus line 126 is the fourth memory of the read memory 11b. It is written to area 1204. The read signal PRD is supplied from the drive control unit 311 to the read memory 11 b. When the read signal PRD becomes high level, the count value and the carry signal held in the read memory 11 b are transmitted to the bit shift circuit 14. The carry signal read from the read memory 11b is input to the addition circuit 12 through the bit shift circuit 14 together with the count value, and is used for calculation of the signal value.

  The bit shift circuit PBS is supplied with the bit shift signal PBS from the drive control unit 311. When the bit shift signal PBS is at high level, the bit shift circuit 14 operates as follows. That is, the bit shift circuit 14 performs bit shift of (NL) bits with respect to the count value output from the first memory area 1201 of the read memory 11b, and sets the lower (NL) bits to 0. By the addition, an N-bit count value is generated. In addition, when the bit shift signal PBS is at high level, the bit shift circuit 14 operates as follows. That is, the bit shift circuit 14 performs bit shift of (NL) bits with respect to the count value output from the second memory area 1202 of the read memory 11b, and sets the lower (NL) bits to 0. By the addition, an N-bit count value is generated. Also, the bit shift circuit 14 does not perform bit shift on the count value output from the third memory area 1203 of the read memory 11 b. Also, the bit shift circuit 14 does not perform bit shift on the count value output from the fourth memory area 1204 of the read memory 11 b. The bit shift circuit 14 outputs the count value subjected to the bit shift and the carry signal not subjected to the bit shift to the addition circuit 12. Here, although the case where the bit shift is not performed on the carry signal has been described as an example, the bit shift may be performed on the carry signal.

  When the bit shift signal PBS is at a low level, the bit shift circuit 14 outputs the count value output from the first memory area 1201 of the read memory 11 b below the count value output from the second memory area 1202 of the read memory 11 b. Add count value. The bit shift circuit 14 outputs the thus generated N-bit count value to the addition circuit 12.

  Since it is preferable that the read rate is not limited by such processing, it is preferable to configure the bit shift circuit 14 and the addition circuit 12 as follows. That is, while the count value and the carry signal are being read from one read memory 11b, the bit is processed so that the predetermined arithmetic processing on the count value and the carry signal read from the other read memory 11b is completed. The shift circuit 14 and the adder circuit 12 are configured.

  The components other than the above among the components provided in the solid-state imaging device 1 according to the present embodiment are the same as the components of the solid-state imaging device 1 according to the first embodiment.

  Next, the operation of the solid-state imaging device according to the present embodiment will be described with reference to FIG. FIG. 13 is a timing chart showing the operation of the solid-state imaging device according to the present embodiment. Also in the present embodiment, the period ΔTread1 corresponding to the readout cycle of the count value is determined in the same manner as in the second embodiment. FIG. 13A shows an operation in which the total number of photons counted during the count period ΔTacc is acquired for each pixel, and an image signal of one frame is generated.

  The operation at timing T1300 is the same as the operation at timing T1000 performed by the solid-state imaging device according to the second embodiment.

  At timing T1301, the drive control unit 311 sets the bit shift signal PBS to the high level. The other operations at timing T1301 are the same as the operations at timing T1001 performed in the solid-state imaging device according to the second embodiment.

  At timings T1302 to T1310, the first reading of the count value is performed. Here, the count value is read from the upper bit section 112 of the counter 111b, and the carry signal is read from the carry memory 114. At this time, the signal from the pixel cell 10b positioned in a certain row and the signal from the pixel cell 10b positioned in a row different from the row in which the pixel cell 10b is positioned are input to the same readout memory 11b.

  Here, the operation from timing T1302 to T1310 will be described using FIG. 13 (B).

  At timing T1302, the drive control unit 311 sets the upper bit enable signal PEN1 supplied to the pixel cells 10b located in the first row and the second row of the pixel array 300 to the low level. As a result, the counting operation of the upper bit portion 112 of the pixel cell 10b located in the first row and the second row of the pixel array 300 is stopped. An inverted signal / PEN1 of the upper bit enable signal PEN1 is input to the carry memory 114 of the pixel cell 10b located in the first row and the second row of the pixel array 300, respectively. Thus, the carry memory 114 can detect a carry from the most significant bit of the lower bit portion 113. The drive control unit 311 sets the pixel selection signal PSEL1 supplied to the selection switch 121b provided in the pixel cell 10b positioned in the first row of the pixel array 300 to a high level. As a result, the pixel cell 10b located in the first row of the pixel array 300 is selected, and the count value of the upper bit portion 112 of the counter 111b is output through the bus line 122b. Further, the drive control unit 311 sets the pixel selection signal PSEL3 supplied to the selection switch 125 provided in the pixel cell 10b located in the second row of the pixel array 300 to a high level. As a result, the pixel cell 10 b located in the second row of the pixel array 300 is selected, and the count value of the upper bit portion 112 of the counter 111 b is output via the bus line 126.

  At timing T1303, the drive control unit 311 supplies the pulsed memory selection signal PMEM to the read memory 11b. As a result, the count value output from the upper bit portion 112 of the counter 111 b of the pixel cell 10 b of the first row is stored in the first memory area 1201 of the read memory 11 b. Further, the count value output from the upper bit portion 112 of the counter 111b of the pixel cell 10b of the second row is stored in the second memory area 1202 of the readout memory 11b.

  At timing T1304, the drive control unit 311 pulses the upper bit portion 112 of the pixel cell 10b located in the first row of the pixel array 300 and the upper bit portion 112 of the pixel cell 10b located in the second row. Supply a reset signal PRES1 of As a result, the upper bit portion 112 of the counter 111 b of the pixel cell 10 b located in the first row of the pixel array 300 is reset. That is, the upper bit portion 112 of the counter 111b of the pixel cell 10a for which the output of the count value is completed is reset.

  At timing T1305, the drive control unit 311 sets the upper bit enable signal PEN1 supplied to the pixel cells 10b positioned in the first row and the second row of the pixel array 300 to the high level. Thereby, the count operation of the upper bit portion 112 of the counter 111b of the pixel cell 10b located in the first row and the second row of the pixel array 300 is stopped. That is, the counting operation of the upper bit unit 112 of the reset counter 111b is stopped. Further, the inverted signal / PEN1 of the upper bit enable signal PEN1 is input to the carry memory 114 of the pixel cell 10b located in the first row and the second row of the pixel array 300, respectively. Therefore, the carry memory 114 of the pixel cell 10b located in the first row and the second row of the pixel array 300 stops detecting the carry from the most significant bit of the lower bit portion 113. . Further, the drive control unit 311 sets the pixel selection signal PSEL2 supplied to the selection switch 123 of the pixel cell 10b located in the first row and the second row of the pixel array 300 to a high level. As a result, the carry signal acquired by the carry memory 114 of the pixel cell 10b located in the first row of the pixel array 300 passes through one of the plurality of wirings provided in the bus line 122b. It is output. Further, a carry signal acquired by carry memory 114 of pixel cell 10 b located in the second row of pixel array 300 is transmitted via one of the plurality of wirings provided in bus line 126. It is output.

  At timing T1306, the drive control unit 311 supplies the pulsed memory selection signal PMEM3 to the read memory 11b. Thus, the carry signal output from the carry memory 114 of the pixel cell 10 b located in the first row of the pixel array 300 is stored in the third memory area 1203 of the read memory 11 b. In addition, the carry signal output from the carry memory 114 of the pixel cell 10 b located in the second row of the pixel array 300 is stored in the fourth memory area 1204 of the read memory 11 b.

  At timing T1307, the drive control unit 311 sets the pixel selection signal PSEL1 supplied to the selection switch 121b of the pixel cell 10b located in the first row of the pixel array 300 to the low level. As a result, the upper bit portion 112 and the carry memory 114 provided in the counter 111 b of the pixel cell 10 b located in the first row of the pixel array 300 are not connected to the bus line 122 b. Further, the drive control unit 311 sets the pixel selection signal PSEL3 supplied to the selection switch 124 of the pixel cell 10b located in the second row of the pixel array 300 to the low level. As a result, the upper bit portion 112 and the carry memory 114 provided in the counter 111 b of the pixel cell 10 b located in the second row of the pixel array 300 are not connected to the bus line 126. In addition, the drive control unit 311 supplies a pulse-like reset signal PRES3 to the pixel cells 10b positioned in the first row and the second row of the pixel array 300, respectively. As a result, the carry memory 114 of the pixel cell 10b located in the first row and the second row of the pixel array 300 is reset. That is, the carry memory 114 which has completed the output of the carry signal is reset. Further, the drive control unit 311 sets the pixel selection signal PSEL2 supplied to the selection switch 123 of the pixel cell 10b positioned in the first row and the second row of the pixel array 300 to the low level. As a result, the output terminal of the least significant bit of the upper bit portion 112 of the counter 111b of the pixel cell 10a located in the first row and the second row of the pixel array 300 is selected via the selection switch 123. It will be in the state connected to switch 121b.

  From timing T1307 to T1308, the drive control unit 311 sequentially supplies the readout signal PRD to the plurality of readout memories 11b corresponding to each of the plurality of columns of the pixel array 300. As a result, the count value and the carry signal respectively held in the plurality of read memories 11 b are sequentially output to the bit shift circuit 14. Since the bit shift signal PBS is at high level, the count value output from the first memory area 1201 of the read memory 11 is carried by the bit shift circuit 14 by (NL) bits. The bit shift circuit 14 outputs an N-bit pixel signal generated by carrying out to the addition circuit 12. The bit shift circuit 14 outputs the carry signal to the addition circuit 12 without carrying out the carry signal output from the third memory area 1203 of the read memory 11 b. The bit shift circuit 14 outputs the carry signal to the addition circuit 12 without carrying out the carry signal output from the fourth memory area 1204 of the read memory 11 b. The adder circuit 12 adds, for example, 1 to the count value from the first memory area 1201 when the carry signal from the third memory area 1203 is, for example, high level. On the other hand, the addition circuit 12 adds, for example, 0 to the count value from the first memory area 1201 when the carry signal from the third memory area 1203 is at low level. The addition circuit 12 adds, for example, 1 to the count value from the second memory area 1202 when, for example, the carry signal from the fourth memory area 1204 is at high level. On the other hand, the addition circuit 12 adds, for example, 0 to the count value from the second memory area 1202 when the carry signal from the fourth memory area 1204 is at low level. Thus, addition processing is sequentially performed by the addition circuit 12. Each count value obtained by the addition processing by the addition circuit 12 is sequentially stored in the frame memory 13 as an N-bit pixel signal in which all the lower (NL) bit data is 0.

  Thereafter, the same operation as the operation from the timing T1302 to the timing T1308 is sequentially performed every two rows from the third row to the J-th row of the pixel array 300. At timing T1310, the read process for the Jth row is completed.

  According to the present embodiment, since reading is performed every two rows, the time required for reading can be almost halved as a whole as compared with the second embodiment.

  Timing T1301 is timing when the count operation is started in all the pixel cells 10b provided in the pixel array 300. Timing T1309 is timing when the counting operation of the upper bit portion 112 of the counter 111a of the pixel cell 10a located in the J-1st row and the Jth row is stopped. A period ΔTread1 from timing T1301 to timing T1309 is set to the shortest time ΔTsat1 or less. By setting ΔTread in this manner, the reading of the count value can be completed before the counters 111 b of all the pixel cells 10 b provided in the pixel array 300 reach the count upper limit value.

  As described above, at timing T1302, the first reading of the count value is started. At timing T1311 when the period ΔTread1 has elapsed from timing T1302, the second reading of the count value is started. The process performed in the second reading of the count value is the same as the process performed in the first reading of the count value.

  As described above, timing T1309 is timing at which the counters 111b positioned on the (J-1) th row and the Jth row are stopped in the second reading of the count value. The timing T1312 is a timing at which the counters 111b positioned on the J-1st row and the Jth row are stopped in the second reading of the count value. The period ΔTread1 from the timing T1309 to the timing T1312 is also set equal to or less than the above-described shortest time ΔTsat1. Thus, the second reading of the count value is performed.

  As described above, at timing T1311, the second reading of the count value is started. At timing T1313 when the period ΔTread1 has elapsed from timing T1311, the third reading of the count value is started. After timing T1313, the same operation as that from timing T1311 to timing T1313 is repeated until the count enable signal PEN transitions to the low level.

  At timing T1314 when the count period ΔTacc has elapsed from timing T1301 at which counting is started, the drive control unit 311 causes the count enable signal PEN to transition to the low level. As a result, the counting of the pulse signal Pout output from the light sensor unit 100 is stopped at the counters 111 b of all the pixel cells 10 b. The counters 111 b provided in each of the plurality of pixel cells 10 b provided in the pixel array 300 respectively hold count values. Further, the drive control unit 311 sets the bit shift signal PBS supplied to the bit shift circuit 14 to the low level. Reading out of an N-bit count value including data of lower (NL) bits is started from the counter 111b of each pixel cell 10b.

  Here, the operation from timing T 1314 to timing T 1320 will be described with reference to FIG.

  At timing T1314, the drive control unit 311 sets the pixel selection signals PSEL1 and PSEL4 supplied to each of the plurality of pixel cells 10b located in the first row of the pixel array 300 to the high level. As a result, the upper bit portions 112 of the counters 111b of the plurality of pixel cells 10b located in the first row of the pixel array 300 are connected to the bus line 122b. Further, the lower bit portions 113 of the counters 111 b of the plurality of pixel cells 10 b located in the first row of the pixel array 300 are connected to the bus line 126 respectively.

  At timing T1315, the drive control unit 311 supplies a pulse-like memory selection signal PMEM to the read memory 11a. As a result, the count value of the upper bit portion 112 of the pixel cell 10 b located in the first row of the pixel array 300 is stored in the first memory area 1201 of the readout memory 11 b. Further, the count value of the lower bit portion 113 of the pixel cell 10b located in the first row of the pixel array 300 is stored in the second memory area 1202 of the readout memory 11b.

  At timing T1316, the drive control unit 311 sets the pixel selection signals PSEL1 and PSEL4 supplied to each of the plurality of pixel cells 10b located in the first row of the pixel array 300 to the low level. As a result, the upper bit portion 112 of each of the plurality of pixel cells 10b located in the first row of the pixel array 300 is not connected to the bus line 122b. Also, the lower bit portion 113 of each of the plurality of pixel cells 10 b located in the first row of the pixel array 300 is not connected to the bus line 126.

  During timing T1316 to T1317, the drive control unit 311 sequentially supplies the readout signal PRD to the plurality of readout memories 11b corresponding to each of the plurality of columns of the pixel array 300. As a result, the count values respectively stored in the plurality of read memories 11 b are sequentially output to the bit shift circuit 14. The bit shift signal PBS is at low level. Therefore, the bit shift circuit 14 lowers the L-bit data read from the first memory area 1201 of the read memory 11b, and reads (NL) bits of the (N−L) bits read from the second memory area 1202 of the read memory 11b. Add data. Thus, an N-bit count value is generated. The N-bit count values respectively corresponding to the respective pixel cells 10 b are sequentially output to the adder circuit 12. The adder circuit 12 adds the count value read out in this manner to the pixel signal read out from the frame memory 13. The pixel signal obtained by the addition processing by the addition circuit 12 is stored in the frame memory 13. At this time, addition processing of the carry signal is not performed by the addition circuit 12. Thereafter, until the timing T1320, operations similar to the operations from the timing T1314 to the timing T1317 are sequentially performed from the second row to the J-th row of the pixel array 300. At timing T1320, the read process for the Jth row is completed. From timing T 1314 to timing T 1320, reading is performed row by row, and therefore, it takes a long time for reading as compared with the case where reading is performed every two rows. However, since the counting operation of the counter 111b is already stopped, no particular problem occurs even if the time required for reading exceeds the above-mentioned ΔTsat1.

  Thereafter, as shown in FIG. 13A, at timings T1320 to T1321, the pixel signal of each pixel stored in the frame memory 13 is output from the solid-state imaging device 1b. Thus, the photographing operation of one frame is completed.

  As described above, also according to the present embodiment, the count value counted within a time shorter than the shortest time ΔTsat1 required for the count value of the counter 111b to reach the count upper limit value is read, and the counter 111a is reset. Is done. The count values read from the counter 111b are sequentially accumulated and held in the frame memory 13 which can hold an image signal having a bit width larger than that of the counter 111b. Therefore, according to the present embodiment, it is possible to prevent the count value of the counter 111b from being saturated during the exposure period, and it is possible to obtain an image with good gradation. Moreover, while the count value acquired by the upper bit unit 112 of the counter 111b is read in the cycle of ΔTread, the count value acquired by the lower bit unit 113 of the counter 111b is read only once in the count period ΔTacc. It is. Therefore, according to the present embodiment, it is possible to collectively read the count values output from the upper bit portion 112 of the counter 111b of the pixel cell 10b located in each of the plurality of rows through the bus lines 122b and 126. It is. Therefore, according to the present embodiment, the time required for reading can be shortened, which in turn can contribute to increasing the number of pixels and the like.

  As mentioned above, although the preferable embodiment of this invention was described, this invention is not limited to these embodiment, A various deformation | transformation and change are possible within the range of the summary.

  The present invention supplies a program that implements one or more functions of the above-described embodiments to a system or apparatus via a network or a recording medium, and one or more processors in a computer of the system or apparatus read and execute the program. Can also be realized. It can also be implemented by a circuit (eg, an ASIC) that implements one or more functions.

  In the second embodiment, the count value acquired by the pixel cell 10a is transmitted via the bus line 122a having a plurality of wirings, but the present invention is not limited to this. For example, the count value of a plurality of bits acquired by the pixel cell 10a may be serially transmitted. In this case, it is also possible to use one wiring for reading the count value acquired by the pixel cell 10a.

100: Light receiving means 110, 110a, 110b: Counting means 300: Pixel array PRES, PRES1: Reset signal 11, 11a, 11b: Reading memory 13: Frame memory

Claims (13)

A pixel array in which a plurality of pixels provided in a matrix are provided with a light sensor unit that emits a pulse having a predetermined pulse width at a frequency according to the light reception frequency of photons;
A counter that counts the number of pulses emitted from the light sensor unit;
A control unit capable of performing control such that reading of the count value from the counter is performed in a cycle equal to or less than a product of the count upper limit value of the counter and the predetermined pulse width; . The solid-state imaging device according to claim 1, further comprising a memory that holds an integrated value of the count value read from the counter.   The solid-state imaging device according to claim 1, wherein the counter is reset after reading the count value from the counter. The bit width of the counter is N,
The counter includes an upper bit portion which is L with a bit width smaller than N, and a lower bit portion which is (NL) with a bit width
During a period in which the number of pulses is counted by the counter, the count value obtained by the upper bit portion is read without reading the count value obtained by the lower bit portion, and The first read process to reset is repeated,
The second read process for reading out the N-bit count value obtained by the counter is performed after the period in which the number of pulses is counted by the counter is completed. The solid-state imaging device according to claim 1. When the count value obtained by the upper bit portion of the counter is read from the upper bit portion in the first read process, the most significant bit of the lower bit portion of the counter The solid-state imaging device according to claim 4, further comprising a detection unit that detects a carry of the carrier. The count value obtained by the upper bit portion is transmitted via a bus line provided with a number of wires smaller than N,
The solid-state imaging device according to claim 4 or 5, wherein the count value obtained by the lower bit part is also transmitted via the bus line. The solid-state imaging device according to claim 6, wherein the number of the wirings provided in the bus line is L. The count value obtained by the upper bit portion of the counter provided to the pixels located in the first row of the pixel array is transmitted via a first bus line,
A count value obtained by the upper bit portion of the counter provided in a pixel located in a second row different from the first row of the pixel array is transmitted via a second bus line The solid-state imaging device according to claim 4 or 5, characterized in that The number of wires provided in the first bus line is L,
9. The solid-state imaging device according to claim 8, wherein the number of wirings provided in the second bus line is L. The first readout process is repeated within a period in which the number of pulses is counted by the counter, and the second readout process is performed after the period in which the number of pulses is counted by the counter is ended. A first operation mode,
The first readout process is not performed within a period in which the number of pulses is counted by the counter, and the second readout process is performed after a period in which the number of pulses is counted by the counter is completed. The solid-state imaging device according to claim 4, which can operate in the second operation mode. The solid-state imaging device according to any one of claims 1 to 10, wherein the light sensor unit includes an avalanche photodiode. A pixel array including a plurality of pixels arranged in a matrix, and a number of pulses emitted from the light sensor unit are provided with a plurality of pixels provided with a light sensor unit that emits a pulse with a predetermined pulse width at a frequency according to the light reception frequency of photons A solid-state imaging device comprising a counter, and a control unit capable of performing control such that reading of the count value from the counter is performed at a cycle equal to or less than the product of the count upper limit value of the counter and the predetermined pulse width; ,
And a processing unit configured to perform predetermined processing on a signal output from the solid-state imaging device. Counting by a counter a pulse of a predetermined pulse width emitted from the optical sensor unit at a frequency corresponding to the light reception frequency of photons;
Reading the count value from the counter at a cycle equal to or less than the product of the count upper limit value of the counter and the predetermined pulse width;
And D. integrating the count value read from the counter.

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