JP7121268B2 - Resistive memory and control method for resistive memory - Google Patents

Description

The present invention relates to a resistance change memory and a control method for the resistance change memory.

A resistance change type memory whose resistance value can be increased or decreased can be used as a non-volatile memory because it can hold resistance values as data instead of the amount of accumulated charge, and it does not require power for holding data.

When writing to a memory element included in a resistance change memory, the current flowing through the memory element is converted into a voltage, and whether or not the memory element has reached a predetermined resistance value is determined based on the result of comparison between the voltage and a predetermined voltage. is determined. Such processing is called write verify. A predetermined voltage is applied to the memory element until the memory element reaches a predetermined resistance value.

On the other hand, when the memory element is read, the current flowing through the memory element is converted into a voltage, and based on the result of comparison between the voltage and a predetermined voltage, whether "0" is written to the memory element or "1" is written. It is determined whether it has been written.

At the time of write verify and read as described above, a sense amplifier is used to amplify the potential difference between the data potential obtained by converting the current flowing through the memory element and the reference potential.
By the way, conventionally, in order to improve the read margin in a ferroelectric memory, a sense amplifier for amplifying the potential difference between the reference potential of "0" and the data potential and the potential difference between the reference potential of "1" and the data potential are used. Some had sense amplifiers to amplify. By short-circuiting the output terminals of both sense amplifiers, the sense amplifier that amplifies the potential difference between the data potential and the one having the larger potential difference from the data potential among the two reference potentials first performs strong amplification, while the other sense amplifier amplifies the potential difference. The data are determined by subordinating the . Hereinafter, such a read system using two sense amplifiers will be referred to as a twin sense amplifier system.

JP 2009-99199 A JP-A-2009-9641 JP 2009-252290 A JP-A-11-167796

However, when the twin sense amplifier system is applied to a resistive memory in which write verify is performed, a write verify sense amplifier is provided in addition to the two read sense amplifiers. Since the sense amplifier itself is a relatively large circuit, there is a problem that an increase in the number of sense amplifiers increases the circuit scale of the resistance change memory.

An object of the present invention in one aspect is to suppress an increase in the circuit scale of a resistance change memory.

In one embodiment, a first sense amplifier and a second sense amplifier are provided, and the first sense amplifier is supplied to a first input terminal of the first sense amplifier when a resistance change memory element is read. a reference potential and a data potential based on the resistance value of the memory element among the second reference potential higher than the first reference potential and supplied to the second input terminal of the second sense amplifier; Amplifies the potential difference from the larger potential difference, and supplies a first verify potential supplied to the first input terminal or a second verify potential supplied to the second input terminal when write-verifying the memory element. a sense amplifier unit for amplifying a potential difference between the data potential and the data potential; and, when the memory element is read, the first reference potential is supplied to the first input terminal, and the second input terminal is applied to the second input terminal. supply the reference potential of the memory element, supply the first verify potential to the first input terminal, and supply the second verify potential to the second input terminal at the time of write verify for the memory element. and a switching circuit.

Also, in one embodiment, a method for controlling a resistive memory is provided.

In one aspect, the present invention can suppress an increase in circuit scale of a resistance change memory.

1 is a diagram illustrating an example of a resistance change memory according to a first embodiment; FIG. FIG. 10 is a diagram illustrating an example of a resistance change memory according to a second embodiment; FIG. It is a figure which shows an example of a memory cell array. FIG. 3 is a diagram showing an example of a memory cell; FIG. It is a figure which shows an example of a column control circuit. 1 is a diagram showing an example of a current-voltage conversion circuit; FIG. FIG. 3 is a diagram showing an example of a supply potential switching circuit and a sense amplifier section; It is a figure which shows an example of a precharge circuit. 4 is a timing chart showing an example of changes in the potential of each signal and each part when "0" is read; 4 is a timing chart showing an example of changes in the potential of each signal and each part when "1" is read; 4 is a timing chart showing an example of changes in the potential of each signal and each part at the time of "0" write verify; 4 is a timing chart showing an example of changes in the potential of each signal and each part at the time of "1" write verify; FIG. 5 is a diagram showing a comparative example of a supply potential switching circuit and a sense amplifier section; FIG. 10 is a diagram showing an example of a twin sense amplifier type sense amplifier unit that supports only read processing; FIG. 10 is a diagram showing an example of a supply potential switching circuit and a sense amplifier section in a resistance change memory according to a third embodiment; 4 is a timing chart showing an example of changes in the potential of each signal and each part when "0" is read; 4 is a timing chart showing an example of changes in the potential of each signal and each part when "1" is read; 4 is a timing chart showing an example of changes in the potential of each signal and each part at the time of "0" write verify; FIG. 10 is a diagram showing an example of write intensity control at the time of “0” write verify; 4 is a timing chart showing an example of changes in the potential of each signal and each part at the time of "1" write verify; FIG. 10 is a diagram showing an example of write intensity control at the time of “1” write verify;

BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, embodiments for carrying out the invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram showing an example of a resistance change memory according to a first embodiment.

A resistance change memory 10 according to the first embodiment has a sense amplifier section 11 and a supply potential switching circuit 12 . Note that FIG. 1 shows a portion for reading data of the memory cell 13 connected to one bit line BL included in the memory cell array. A portion for reading data from memory cells connected to other bit lines also has the same configuration as in FIG. In FIG. 1, illustration of a circuit for writing data to the memory cell 13 and a circuit for converting the current flowing through the resistance change type memory element 13a included in the memory cell 13 into a voltage is omitted.

The resistance change memory element 13a includes a memory element adopting an all-solid secondary battery structure, a memory transistor storing data by injecting hot carriers into a floating gate or a sidewall, and the like.

The resistance change memory 10 performs reading by a twin sense amplifier system, and the sense amplifier section 11 has two sense amplifiers 11a and 11b.
When reading the memory element 13a, the input terminal of the sense amplifier 11a is supplied with the reference potential V0ref, and the input terminal of the sense amplifier 11b is supplied with the reference potential V1ref higher than the reference potential V0ref. As a result, the potential Vin1 of the input terminal of the sense amplifier 11a becomes Vin1=V0ref, and the potential Vin2 of the input terminal of the sense amplifier 11b becomes Vin2=V1ref. The reference potential V0ref is a reference value of the data potential Vdata obtained by current-voltage conversion when the data in the memory element 13a is "0". The reference potential V1ref is a reference value of the data potential Vdata obtained by current-voltage conversion when the data of the memory element 13a is "1".

The sense amplifier 11a performs differential amplification, and has an input terminal to which the data potential Vdata is supplied in addition to the input terminals described above. Its input terminal is the same as the output terminal of the sense amplifier 11a. The same applies to the sense amplifier 11b.

At the time of reading, the sense amplifier unit 11 amplifies the potential difference between the reference potential V0ref and the reference potential V1ref, whichever has the greater potential difference from the data potential Vdata. In the example of FIG. 1, since the output terminals of the sense amplifiers 11a and 11b are short-circuited, the sense amplifier that amplifies the potential difference between the data potential Vdata and the one of the reference potentials V0ref and V1ref having a larger potential difference from the data potential Vdata is provided. Amplify strongly first. As a result, the output potential Vout of the sense amplifier section 11 is determined by subordinating the sense amplifier to the other sense amplifier.

On the other hand, during write-verify for the memory element 13a, a verify potential is supplied to the input terminals of the sense amplifiers 11a and 11b. Write-verify includes "0" write-verify performed when "0" is written to the memory element 13a and "1" write-verify performed when "1" is written to the memory element 13a. Different verify potentials are used for "0" write verify and "1" write verify.

For example, as shown in FIG. 1, during "0" write verify, the input terminals of the sense amplifiers 11a and 11b are supplied with the reference potential V0ref as the verify potential. As a result, Vin1=Vin2=V0ref. At the time of "1" write verify, the reference potential V1ref is supplied as a verify potential to the input terminals of the sense amplifiers 11a and 11b. As a result, Vin1=Vin2=V1ref.

Then, during write verify, the sense amplifier unit 11 amplifies the potential difference between the verify potential and the data potential Vdata.
At the time of write-verify, the output terminals of the sense amplifiers 11a and 11b may be electrically disconnected by a switch (not shown), and different verify potentials may be supplied to the input terminals of the sense amplifiers 11a and 11b. In that case, a signal obtained by amplifying the potential difference between each verify potential and the data potential Vdata is output. An example thereof will be described in the third embodiment.

The supply potential switching circuit 12 supplies the reference potential V0ref to the input terminal of the sense amplifier 11a and the reference potential V1ref to the input terminal of the sense amplifier 11b when reading the memory element 13a. Further, the supply potential switching circuit 12 supplies a verify potential to the sense amplifiers 11a and 11b at the time of write verify for the memory element 13a. In the example of FIG. 1, the supply potential switching circuit 12 supplies the reference potential V0ref as the verify potential to the input terminals of the sense amplifiers 11a and 11b during "0" write verify. Further, the supply potential switching circuit 12 supplies the reference potential V1ref as a verify potential to the input terminals of the sense amplifiers 11a and 11b during "1" write verify.

A signal sel indicating whether the memory element 13a is read, "0" write-verified, or "1" write-verified is supplied from an operation selection circuit (not shown).

An operation example of the resistance change type memory 10 according to the first embodiment will be described below.
When the memory element 13a is read, the data potential Vdata when "0" is written in the memory element 13a, as shown in the lower part of FIG. ) may be higher than Further, the data potential Vdata when "1" is written in the memory element 13a may be lower than the reference value (reference potential V1ref) due to deterioration such as retention.

For example, when data potential Vdata is Vdata=Vd1, sense amplifier unit 11 amplifies the potential difference between reference potential V1ref and data potential Vdata because Vd1−V0ref<V1ref−Vd1. As a result, a value representing "0" is obtained as the output potential Vout. For example, when the data potential Vdata is Vdata=Vd2, the sense amplifier unit 11 amplifies the potential difference between the reference potential V0ref and the data potential Vdata because Vd2−V0ref>V1ref−Vd2. As a result, a value representing "1" is obtained as the output potential Vout.

At the time of "0" write-verify for the memory element 13a, the supply potential switching circuit 12 supplies, for example, the reference potential V0ref to the input terminals of the sense amplifiers 11a and 11b. Thereby, the sense amplifier unit 11 amplifies the potential difference between the data potential Vdata and the reference potential V0ref. When the data potential Vdata is lower than the reference potential V0ref (when "0" is appropriately written), the output potential Vout becomes low. When the data potential Vdata is higher than the reference potential V0ref (when "0" is not properly written), the output potential Vout becomes high.

At the time of "1" write-verify for the memory element 13a, the supply potential switching circuit 12 supplies, for example, the reference potential V1ref to the input terminals of the sense amplifiers 11a and 11b. Thereby, the sense amplifier unit 11 amplifies the potential difference between the data potential Vdata and the reference potential V1ref. When the data potential Vdata is lower than the reference potential V1ref (when "1" is not properly written), the output potential Vout becomes low. When the data potential Vdata is higher than the reference potential V1ref (when "1" is appropriately written), the output potential Vout becomes high.

A write control circuit (not shown) determines whether or not to continue writing to the memory element 13a based on the output potential Vout at each write verify.
As described above, in the resistance change type memory 10 of the first embodiment, the supply potential switching circuit 12 changes the potentials supplied to the sense amplifiers 11a and 11b that implement the read of the twin sense amplifier method during reading and writing. It is switched between when verifying and when verifying. As a result, write verify can be performed using the sense amplifiers 11a and 11b used for reading. In other words, there is no need to separately provide a sense amplifier for write verification, and an increase in the circuit scale of the resistance change memory 10 can be suppressed.

(Second embodiment)
FIG. 2 is a diagram showing an example of a resistance change memory according to the second embodiment.
A resistance change memory 20 according to the second embodiment includes an interface circuit (denoted as an I/F circuit in FIG. 2) 21, an address register 22, a state machine 23, a command register 24, and a data input/output buffer 25. have. Furthermore, the resistance change memory 20 has a row control circuit 26, a column control circuit 27, and a memory cell array 28. FIG.

The interface circuit 21 transmits and receives data, addresses, and commands to and from a device external to the resistance change memory 20 (for example, a processor connected to the interface circuit 21 via a bus).

The address register 22 holds an address (read address or write address) supplied from an external device via the interface circuit 21 . The address includes a row address and a column address. For example, the upper bits of the address are the row address and the lower bits are the column address.

The state machine 23 controls the data input/output buffer 25, the row control circuit 26, the column control circuit 27, etc. based on the command supplied from the command register 24. FIG.
The command register 24 holds commands supplied from an external device via the interface circuit 21 .

The data input/output buffer 25 holds write data supplied from an external device via the interface circuit 21 or read data read from the memory cell array 28 .

The row control circuit 26 applies a predetermined voltage to any of a plurality of word lines (not shown) included in the memory cell array 28 under the control of the state machine 23 based on the row address supplied from the address register 22. .

The column control circuit 27 writes to and reads from memory cells included in the memory cell array 28 under the control of the state machine 23 based on the column address supplied from the address register 22 .

FIG. 3 is a diagram showing an example of a memory cell array.
, WLn, bit lines BL1, BL2, . . . , BLk, source lines SL1, SL2, . have.

Each of the plurality of memory cells is connected to one of word lines WL1 to WLn, one of bit lines BL1 to BLk, and one of source lines SL1 to SLk. For example, memory cell 28a is connected to word line WL1, bit line BL1 and source line SL1, and memory cell 28b is connected to word line WL1, bit line BL2 and source line SL2. Also, the memory cell 28c is connected to a word line WLn, a bit line BLk and a source line SLk.

FIG. 4 is a diagram showing an example of a memory cell.
The memory cell 28a has an n-channel MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) 28a1 and a resistance change memory element 28a2.

The gate of an n-channel MOSFET (hereinafter referred to as nMOS transistor) 28a1 is connected to word line WL1, and one of the drain and source of nMOS transistor 28a1 is connected to bit line BL1. The other of the drain and source of the nMOS transistor 28a1 is connected to one terminal of the memory element 28a2. The other terminal of memory element 28a2 is connected to source line SL1.

The resistance change memory element 28a2 is a memory element adopting an all-solid secondary battery structure, a memory transistor that stores data by injecting hot carriers into a floating gate or a sidewall, or the like.

Other memory cells in memory cell array 28 have the same configuration as memory cell 28a shown in FIG.
FIG. 5 is a diagram showing an example of a column control circuit.

The column control circuit 27 has 1-bit processing units 27a1, 27a2, .
The 1-bit processing unit 27a1 is a circuit that performs processing related to reading and writing of 1-bit data DQ<0>, and includes column switches 27b and 27c, a source line driver 27d, a bit line driver 27e, and a current-voltage conversion circuit 27f. have. Further, the 1-bit processing section 27a1 has a write control circuit 27g, a supply potential switching circuit 27h, a sense amplifier section 27i, an operation selection circuit 27j, a verify result determination circuit 27k, a data input circuit 27l, and a data output circuit 27m.

Based on the column address supplied from the address register 22, the column switch 27b connects one of the source lines SL1 to SLk to the source line driver 27d. Based on the column address supplied from the address register 22, the column switch 27c connects one of the bit lines BL1 to BLk to the bit line driver 27e.

The source line driver 27d generates voltages to be applied to the source lines SL1 to SLk under the control of the write control circuit 27g. The bit line driver 27e generates voltages to be applied to the bit lines BL1 to BLk under the control of the write control circuit 27g.

The current-voltage conversion circuit 27f converts the current flowing through any one of the bit lines BL1 to BLk into a voltage when a read instruction signal or a verify instruction signal output from the state machine 23 instructs execution of read or write verify. Convert.

The write control circuit 27g controls the source line driver 27d and the bit line based on the value of data DQ<0> externally supplied via the data input circuit 27l when a write instruction signal instructs the execution of writing. It causes the driver 27e to generate a predetermined voltage for writing. A write instruction signal is supplied from the state machine 23 . If the verify result output from the verify result determination circuit 27k indicates that the write was performed correctly, the write control circuit 27g causes the source line driver 27d and the bit line driver 27e to generate a predetermined voltage for writing. stop.

The supply potential switching circuit 27h switches the potential to be supplied to the sense amplifier section 27i between read and write verify based on a signal supplied from the operation selection circuit 27j. The sense amplifier section 27i amplifies the potential difference between the potential supplied by the supply potential switching circuit 27h and the data potential D<0> obtained by the current-voltage conversion circuit 27f, and outputs the amplified potential difference.

The operation selection circuit 27j selects which operation to perform based on the read instruction signal and the verify instruction signal. Then, the operation selection circuit 27j supplies a signal corresponding to the selected operation to the supply potential switching circuit 27h and the sense amplifier section 27i at a predetermined timing.

When the operation selection circuit 27j is instructed to perform write verification, and the value of the data DQ<0> is "0", the operation selection circuit 27j normally writes "0" to the verify result determination circuit 27k by the 0 determination selection signal. is performed. Further, when the value of data DQ<0> is "1", the operation selection circuit 27j determines whether "1" was normally written to the verify result determination circuit 27k by the 1 determination selection signal. Let

The verify result determination circuit 27k determines "0" or "1" based on the output signal of the sense amplifier unit 27i and the 0 determination selection signal or the 1 determination selection signal when the verify instruction signal instructs execution of write verification. ” was written normally. Then, the verify result determination circuit 27k outputs the determination result (verify result).

The data input circuit 27l supplies the data DQ<0> to the write control circuit 27g and the operation selection circuit 27j when the input instruction signal output from the state machine 23 instructs the input of the data DQ<0>. do.

The data output circuit 27m outputs the output signal of the sense amplifier section 27i as the data DQ<0> when the output of the data DQ<0> is instructed by the output instruction signal output from the state machine 23. .

The other 1-bit processing units 27a2 to 27am also have the same configuration as the 1-bit processing unit 27a1.
FIG. 6 is a diagram showing an example of a current-voltage conversion circuit.

The current-voltage conversion circuit 27f has, for example, a p-channel MOSFET (hereinafter referred to as pMOS transistor) 27f1.
The power supply potential VDD is supplied to the drain of the pMOS transistor 27f1, and the bias voltage VBIAS for turning on the pMOS transistor 27f1 is supplied to the gate. Although not shown in FIG. 6, the source of the pMOS transistor 27f1 is connected to one of the bit lines BL1 to BLk by the column switch 27c shown in FIG. The example of FIG. 6 shows an example in which the source of the pMOS transistor 27f1 is connected to the bit line BL1. Also, the potential of the source of the pMOS transistor 27f1 is supplied to the sense amplifier section 27i as the data potential D<0>.

The current-voltage conversion circuit 27f has a switch that electrically disconnects the sense amplifier section 27i from the column switch 27c shown in FIG. may

In such a current-voltage conversion circuit 27f, the pMOS transistor 27f1 functions as a constant current source.
For example, when the memory cell 28a is selected, the resistance of the memory element 28a2 is Rcell, and the current flowing through the memory element 28a2 by the constant current source is Iref, the data potential D<0> is D<0>=Rcell× Iref. That is, the data potential D<0> changes according to the value of Rcell.

FIG. 7 is a diagram showing an example of a supply potential switching circuit and a sense amplifier section.
The supply potential switching circuit 27h has pMOS transistors 27h1, 27h3, 27h5 and 27h7 and nMOS transistors 27h2, 27h4, 27h6 and 27h8.

A reference potential V0ref is supplied to the sources of the pMOS transistors 27h1 and 27h7 and the drains of the nMOS transistors 27h2 and 27h8. A reference potential V1ref is supplied to the sources of the pMOS transistors 27h3 and 27h5 and the drains of the nMOS transistors 27h4 and 27h6. A signal trans0b is supplied to the gate of the pMOS transistor 27h1, and a signal trans0t is supplied to the gate of the nMOS transistor 27h2. A signal trans1vb is supplied to the gate of the pMOS transistor 27h3, and a signal trans1vt is supplied to the gate of the nMOS transistor 27h4. A signal trans1b is supplied to the gate of the pMOS transistor 27h5, and a signal trans1t is supplied to the gate of the nMOS transistor 27h6. A signal trans0vb is supplied to the gate of the pMOS transistor 27h7, and a signal trans0vt is supplied to the gate of the nMOS transistor 27h8. The drains of the pMOS transistors 27h1 and 27h3 and the sources of the nMOS transistors 27h2 and 27h4 are connected to the input terminal of the sense amplifier 27ia included in the sense amplifier section 27i. The drains of the pMOS transistors 27h5 and 27h7 and the sources of the nMOS transistors 27h6 and 27h8 are connected to the input terminal of the sense amplifier 27ib included in the sense amplifier section 27i.

The signals trans0b, trans1vb, trans1vt, trans0t, trans1b, trans0vb, trans0vt and trans1t are supplied from the operation selection circuit 27j.

The sense amplifier section 27i has a pMOS transistor 27i1, an nMOS transistor 27i2, precharge circuits (denoted as "PRE" in the figure) 27i3, 27i4, 27i5, a NAND circuit 27i6, and an inverter circuit 27i7. Further, the sense amplifier section 27i has sense amplifiers 27ia and 27ib.

A data potential D<0> is supplied to the source of the pMOS transistor 27i1 and the drain of the nMOS transistor 27i2. A signal transb is supplied to the gate of the pMOS transistor 27i1, and a signal transt is supplied to the gate of the nMOS transistor 27i2. The drain of the pMOS transistor 27i1 and the source of the nMOS transistor 27i2 are connected to the output terminal of the precharge circuit 27i4, the output terminals of the sense amplifiers 27ia and 27ib (also serving as one of the two input terminals), and one input terminal of the NAND circuit 27i6. is connected. The signals transb and transst are supplied from the operation selection circuit 27j.

The output terminal of the precharge circuit 27i3 is connected to the drains of the pMOS transistors 27h1 and 27h3, the sources of the nMOS transistors 27h2 and 27h4 of the supply potential switching circuit 27h, and the input terminal of the sense amplifier 27ia.

The output terminal of the precharge circuit 27i5 is connected to the drains of the pMOS transistors 27h5 and 27h7, the sources of the nMOS transistors 27h6 and 27h8 of the supply potential switching circuit 27h, and the input terminal of the sense amplifier 27ib.

FIG. 8 is a diagram showing an example of a precharge circuit.
FIG. 8 shows an example of the precharge circuit 27i3. Precharge circuits 27i4 and 27i5 have the same configuration as precharge circuit 27i3 shown in FIG.

The precharge circuit 27i3 has an nMOS transistor 27i3a and a pMOS transistor 27i3b. A precharge potential VPR is supplied to the drain of the nMOS transistor 27i3a and the source of the pMOS transistor 27i3b. A signal pret is supplied to the gate of the nMOS transistor 27i3a, and a signal preb is supplied to the gate of the pMOS transistor 27i3b. The source of the nMOS transistor 27i3a and the drain of the pMOS transistor 27i3b are connected to the output terminal OUT of the precharge circuit 27i3. Signals pret and preb are supplied from an operation selection circuit 27j.

Returning to the description of FIG.
One input terminal of the NAND circuit 27i6 is connected to the drain of the pMOS transistor 27i1, the source of the nMOS transistor 27i2, the output terminal of the precharge circuit 27i4, and the output terminals of the sense amplifiers 27ia and 27ib. A signal saouten is supplied from the operation selection circuit 27j to the other input terminal of the NAND circuit 27i6. The output terminal of the NAND circuit 27i6 is connected to the input terminal of the inverter circuit 27i7, and the output signal saout of the sense amplifier section 27i is output from the output terminal of the inverter circuit 27i7.

The sense amplifier 27ia has pMOS transistors 27ia1, 27ia2 and 27ia3, nMOS transistors 27ia4, 27ia5 and 27ia6, and precharge circuits 27ia7 and 27ia8.

The power supply potential VDD is supplied to the source of the pMOS transistor 27ia1, and the signal salatb is supplied to the gate of the pMOS transistor 27ia1. The drain of the pMOS transistor 27ia1 is connected to the sources of the pMOS transistors 27ia2 and 27ia3 and the output terminal of the precharge circuit 27ia7. The drain of the pMOS transistor 27ia2 and the drain of the nMOS transistor 27ia4 function as input terminals of the sense amplifier 27ia. The drain of the pMOS transistor 27ia2 and the drain of the nMOS transistor 27ia4 are connected to the gates of the pMOS transistor 27ia3 and the nMOS transistor 27ia5. The drain of the pMOS transistor 27ia3 and the drain of the nMOS transistor 27ia5 function as output terminals of the sense amplifier 27ia. The drain of the pMOS transistor 27ia3 and the drain of the nMOS transistor 27ia5 are connected to the gates of the pMOS transistor 27ia2 and the nMOS transistor 27ia4. The sources of the nMOS transistors 27ia4 and 27ia5 are connected to the drain of the nMOS transistor 27ia6. The source of the nMOS transistor 27ia6 is grounded, and the gate of the nMOS transistor 27ia6 is supplied with the signal salatt.

The output terminal of the precharge circuit 27ia7 is connected to the drain of the pMOS 27ia1 and the sources of the pMOS transistors 27ia2 and 27ia3. The output terminal of the precharge circuit 27ia8 is connected to the sources of the nMOSs 27ia4 and 27ia5 and the drain of the nMOS transistor 27ia6. Precharge circuits 27ia7 and 27ia8 have the same configuration as precharge circuit 27i3 shown in FIG.

The signals salatb and salatt are supplied from the operation selection circuit 27j.
The sense amplifier 27ib has pMOS transistors 27ib1, 27ib2 and 27ib3, nMOS transistors 27ib4, 27ib5 and 27ib6, and precharge circuits 27ib7 and 27ib8. Since the connection relationship between these elements is the same as that of the sense amplifier 27ia, the description thereof is omitted.

An operation example of the resistance change memory 20 of the second embodiment, particularly the supply potential switching circuit 27h and the sense amplifier section 27i will be described below.
FIG. 9 is a timing chart showing an example of changes in the potential of each signal and each part when "0" is read.

At timing t1, the potentials of the signals pret, transb, trans0b, trans1b, trans0vb, trans1vb, and salatb are the power supply potential VDD. The potentials of the signals preb, transt, trans0t, trans1t, trans0vt, trans1vt, salatt, saouten and the output signal saout are the ground potential VSS. Also, the potentials so1r, sod, and so0r are the precharge potential VPR.

The operation selection circuit 27j lowers the potential of the signal pret from the power supply potential VDD to the ground potential VSS and raises the potential of the signal preb from the ground potential VSS to the power supply potential VDD from timing t1 to timing t2. As a result, both the nMOS transistor 27i3a and the pMOS transistor 27i3b shown in FIG. 8 are turned off.

Further, the operation selection circuit 27j lowers the potentials of the signals transb, trans0b, and trans1b from the power supply potential VDD to the ground potential VSS from timing t2 to timing t3. Furthermore, the operation selection circuit 27j raises the potentials of the signals transt, trans0t, and trans1t from the ground potential VSS to the power supply potential VDD from timing t2 to timing t3. This turns on the pMOS transistors 27h1, 27h5 and 27i1 and the nMOS transistors 27h2, 27h6 and 27i2.

On the other hand, the potentials of the signals trans0vb and trans1vb remain at the power supply potential VDD, and the signals trans0vt and trans1vt remain at the ground potential VSS. Therefore, the pMOS transistors 27h3 and 27h7 and the nMOS transistors 27h4 and 27h8 are off.

As a result, the potential so0r of the input terminal of the sense amplifier 27ia, which was at the precharge potential VPR, drops to the reference potential V0ref, and the potential so1r of the input terminal of the sense amplifier 27ib, which was at the precharge potential VPR, rises to the reference potential V1ref. . Also, the potential sod of the output terminals of the sense amplifiers 27ia and 27ib is equal to the data potential D<0>, and is lower than the precharge potential VPR when "0" is read.

Further, the operation selection circuit 27j raises the potentials of the signals transb, trans0b, and trans1b from the ground potential VSS to the power supply potential VDD from timing t4 to timing t5. Furthermore, the operation selection circuit 27j lowers the potentials of the signals transt, trans0t, and trans1t from the power supply potential VDD to the ground potential VSS from timing t4 to timing t5. This turns off the pMOS transistors 27h1, 27h5 and 27i1 and the nMOS transistors 27h2, 27h6 and 27i2.

Then, from timing t5 to timing t6, the operation selection circuit 27j lowers the potential of the signal salatb from the power supply potential VDD to the ground potential VSS, and raises the potential of the signal salatt from the ground potential VSS to the power supply potential VDD. This causes the sense amplifiers 27ia and 27ib to function.

At this time, since sod-so0r<so1r-sod, the sense amplifier unit 27i amplifies the potential difference between the potential so1r and the potential sod. As a result, the potential sod becomes the ground potential VSS. Also, the potentials so1r and so0r become the power supply potential VDD.

Thereafter, the operation selection circuit 27j raises the potential of the signal saouten from the ground potential VSS to the power supply potential VDD from timing t7 to timing t8. At this time, since the potential sod is the ground potential VSS, the potential of the output signal saout also remains at the ground potential VSS.

The data output circuit 27m outputs the output signal saout at this time as data DQ<0> (1-bit read data).
After that, from timing t9 to timing t10, the operation selection circuit 27j raises the potential of the signal salatb from the ground potential VSS to the power supply potential VDD, and lowers the potential of the signal salatt from the power supply potential VDD to the ground potential VSS. As a result, the sense amplifiers 27ia and 27ib stop functioning. Further, the operation selection circuit 27j lowers the potential of the signal saouten from the power supply potential VDD to the ground potential VSS.

Further, the operation selection circuit 27j raises the potential of the signal pret from the ground potential VSS to the power supply potential VDD and lowers the potential of the signal preb from the power supply potential VDD to the ground potential VSS from timing t10 to timing t11. As a result, the potentials so1r, so0r, and sod return to the precharge potential VPR.

FIG. 10 is a timing chart showing an example of changes in the potential of each signal and each part when "1" is read.
Changes in each signal and the potential of each part from timing t20 to timing t21 are the same as when "0" is read.

Further, from timing t21 to timing t22, changes in the potentials of each signal and each part are almost the same as when "0" is read. Higher than VPR.

Changes in each signal and the potential of each part from timing t23 to timing t24 are the same as when "0" is read. The changes in each signal and the potential of each part from timing t24 to timing t25 are almost the same as when "0" is read. Amplifies the potential difference with the potential sod. As a result, the potential sod becomes the power supply potential VDD. Also, the potentials so1r and so0r become the ground potential VSS.

Thereafter, the operation selection circuit 27j raises the potential of the signal saouten from the ground potential VSS to the power supply potential VDD from timing t26 to timing t27. At this time, since the potential sod is the power supply potential VDD, the potential of the output signal saout rises from the ground potential VSS to the power supply potential VDD.

The data output circuit 27m outputs the output signal saout at this time as data DQ<0> (1-bit read data).
After that, from timing t28 to timing t29, the operation selection circuit 27j raises the potential of the signal salatb from the ground potential VSS to the power supply potential VDD, and lowers the potential of the signal salatt from the power supply potential VDD to the ground potential VSS. As a result, the sense amplifiers 27ia and 27ib stop functioning. Further, the operation selection circuit 27j lowers the potential of the signal saouten from the power supply potential VDD to the ground potential VSS. As a result, the potential of the output signal saout also drops from the power supply potential VDD to the ground potential VSS.

The change in the potential of each signal and each part from timing t29 to timing t30 after that is the same as when "0" is read.
FIG. 11 is a timing chart showing an example of changes in the potential of each signal and each part during "0" write verify.

Changes in each signal and the potential of each part from timing t40 to timing t41 are the same as during reading.
The operation selection circuit 27j lowers the potentials of the signals transb, trans0b, and trans0vb from the power supply potential VDD to the ground potential VSS from timing t41 to timing t42. Furthermore, the operation selection circuit 27j raises the potentials of the signals transt, trans0t, and trans0vt from the ground potential VSS to the power supply potential VDD from timing t41 to timing t42. This turns on the pMOS transistors 27h1, 27h7 and 27i1 and the nMOS transistors 27h2, 27h8 and 27i2.

On the other hand, the potentials of the signals trans1b and trans1vb remain at the power supply potential VDD, and the signals trans1t and trans1vt remain at the ground potential VSS. Therefore, the pMOS transistors 27h3 and 27h5 and the nMOS transistors 27h4 and 27h6 are off.

As a result, the potentials so0r and so1r of the input terminals of the sense amplifiers 27ia and 27ib, which were at the precharge potential VPR, drop to the reference potential V0ref. Also, the potential sod of the output terminals of the sense amplifiers 27ia and 27ib is equal to the data potential D<0>.

Further, the operation selection circuit 27j raises the potentials of the signals transb, trans0b, and trans0vb from the ground potential VSS to the power supply potential VDD from timing t43 to timing t44. Furthermore, the operation selection circuit 27j lowers the potentials of the signals transt, trans0t, and trans0vt from the power supply potential VDD to the ground potential VSS from timing t43 to timing t44. As a result, the pMOS transistors 27h1, 27h7 and 27i1 and the nMOS transistors 27h2, 27h8 and 27i2 are turned off.

Then, from timing t44 to timing t45, the operation selection circuit 27j lowers the potential of the signal salatb from the power supply potential VDD to the ground potential VSS, and raises the potential of the signal salatt from the ground potential VSS to the power supply potential VDD. This causes the sense amplifiers 27ia and 27ib to function.

At this time, the sense amplifier unit 27i amplifies the potential difference between the potential sod and the potentials so0r and so1r (=reference potential V0ref). When sod<V0ref, the potential sod becomes the ground potential VSS, and when sod>V0ref, the potential sod becomes the power supply potential VDD. In the example of FIG. 11, sod<V0ref, and the potential sod has changed to the ground potential VSS. When the potential sod changes to the ground potential VSS, the potentials so0r and so1r change to the power supply potential VDD. When the potential sod changes to the power supply potential VDD, the potentials so0r and so1r change to the ground potential VSS. change to

Thereafter, the operation selection circuit 27j raises the potential of the signal saouten from the ground potential VSS to the power supply potential VDD from timing t46 to timing t47. At this time, when the potential sod is the ground potential VSS, the potential of the output signal saout is also the ground potential VSS, and when the potential sod is the power supply potential VDD, the potential of the output signal saout is also the power supply potential VDD.

When the potential of the output signal saout is the power supply potential VDD at timing t47 during "0" write verify, the verify result determination circuit 27k determines that the write of "0" is not performed normally ("fail"). , the judgment result to that effect is output. In this case, the write control circuit 27g continues the control for writing "0".

On the other hand, when the potential of the output signal saout is the ground potential VSS at timing t47 during "0" write verify, the verify result determination circuit 27k determines that the write of "0" was performed normally ("pass"). and outputs the judgment result to that effect. In this case, the write control circuit 27g stops the source line driver 27d and the bit line driver 27e from generating the write voltage of "0".

After that, from timing t48 to timing t49, the operation selection circuit 27j raises the potential of the signal salatb from the ground potential VSS to the power supply potential VDD, and lowers the potential of the signal salatt from the power supply potential VDD to the ground potential VSS. As a result, the sense amplifiers 27ia and 27ib stop functioning. Further, the operation selection circuit 27j lowers the potential of the signal saouten from the power supply potential VDD to the ground potential VSS. As a result, when the potential of the output signal saout has risen to the power supply potential VDD, it drops to the ground potential VSS.

The changes in each signal and the potential of each part from timing t49 to timing t50 after that are the same as those at the time of reading.
FIG. 12 is a timing chart showing an example of changes in the potential of each signal and each part during "1" write verify.

Changes in each signal and the potential of each part from timing t60 to timing t61 are the same as during reading.
The operation selection circuit 27j lowers the potentials of the signals transb, trans1b, and trans1vb from the power supply potential VDD to the ground potential VSS from timing t61 to timing t62. Furthermore, the operation selection circuit 27j raises the potentials of the signals transt, trans1t, and trans1vt from the ground potential VSS to the power supply potential VDD from timing t61 to timing t62. This turns on the pMOS transistors 27h3, 27h5 and 27i1 and the nMOS transistors 27h4, 27h6 and 27i2.

On the other hand, the potentials of the signals trans0b and trans0vb remain at the power supply potential VDD, and the signals trans0t and trans0vt remain at the ground potential VSS. Therefore, the pMOS transistors 27h1 and 27h7 and the nMOS transistors 27h2 and 27h8 are off.

As a result, the potentials so0r and so1r of the input terminals of the sense amplifiers 27ia and 27ib, which were at the precharge potential VPR, rise to the reference potential V1ref. Also, the potential sod of the output terminals of the sense amplifiers 27ia and 27ib is equal to the data potential D<0>.

Further, the operation selection circuit 27j raises the potentials of the signals transb, trans1b, and trans1vb from the ground potential VSS to the power supply potential VDD from timing t63 to timing t64. Further, the operation selection circuit 27j lowers the potentials of the signals transt, trans1t, and trans1vt from the power supply potential VDD to the ground potential VSS from timing t63 to timing t64. This turns off the pMOS transistors 27h3, 27h5 and 27i1 and the nMOS transistors 27h4, 27h6 and 27i2.

Then, from timing t64 to timing t65, the operation selection circuit 27j lowers the potential of the signal salatb from the power supply potential VDD to the ground potential VSS, and raises the potential of the signal salatt from the ground potential VSS to the power supply potential VDD. This causes the sense amplifiers 27ia and 27ib to function.

At this time, the sense amplifier unit 27i amplifies the potential difference between the potential sod and the potentials so0r and so1r (=reference potential V1ref). When sod<V1ref, the potential sod becomes the ground potential VSS, and when sod>V1ref, the potential sod becomes the power supply potential VDD. In the example of FIG. 12, sod>V1ref, and the potential sod has changed to the power supply potential VDD. When the potential sod changes to the ground potential VSS, the potentials so0r and so1r change to the power supply potential VDD. When the potential sod changes to the power supply potential VDD, the potentials so0r and so1r change to the ground potential VSS. change to

Thereafter, the operation selection circuit 27j raises the potential of the signal saouten from the ground potential VSS to the power supply potential VDD from timing t66 to timing t67. At this time, when the potential sod is the ground potential VSS, the potential of the output signal saout is also the ground potential VSS, and when the potential sod is the power supply potential VDD, the potential of the output signal saout is also the power supply potential VDD.

When the potential of the output signal saout is the ground potential VSS at the timing t67 during "1" write verify, the verify result determination circuit 27k determines that the write of "1" is not performed normally ("fail"). , the judgment result to that effect is output. In this case, the write control circuit 27g continues the control for writing "1".

On the other hand, when the potential of the output signal saout is the power supply potential VDD at the timing t67 during "1" write verify, the verify result determination circuit 27k determines that the write of "1" was performed normally ("pass"). and outputs the judgment result to that effect. In this case, the write control circuit 27g stops the source line driver 27d and the bit line driver 27e from generating the write voltage of "1".

The changes in each signal and the potential of each part from timing t68 to timing t69 are the same as those at the time of "0" write verify. Further, changes in each signal and the potential of each part from the timing t69 to the timing t70 are the same as those at the time of reading.

As described above, during reading, the sense amplifier 27ia is supplied with the reference potential V0ref, and the sense amplifier 27ib is supplied with the reference potential V1ref. During "0" write-verify, the reference potential V0ref is supplied to both the sense amplifiers 27ia and 27ib, and during "1" write-verify, the reference potential V1ref is supplied to both the sense amplifiers 27ia and 27ib.

As described above, according to the resistance change type memory 20 of the second embodiment, the supply potential switching circuit 27h changes the potential supplied to the sense amplifiers 27ia and 27ib for realizing the read of the twin sense amplifier method. It is switched between when write-verify is performed. As a result, write-verify can be performed using the sense amplifiers 27ia and 27ib used for reading. That is, there is no need to separately provide a sense amplifier for write verification, and an increase in the circuit scale of the resistance change type memory 20 can be suppressed.

(Comparative example 1)
FIG. 13 is a diagram showing a comparative example of the supply potential switching circuit and the sense amplifier section.
The supply potential switching circuit 30 has pMOS transistors 30a, 30c, 30e and nMOS transistors 30b, 30d, 30f.

A reference potential V0ref is supplied to the source of the pMOS transistor 30a and the drain of the nMOS transistor 30b, and a reference potential V1ref is supplied to the source of the pMOS transistor 30c and the drain of the nMOS transistor 30d. A reference potential Vrdref is supplied to the source of the pMOS transistor 30e and the drain of the nMOS transistor 30f. The reference potential Vrdref is an intermediate potential between the reference potential V0ref and the reference potential V1ref, and is used during reading.

A signal trans0b is supplied to the gate of the pMOS transistor 30a, and a signal trans0t is supplied to the gate of the nMOS transistor 30b. A signal trans1b is supplied to the gate of the pMOS transistor 30c, and a signal trans1t is supplied to the gate of the nMOS transistor 30d. Further, a signal transrdb is supplied to the gate of the pMOS transistor 30e, and a signal transrdt is supplied to the gate of the nMOS transistor 30f.

The drains of the pMOS transistors 30 a , 30 c and 30 e and the sources of the nMOS transistors 30 b , 30 d and 30 f are connected to the sense amplifier section 31 .
The sense amplifier section 31 has pMOS transistors 31a, 31c, 31e, nMOS transistors 31b, 31d, 31f, precharge circuits 31g, 31h, a sense amplifier 31i, a NAND circuit 31j, and an inverter circuit 31k.

A data potential D<0> is supplied to the sources of the pMOS transistors 31a, 31c and 31e and the drains of the nMOS transistors 31b, 31d and 31f. A signal transrdb is supplied to the gate of the pMOS transistor 31a, and a signal transrdt is supplied to the gate of the nMOS transistor 31b. A signal trans1b is supplied to the gate of the pMOS transistor 31c, and a signal trans1t is supplied to the gate of the nMOS transistor 31d. A signal trans0b is supplied to the gate of the pMOS transistor 31e, and a signal trans0t is supplied to the gate of the nMOS transistor 31f. The drains of the pMOS transistors 31a, 31c and 31e and the sources of the nMOS transistors 31b, 31d and 31f are connected to the output terminal of the sense amplifier 31i and one input terminal of the NAND circuit 31j.

The output terminal of the precharge circuit 31g is connected to the drains of the pMOS transistors 30a, 30c and 30e, the sources of the nMOS transistors 30b, 30d and 30f, and the input terminal of the sense amplifier 31i. The output terminal of the precharge circuit 31h is connected to the drains of the pMOS transistors 31a, 31c and 31e, the sources of the nMOS transistors 31b, 31d and 31f, and the output terminal (also serving as one of the two input terminals) of the sense amplifier 31i. there is

The sense amplifier 31i has pMOS transistors 31i1, 31i2 and 31i3, nMOS transistors 31i4, 31i5 and 31i6, and precharge circuits 31i7 and 31i8. Since the connection relationship of these elements is the same as that of the sense amplifier 27ia of FIG. 7, the description thereof is omitted.

The connection relationship between the NAND circuit 31j and the inverter circuit 31k is also the same as the connection relationship between the NAND circuit 27i6 and the inverter circuit 27i7 in FIG.
In the supply potential switching circuit 30 and the sense amplifier section 31 of the comparative example, the pMOS transistor 30a and the nMOS transistor 30b are turned on during "0" write verify, and the reference potential V0ref is supplied to the input terminal of the sense amplifier 31i. . Also, the pMOS transistor 31e and the nMOS transistor 31f are turned on, and the data potential D<0> is supplied to the output terminal of the sense amplifier 31i. Then, when the data potential D<0> is lower than the reference potential V0ref, the output signal saout becomes the ground potential VSS indicating that "0" is normally written.

At the time of "1" write verify, the pMOS transistor 30c and the nMOS transistor 30d are turned on, and the reference potential V1ref is supplied to the input terminal of the sense amplifier 31i. Also, the pMOS transistor 31c and the nMOS transistor 31d are turned on, and the data potential D<0> is supplied to the output terminal of the sense amplifier 31i. Then, when the data potential D<0> is higher than the reference potential V1ref, the output signal saout becomes the power supply potential VDD indicating that "1" is normally written.

On the other hand, during reading, the pMOS transistor 30e and the nMOS transistor 30f are turned on, and the reference potential Vrdref is supplied to the input terminal of the sense amplifier 31i. Also, the pMOS transistor 31a and the nMOS transistor 31b are turned on, and the data potential D<0> is supplied to the output terminal of the sense amplifier 31i. When the data potential D<0> is lower than the reference potential Vrdref, the output signal saout becomes the ground potential VSS indicating that "0" has been read. Further, when the data potential D<0> is higher than the reference potential Vrdref, the output signal saout becomes the power supply potential VDD indicating that "1" has been read.

In this way, at the time of reading, data is determined by the magnitude relationship between the reference potential Vrdref, which is an intermediate potential between the reference potential V0ref and the reference potential V1ref, and the data potential D<0>.

On the other hand, in the resistance change type memory 20 using the sense amplifiers 27ia and 27ib, the difference between the data potential D<0> and the one of the reference potentials V0ref and V1ref having a larger potential difference from the data potential D<0> at the time of reading. The sense amplifier, which amplifies the potential difference, performs strong amplification first. Since the sense amplifier subordinates the other sense amplifier to determine the data, the read margin can be improved as compared with the system using one sense amplifier.

(Comparative example 2)
FIG. 14 is a diagram showing an example of a twin sense amplifier type sense amplifier unit that supports only read processing. In FIG. 14, the same reference numerals are assigned to the same elements as in FIG.

The sense amplifier section 40 has pMOS transistors 41a, 41c and nMOS transistors 41b, 41d.
A reference potential V0ref is supplied to the source of the pMOS transistor 41a and the drain of the nMOS transistor 41b. The drain of the pMOS transistor 41a and the source of the nMOS transistor 41b are connected to the input terminal of the sense amplifier 27ia. A reference potential V1ref is supplied to the source of the pMOS transistor 41c and the drain of the nMOS transistor 41d. The drain of the pMOS transistor 41c and the source of the nMOS transistor 41d are connected to the input terminal of the sense amplifier 27ib. A signal transb is supplied to the gates of the pMOS transistors 41a and 41c, and a signal transt is supplied to the gates of the nMOS transistors 41b and 41d.

During reading, the pMOSs 41a and 41c are turned on, the nMOSs 41b and 41d are turned on, the input terminal of the sense amplifier 27ia is supplied with the reference potential V0ref, and the input terminal of the sense amplifier 27ib is supplied with the reference potential V1ref. A read process similar to that of the resistance change type memory 20 of the second embodiment is performed.

However, since the sense amplifier unit 40 as described above only supports read processing, another sense amplifier is provided to perform write-verify for the resistance change memory element.

On the other hand, in the resistance change type memory 20 of the second embodiment, the supply potential switching circuit 27h switches the potential to be supplied to the sense amplifiers 27ia and 27ib during reading and during write verify. As a result, there is no need to separately provide a sense amplifier for write verification, and an increase in the circuit scale of the resistance change memory 20 can be suppressed.

(Third Embodiment)
The overall configuration and the column control circuit of the resistance-change memory according to the third embodiment are the same as the overall configuration and the column control circuit of the resistance-change memory 20 according to the second embodiment shown in FIGS. The configuration is almost the same as that of

In the resistance change memory of the third embodiment, the configurations of the supply potential switching circuit and the sense amplifier section are different from the configurations of the supply potential switching circuit 27h and the sense amplifier section 27i of the resistance change memory 20 shown in FIG. ing.

FIG. 15 is a diagram showing an example of a supply potential switching circuit and a sense amplifier section in the resistance change memory according to the third embodiment.
The supply potential switching circuit 50 in the resistive memory of the third embodiment has nMOS transistors 50a, 50c, 50f and 50h and pMOS transistors 50b, 50d, 50e and 50g.

A reference potential V0ref is supplied to the drain of the nMOS transistor 50a and the source of the pMOS transistor 50b, and a reference potential Vs1ref is supplied to the drain of the nMOS transistor 50c and the source of the pMOS transistor 50d. A reference potential Vs0ref is supplied to the source of the pMOS transistor 50e and the drain of the nMOS transistor 50f, and a reference potential V1ref is supplied to the source of the pMOS transistor 50g and the drain of the nMOS transistor 50h.

The reference potential Vs0ref is higher than the reference potential V0ref and has a smaller potential difference from the reference potential V0ref than the reference potential V1ref (and the reference potential Vs1ref). The reference potential Vs1ref is lower than the reference potential V1ref and has a smaller potential difference from the reference potential V1ref than the reference potential V0ref (and the reference potential Vs0ref).

A signal ref0chgb is supplied to the gates of the nMOS transistor 50a and the pMOS transistor 50d, and a signal ref0chgt is supplied to the gates of the pMOS transistor 50b and the nMOS transistor 50c. A signal ref1chgb is supplied to the gates of the pMOS transistor 50e and the nMOS transistor 50h, and a signal ref1chgt is supplied to the gates of the nMOS transistor 50f and the pMOS transistor 50g.

The signals ref0chgb, ref0chgt, ref1chgb and ref1chgt are supplied from the operation selection circuit 27j shown in FIG.
The sources of the nMOS transistors 50 a and 50 c and the drains of the pMOS transistors 50 b and 50 d are connected to the input terminal side of the sense amplifier 27 ia included in the sense amplifier section 51 . The drains of the pMOS transistors 50 e and 50 g and the sources of the nMOS transistors 50 f and 50 h are connected to the input terminal side of the sense amplifier 27 ib included in the sense amplifier section 51 .

The sense amplifier section 51 has two sense amplifiers 27ia and 27ib like the sense amplifier section 27i of the resistance change type memory 20 of the second embodiment. Further, the sense amplifier section 51 has pMOS transistors 51a, 51d, 51e, 51h and 51n, and nMOS transistors 51b, 51c, 51f, 51g and 51m. The sense amplifier section 51 also has precharge circuits 51i, 51j, 51k, 51l, NAND circuits 51o0, 51o1, and inverter circuits 51p0, 51p1.

The source of the pMOS transistor 51a and the drain of the nMOS transistor 51b are connected to the sources of the nMOS transistors 50a and 50c and the drains of the pMOS transistors 50b and 50d. A data potential D<0> is supplied to the drains of the nMOS transistors 51c and 51f and the sources of the pMOS transistors 51d and 51e. The drain of the nMOS transistor 51g and the source of the pMOS transistor 51h are connected to the drains of the pMOS transistors 50e and 50g and the sources of the nMOS transistors 50f and 50h. A signal transt is supplied to the gates of the nMOS transistors 51b, 51c, 51f and 51g, and a signal transb is supplied to the gates of the pMOS transistors 51a, 51d, 51e and 51h.

The signals transb and transst are supplied from the operation selection circuit 27j shown in FIG.
The drain of the pMOS transistor 51a and the source of the nMOS transistor 51b are connected to the input terminal of the sense amplifier 27ia and the output terminal of the precharge circuit 51i. The source of the nMOS transistor 51g and the drain of the pMOS transistor 51h are connected to the input terminal of the sense amplifier 27ib and the output terminal of the precharge circuit 51l.

The source of the nMOS transistor 51c and the drain of the pMOS transistor 51d are connected to one of the drain and source of the nMOS transistor 51m and one of the drain and source of the pMOS transistor 51n. The source of the nMOS transistor 51c and the drain of the pMOS transistor 51d are further connected to the output terminal of the sense amplifier 27ia, the output terminal of the precharge circuit 51j, and one input terminal of the NAND circuit 51o0.

The drain of the pMOS transistor 51e and the source of the nMOS transistor 51f are connected to the other of the drain and source of the nMOS transistor 51m and the other of the drain and source of the pMOS transistor 51n. The drain of the pMOS transistor 51e and the source of the nMOS transistor 51f are further connected to the output terminal of the sense amplifier 27ib, the output terminal of the precharge circuit 51k, and one input terminal of the NAND circuit 51o1.

A signal twint is supplied to the gate of the nMOS transistor 51m, and a signal twinb is supplied to the gate of the pMOS transistor 51n. Signals twint and twinb are supplied from the operation selection circuit 27j shown in FIG.

The signal saouten0 is supplied to the other input terminal of the NAND circuit 51o0, and the signal saouten1 is supplied to the other input terminal of the NAND circuit 51o1. The signals saouten0 and saouten1 are supplied from the operation selection circuit 27j shown in FIG.

The output terminal of the NAND circuit 51o0 is connected to the input terminal of the inverter circuit 51p0, and the output terminal of the NAND circuit 51o1 is connected to the input terminal of the inverter circuit 51p1. As the output signal of the sense amplifier section 51, the output signal saout0 is output from the output terminal of the inverter circuit 51p0, and the output signal saout1 is output from the output terminal of the inverter circuit 51p1.

The precharge circuits 51i to 51l have the same configuration as the precharge circuit 27i3 shown in FIG.
An operation example of the resistance change type memory according to the third embodiment, in particular, the supply potential switching circuit 50 and the sense amplifier section 51 will be described below.

FIG. 16 is a timing chart showing an example of changes in the potential of each signal and each part when "0" is read.
During reading, the potentials of the signals twint, ref0chgb and ref1chgb are fixed at the power supply potential VDD, and the potentials of the signals twinb, ref0chgt and ref1chgt are fixed at the ground potential VSS. Therefore, the nMOS transistors 50a, 50h, 51m and the pMOS transistors 50b, 50g, 51n are turned on, and the nMOS transistors 50c, 50f and the pMOS transistors 50d, 50e are turned off.

At timing t80, the potentials of the signals pret, transb, and salatb are the power supply potential VDD. The potentials of the signals preb, transt, salatt, saouten0, saouten1 and the output signals saout0, saout1 are the ground potential VSS. Also, the potentials so1r, so0d, sao1d, and so0r are the precharge potential VPR.

The operation selection circuit 27j lowers the potential of the signal pret from the power supply potential VDD to the ground potential VSS and raises the potential of the signal preb from the ground potential VSS to the power supply potential VDD from timing t80 to timing t81. As a result, both the nMOS transistor 27i3a and the pMOS transistor 27i3b shown in FIG. 8 are turned off.

Further, the operation selection circuit 27j lowers the potential of the signal transb from the power supply potential VDD to the ground potential VSS and raises the potential of the signal transt from the ground potential VSS to the power supply potential VDD from timing t81 to timing t82. This turns on the nMOS transistors 51b, 51c, 51f and 51g and the pMOS transistors 51a, 51d, 51e and 51h.

At this time, the potential so0r of the input terminal of the sense amplifier 27ia, which was the precharge potential VPR, drops to the reference potential V0ref, and the potential so1r of the input terminal of the sense amplifier 27ib, which was the precharge potential VPR, rises to the reference potential V1ref. . Further, the output terminals of the sense amplifiers 27ia and 27ib are short-circuited, and their potentials so0d and so1d become equal to the data potential D<0>, which is lower than the precharge potential VPR when "0" is read.

Further, the operation selection circuit 27j raises the potential of the signal transb from the ground potential VSS to the power supply potential VDD and lowers the potential of the signal transt from the power supply potential VDD to the ground potential VSS from the timing t83 to the timing t84. As a result, the nMOS transistors 51b, 51c, 51f and 51g and the pMOS transistors 51a, 51d, 51e and 51h are turned off.

Then, from timing t84 to timing t85, the operation selection circuit 27j lowers the potential of the signal salatb from the power supply potential VDD to the ground potential VSS, and raises the potential of the signal salatt from the ground potential VSS to the power supply potential VDD. This causes the sense amplifiers 27ia and 27ib to function.

At this time, since so0d (=so1d)-so0r<so1r-so0d (=so1d), the sense amplifier unit 27i amplifies the potential difference between the potential so1r and the potential so0d (=so1d). As a result, the potential so0d (=so1d) becomes the ground potential VSS. Also, the potentials so1r and so0r become the power supply potential VDD.

Thereafter, the operation selection circuit 27j raises the potential of the signal saouten0 from the ground potential VSS to the power supply potential VDD from timing t86 to timing t87. At this time, since the potential so0d is the ground potential VSS, the potential of the output signal saout0 also remains at the ground potential VSS. During reading, the potential of the signal saouten1 is fixed to the ground potential VSS. Therefore, the potential of the output signal saout1 is also fixed at the ground potential VSS.

The data output circuit 27m outputs the output signal saout0 at this time as data DQ<0> (1-bit read data).
After that, from timing t88 to timing t89, the operation selection circuit 27j raises the potential of the signal salatb from the ground potential VSS to the power supply potential VDD, and lowers the potential of the signal salatt from the power supply potential VDD to the ground potential VSS. As a result, the sense amplifiers 27ia and 27ib stop functioning. Further, the operation selection circuit 27j lowers the potential of the signal saouten0 from the power supply potential VDD to the ground potential VSS.

Further, the operation selection circuit 27j raises the potential of the signal pret from the ground potential VSS to the power supply potential VDD and lowers the potential of the signal preb from the power supply potential VDD to the ground potential VSS from timing t89 to timing t90. As a result, the potentials so1r, so0r, so0d, and so1d return to the precharge potential VPR.

FIG. 17 is a timing chart showing an example of changes in the potential of each signal and each part when "1" is read.
Changes in each signal and the potential of each part from timing t100 to timing t101 are the same as when "0" is read.

Also, from timing t101 to timing t102, changes in the potential of each signal and each section are substantially the same as when "0" is read. However, the potential so0d (=so1d) of the output terminals of the sense amplifiers 27ia and 27ib is higher than the precharge potential VPR.

Changes in each signal and the potential of each part from timing t103 to timing t104 are the same as when "0" is read. Changes in each signal and the potential of each part from timing t104 to timing t105 are almost the same as when "0" is read. However, when "1" is read, since so0d (=so1d)-so0r>so1r-so0d (=so1d), the sense amplifier unit 27i amplifies the potential difference between the potential so0r and the potential so0d (=so1d). do. As a result, the potential so0d (=so1d) becomes the power supply potential VDD. Also, the potentials so1r and so0r become the ground potential VSS.

Thereafter, the operation selection circuit 27j raises the potential of the signal saouten0 from the ground potential VSS to the power supply potential VDD from timing t106 to timing t107. At this time, since the potential so0d (=so1d) is the power supply potential VDD, the potential of the output signal saout0 rises from the ground potential VSS to the power supply potential VDD.

The data output circuit 27m outputs the output signal saout0 at this time as data DQ<0> (1-bit read data).
After that, from timing t108 to timing t109, the operation selection circuit 27j raises the potential of the signal salatb from the ground potential VSS to the power supply potential VDD, and lowers the potential of the signal salatt from the power supply potential VDD to the ground potential VSS. As a result, the sense amplifiers 27ia and 27ib stop functioning. Further, the operation selection circuit 27j lowers the potential of the signal saouten0 from the power supply potential VDD to the ground potential VSS. As a result, the potential of the output signal saout0 also drops from the power supply potential VDD to the ground potential VSS.

The change in each signal and the potential of each part from timing t109 to timing t110 after that is the same as when "0" is read.
FIG. 18 is a timing chart showing an example of changes in the potential of each signal and each part during "0" write verify.

During "0" write verify, the potential of the signal ref0chgb is fixed at the power supply potential VDD, and the potential of the signal ref0chgt is fixed at the ground potential VSS. Therefore, the nMOS transistor 50a and the pMOS transistor 50b are turned on, and the nMOS transistor 50c and the pMOS transistor 50d are turned off.

The operation selection circuit 27j lowers the potentials of the signals twint, ref1chgb, and pret from the power supply potential VDD to the ground potential VSS from timing t120 to timing t121. Further, the operation selection circuit 27j raises the potentials of the signals twintb, ref1chgt, and preb from the ground potential VSS to the power supply potential VDD from timing t120 to timing t121.

As a result, the pMOS transistor 50e and the nMOS transistor 50f are turned on, and the pMOS transistors 50g and 51n and the nMOS transistors 50h and 51m are turned off.
Also, both the nMOS transistor 27i3a and the pMOS transistor 27i3b shown in FIG. 8 are turned off.

The operation selection circuit 27j lowers the potential of the signal transb from the power supply potential VDD to the ground potential VSS and raises the potential of the signal transt from the ground potential VSS to the power supply potential VDD from timing t121 to timing t122. This turns on the nMOS transistors 51b, 51c, 51f and 51g and the pMOS transistors 51a, 51d, 51e and 51h.

At this time, the potential so0r of the input terminal of the sense amplifier 27ia, which was the precharge potential VPR, drops to the reference potential V0ref, and the potential so1r of the input terminal of the sense amplifier 27ib, which was the precharge potential VPR, drops to the reference potential Vs0ref. . Also, the potentials so0d and so1d of the output terminals of the sense amplifiers 27ia and 27ib are equal to the data potential D<0>.

Further, the operation selection circuit 27j raises the potential of the signal transb from the ground potential VSS to the power supply potential VDD and lowers the potential of the signal transt from the power supply potential VDD to the ground potential VSS from the timing t123 to the timing t124. As a result, the nMOS transistors 51b, 51c, 51f and 51g and the pMOS transistors 51a, 51d, 51e and 51h are turned off.

Then, from timing t124 to timing t125, the operation selection circuit 27j lowers the potential of the signal salatb from the power supply potential VDD to the ground potential VSS, and raises the potential of the signal salatt from the ground potential VSS to the power supply potential VDD. This causes the sense amplifiers 27ia and 27ib to function.

At this time, the output terminals of the sense amplifiers 27ia and 27ib are electrically disconnected by turning off the nMOS transistor 51m and the pMOS transistor 51n, unlike during reading. That is, the nMOS transistor 51m and the pMOS transistor 51n function as switches. Thereby, each of sense amplifiers 27ia and 27ib operates independently. That is, the sense amplifier 27ia amplifies the potential difference between the potential so0d and the potential so0r (=reference potential V0ref), and the sense amplifier 27ib amplifies the potential difference between the potential so1d and the potential so1r (=reference potential Vs0ref).

When so0d<V0ref, the potential so0d becomes the ground potential VSS, and when so0d>V0ref, the potential so0d becomes the power supply potential VDD. In the example of FIG. 18, so0d>V0ref, and the potential so0d has changed to the power supply potential VDD. Further, when the potential so0d changes to the ground potential VSS, the potential so0r changes to the power supply potential VDD, and when the potential so0d changes to the power supply potential VDD, the potential so0r changes to the ground potential VSS.

When so1d<Vs0ref, the potential so1d becomes the ground potential VSS, and when so1d>Vs0ref, the potential so1d becomes the power supply potential VDD. In the example of FIG. 18, so1d<Vs0ref, and the potential so1d has changed to the ground potential VSS. Further, when the potential so1d changes to the ground potential VSS, the potential so1r changes to the power supply potential VDD, and when the potential so1d changes to the power supply potential VDD, the potential so1r changes to the ground potential VSS.

Thereafter, the operation selection circuit 27j raises the potentials of the signals saouten0 and saouten1 from the ground potential VSS to the power supply potential VDD from timing t126 to timing t127. At this time, when the potential so0d is the ground potential VSS, the potential of the output signal saout0 is also the ground potential VSS, and when the potential so0d is the power supply potential VDD, the potential of the output signal saout0 is also the power supply potential VDD. Further, when the potential so0d is the ground potential VSS, the potential of the output signal saout0 is also the ground potential VSS, and when the potential so0d is the power supply potential VDD, the potential of the output signal saout0 is also the power supply potential VDD.

At timing t127 during "0" write verify, if the potential of the output signal saout0 is the power supply potential VDD, the verify result determination circuit 27k determines that the write of "0" is not performed normally ("fail"). , the judgment result to that effect is output. In this case, the write control circuit 27g continues the control for writing "0".

However, at timing t127, when the potential of the output signal saout1 is the ground potential VSS, the verify result determination circuit 27k causes the write control circuit 27g to make the write strength weaker than when the potential of the output signal saout1 is the power supply potential VDD. Instruct that

The write control circuit 27g can weaken the write intensity by, for example, reducing the write voltage or shortening the application time of the write voltage.
On the other hand, when the potential of the output signal saout0 is the ground potential VSS at timing t127 during "0" write verify, the verify result determination circuit 27k determines that the write of "0" was performed normally ("pass"). and outputs the judgment result to that effect. In this case, the write control circuit 27g stops the source line driver 27d and the bit line driver 27e from generating the write voltage of "0".

FIG. 19 is a diagram showing an example of write intensity control at the time of "0" write verify.
When output signal saout0 is at L (Low) level (ground potential VSS in the example of FIG. 18), data potential D<0> is lower than reference potential V0ref. That is, "0" is normally written.

On the other hand, when output signal saout0 is at H (High) level (power supply potential VDD in the example of FIG. 18), data potential D<0> is higher than reference potential V0ref. In this case, "0" is not written normally. Therefore, the write operation is continued. However, the value of data potential D<0> varies. When the data potential D<0> is already in the vicinity of the reference potential V0ref, if writing is performed with the same write intensity as when the data potential D<0> is not in the vicinity of the reference potential V0ref, overwriting may occur. have a nature.

In the resistance change memory according to the third embodiment, when the data potential D<0> is higher than the reference potential V0ref and lower than the reference potential Vs0ref, the output signal saout0 is at H level and the output signal sout1 is at L level. become. At this time, the write control circuit 27g reduces the write intensity compared to when the data potential D<0> is higher than the reference potential Vs0ref (when both the output signals saout0 and saout1 are at H level), thereby preventing overwriting. Prevent.

Thereafter, in FIG. 18, the operation selection circuit 27j raises the potential of the signal salatb from the ground potential VSS to the power supply potential VDD and lowers the potential of the signal salatt from the power supply potential VDD to the ground potential VSS from timing t128 to timing t129. . As a result, the sense amplifiers 27ia and 27ib stop functioning. Further, the operation selection circuit 27j lowers the potentials of the signals saouten0 and saouten1 from the power supply potential VDD to the ground potential VSS. As a result, when the potentials of the output signals saout0 and saout1 have risen to the power supply potential VDD, they drop to the ground potential VSS.

Changes in the potential of each signal and each part from timing t129 to timing t130 after that are the same as during reading.
FIG. 20 is a timing chart showing an example of changes in the potential of each signal and each part during "1" write verify.

During "1" write verify, the potential of the signal ref1chgb is fixed at the power supply potential VDD, and the potential of the signal ref1chgt is fixed at the ground potential VSS. Therefore, the pMOS transistor 50g and the nMOS transistor 50h are turned on, and the pMOS transistor 50e and the nMOS transistor 50f are turned off.

The operation selection circuit 27j lowers the potentials of the signals twint, ref0chgb, and pret from the power supply potential VDD to the ground potential VSS from timing t140 to timing t141. Further, the operation selection circuit 27j raises the potentials of the signals twintb, ref0chgt, and preb from the ground potential VSS to the power supply potential VDD from timing t140 to timing t141.

As a result, the nMOS transistor 50c and the pMOS transistor 50d are turned on, and the nMOS transistors 50a and 51m and the pMOS transistors 50b and 51n are turned off.
Also, both the nMOS transistor 27i3a and the pMOS transistor 27i3b shown in FIG. 8 are turned off.

The operation selection circuit 27j lowers the potential of the signal transb from the power supply potential VDD to the ground potential VSS and raises the potential of the signal transt from the ground potential VSS to the power supply potential VDD from timing t141 to timing t142. This turns on the nMOS transistors 51b, 51c, 51f and 51g and the pMOS transistors 51a, 51d, 51e and 51h.

At this time, the potential so0r of the input terminal of the sense amplifier 27ia, which was the precharge potential VPR, rises to the reference potential Vs1ref, and the potential so1r of the input terminal of the sense amplifier 27ib, which was the precharge potential VPR, rises to the reference potential V1ref. . Also, the potentials so0d and so1d of the output terminals of the sense amplifiers 27ia and 27ib are equal to the data potential D<0>.

Changes in each signal and the potential of each part from timing t143 to timing t144 and from timing t144 to timing t145 are substantially the same as those at the time of "0" write verify.
However, the sense amplifier 27ia amplifies the potential difference between the potential so0d and the potential so0r (=reference potential Vs1ref), and the sense amplifier 27ib amplifies the potential difference between the potential so1d and the potential so1r (=reference potential V1ref).

When so0d<Vs1ref, the potential so0d becomes the ground potential VSS, and when so0d>Vs1ref, the potential so0d becomes the power supply potential VDD. In the example of FIG. 20, so0d>Vs1ref, and the potential so0d has changed to the power supply potential VDD. Further, when the potential so0d changes to the ground potential VSS, the potential so0r changes to the power supply potential VDD, and when the potential so0d changes to the power supply potential VDD, the potential so0r changes to the ground potential VSS.

When so1d<V1ref, the potential so1d becomes the ground potential VSS, and when so1d>V1ref, the potential so1d becomes the power supply potential VDD. In the example of FIG. 20, so1d<V1ref, and the potential so1d has changed to the ground potential VSS. Further, when the potential so1d changes to the ground potential VSS, the potential so1r changes to the power supply potential VDD, and when the potential so1d changes to the power supply potential VDD, the potential so1r changes to the ground potential VSS.

Changes in each signal and the potential of each part from timing t146 to timing t147 are the same as those at the time of "0" write verify.
When the potential of the output signal saout1 is the ground potential VSS at timing t147 during "1" write verify, the verify result determination circuit 27k determines that the write of "1" is not performed normally ("fail"). , the judgment result to that effect is output. In this case, the write control circuit 27g continues the control for writing "1".

However, at timing t147, when the potential of the output signal saout0 is the power supply potential VDD, the verify result determination circuit 27k instructs the write control circuit 27g to set the write strength to be higher than when the potential of the output signal saout0 is the ground potential VSS. Instruct to weaken.

On the other hand, when the potential of the output signal saout1 is the power supply potential VDD at timing t147 during "1" write verify, the verify result determination circuit 27k determines that the write of "1" was performed normally ("pass"). and outputs the judgment result to that effect. In this case, the write control circuit 27g stops the source line driver 27d and the bit line driver 27e from generating the write voltage of "0".

FIG. 21 is a diagram showing an example of write intensity control at the time of "1" write verify.
When output signal saout1 is at H level (power supply potential VDD in the example of FIG. 20), data potential D<0> is higher than reference potential V1ref. That is, "1" is normally written.

On the other hand, when output signal saout1 is at L level (ground potential VSS in the example of FIG. 20), data potential D<0> is lower than reference potential V1ref. In this case, "1" is not written normally. Therefore, the write operation is continued. However, the value of data potential D<0> varies. When the data potential D<0> is already near the reference potential V1ref, if writing is performed with the same write intensity as when the data potential D<0> is not near the reference potential V1ref, overwriting may occur. have a nature.

In the resistance change memory according to the third embodiment, when the data potential D<0> is lower than the reference potential V1ref and higher than the reference potential Vs1ref, the output signal saout is at H level and the output signal sout1 is at L level. become. At this time, the write control circuit 27g reduces the write intensity compared to when the data potential D<0> is lower than the reference potential Vs1ref (when both the output signals saout0 and saout1 are at the L level), thereby preventing overwriting. Prevent.

After that, the changes in each signal and the potential of each part from timing t148 to timing t149 in FIG. 20 are the same as those at the time of "0" write verify. Further, changes in the potential of each signal and each part from timing t149 to timing t150 are the same as during reading.

In the resistance change type memory of the third embodiment as described above, the supply potential switching circuit 50 changes the potentials supplied to the sense amplifiers 27ia and 27ib that implement the read of the twin sense amplifier method during read and during write verify. and are switched. Therefore, an effect similar to that of the resistance change type memory 20 of the second embodiment can be obtained. Furthermore, in the resistance change type memory of the third embodiment, the sense amplifier section 51 uses two reference potentials each during "0" write verify and "1" write verify. Reference potentials V0ref and Vs0ref are used during "0" write-verify, and reference potentials V1ref and Vs1ref are used during "1" write-verify. The sense amplifier unit 51 then outputs two output signals saout0 and saout1 based on the result of amplification of the data potential D<0> and these two reference potentials. This makes it possible to determine how far the write has progressed. Also, by adjusting the write strength based on the output signals saout0 and saout1, overwriting can be prevented, and writing can be performed under appropriate conditions.

Further, when the data potential D<0> is far from the target reference potential V0ref or the reference potential V1ref, the write intensity increases, so that the write time can be shortened.
While one aspect of the resistance-change memory and the control method of the resistance-change memory of the present invention has been described above based on the embodiments, these are only examples and are not limited to the above description.

10 resistance change type memory 11 sense amplifier section 11a, 11b sense amplifier 12 supply potential switching circuit 13 memory cell 13a memory element BL bit line sel signal Vdata data potential Vin1, Vin2 potential Vout output potential V0ref, V1ref reference potential

Claims (3)

a first reference potential supplied to a first input terminal of the first sense amplifier when a resistance change memory element is read; 1 reference potential and supplied to the second input terminal of the second sense amplifier, the one having a larger potential difference from the data potential based on the resistance value of the memory element. amplifies the potential difference, and in write-verifying the memory element, a first verify potential supplied to the first input terminal or a second verify potential supplied to the second input terminal, and the data potential; a sense amplifier section that amplifies the potential difference between
When the memory element is read, the first input terminal is supplied with the first reference potential, the second input terminal is supplied with the second reference potential, and when the memory element is write-verified, the a supply potential switching circuit for supplying the first verify potential to a first input terminal and supplying the second verify potential to the second input terminal ;
The sense amplifier section short-circuits the first output terminal of the first sense amplifier and the second output terminal of the second sense amplifier when reading the memory element, and short-circuits the second output terminal of the second sense amplifier when writing to the memory element. , a switch for electrically disconnecting the first output terminal and the second output terminal;
When the first reference potential is supplied to the first input terminal as the first verify potential, the supply potential switching circuit connects the second input terminal to the second reference potential as the first verify potential at the time of write-verifying the memory element. A third reference potential higher than the first reference potential and having a smaller potential difference from the first reference potential than the second reference potential is supplied as a verify potential of the second input terminal. When the second reference potential is supplied as the second verify potential, the first input terminal is supplied with the first reference potential and the first reference potential lower than the second reference potential as the first verify potential. supplying a fourth reference potential having a smaller potential difference from the second reference potential than the reference potential of No. 3;
The sense amplifier section generates a first signal based on an amplification result obtained by amplifying a potential difference between the first reference potential and the data potential, the third reference potential, and the data potential during write-verify for the memory element. output a second signal based on the result of amplification of the potential difference between the second reference potential and the data potential, or output a third signal based on the result of amplification of the potential difference between the second reference potential and the data potential and the third signal outputting a fourth signal based on an amplification result obtained by amplifying a potential difference between the reference potential of 4 and the data potential;
Resistive memory. 2. A write control circuit for changing write intensity for said memory element based on values of said first signal and said second signal or values of said third signal and said fourth signal. The resistance change type memory described in . A sense amplifier unit including a first sense amplifier and a second sense amplifier supplies a first reference signal to a first input terminal of the first sense amplifier when reading a resistance change memory element. A potential difference between a potential and a data potential based on a resistance value of the memory element, among a second reference potential higher than the first reference potential and supplied to a second input terminal of the second sense amplifier. amplifies the potential difference between the larger one and the first verify potential supplied to the first input terminal or the second verify potential supplied to the second input terminal at the time of write verify for the memory element. , amplifies the potential difference from the data potential,
A supply potential switching circuit supplies the first reference potential to the first input terminal, supplies the second reference potential to the second input terminal, and supplies the second reference potential to the memory element when the memory element is read. supplying the first verify potential to the first input terminal, supplying the second verify potential to the second input terminal, and
The sense amplifier section short-circuits the first output terminal of the first sense amplifier and the second output terminal of the second sense amplifier when reading the memory element, and short-circuits the second output terminal of the second sense amplifier when writing to the memory element. , a switch for electrically disconnecting the first output terminal and the second output terminal;
When the first reference potential is supplied to the first input terminal as the first verify potential, the supply potential switching circuit connects the second input terminal to the second reference potential as the first verify potential during write verification of the memory element. A third reference potential higher than the first reference potential and having a smaller potential difference from the first reference potential than the second reference potential is supplied as a verify potential of the third reference potential to the second input terminal. When the second reference potential is supplied as the second verify potential, the first input terminal is supplied with the first reference potential and the first reference potential lower than the second reference potential as the first verify potential. supplying a fourth reference potential having a smaller potential difference from the second reference potential than the reference potential of No. 3;
The sense amplifier section generates a first signal based on an amplification result obtained by amplifying a potential difference between the first reference potential and the data potential, the third reference potential, and the data potential during write-verify for the memory element. or output a second signal based on the result of amplification of the potential difference between the second reference potential and the data potential, or output a third signal based on the result of amplification of the potential difference between the second reference potential and the data potential and the third signal outputting a fourth signal based on an amplification result obtained by amplifying a potential difference between the reference potential of 4 and the data potential;
Control method of resistance change type memory.

Images