KR20150026711A

KR20150026711A - Dead zone free voltage generation circuit

Info

Publication number: KR20150026711A
Application number: KR20130150838A
Authority: KR
Inventors: 서영훈; 이규찬; 조승현
Original assignee: 삼성전자주식회사
Priority date: 2013-08-28
Filing date: 2013-12-05
Publication date: 2015-03-11

Abstract

The present invention discloses a voltage generating circuit that generates a dead-zone-free bit line pre-charge voltage. The voltage generation circuit generates a bit line precharge voltage used to precharge the bit line and the complementary bit line. The voltage generating circuit generates a bit line precharge voltage by using an amplifier for comparing a reference voltage and a bit line precharge voltage according to an offset signal and a driver including pull-up and pull-down transistors. The voltage generating circuit measures the current at the output node at which the bit line precharge voltage is generated, and determines whether or not the current of the output node is below the reference current. The offset signal is changed until the pull-up transistor current of the output node becomes less than or equal to the reference current and until the pull-down transistor current of the output node becomes less than or equal to the reference current. A bit line free charge voltage is generated with the reference voltage as a target according to the changed offset signal.

Description

[0001] The present invention relates to a dead zone free voltage generation circuit,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to generating a bit line precharge voltage using a dead zone precharge voltage generating circuit.

Semiconductor memory devices are typically used to store data. BACKGROUND ART Dynamic random access memory (DRAM) is a volatile memory device, which is composed of memory cells. A memory cell of a DRAM is composed of one transistor and one capacitor, and can store data as a charge in the capacitor in the form of "1" or "0 ". Since the charge stored in the capacitor may be lost over time, the DRAM periodically needs a refresh operation to read, sense, and rewrite the data to retain the stored data.

The memory cells of the DRAM are connected to the word lines and the bit lines. When the cell transistors are turned on in response to the word line enable signals, the data stored in the cell capacitors can be output to the bit lines. When data stored in the cell capacitor is output to the bit line, charge sharing occurs between the cell capacitor and the capacitor held by the bit line. In order to sense the data output to the bit line, the bit line is precharged to the bit line precharge voltage in advance. However, if the bit line precharge voltage is unstable, a sensing error may occur when sensing the data stored in the cell capacitor.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a voltage generating circuit that generates a stable bit line precharge voltage.

According to an aspect of the present invention, there is provided a voltage generator circuit comprising: a current comparator for comparing a current of an output node where a bit line precharge voltage is generated with a reference current; And a bit line precharge voltage generating unit for generating a bit line precharge voltage with a reference voltage as a target in response to an offset signal when the bit line precharge voltage is equal to or less than the threshold voltage.

According to embodiments of the present invention, the voltage generating circuit may further include a reference voltage providing unit having resistors connected between the first power supply voltage and the ground voltage, and providing a reference voltage at a node between the resistors.

According to embodiments of the present invention, a bit line pre-charge voltage generator includes an amplifier for providing first and second control signals based on a reference voltage and a bit line pre-charge voltage, And driving the output node to the bit line precharge voltage in response to the bit line precharge voltage.

According to embodiments of the present invention, the amplifier amplifies the difference between the reference voltage and the bit line precharge voltage, which is connected between the second power supply voltage and the ground voltage and is received at the input terminals according to the first offset signal, And a second amplifying unit connected between the second power supply voltage and the ground voltage and amplifying the difference between the reference voltage and the bit line precharge voltage received at the input terminals according to the second offset signal, And a second amplifying unit for outputting a control signal.

According to embodiments of the present invention, the first amplification unit includes a current mirror, first and second inputs, first and second offset controls, and a current source. The current mirror may be designed to include first and second transistors whose second power supply voltage is connected to the source, and the second transistor to the input side. The first input unit includes a plurality of transistors connected in parallel to each other with a reference voltage applied to the gate thereof. The drain of at least one of the plurality of transistors may be connected to the drain of the first transistor and output as a first control signal. The second input unit includes a plurality of transistors connected in parallel to each other, and a drain of at least one of the plurality of transistors may be connected to a drain of the second transistor. The first offset control part may include a plurality of transistors connected in parallel to which the drain of the first transistor is connected to the drain, the drain of the transistors of the first input part is correspondingly connected to the source, and the first offset signal is connected to the gate. have. The second offset control unit includes a plurality of transistors connected in parallel to which a drain of the second transistor is connected to a drain and a drain of the transistors of the second input unit is correspondingly connected to a source, The gate may be connected to the second power supply voltage. The current source may be electrically connected between the source of the transistors of the first and second inputs and the ground voltage.

According to embodiments of the present invention, the first amplifier may further include a test controller for disabling the operation of the first amplifier. The test control may include a third transistor having a first test signal coupled to the gate and connected in parallel to the first transistor and a fourth transistor having a first test signal coupled to the gate and coupled between the current source and the ground voltage have.

According to embodiments of the present invention, the second amplification unit may include a current mirror, first and second inputs, first and second offset controls, and a current source. The current mirror may be designed to include first and second transistors whose ground voltage is connected to the source and the second transistor to the input side. The first input unit includes a plurality of transistors connected in parallel to each other, and the drain of at least one of the plurality of transistors may be connected to the drain of the first transistor and output as a second control signal. The second input unit may include a plurality of transistors connected in parallel to which a bit line precharge voltage is connected to the gate, and a drain of at least one of the plurality of transistors may be connected to a drain of the second transistor. The first offset control part may include a plurality of transistors connected in parallel to which the drain of the first transistor is connected to the drain, the drain of the transistors of the first input part is correspondingly connected to the source, and the second offset signal is connected to the gate. have. The second offset control unit includes a plurality of transistors connected in parallel to which a drain of the second transistor is connected to a drain and a drain of the transistors of the second input unit is correspondingly connected to a source, The gate may be connected to ground. The current source may be electrically connected between the second power supply voltage and the source of the transistors of the first and second inputs.

According to embodiments of the present invention, the second amplifier may further include a test controller for disabling the operation of the second amplifier. The test control unit includes a third transistor having a second test signal connected to the gate and connected in parallel to the first transistor, and a fourth transistor having a second test signal connected to the gate and connected between the second power supply voltage and the current source can do.

According to embodiments of the present invention, the driver includes a first transistor connected between the second power supply voltage and the output node and pulling up the output node in response to the first control signal, and a second transistor coupled between the output node and the ground voltage And a second transistor for pulling-down driving the output node in response to the second control signal.

According to embodiments of the present invention, in response to a first control signal generated when a reference voltage is applied to the input terminals of the first amplifier, the current comparator compares a current flowing in the first transistor with a reference current, It is possible to change the first offset signals until the current flowing in one transistor becomes less than or equal to the reference current.

According to embodiments of the present invention, in response to a second control signal generated when a reference voltage is applied to the input terminals of the second amplifier, the current comparator compares a current flowing in the second transistor with a reference current, It is possible to change the second offset signals until the current flowing in the two transistors becomes less than or equal to the reference current.

According to another aspect of the present invention, there is provided a bit line pre-charge voltage generating method including: an amplifying unit for comparing a reference voltage with a bit line pre-charge voltage; and a bit line pre- Measuring a current at an output node where a bit line free charge voltage is generated, the method comprising the steps of: determining whether the current of the output node is less than or equal to a reference current; And generating a bit line precharge voltage with the reference voltage as a target according to the changed offset signal.

According to embodiments of the present invention, the step of changing the offset signal of the amplification section may change the offset signal until the current of the pull-up transistor is below the reference current.

According to embodiments of the present invention, the step of changing the offset signal of the amplification section may change the offset signal until the current of the pull-down transistor is below the reference current.

According to embodiments of the present invention, a bit line precharge voltage generation method may generate a bit line precharge voltage without a dead zone.

The above-described voltage generating circuit of the present invention generates a dead-zone free bit line charge voltage so that the bit line precharge voltage is generated without dispersion. Thereby providing a stable bit line pre-charge voltage level in sensing data "0" or "1 ".

1 is a view for explaining a dead zone pre-voltage generating circuit according to an embodiment of the present invention.
FIG. 2 is a view for explaining distribution of a bit line precharge voltage when a conventional bit line precharge voltage has a dead zone. FIG.
3 is a view for explaining the configuration of the first amplifier of FIG. 1 according to the embodiment of the present invention.
4 is a diagram illustrating a configuration of a second amplifier of FIG. 1 according to an embodiment of the present invention.
5 is a first example of the current comparator of FIG. 1 according to an embodiment of the present invention.
6 is a second example of the current comparator of FIG. 1 according to the embodiment of the present invention.
7 is a third example of the current comparator of FIG. 1 according to the embodiment of the present invention.
8 is a fourth example of the current comparator of FIG. 1 according to the embodiment of the present invention.
9 is a first example of a semiconductor memory device incorporating a voltage generating circuit according to an embodiment of the present invention.
10 is a flowchart illustrating a first offset signal trimming method according to an embodiment of the present invention.
11 is a flowchart illustrating a second offset signal trimming method according to an embodiment of the present invention.
12 and 13 are graphs for explaining the operation of the voltage generating circuit according to the embodiment of the present invention.
14 is a second example of a semiconductor memory device incorporating a voltage generating circuit according to an embodiment of the present invention.
15 is a diagram for explaining the configuration of the memory core of FIG. 14 according to the embodiment of the present invention.
16A and 16B are diagrams illustrating voltage waveforms of the bit line and the complementary bit line when sensing data stored in the cell capacitor of FIG.
17 and 18 are diagrams illustrating a memory module including a memory chip incorporating a voltage generating circuit according to embodiments of the present invention.
19 is a block diagram showing an example of application of a memory chip incorporating a voltage generation circuit according to the embodiments of the present invention to a mobile system.
20 is a block diagram showing an example of application of a memory module equipped with a memory chip incorporating a voltage generating circuit according to the embodiments of the present invention to a computing system.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

1 is a view for explaining a dead zone pre-voltage generating circuit according to an embodiment of the present invention. The dead zone pre-voltage generating circuit of Fig. 1 can be used to generate the bit line pre-charge voltage VBL.

Referring to FIG. 1, the dead zone pre-voltage generating circuit 100 includes a reference voltage providing unit 110, a bit line pre-charge voltage generating unit 120, and a current comparing unit 130.

The reference voltage providing unit 110 may include a first resistor R1 and a second resistor R2 connected in series between the first power source voltage VREF and the ground voltage VSS. The reference voltage providing unit 110 provides the reference voltage VREF / 2 at the first node NA between the first resistor R1 and the second resistor R2 as a voltage divider.

The bit line pre-charge voltage generating unit 120 includes an amplifying unit 122 and a driving unit 124. The bit line pre-charge voltage generating unit 120 may further include first and second switches 126 and 128. The first switch 126 connects the reference voltage VREF / 2 to the second node NB and the second switch 128 connects the bit line precharge voltage VBL to the second node NB. .

The amplifying unit 122 provides the first control signal CP and the second control signal CN based on the reference voltage VREF / 2 and the voltage of the second node NB. The amplifying unit 122 includes a first amplifier 300 and a second amplifier 400 of a differential type. The first amplifier 300 amplifies the difference between the reference voltage VREF / 2 and the voltage VFB at the second node NB according to the first offset signal OSP <0: 3> (CP). The second amplifier 400 amplifies the difference between the reference voltage VREF / 2 and the second node voltage VFB according to the second offset signal OSN <0: 3> and provides the second control signal CN do. The first and second amplifiers 300 and 400 are connected between the second power supply voltage VDD and the ground voltage VSS. The second power source voltage VDD may be set to the same voltage level as the first power source voltage VREF or higher than the first power source voltage VREF. According to the embodiment, the first power supply voltage VREF may be generated by deriving from the second power supply voltage VDD.

The driving unit 124 drives the third node NC to the bit line precharge voltage VBL in response to the first and second control signals CP and CN. The driving unit 124 includes a first transistor PD connected between the second power supply voltage VDD and a third node NC and having a gate receiving a first control signal CP, And a second transistor ND connected between the ground voltage VSS and a gate thereof receiving the second control signal CN. The first transistor PD may be a PMOS transistor, and the second transistor ND may be an NMOS transistor. The first transistor PD drives the third node NC in response to the first control signal CP and the second transistor ND drives the third node NC in response to the second control signal CN. (NC).

The driving unit 124 is a push-pull output circuit composed of the first and second transistors PD and ND, and is designed not to generate a through current. The driving unit 124 can implement the dead zone free (i.e., dead zone free) (see FIG. 13A). In general, the through current in the push-pull output circuit was negligible with respect to the conventional operating current of several mA orders. However, in order to reduce the current consumption, the through current which has been neglected in the prior art becomes a problem. A circuit approach to suppressing the through current is being developed in accordance with DRAM standby current reduction requirements. The first transistor PD and the second transistor ND can be prevented from being turned on at the same time when the bit line precharge voltage VBL is placed in the dead zone in order to suppress the penetration current. However, since the bit line precharge voltage VBL is in a metastable state, the bit line precharge voltage VBL has a scattering, as shown in FIG.

When the bit line pre-charge voltage VBL having such a scatter is applied to the bit line, sensing of data "0" or data "1 " decreases either one of the charge shimming and the operation of the sense amplifier deteriorates . Accordingly, according to the embodiment of the present invention, the bit line precharge voltage supplied from the third node (NC) using the current comparator that compares the pull-up current and pull-down current of the driver 124 with the reference current, So that the voltage VBL is generated without a dead zone. The bit line precharge voltage VBL generated without a dead zone can set the reference voltage VREF / 2 as a target.

1, the first switch 126 is turned on when comparing the pull-up current and pull-down current of the driver 124 in the test with the reference current, and the bit line pre- And is turned off in the normal operation for generating the precharge voltage VBL. The second switch 128 is turned on in the normal operation and turned off in the test operation.

The current comparator 130 compares the current of the third node NC at which the bit line precharge voltage VBL is generated with the reference current to provide the comparison signal COMP. The current comparing unit 130 will be described later with reference to Figs.

3 is a view for explaining the configuration of the first amplifier of FIG. 1 according to the embodiment of the present invention.

Referring to FIG. 3, the first amplifier 300 includes first and second PMOS transistors 301 and 302, first and second input units 310 and 320, first and second offset control units 330 and 330, , 340, and a current source 305. The first amplifier 300 amplifies the difference between the reference voltage VREF / 2 and the second node voltage VFB received at the input terminals according to the first offset signal OSP <0: 3> And outputs a signal CP.

The first amplifier 300 may further include a test controller 350. The test control unit 350 responds to the first test signal ON at the time of testing and operates in conjunction with the current comparing unit. The test control unit 350 includes a PMOS transistor 351 connected between the second power supply voltage VDD and the first control signal CP and an NMOS transistor 352 connected between the current source 305 and the ground voltage VSS. . The gates of the PMOS transistor 351 and the NMOS transistor 352 are connected to the first test signal ON.

The first test signal ON is provided at a logic low and the PMOS transistor 351 is turned on so that the first control signal CP is set to logic high and the NMOS transistor 352 is turned off, The operation of the amplifier 300 is disabled. The NMOS transistor 352 is turned on and the current source 305 is connected to the ground voltage VSS so that the operation of the first amplifier 300 is turned on. Lt; / RTI >

The first and second PMOS transistors 301 and 302 constitute a current mirror with the second PMOS transistor 302 on the input side. The sources of the first and second PMOS transistors 301 and 302 are connected to the second power supply voltage VDD. The gate of the first PMOS transistor 301 is connected to the gate and the drain of the second PMOS transistor 302.

The first and second input units 310 and 320 form a differential form and input a reference voltage VREF / 2 and a second node voltage VFB for comparison.

The first input unit 310 includes a plurality of NMOS transistors 311, 312, 313, 314, and 315 connected in parallel. The gates of the 311-315 NMOS transistors are connected to the reference voltage VREF / 2 and the source is electrically connected to the ground voltage VSS through the current source 305 and the 352 NMOS transistor. The drain of the 311 NMOS transistor is connected to the drain of the first PMOS transistor 301 and is output as the first control signal CP. The size of each of the 311, 312, 313, 314, and 315 NMOS transistors may be designed to have a ratio of 20: 8: 4: 2: 1, for example.

The second input unit 320 includes a plurality of NMOS transistors 321, 322, 323, 324, and 325 connected in parallel. The gates of the 321-325 NMOS transistors are connected to the second node voltage VFB and the source is electrically connected to the ground voltage VSS through the current source 305 and the 352 NMOS transistor. The drain of the 321 NMOS transistor is connected to the gate and drain of the second PMOS transistor 302. Each of the 321, 322, 323, 324 and 325 NMOS transistors corresponds to each of the 311, 312, 313, 314 and 315 NMOS transistors of the first input 310 and has a size of, for example, 20: 8: 4: 2: 1 Ratio. &Lt; / RTI >

The first offset controller 330 includes a plurality of NMOS transistors 332, 333, 334, and 335 connected in parallel. The drains of the NMOS transistors 332 and 335 are connected to a first control signal CP connected to the drain of the first PMOS transistor 301. The gates of the NMOS transistors 332, 333, 334 and 335 are correspondingly connected to the first offset signals OSP <0: 3>. The sources of the NMOS transistors 332, 333, 334 and 335 are correspondingly connected to the drains of the 312, 313, 314 and 315 NMOS transistors of the first input 310. The size of each of the 332, 333, 334, and 335 NMOS transistors may be designed to be equal to the size of the corresponding 312, 313, 314, and 315 NMOS transistors. For example 8: 4: 2: 1.

The second offset controller 340 includes a plurality of NMOS transistors 342, 343, 344, and 345 connected in parallel. The drains of the 342-345 NMOS transistors are connected to the drains and gates of the second PMOS transistor 302. The gates of the 342 NMOS transistors are connected to the second power supply voltage VDD and the gates of the 343, 344 and 345 NMOS transistors are connected to the ground voltage VSS. The sources of each of the 342, 343, 344 and 345 NMOS transistors are correspondingly connected to the drains of the 322, 323, 324 and 325 NMOS transistors of the second input 320. The size of each of the 342, 343, 344, and 345 NMOS transistors may be designed to be equal to the size of the corresponding 322, 323, 324, and 325 NMOS transistors. For example 8: 4: 2: 1.

The first amplifier 300 includes a first input unit 310 receiving a reference voltage VREF / 2 and a second input unit 320 receiving a configuration of the first offset control unit 330 and a second node voltage VFB, And the second offset controller 340 are configured symmetrically with respect to each other. This can improve the sensing sensitivity by preventing the influence of the impedance mismatch in amplifying the difference between the reference voltage VREF / 2 and the second node voltage VFB.

4 is a diagram illustrating a configuration of a second amplifier of FIG. 1 according to an embodiment of the present invention.

Referring to FIG. 4, the second amplifier 400 includes first and second NMOS transistors 401 and 402, first and second input units 410 and 420, first and second offset control units 430 and 430, , 440, and a current source 405. The second amplifier 400 amplifies the difference between the reference voltage VREF / 2 and the second node voltage VFB received at the input terminals according to the second offset signal OSN <0: 3> And outputs a signal CN.

The second amplifier 400 may further include a test controller 450. The test controller 450 responds to the second test signal (ONB) at the time of testing and operates in conjunction with the current comparator. The test control unit 450 includes an NMOS transistor 451 connected between the second control signal CN and the ground voltage VSS and a PMOS transistor 452 connected between the second power supply voltage VDD and the current source 405. [ . The gates of the NMOS transistor 451 and the PMOS transistor 452 are connected to the second test signal ONB.

The second test signal ONB is provided with a logic high and the NMOS transistor 451 is turned on and the second control signal CN is set to a logic low and the PMOS transistor 452 is turned off, The operation of the amplifier 400 is disabled. The second test signal ONB is provided at a logic low and the PMOS transistor 452 is turned on and the current source 405 is connected to the second power supply voltage VDD to operate the second amplifier 400 Is enabled.

The first and second NMOS transistors 401 and 402 constitute a current mirror having the second NMOS transistor 402 as an input side. The sources of the first and second NMOS transistors 401 and 402 are connected to the ground voltage VSS. The gate of the first NMOS transistor 401 is connected to the gate and the drain of the second NMOS transistor 402.

The first and second input units 410 and 420 form a differential form and input and compare the reference voltage VREF / 2 and the second node voltage VFB.

The first input unit 410 includes a plurality of PMOS transistors 411, 412, 413, 414, and 415 connected in parallel. The gates of the 411-415 PMOS transistors are connected to the reference voltage VREF / 2 and the source is electrically connected to the second power supply voltage VDD through the current source 405 and the 452 PMOS transistor. The drain of the 411 PMOS transistor is connected to the drain of the first PMOS transistor 401 and is output as the second control signal CN. The size of each of the 411, 412, 413, 414, and 415 PMOS transistors may be designed to have a ratio of 20: 8: 4: 2: 1, for example.

The second input unit 420 includes a plurality of PMOS transistors 421, 422, 423, 424, and 425 connected in parallel. The gates of the 421-425 PMOS transistors are connected to the second node voltage VFB and the source is electrically coupled to the second supply voltage VDD through the current source 405 and the 452 PMOS transistor. The drain of the 421 PMOS transistor is connected to the gate and the drain of the second PMOS transistor 402. Each of the 421, 422, 423, 424 and 425 PMOS transistors corresponds to each of the 411, 412, 413, 414 and 415 NMOS transistors of the first input 410 and has a size of, for example, 20: 8: 4: 2: 1 Ratio. &Lt; / RTI >

The first offset controller 430 includes a plurality of PMOS transistors 432, 433, 434, and 435 connected in parallel. The drains of the PMOS transistors 432-435 are coupled to a second control signal CN coupled to the drain of the first NMOS transistor 401. [ The gates of the PMOS transistors 432, 433, 434 and 435 are correspondingly connected to the second offset signals OSN <0: 3>. The sources of the 432, 433, 434 and 435 PMOS transistors are correspondingly connected to the drains of the 412, 413, 414 and 415 PMOS transistors of the first input 410. The size of each of the 432, 433, 434, and 435 PMOS transistors may be designed to be equal to the size of the corresponding 412, 413, 414, and 415 PMOS transistors. For example 8: 4: 2: 1.

The second offset controller 440 includes a plurality of PMOS transistors 442, 443, 444, and 445 connected in parallel. The drains of the 442-445 PMOS transistors are connected to the drains and gates of the second NMOS transistor 402. The gates of the 442 PMOS transistors are connected to the ground voltage VSS and the gates of the 443, 444 and 445 PMOS transistors are connected to the second power supply voltage VDD. The sources of the 442, 443, 444 and 445 PMOS transistors are correspondingly connected to the drains of the 422, 423, 424 and 425 PMOS transistors of the second input 420. The size of each of the 442, 443, 444, 445 PMOS transistors may be designed to be equal to the size of the corresponding 422, 423, 424, 425 PMOS transistors. For example 8: 4: 2: 1.

The second amplifier 400 includes a first input unit 410 receiving the reference voltage VREF / 2 and a second input unit 420 receiving the configuration of the first offset control unit 430 and the second node voltage VFB. And the second offset controller 440 are configured symmetrically with respect to each other. This can improve the sensing sensitivity by preventing the influence of the impedance mismatch in amplifying the difference between the reference voltage VREF / 2 and the second node voltage VFB.

The bit line precharge voltage generating circuit 100 of FIG. 1, in conjunction with the first and second amplifiers 300 and 400 of FIGS. 3 and 4, compares the comparison signal COMP The first and second offset signals OSP <0: 3> and OSN <0: 3> may be changed in response to the first and second offset signals OSP <0: 3> and OSN <0: 3>. The first and second offset signals OSP <0: 3> and OSN <0: 3> become the reference current when the current of the third node NC at which the bit line precharge voltage VBL is generated becomes the reference current or less Can be set. In the normal operation, the first and second amplifiers 300 and 400 output the reference voltage VREF / 2 according to the set first and second offset signals OSP <0: 3>, OSN <0: 3> And the bit line precharge voltage VBL to generate the first and second control signals CP and CN. The driving unit 124 may drive the third node NC to the bit line precharge voltage VBL in response to the first and second control signals CP and CN. The bit line precharge voltage generating circuit 100 can generate the bit line precharge voltage VBL with the reference voltage VREF / 2 as a target.

5 is a first example of the current comparator of FIG. 1 according to an embodiment of the present invention.

Referring to FIG. 5, the current comparator 130a compares the first transistor current i _PD of the driver during the test with the reference current i _REF and generates a comparison signal COMP. The first transistor current i _PD of the driving unit is a current flowing in the first transistor PD when the first switch 126 is on and the second switch 128 is off. The first and second input terminals of the first amplifier 300 of the driving unit are short-circuited by the ON-state first switch 126 to connect the reference voltage VREF / 2. The first control signal CP, which is the output terminal of the first amplifier 300, is provided to the gate of the first transistor PD. In the first transistor PD, the first transistor current i _PD flows in response to the first control signal CP. At this time, the second control signal CN, which is the output terminal of the second amplifier 400, is set to a logic low and the second transistor ND is turned off.

The current comparator 130a includes a test switch 510, first through third current mirrors 520, 530 and 540, and a current source 550. The test switch 510 is turned on to connect the third node NC of the driving unit to the current comparator 130a during the test, and is turned off in the normal operation. The test switch 510 is connected between the third node NC and the first current mirror 520.

The first current mirror 520 includes first and second NMOS transistors 521 and 522 and constitutes a current mirror having the first NMOS transistor 521 as an input side. The drain of the first NMOS transistor 521 is connected to the test switch 510. The gate of the second NMOS transistor 522 is connected to the gate and the drain of the first NMOS transistor 521. The sources of the first and second NMOS transistors 521 and 522 are connected to the ground voltage VSS.

The second current mirror 530 includes first and second PMOS transistors 531 and 532 and forms a current mirror with the first PMOS transistor 531 as the input side. The sources of the first and second PMOS transistors 531 and 532 are connected to the second power supply voltage VDD. The gate of the second PMOS transistor 532 is connected to the gate and drain of the first PMOS transistor 531 and is connected to the drain of the second NMOS transistor 522 of the first current mirror 520.

The third current mirror 540 includes third and fourth NMOS transistors 541 and 542 and constitutes a current mirror having the third NMOS transistor 541 as an input side. The drain of the third NMOS transistor 541 is connected to the current source 550. The gate of the fourth NMOS transistor 542 is connected to the gate and the drain of the third NMOS transistor 541. The sources of the third and fourth NMOS transistors 541 and 542 are connected to the ground voltage VSS. The drain of the fourth NMOS transistor 542 is connected to the drain of the second PMOS transistor 532 of the second current mirror 530 and is output as a comparison signal COMP.

The current source 550 is connected between the second power supply voltage VDD and the third NMOS transistor 541 of the third current mirror and provides the reference current i _REF . The reference current i _REF may be set at various current levels during testing.

In the current comparator 130a, the test switch 510 is turned on in the test, and the first transistor current i _PD of the driver is supplied to the first current mirror 520. The amount of current of the first current mirror 520 and the second current mirror 530 is determined along the first transistor current i _PD . The reference current i _{REF is} provided to the third current mirror 540. The reference current i _REF and the first transistor current i _PD are compared at the node between the second current mirror 530 and the third current mirror 540 and output as the comparison signal COMP. If the first transistor current i _PD is greater than the reference current i _REF , the comparison signal COMP is generated at a logic high and if the first transistor current i _PD is less than the reference current i _REF , COMP) is generated as a logic low.

To: (OSP <3 0>) if the comparison signal (COMP) is a logic high, the first transistor current (i _PD), the first offset signal of the first amplifier 300 to be greater than the reference current (i _REF) Can be adjusted. For example, if the first offset signal OSP <0: 3> is initially set to "1111", the first offset signal OSP <0: 3>Quot; 0111 ", so that the voltage level of the first control signal CP can be adjusted to be higher. Thus, the current i _PD of the first transistor PD responsive to the increased voltage level of the first control signal CP is reduced.

If the first transistor current i _PD is still greater than the reference current i _REF and the comparison signal COMP is logic high then the first offset signal OSP < 0 : 3 >) to "0110 ", so that the voltage level of the first control signal CP can be adjusted to be higher. That is, the first offset signal OSP <0: 3> is changed and the voltage level of the first control signal CP is raised until the first transistor current i _PD becomes equal to or smaller than the reference current i _REF The operation of comparing the first transistor current (i _PD ) with the reference current (i _REF ) can be repeatedly monitored. The first offset signal OSP <0: 3> when the first transistor current i _PD becomes equal to or smaller than the reference current i _REF is supplied to the first amplifier 300 in the normal operation.

6 is a second example of the current comparator of FIG. 1 according to the embodiment of the present invention.

Referring to FIG. 6, the current comparator 130b compares the first transistor current (i _PD ) of the driver during the test with the reference current (i _REF ) and generates a comparison signal COMP. The first transistor current i _PD of the driving unit is a current flowing in the first transistor PD when the first switch 126 is on and the second switch 128 is off. The first and second input terminals of the first amplifier 300 of the driving unit are short-circuited by the ON-state first switch 126 to connect the reference voltage VREF / 2. The first control signal CP, which is the output terminal of the first amplifier 300, is provided to the gate of the first transistor PD. In the first transistor PD, the first transistor current i _PD flows in response to the first control signal CP. At this time, the second control signal CN, which is the output terminal of the second amplifier 400, is set to a logic low and the second transistor ND is turned off.

The current comparator 130b includes a test switch 610, a current source 620, and a buffer unit 630. The test switch 610 is turned on to connect the third node NC of the driving unit during the test with the current comparator 130a, and is turned off in the normal operation. The test switch 510 is connected between the third node NC and the current source 620. The current source 620 is connected between the test switch 610 and the ground voltage VSS and provides a reference current i _REF . The reference current i _REF may be set at various current levels during testing. The buffer unit 630 is connected to a connection node between the test switch 610 and the current source 620 and outputs a comparison signal COMP.

In the current comparator 130b, the test switch 610 is turned on and the first transistor current i _PD of the driver is supplied to the current comparator 130b. The reference current i _REF and the first transistor current i _PD are compared at the node between the test switch 610 and the current source 620. If the first transistor current i _PD is greater than the reference current i _REF , the comparison signal COMP, which is the output of the buffer unit 630, is generated at a logic high and the first transistor current i _PD is the reference current i _REF ), the comparison signal COMP is generated at a logic low.

If the comparison signal COMP is logic high, the operation of changing the first offset signal OSP < 0: 3 > and comparing the first transistor current i _PD and the reference current i _{REF is} referred to as a first transistor current i _PD is less than or equal to the reference current i _REF . The first offset signal OSP <0: 3> when the first transistor current i _PD becomes equal to or smaller than the reference current i _REF is supplied to the first amplifier 300 in the normal operation.

7 is a third example of the current comparator of FIG. 1 according to the embodiment of the present invention.

Referring to FIG. 7, the current comparator 130c compares the second transistor current (i _ND ) of the driver during the test with the reference current (i _REF ) and generates a comparison signal COMP. The second transistor current (i _ND ) of the driving unit is a current flowing to the second transistor (ND) when the first switch (126) is in an on state and the second switch (128) is in an off state. The first and second input terminals of the second amplifier 400 of the driving unit are short-circuited by the ON-state first switch 126 and the reference voltage VREF / 2 is connected. The second control signal CN, which is the output terminal of the second amplifier 400, is provided to the gate of the second transistor ND. The second transistor current (i _ND ) flows to the second transistor ( _ND ) in response to the second control signal (CN). At this time, the first control signal CP, which is the output terminal of the first amplifier 300, is set to logic high so that the first transistor PD is turned off.

The current comparator 130c includes a test switch 710, first to third current mirrors 720, 730, and 740, and a current source 750. The test switch 710 is turned on to connect the third node NC of the driver during the test with the current comparator 130c, and is turned off in the normal operation. The test switch 710 is connected between the third node NC and the first current mirror 720.

The first current mirror 720 includes first and second PMOS transistors 721 and 722 and constitutes a current mirror with the first PMOS transistor 721 on the input side. The drain of the first PMOS transistor 721 is connected to the test switch 710. The gate of the second PMOS transistor 722 is connected to the gate and the drain of the first PMOS transistor 721. The sources of the first and second PMOS transistors 721 and 722 are connected to the second power supply voltage VDD.

The second current mirror 730 includes first and second NMOS transistors 731 and 732 and constitutes a current mirror having the first NMOS transistor 731 as its input side. The sources of the first and second NMOS transistors 731 and 732 are connected to the ground voltage VSS. The gate of the second NMOS transistor 732 is connected to the gate and the drain of the first NMOS transistor 731 and is connected to the drain of the second PMOS transistor 722 of the first current mirror 720.

The third current mirror 740 comprises third and fourth PMOS transistors 741 and 742 and constitutes a current mirror with the third PMOS transistor 741 on the input side. The drain of the third PMOS transistor 741 is connected to the current source 750. The gate of the fourth PMOS transistor 742 is connected to the gate and the drain of the third PMOS transistor 741. The sources of the third and fourth PMOS transistors 741 and 742 are connected to the second power supply voltage VDD. The drain of the fourth PMOS transistor 742 is connected to the drain of the second NMOS transistor 732 of the second current mirror 730 and is output as the comparison signal COMP.

The current source 750 is connected between the third PMOS transistor 741 of the third current mirror 740 and the ground voltage VSS and provides a reference current i _REF . The reference current i _REF may be set at various current levels during testing.

The test switch 710 is turned on in the current comparator 130c and the amount of current flowing through the first current mirror 720 and the second current mirror 730 along the second transistor current i _ND of the driver is determined do. The amount of current of the third current mirror 740 is determined according to the reference current i _REF . The reference current i _REF and the second transistor current i _ND are compared at the node between the second current mirror 730 and the third current mirror 740 and output as the comparison signal COMP. If the second transistor current i _ND is greater than the reference current i _REF , the comparison signal COMP is generated at a logic low and if the second transistor current i _ND is less than the reference current i _REF , COMP) is generated as a logic high.

A: (OSN <3 0>), if the comparison signal (COMP), a logic low, the second transistor current (i _ND), a reference current (i _REF), a second offset signal of the second amplifier 400 to be greater than Can be adjusted. For example, if the second offset signal OSN <0: 3> was initially set to "0000", the second offset signal OSN <0: 3> 1000 "so that the voltage level of the second control signal CN is lowered. Thus, the current (i _ND ) of the second transistor ND responding to the lowered voltage level of the second control signal CN is reduced.

If the second transistor current i _ND is still greater than the reference current i _REF and the comparison signal COMP is logic low then the second offset signal OSN < 0 : 3 >) to "1001 ", so that the voltage level of the second control signal CN can be further lowered. That is, the second offset signal OSN <0: 3> is changed and the voltage level of the second control signal CN is lowered until the second transistor current i _ND becomes equal to or smaller than the reference current i _REF The operation of comparing the second transistor current (i _ND ) with the reference current (i _REF ) can be repeatedly monitored. The second offset signal OSP <0: 3> when the second transistor current i _ND becomes equal to or smaller than the reference current i _REF is supplied to the second amplifier 400 in the normal operation.

8 is a fourth example of the current comparator of FIG. 1 according to the embodiment of the present invention.

Referring to FIG. 8, the current comparator 130d compares the second transistor current (i _ND ) of the driver during the test with the reference current (i _REF ) and generates a comparison signal COMP. The second transistor current (i _ND ) of the driving unit is a current flowing to the second transistor (ND) when the first switch (126) is in an on state and the second switch (128) is in an off state. The first and second input terminals of the second amplifier 400 of the driving unit are short-circuited by the ON-state first switch 126 and the reference voltage VREF / 2 is connected. The second control signal CN, which is the output terminal of the second amplifier 400, is provided to the gate of the second transistor ND. The second transistor current (i _ND ) flows to the second transistor ( _ND ) in response to the second control signal (CN). At this time, the first control signal CP, which is the output terminal of the first amplifier 300, is set to logic high so that the first transistor PD is turned off.

The current comparison unit 130d includes a test switch 810, a current source 820, and a buffer unit 830. [ The test switch 810 is turned on to connect the third node NC of the driver during the test with the current comparator 130d, and is turned off in the normal operation. The test switch 810 is connected between the third node (NC) and the current source 820. The current source 820 is connected between the second power supply voltage VDD and the test switch 610 and provides a reference current i _REF . The reference current i _REF may be set at various current levels during testing. The buffer unit 830 is connected to a connection node between the test switch 810 and the current source 820 and outputs a comparison signal COMP.

In the current comparator 130d, the test switch 810 is turned on and the second transistor current i _ND of the driver is supplied to the current comparator 130d. The reference current i _REF and the second transistor current i _ND are compared at the connection node between the test switch 810 and the current source 820. If the second transistor current i _ND is larger than the reference current i _REF , the comparison signal COMP, which is the output of the buffer unit 630, is generated at a logic low and the second transistor current i _ND is the reference current i _REF ), the comparison signal COMP is generated as a logic high.

If the comparison signal COMP is logic low, the operation of changing the second offset signal OSN <0: 3> and comparing the second transistor current i _ND with the reference current i _REF is the second transistor current i _ND ) is less than or equal to the reference current i _REF . The second offset signal OSN <0: 3> when the second transistor current i _ND becomes equal to or smaller than the reference current i _REF is supplied to the second amplifier 400 in the normal operation.

9 is a first example of a semiconductor memory device incorporating a voltage generating circuit according to an embodiment of the present invention.

Referring to FIG. 9, semiconductor memory device 900 may include a voltage generation circuit 100 and a test circuit block 200.

The voltage generating circuit 100 generates the reference voltage VREF (0) using the first and second amplifiers 300 and 400 according to the first and second offset signals OSP <0: 3> and OSN < / 2) and the bit line pre-charge voltage VBL to generate the first and second control signals CP and CN. The driving unit 124 may drive the third node NC to the bit line precharge voltage VBL in response to the first and second control signals CP and CN.

The test circuit block 200 provides first and second test signals (ON and ONB) to the voltage generating circuit 100 to the voltage generating circuit 100 at the time of testing. The test circuit block 200 outputs the first offset signals OSP <0: 3> and the second offset signals OSP <0: 3> in response to the comparison signal COMP provided by the voltage generating circuit 100 in response to the clock signal CLK. (OSP < 0: 3 >). The test circuit block 200 outputs the first and second offset signals OSP < 0 (OSP > 0) in response to the comparison signal COMP when the current of the output node at which the bit line pre- : 3>, OSN <0: 3>) can be set. The set first and second offset signals OSP <0: 3>, OSN <0: 3> are provided to the first and second amplifiers 300 and 400. Accordingly, the voltage generating circuit 100 can generate the bit line precharge voltage VBL with the reference voltage VREF / 2 as a target.

10 is a flowchart illustrating a first offset signal trimming method according to an embodiment of the present invention. The first offset signal trimming method of FIG. 10 is described in connection with FIGS. 1, 3, 5, 6, and 9.

Referring to FIG. 10, the current iPD of the first transistor PD of the driving unit 124 is measured (S1010). The measurement of the first transistor current i _PD can be performed using the current comparator 130 of FIG. It is determined whether the measured first transistor current i _PD is less than or equal to the reference current i _REF (S1020). The determination as to whether or not the reference current i _REF is less than or equal to the reference current i _REF may be performed using the comparison signal COMP of the current comparator 130. As a result of the determination, if the first transistor current i _PD is less than the reference current i _REF (YES in step S1020), the first offset signal OSP <0: 3> is set in the test circuit block 200 of FIG. (S1040). As a result of the determination, if the first transistor current i _PD is larger than the reference current i _REF (NO in step S1020), the test circuit block 200 changes the first offset signal OSP <0: 3> (S1030). After the first offset signal OSP <0: 3> is changed (S1030) until the first transistor current i _PD becomes equal to or lower than the reference current i _REF , the first offset signal OSP < 0: 3 >) (S1040).

11 is a flowchart illustrating a second offset signal trimming method according to an embodiment of the present invention. The second offset signal trimming method of FIG. 11 is described in connection with FIGS. 1, 4, 7, 8, and 9.

Referring to FIG. 11, the current i _ND of the second transistor ND of the driving unit 124 is measured (S 1110). The measurement of the second transistor current i _ND can be performed using the current comparator 130 of FIG. It is determined whether the measured second transistor current i _ND is less than or equal to the reference current i _REF (S1120). The determination as to whether or not the reference current i _REF is less than or equal to the reference current i _REF may be performed using the comparison signal COMP of the current comparator 130. As a result of the determination, if the second transistor current i _ND is less than the reference current i _REF (YES in step S 1120), the second offset signal OSN <0: 3> is set in the test circuit block 200 of FIG. (S1140). As a result of the determination, if the second transistor current i _ND is larger than the reference current i _REF (NO in step S1120), the second circuit 200 changes the second offset signal OSN <0: 3> S1130) and after changing the second offset signal OSN <0: 3> until the second transistor current i _ND becomes equal to or smaller than the reference current i _REF (S1130), the second offset signal OSN < 0: 3 >) (S1140).

12 and 13 are graphs for explaining the operation of the voltage generating circuit according to the embodiment of the present invention.

Referring to FIG. 12, when the first transistor current i _PD is less than or equal to the reference current i _REF , the comparison signal COMP is generated at a logic low. It can be seen that the first offset signal OSP < 0: 3 > is set. Further, when the second transistor current i _ND is equal to or _smaller than the reference current i _REF , the comparison signal COMP is generated as a logic high. It can be seen that the second offset signal OSN < 0: 3 > is set.

13, the current I (VBL) at the third node NC (FIG. 1) when the bit line pre-charge voltage VBL is generated at the reference voltage VREF / 2 level is 0uA It appears (A). That is, the driver 124 of the push-pull output circuit composed of the first and second transistors PD and ND does not generate a through current. The driving unit 124 can implement the dead zone free, i.e., the dead zone free. In contrast, when the bit line precharge voltage VBL is designed to be located in the dead zone (B), the bit line precharge voltage VBL is in the metastable state, As described above, the bit line precharge voltage VBL has dispersion.

14 is a second example of a semiconductor memory device incorporating a voltage generating circuit according to an embodiment of the present invention.

14, the semiconductor memory device 1400 includes a memory core 1500, a local sense amplifier 1410, an input / output sense amplifier 1420, an input / output buffer 1430, and a voltage generator 1440.

The memory core 1500 precharges the bit line BL and the complementary bit line BLB to the bit line precharge voltage VBL and the voltage difference between the bit line BL and the complementary bit line BLB And provides the amplified voltage difference to the local input / output line pair (LIO, LIOB). The local sense amplifier 1410 amplifies the voltage signal of the local input / output line pair (LIO, LIOB) and provides it as a global input / output line pair (GIO, GIOB). The input / output sense amplifier 1420 amplifies voltage signals of the global input / output line pair (GIO, GIOB). The input / output buffer 1430 buffers the output of the input / output sense amplifier 1420 and outputs it as the output data DOUT or buffers the input data DIN. The output data DOUT of the input / output buffer 1430 is provided to the outside of the semiconductor memory device 1400 through the output pad. The voltage generating unit 1440 generates various voltages VCP, VREF, and VBL using the power supply voltage VDD. The VCP voltage represents the cell plate voltage, the VREF and VDD voltages represent the memory core voltage, and VBL represents the bit line free charge voltage. The voltage generator 1440 may include the dead zone pre-voltage generator 100 of FIG. 1 to generate the bit line pre-charge voltage VBL.

15 is a diagram for explaining a configuration of the memory core of FIG. 14 according to an embodiment of the present invention.

15, a memory core 1500 includes a first memory cell 1510 connected to a bit line BL, a second memory cell 1520 connected to a complementary bit line BLB, a bit line sense amplifier 1530, a first equalizer 1540, a column selection circuit 1550, and an amplification control unit 1560.

The first memory cell 1510 includes a cell transistor MN1 and a cell capacitor CC1 serially connected to each other. The second memory cell 1520 includes a cell transistor MN2 and a cell capacitor CC2 that are connected in series with each other. A cell plate voltage VCP is applied to one end of the cell capacitors CC1 and CC2. The drain of the MN1 cell transistor is connected to the bit line BL, and the gate is connected to the word line WLi. The drain of the MN2 cell transistor is connected to the complementary bit line BLB, and the gate is connected to the word line WLj.

The first equalizer 1540 includes NMOS transistors MN5, MN6, MN7. The MN5 transistor is connected between the bit line BL and the complementary bit line BLB, and the gate thereof is connected with the equalization control signal PEQi. The drain of the MN6 transistor is connected to the bit line BL, the source is connected to the bit line precharge voltage VBL and the gate is connected to the equalization control signal PEQi. The MN7 transistor is connected to the complementary bit line BLB, the source is connected to the bit line precharge voltage VBL, and the gate is connected to the equalization control signal PEQi. The first equalizer 1540 precharges the bit line BL and the complementary bit line BLB to the bit line precharge voltage VBL in response to the equalization control signal PEQi.

The bit line sense amplifier 1530 includes PMOS transistors MP1 and MP2 connected in series between the bit line BL and the complementary bit line BLB and a PMOS transistor MP1 and MP2 connected in series between the bit line BL and the complementary bit line BLB. And NMOS transistors MN3 and MN4 connected thereto. The MP1 and MP2 transistors sense and amplify the voltage difference between the bit line BL and the complementary bit line BLB using the power supply voltage VDD. MN3 and MN4 sense and amplify the voltage difference between the bit line BL and the complementary bit line BLB using the ground voltage VSS.

The column selection circuit 1550 includes NMOS transistors MN8 and MN9. The MN8 transistor electrically connects the bit line BL to the local input / output line LIO in response to the column selection signal CSL. The MN9 transistor electrically couples the complementary bit line BLB to the complementary local input / output line LIOB in response to the column selection signal CSL.

The amplification control unit 1560 includes a second equalizer 1561, a PMOS transistor MP3, and an NMOS transistor MN13. The second equalizer 1561 includes NMOS transistors MN10, MN11, and MN12. An equalization control signal PEQi is connected to the gates of the MN10, MN11 and MN12 transistors, and a bit line precharge voltage VBL is connected to the sources of the MN11 and MN12 transistors. The second equalizer 156 is connected to the sources of the MP1 and MP2 transistors of the bit line sense amplifier 1530 through the first power supply line LA and is connected to the bit line sense amplifier And MN3 and MN4 transistors of transistor 1530, respectively. The second equalizer 1561 precharges the first power supply line LA and the second power supply line LAB to the bit line precharge voltage VBL in response to the equalization control signal PEQi. The MP3 transistor provides the power supply voltage VDD to the bit line sense amplifier 1530 through the first power supply line LA in response to the switch control signal LAPG. The MN13 transistor provides the ground voltage VSS to the bit line sense amplifier 1530 through the second power supply line LAB in response to the switch control signal LANG.

When data stored in the CC1 cell capacitor is output to the bit line BL, charge sharing occurs between the capacitors of the cell capacitor CC1 and the bit line BL. Likewise, when data stored in the CC2 cell capacitor is output to the complementary bit line BLB, charge sharing between the capacitor of the cell capacitor CC2 and the complementary bit line BLB occurs. The bit line BL and the complementary bit line BLB are precharged to the bit line precharge voltage VBL in order to efficiently sense the data stored in the memory cells 1510 and 1520.

16A and 16B are diagrams for explaining the voltage waveforms of the bit line and the complementary bit line when sensing data "1" or "0" stored in the cell capacitor CC1 of FIG.

16A, when the bit line sense amplifier 1530 detects data "1 ", the bit line BL and the complementary bit line BLB are precharged to the bit line precharge voltage VBL in advance The bit line BL is increased by dV1. When the amplifying operation is completed by the bit line sense amplifier 1530, the voltage of the bit line BL becomes the power supply voltage VDD level and the complementary bit line BLB becomes the ground voltage VSS level.

16B, when the bit line sense amplifier 1530 detects data "0 ", the bit line BL and the complementary bit line BLB are precharged to the bit line precharge voltage VBL in advance The bit line BL is reduced by dV2. When the amplifying operation is completed by the bit line sense amplifier 1530, the voltage of the bit line BL becomes the ground voltage (VSS) level and the complementary bit line BLB becomes the power supply voltage (VDD) level.

17 and 18 are diagrams illustrating a memory module including a memory chip incorporating a voltage generating circuit according to various embodiments of the present invention.

17, a memory module 1700 includes a plurality of memory chips 1710a-1710h, a command / address register chip 1720, and data buffer chips 1730a (corresponding to memory chips 1710a-1710h) -1730h). The command / address register chip 1720 receives the command CMD and the address ADDR from the memory controller 1750 via the control bus 1722 and buffers the received command CMD and address ADDR, It can have the function of driving. The command CMD and the address ADDR output from the command / address register chip 1720 may be provided to the memory chips 1710a-1710h via the first bus 1724. [

Each of the data buffer chips 1730a-1730h may be correspondingly connected to each of the memory chips 1710a-1710h. Each of the data buffer chips 1730a-1730h receives and buffers data DQ of the memory chips 1710a-1710h from the memory controller 1750 via the data bus 1732 and stores the data DQ in the corresponding memory chips 1710a-1710h . Each of the data buffer chips 1730a-1730h may transmit data received from the corresponding memory chip 1710a-1710h to the memory controller 1750 via the data bus 1732. [

The memory chips 1710a-1710h may include a voltage generation circuit that generates a bit line precharge voltage used to precharge the bit line and the complementary bit line. The voltage generating circuit may generate a bit line precharge voltage using an amplifier for comparing a reference voltage and a bit line precharge voltage and a driver including pull-up and pull-down transistors. The voltage generating circuit measures the current at the output node at which the bit line precharge voltage is generated, determines whether the current of the output node is below the reference current, and determines whether the pull- Down transistor current of the output node is less than or equal to the reference current and the bit line free charge voltage can be generated to target the reference voltage according to the changed offset signal. The voltage generation circuit can generate the bit line free charge voltage without a dead zone.

Referring to Figure 18, memory module 1800 includes a plurality of memory chips 1810a-1810h and a command / address register chip 1820. [ The command / address register chip 1820 receives the command CMD and the address ADDR from the memory controller 1850 via the control bus 1822 and buffers the received command CMD and address ADDR, It can have the function of driving. The command CMD and address ADDR output from the command / address register chip 1820 may be provided to the memory chips 1810a-1810h via the first bus 1824. [

Each of the memory chips 1810a-1810h may be coupled to the memory controller 1850 via data buses 1832a-1832h directly wired from the memory controller 1850. [ Each of the memory chips 1810a-1810h may receive data DQ from the memory controller 1850 via correspondingly connected data buses 1832a-1832h. The data DQ output from each of the memory chips 1810a-1810h may be transferred to the memory controller 1850 via the data buses 1832a-1832h and 1832b.

The memory chips 1810a-1810h may include a voltage generation circuit that generates a bit line precharge voltage used to precharge the bit line and the complementary bit line. The voltage generating circuit may generate a bit line precharge voltage using an amplifier for comparing a reference voltage and a bit line precharge voltage and a driver including pull-up and pull-down transistors. The voltage generating circuit measures the current at the output node at which the bit line precharge voltage is generated, determines whether the current of the output node is below the reference current, and determines whether the pull- Down transistor current of the output node is less than or equal to the reference current and the bit line free charge voltage can be generated to target the reference voltage according to the changed offset signal. The voltage generation circuit can generate the bit line free charge voltage without a dead zone.

19 is a block diagram showing an example of application of a memory chip incorporating a voltage generation circuit according to the embodiments of the present invention to a mobile system.

19, the mobile system 1900 includes an application processor 1910, a communication unit 1920, a volatile memory device 1930, a non-volatile memory device 1940, a user interface 1950, and a power supply (1960). According to an embodiment, the mobile system 1900 may be a mobile phone, a smart phone, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera Camera, a music player, a portable game console, a navigation system, and the like.

The application processor 1910 may execute applications that provide Internet browsers, games, animations, and the like. According to an embodiment, the application processor 1910 may include a single processor core or a plurality of processor cores (Multi-Core). For example, the application processor 1910 may include a dual-core, a quad-core, and a hexa-core. In addition, according to the embodiment, the application processor 1910 may further include a cache memory located inside or outside.

The communication unit 1920 can perform wireless communication or wired communication with an external device. For example, the communication unit 1920 may be an Ethernet communication, a Near Field Communication (NFC), a Radio Frequency Identification (RFID) communication, a Mobile Telecommunication, a memory card communication, A universal serial bus (USB) communication, and the like. For example, the communication unit 1920 may include a baseband chipset, and may support communication such as GSM, GRPS, WCDMA, and HSxPA.

The volatile memory device 1930 may store data processed by the application processor 1910, or may operate as a working memory. Volatile memory device 1930 may be a dynamic random access memory such as DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, RDRAM, and the like.

The volatile memory device 1930 may include a voltage generation circuit that generates a bit line precharge voltage used to precharge the bit line and the complementary bit line. The voltage generating circuit may generate a bit line precharge voltage using an amplifier for comparing a reference voltage and a bit line precharge voltage and a driver including pull-up and pull-down transistors. The voltage generating circuit measures the current at the output node at which the bit line precharge voltage is generated, determines whether the current of the output node is below the reference current, and determines whether the pull- Down transistor current of the output node is less than or equal to the reference current and the bit line free charge voltage can be generated to target the reference voltage according to the changed offset signal. The voltage generation circuit can generate the bit line free charge voltage without a dead zone.

Non-volatile memory device 1940 may store a boot image for booting mobile system 1900. For example, the nonvolatile memory device 1940 may be an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistance random access memory (RRAM) A Floating Gate Memory, a Polymer Random Access Memory (PoRAM), a Magnetic Random Access Memory (MRAM), a Ferroelectric Random Access Memory (FRAM), or the like.

The user interface 1950 may include one or more input devices, such as a keypad, a touch screen, and / or a speaker, a display device, and one or more output devices. It is possible to supply the operating voltage of the power supply 1960. In addition, according to an embodiment, the mobile system 1900 may include a camera image processor (CIP), a memory card, a solid state drive (SSD), a hard disk drive A hard disk drive (HDD), a CD-ROM, and the like.

The components of the mobile system 1900 or the mobile system 1900 may be implemented using various types of packages, such as Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages ), Plastic Leaded Chip Carrier (PLCC), Die in Waffle Pack, Die in Water Form, COB (Chip On Board), Ceramic Dual In-Line Package (CERDIP), MQFP Metric Quad Flat Pack, Thin Quad Flat-Pack (TQFP), Small Outline Integrated Circuit (SOIC), Shrink Small Outline Package (SSOP), Thin Small Outline Package (TSOP) System In Package, Multi Chip Package (MCP), Water-level Fabricated Package (WFP), and Water-level Processed Stack Package (WSP).

20 is a block diagram showing an example of application of a memory module equipped with a memory chip incorporating a voltage generating circuit according to the embodiments of the present invention to a computing system.

20, a computer system 2000 includes a processor 2010, an input / output hub 2020, an input / output controller hub 2030, at least one memory module 2040, and a graphics card 2050. According to an embodiment, the computer system 2000 may be a personal computer (PC), a server computer, a workstation, a laptop, a mobile phone, a smart phone, A personal digital assistant (PDA), a portable multimedia player (PMP), a digital camera, a digital television, a set-top box, A music player, a portable game console, a navigation system, and the like.

Processor 2010 may execute various computing functions, such as certain calculations or tasks. For example, the processor 2010 may be a microprocessor or a central processing unit (CPU). According to an embodiment, the processor 2010 may include one processor core (Core) or a plurality of processor cores (Multi-Core). For example, the processor 2010 may include a dual-core, a quad-core, a hexa-core, and the like. Also shown in FIG. 20 is a computing system 2000 that includes one processor 2010, but according to an embodiment, the computing system 2000 may include a plurality of processors. Also, according to the embodiment, the processor 2010 may further include a cache memory located inside or outside.

The processor 2010 may include a memory controller 2011 that controls the operation of the memory module 2040. The memory controller 2011 included in the processor 2010 may be referred to as an integrated memory controller (IMC). The memory interface between the memory controller 2011 and the memory module 2040 may be implemented as a single channel including a plurality of signal lines or a plurality of channels. Also, one or more memory modules 2040 may be connected to each channel. According to an embodiment, the memory controller 2011 may be located in the input / output hub 2020. [ The input / output hub 2020 including the memory controller 2011 may be referred to as a memory controller hub (MCH).

The memory module 2040 may include a plurality of memory chips and a buffer chip that store data provided from the memory controller. The memory chips may be dynamic random access memories such as, for example, DDR SDRAM, LPDDR SDRAM, GDDR SDRAM, RDRAM, and the like.

The memory chip may include a voltage generation circuit that generates a bit line precharge voltage used to precharge the bit line and the complementary bit line. The voltage generating circuit may generate a bit line precharge voltage using an amplifier for comparing a reference voltage and a bit line precharge voltage and a driver including pull-up and pull-down transistors. The voltage generating circuit measures the current at the output node at which the bit line precharge voltage is generated, determines whether the current of the output node is below the reference current, and determines whether the pull- Down transistor current of the output node is less than or equal to the reference current and the bit line free charge voltage can be generated to target the reference voltage according to the changed offset signal. The voltage generation circuit can generate the bit line free charge voltage without a dead zone.

The input / output hub 2020 can manage data transfer between the processor 2010 and devices such as the graphics card 2050. [ The input / output hub 2020 can be connected to the processor 2010 through various types of interfaces. For example, the input / output hub 2020 and the processor 2010 may include a front side bus (FSB), a system bus, a hypertransport, a lighting data transport 20 can be connected to various standard interfaces such as an LDT, a QuickPath Interconnect (QPI), a common system interface, and a Peripheral Component Interface-Express (CSI) 2020, although the computing system 2000 may include a plurality of input / output hubs, according to an embodiment.

The input / output hub 2020 may provide various interfaces with the devices. For example, the input / output hub 2020 may include an Accelerated Graphics Port (AGP) interface, a Peripheral Component Interface-Express (PCIe) interface, a Communications Streaming Architecture (CSA) Can be provided.

The graphics card 2050 may be connected to the input / output hub 2020 via AGP or PCIe. The graphics card 2050 may control a display device (not shown) for displaying an image. Graphics card 2050 may include an internal processor and internal processor and internal semiconductor memory device for image data processing. Output hub 2020 may include a graphics device in the interior of the input / output hub 2020, with or instead of the graphics card 2050 located outside of the input / output hub 2020 . The graphics device included in the input / output hub 2020 may be referred to as Integrated Graphics. In addition, the input / output hub 2020 including the memory controller and the graphics device may be referred to as a graphics and memory controller hub (GMCH).

The input / output controller hub 2030 can perform data buffering and interface arbitration so that various system interfaces operate efficiently. The input / output controller hub 2030 may be connected to the input / output hub 2020 through an internal bus. For example, the input / output hub 2020 and the input / output controller hub 2030 may be connected through a direct media interface (DMI), a hub interface, an enterprise southbridge interface (ESI), a PCIe .

The I / O controller hub 2030 may provide various interfaces with peripheral devices. For example, the input / output controller hub 2030 may include a universal serial bus (USB) port, a serial Advanced Technology Attachment (SATA) port, a general purpose input / output (GPIO) (LPC) bus, Serial Peripheral Interface (SPI), PCI, PCIe, and the like.

Depending on the embodiment, two or more components of the processor 2010, the input / output hub 2020, or the input / output controller hub 2030 may be implemented as one chipset.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims

A voltage generating circuit for generating a bit line precharge voltage,
A current comparator comparing a current of an output node at which the bit line precharge voltage is generated with a reference current; And
And a bit line precharge voltage generating unit for generating the bit line precharge voltage with a reference voltage as a target in response to an offset signal when the current of the output node is equal to or less than the reference current.

2. The semiconductor memory device according to claim 1, wherein the bit line precharge voltage generator
An amplifier for providing first and second control signals based on the reference voltage and the bit line pre-charge voltage; And
And a driver for driving the output node to the bit line precharge voltage in response to the first and second control signals.

3. The receiver of claim 2, wherein the amplifying unit
And a second control circuit coupled between the second power supply voltage and the ground voltage for amplifying the difference between the reference voltage and the bit line charge voltage received at the input terminals according to the first offset signal, An amplifying unit; And
And amplifying a difference between the reference voltage and the bit line precharge voltage, which is connected between the second power supply voltage and the ground voltage and is received at the input terminals according to the second offset signal, and outputs the second control signal And a second amplifier unit.

The apparatus as claimed in claim 3, wherein the driving unit
A first transistor coupled between a second power supply voltage and the output node and responsive to the first control signal for pulling up the output node; And
And a second transistor connected between the output node and the ground voltage, for pulling-down driving the output node in response to the second control signal.

The apparatus of claim 4, wherein the current comparator
Wherein the current comparator compares a current flowing in the first transistor with the reference current in response to the first control signal generated when the reference voltage is applied to the input terminals of the first amplifier, And changes the first offset signals until the reference current becomes equal to or less than the reference current.

The apparatus of claim 4, wherein the current comparator
Wherein the current comparator compares the current flowing in the second transistor with the reference current in response to the second control signal generated when the reference voltage is applied to the input terminals of the second amplifier, And to change the second offset signals until the reference current becomes equal to or less than the reference current.

A method of generating a bit line free-guard voltage using an amplifier for comparing a reference voltage with a bit line pre-charge voltage and a driver including pull-up and pull-down transistors,
Measuring a current at an output node where the bit line pre-charge voltage is generated;
Determining whether the current of the output node is less than or equal to a reference current;
Changing an offset signal of the amplification unit according to the determination; And
And generating the bit line precharge voltage with the reference voltage as a target according to the changed offset signal.

8. The method of claim 7, wherein changing the offset signal of the amplification unit
And the offset signal is changed until the current of the pull-up transistor becomes less than or equal to the reference current.

8. The method of claim 7, wherein changing the offset signal of the amplification unit
And the offset signal is changed until the current of the pull-down transistor becomes less than or equal to the reference current.

8. The method of claim 7, wherein the bit line precharge voltage generating method comprises:
Wherein the bit line precharge voltage is generated without a dead zone.