JP6515606B2 - Semiconductor integrated circuit device and electronic device using the same - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device incorporating an electrically rewritable nonvolatile memory such as a flash memory or an EEPROM (Electrically Erasable Programmable Read-Only Memory). Furthermore, the present invention relates to an electronic device and the like using such a semiconductor integrated circuit device.

  In recent years, electrically rewritable non-volatile memories such as flash memories and EEPROMs (Electrically Erasable Programmable Read-Only Memories) have become widespread. In a semiconductor integrated circuit device incorporating such a non-volatile memory, when a verify circuit is not mounted, a program (data writing) is measured at the time of shipping inspection while measuring the current flowing in the memory cell using an LSI tester or the like. Thus, the threshold voltage of the reference memory cell (reference cell) is adjusted. Therefore, it takes time to set up the power supply in order to set the threshold voltage, and the inspection cost is also increased. On the other hand, when the verify circuit is mounted, a complex circuit such as a reference cell for setting the threshold voltage of the reference cell and a control circuit for switching between the program operation and the determination operation is required.

  As a related technique, Patent Document 1 discloses a scaling scheme with a reference that follows variations in the electrical characteristics of the array cell. The programmable reference includes one or more reference cells, each reference cell having a floating gate programmed in a controlled environment to set its threshold. The same voltage is applied to the gates of the array cell and the reference cell to read out the state of the array cell. In addition, the outputs of the array cell and the reference cell are maintained under the same bias conditions. During data readout, the drain of the reference cell provides an output that is compared to the drain output of the array cell to determine the threshold of the array cell relative to the threshold of the reference cell.

  Further, Patent Document 2 discloses a nonvolatile semiconductor memory device in which the threshold value of a reference cell is accurately set to a desired value after the threshold value setting is automated in order to suppress an increase in test time. This semiconductor memory device includes an array of electrically rewritable memory cells, a reference cell having a threshold serving as a reference for comparison when reading data held in the memory cell, and a setting circuit for setting the threshold in the reference cell And a plurality of reference cells each having a different reference value serving as a determination reference of a value set as a threshold in the reference cell, and the setting circuit is written in the reference cell write circuit and the reference cell. A determination unit that determines whether the threshold has reached any of the reference values of a plurality of reference cells; and a control circuit that controls a write signal when resetting the threshold to the reference cell according to each of the reference values. Prepare.

Unexamined-Japanese-Patent No. 7-192478 (Paragraphs 0009-0010, FIG. 4) Unexamined-Japanese-Patent No. 2007-164934 (Paragraphs 0011-0012)

  In Patent Document 1, one reference cell is used for one determination level, and basically, the comparison of the threshold is performed by comparing the output of the array cell with the outputs of a plurality of reference cells. Further, in Patent Document 2, a plurality of reference cells are used to set a threshold in a reference cell. In the case of using a plurality of reference cells as such, a decoding circuit is also required, and the number of additional circuits is increased.

  Therefore, in view of the above-described point, a first object of the present invention is to allow the determination current to be compared when reading data stored in a memory cell to be appropriately set using a small number of reference cells. It is to be. A second object of the present invention is to provide a semiconductor integrated circuit device capable of accurately checking or setting the threshold voltage of a reference cell or the like without increasing the circuit scale too much. Furthermore, a third object of the present invention is to provide an electronic device and the like using such a semiconductor integrated circuit device.

  In order to solve at least a part of the above problems, a semiconductor integrated circuit device according to one aspect of the present invention includes a memory cell including a transistor for storing data according to charges stored in a floating gate; A first reference cell including a transistor having a threshold voltage; a second reference cell including a transistor having a second threshold voltage greater than the first threshold voltage; a current flowing through the first reference cell; And a data read circuit for reading out data stored in the memory cell by generating a determination current based on the current flowing in the reference cell and comparing the current flowing in the memory cell with the determination current.

  According to one aspect of the present invention, when the data stored in the memory cell is read, the determination current to be compared is the current flowing through the first reference cell and the current flowing through the second reference cell. It can set appropriately based on. Further, the determination current can be changed in the read mode and the verify mode of the memory cell.

  Here, the semiconductor integrated circuit device may further include a verify circuit that sets the threshold voltage of the second reference cell based on the threshold voltage of the first reference cell. In the verify mode of the reference cell, only the second reference cell is to be verified. Therefore, the decoding circuit for selecting the reference cell becomes unnecessary, and the scale of the reference cell is not increased. The threshold voltage can be set accurately.

  In that case, in the verify mode of the reference cell, the data read circuit compares the current proportional to the current flowing to the second reference cell with the current proportional to the current flowing to the first reference cell, and the verify circuit When the current proportional to the current flowing to the second reference cell is larger than the current proportional to the current flowing to the first reference cell, the threshold voltage of the second reference cell may be increased. Thus, the threshold voltage of the second reference cell can be accurately set in accordance with the ratio of the current flowing in the first reference cell to the current flowing in the second reference cell.

  In the above, the data read circuit compares the current flowing in the memory cell with the determination current in the read mode, and in the verify mode of the reference cell, a current proportional to the current flowing in the second reference cell is used as the first reference cell. A sense amplifier may be included to output a determination signal representing a comparison result in comparison with a current proportional to the flowing current. Thereby, since the same sense amplifier can be shared in the read mode and the verify mode of the reference cell, the threshold voltage of the reference cell can be accurately confirmed without increasing the circuit scale too much.

  In that case, the data reading circuit supplies a first current mirror circuit supplying a current proportional to the current flowing to the first reference cell, and a second current supplying a current proportional to the current flowing to the second reference cell. A current mirror circuit, a selector circuit selecting a supply destination of current supplied from the second current mirror circuit according to a signal setting the verify mode of the reference cell, and a second current mirror circuit in the verify mode of the reference cell And a third current mirror circuit supplying a current proportional to the current supplied from the sense amplifier, the sense amplifier, in the read mode, current flowing to the memory cell from the current supplied from the first current mirror circuit. Judgment current which is the sum of the current supplied from the second current mirror circuit Comparison, in the verify mode of the reference cell may be compared to the current supplied to the current supplied from the third current mirror circuit from the first current mirror circuit.

  Thereby, in the read mode, the sense amplifier compares the current flowing in the memory cell with the determination current generated based on the current flowing in the first reference cell and the current flowing in the second reference cell, In the verify mode, the current proportional to the current flowing to the second reference cell can be compared with the current proportional to the current flowing to the first reference cell.

  An electronic device according to one aspect of the present invention includes any one of the semiconductor integrated circuit devices described above. Thus, the determination current to be compared when reading data stored in the nonvolatile memory built in the semiconductor integrated circuit device can be appropriately set based on the current flowing through the two reference cells. An electronic device can be provided.

FIG. 1 is a block diagram showing an example of the configuration of a non-volatile memory according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration example of a memory cell array shown in FIG. 1 and its periphery. FIG. 2 is a circuit diagram showing a configuration example of a data read circuit shown in FIG. 1 and the periphery thereof. FIG. 7 is a diagram showing an example of setting of determination levels in the read mode of the data read circuit. FIG. 2 is a circuit diagram showing a configuration example of a verify circuit shown in FIG. 6 is a timing chart showing an operation example of the verify circuit shown in FIG. FIG. 1 is a block diagram showing an example of the configuration of an electronic device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same reference numerals are given to the same components, and the overlapping description is omitted.
<Non-volatile memory>
FIG. 1 is a block diagram showing a configuration example of a non-volatile memory built in a semiconductor integrated circuit device according to an embodiment of the present invention. The semiconductor integrated circuit device according to one embodiment of the present invention may incorporate only an electrically rewritable nonvolatile memory such as a flash memory or an EEPROM, or has a predetermined function in addition to the nonvolatile memory. A functional block such as a circuit block or a CPU (central processing unit) may be incorporated. In the following, a flash memory will be described as an example of the non-volatile memory.

  As shown in FIG. 1, the non-volatile memory includes a memory cell array 10, a power supply circuit 20, a word line booster circuit 30, a word line drive circuit 40, a source line drive circuit 50, a switch circuit 60, and a memory. And a control circuit 70. The memory control circuit 70 controls the power supply circuit 20 to the switch circuit 60 so that the plurality of memory cells included in the memory cell array 10 perform the erase operation, the write operation, or the read operation.

  The plurality of memory cells of the memory cell array 10 are arranged in a matrix of m rows and n columns (m and n are integers of 2 or more). For example, the memory cell array 10 includes 2048 rows of memory cells. In addition, one row of memory cells includes 1024 memory cells, and can store 128 8-bit data.

  The memory cell array 10 includes a plurality of word lines WL0, WL1,..., WLm, a plurality of source lines SL0, SL1,..., SLm and a plurality of bit lines BL0, BL1,. And contains. Each of those word lines is connected to a plurality of memory cells arranged in each row. Also, each of those bit lines is connected to a plurality of memory cells arranged in each column.

  For example, a reference power supply potential VSS, a high power supply potential VPP for data erasing and data writing, and a logic power supply potential VDD for a logic circuit are supplied to the power supply circuit 20 from the outside. Alternatively, the power supply circuit 20 may generate another power supply potential by stepping up or down one power supply potential of a plurality of externally supplied power supply potentials.

  The reference power supply potential VSS is a reference potential that is a reference relative to other potentials, and in the following, the case where the reference power supply potential VSS is the ground potential (0 V) will be described. The high power supply potential VPP is a predetermined potential higher than the reference power supply potential VSS, and is, for example, about 5V to 10V. The logic power supply potential VDD is a potential higher than the reference power supply potential VSS and lower than the high power supply potential VPP, and is, for example, about 1.2 V to 1.8 V. Logic power supply potential VDD may be shared with the power supply potential of a functional circuit used together with nonvolatile memory in the semiconductor integrated circuit device.

  The power supply circuit 20 supplies the logic power supply potential VDD to the memory control circuit 70 and, under the control of the memory control circuit 70, the high power supply potential VPP and the logic power supply potential VDD to each part of the non-volatile memory as necessary. Supply. In FIG. 1, the power supply potential supplied from power supply circuit 20 to word line boosting circuit 30 is shown as word line power supply potential VWL, and the power supply potential supplied from power supply circuit 20 to source line drive circuit 50 is the source line. It is shown as power supply potential VSL.

  For example, in the erase mode in which the memory cell is put into the erase state, the power supply circuit 20 supplies the high power supply potential VPP to the word line booster circuit 30 and the source line drive circuit 50. Word line booster circuit 30 supplies high power supply potential VPP to word line drive circuit 40.

  In the write mode for writing data in the memory cell, the power supply circuit 20 supplies the high power supply potential VPP to the word line booster circuit 30 and the source line drive circuit 50. Word line booster circuit 30 supplies high power supply potential VPP to word line drive circuit 40.

  In the read mode in which data is read from the memory cell, the power supply circuit 20 supplies the logic power supply potential VDD to the word line booster circuit 30 and the source line drive circuit 50. The word line boosting circuit 30 raises the logic power supply potential VDD to generate a word line boosted potential VUP (for example, 2.8 V), and supplies the word line boosted potential VUP to the word line drive circuit 40.

  In the verify mode of the memory cell, the power supply circuit 20 supplies the logic power supply potential VDD to the word line booster circuit 30 and the source line drive circuit 50. Word line booster circuit 30 supplies logic power supply potential VDD to word line drive circuit 40.

  In the verify mode of the reference cell, the power supply circuit 20 supplies the high power supply potential VPP and the logic power supply potential VDD to the word line boosting circuit 30, and supplies the high power supply potential VPP to the source line drive circuit 50. The word line boosting circuit 30 supplies the high power supply potential VPP and the logic power supply potential VDD to the word line drive circuit 40.

  The word line drive circuit 40 is connected to the plurality of word lines WL 0, WL 1,..., WLm, and drives the word lines connected to the memory cells selected by the memory control circuit 70. The source line drive circuit 50 is connected to the plurality of source lines SL1, SL2,..., SLm, and drives the source line connected to the memory cell selected by the memory control circuit 70.

  Switch circuit 60 includes, for example, a plurality of transistors respectively connected to a path of a plurality of bit lines BL0, BL1,..., BLn, which are turned on or off under control of memory control circuit 70. Do. The memory control circuit 70 can be connected to the memory cells connected to the plurality of bit lines BL0, BL1,..., BLn via the switch circuit 60.

  The memory control circuit 70 includes, for example, a logic circuit including a combinational circuit and a sequential circuit, an analog circuit, and the like, and includes reference cells RC1 and RC2, a data read circuit 71, and a verify circuit 72. The memory control circuit 70 is supplied with a chip select signal CS, a mode select signal MS, an operation clock signal CK, and an address signal AD.

  When the nonvolatile memory is selected by the chip select signal CS, the memory control circuit 70 performs the erase mode, the write mode, the read mode, the memory cell verify mode, or the reference according to the mode select signal MS. Set to cell verify mode.

  In the write mode, the read mode, and the verify mode of the memory cell, the memory control circuit 70 accesses each part of the non-volatile memory to access the memory cell designated by the address signal AD in synchronization with the operation clock signal CK. Control.

  In the write mode, the memory control circuit 70 inputs write data, and controls each part of the non-volatile memory to write data in the memory cell designated by the address signal AD. In the read mode and the memory cell verify mode, the memory control circuit 70 controls each part of the non-volatile memory to read data from the memory cell designated by the address signal AD, and outputs read data.

  For example, in the read mode, the memory control circuit 70 turns on the transistor of the switch circuit 60 connected to the memory cell designated by the address signal AD, and reads data based on the read current flowing to the memory cell. At this time, the data read circuit 71 generates a determination current based on the current flowing in the reference cell RC1 and the current flowing in the reference cell RC2, and uses the read current flowing in the memory cell designated by the address signal AD as the determination current. By comparing, it is determined whether the data stored in the designated memory cell is "0" or "1".

<Memory cell array>
FIG. 2 is a circuit diagram showing a configuration example of the memory cell array shown in FIG. 1 and the periphery thereof. Each memory cell MC includes an N-channel MOS transistor having a control gate, a floating gate, a source, and a drain. The transistor of the memory cell MC stores one bit of data according to the charge stored in the floating gate.

  Each of word lines WL0 to WLm is connected to the control gate of the transistor of the plurality of memory cells MC arranged in each row. Each of source lines SL0 to SLm is connected to the sources of the transistors of the plurality of memory cells MC arranged in each row. Further, each of the bit lines BL0 to BLn is connected to the drains of the transistors of the plurality of memory cells MC arranged in each column.

  Word line drive circuit 40 (FIG. 1) includes a plurality of word line drivers 41 for driving control gates of the transistors of memory cells MC connected to word lines WL0 to WLm, a plurality of N channel MOS transistors 42, and word lines. And an inverter 43 for supplying a high potential side power supply potential of the driver 41. Each word line driver 41 is configured by, for example, a level shifter, a buffer circuit, or an inverter. The word line power supply potential VWL or the word line boosted potential VUP is supplied from the inverter 43 to each word line driver 41.

  A high active row selection signal activated to a high level when selecting one or more rows of memory cells from among the plurality of memory cells constituting the memory cell array is input to the input terminals of the plurality of word line drivers 41. SW0 to SWm are input from the memory control circuit 70. Word line driver 41 outputs word line power supply potential VWL or word line boosted potential VUP to the word line when the row selection signal is active, and the reference power supply potential VSS when the row selection signal is non-active. Output to word line.

  Source line drive circuit 50 (FIG. 1) includes source line driver 51, a plurality of transmission gates TG, and a plurality of inverters 52 in order to drive the sources of the transistors of memory cells MC connected to source lines SL0 to SLm. And contains. The source line driver 51 is configured by, for example, a level shifter, a buffer circuit, or an inverter. The plurality of transmission gates TG are connected between the output terminal of the source line driver 51 and the source lines SL0 to SLm.

  The source line power supply potential VSL is supplied to the source line driver 51 from the power supply circuit 20 (FIG. 1). A high active source line drive signal SSL, which is activated to a high level when applying a high power supply potential to the source line, is input from the memory control circuit 70 to the input terminal of the source line driver 51. The source line driver 51 outputs the source line power supply potential VSL when the source line drive signal SSL is active, and outputs the reference power supply potential VSS when the source line drive signal SSL is non-active.

  Each transmission gate TG is formed of an N channel MOS transistor and a P channel MOS transistor, and functions as a switch circuit that opens and closes the connection between the output terminal of the source line driver 51 and the source line. In the transmission gate TG, the gate of the N channel MOS transistor is connected to the output terminal of the word line driver 41, and the gate of the P channel MOS transistor is connected to the output terminal of the inverter 52.

  Word line power supply potential VWL or word line boosted potential VUP is supplied to inverter 52 from word line drive circuit 40 (FIG. 1). Row selection signals SW0 to SWm are input to input terminals of the inverter 52. The inverter 52 inverts the row selection signals SW0 to SWm, and applies the inverted signal to the gate of the P-channel MOS transistor of the transmission gate TG.

  Switch circuit 60 includes N channel MOS transistors Q0 to Qn connected between the memory control circuit 70 and the drains of the transistors of memory cells MC connected to bit lines BL0 to BLn. The gates of the transistors Q0 to Qn are high active column selection signals SB0 to SBn which are activated to a high level when one or more memory cells are selected from the plurality of memory cells constituting the memory cell array. Is applied from the memory control circuit 70.

  In the write mode, memory control circuit 70 activates corresponding row selection signal and column selection signal to select the word line and bit line connected to memory cell MC designated by the address signal, and other than that. The row selection signal and the column selection signal are made inactive, and the source line drive signal SSL is made active. Hereinafter, as an example, the case where word line WL0 and bit line BL0 are selected will be described.

  The high power supply potential VPP is supplied to the inverter 43, the source line driver 51, and the inverter 52. The high power supply potential VPP is supplied to the high potential side power supply terminal of the word line driver 41 by the inverter 43 to which the non-active erase mode signal ER is input. The word line driver 41 to which the active row selection signal SW0 is input outputs the high power supply potential VPP to the word line WL0. Further, the source line driver 51 to which the active source line drive signal SSL is input outputs the high power supply potential VPP.

  The inverter 52 to which the active row selection signal SW0 is input inverts the high power supply potential VPP, and applies the reference power supply potential VSS to the gate of the P-channel MOS transistor of the transmission gate TG. Thereby, transmission gate TG is turned on, and high power supply potential VPP output from source line driver 51 is applied to source line SL0.

  Further, the transistor Q0 of the switch circuit 60 to which the active column selection signal SB0 is input is turned on, and the memory control circuit 70 applies the reference power supply potential VSS to the bit line BL0. Thus, memory control circuit 70 applies word line drive circuit 40 (FIG. 1) and source line drive circuit to apply high power supply potential VPP to the control gate and source of the transistor of memory cell MC specified by the address signal. While controlling 50 (FIG. 1), the reference power supply potential VSS is applied to the drain.

  As a result, current flows from the source to the drain of the transistor of the memory cell MC specified by the address signal. The hot carriers (electrons in this embodiment) generated by the current are injected into the floating gate, so that negative charges are accumulated in the floating gate, and thus the threshold voltage of the transistor is increased.

  On the other hand, the word line driver 41 to which non-active row selection signals SW1 to SWm are input outputs the reference power supply potential VSS to the word lines WL1 to WLm. The inverter 52 receiving the non-active row selection signals SW1 to SWm inverts the reference power supply potential VSS and applies the high power supply potential VPP to the gate of the P channel MOS transistor of the transmission gate TG. Therefore, the transmission gate TG connected to the word lines WL1 to WLm is turned off. Further, the transistors Q1 to Qn of the switch circuit 60 to which the non-active column selection signals SB1 to SBn are input are turned off. As a result, since no current flows between the source and drain of the transistor of the memory cell MC not designated by the address signal, the threshold voltage of the transistor does not change.

  In the erase mode, memory control circuit 70 activates the corresponding row select signal to select the word line connected to memory cell MC designated by the address signal, and makes the other row select signals non-active. At the same time, the column selection signals SB0 to SBn are deactivated, and the source line drive signal SSL is activated. Hereinafter, the case where word line WL0 is selected will be described as an example.

  The high power supply potential VPP is supplied to the inverter 43, the source line driver 51, and the inverter 52. The reference power supply potential VSS is applied to the high potential side power supply terminal of the word line driver 41 by the inverter 43 to which the active erase mode signal ER is input. The word line driver 41 to which the active row selection signal SW0 is input is not activated, but the reference power supply potential VSS is applied to the word line WL0 by the N channel MOS transistor 42 having the gate to which the active erase mode signal ER is applied. Ru. Further, the source line driver 51 to which the active source line drive signal SSL is input outputs the high power supply potential VPP.

  The inverter 52 to which the active row selection signal SW0 is input inverts the high power supply potential VPP, and applies the reference power supply potential VSS to the gate of the P-channel MOS transistor of the transmission gate TG. As a result, the P-channel MOS transistor of transmission gate TG is turned on, and high power supply potential VPP output from source line driver 51 is applied to source line SL0.

  In addition, the transistors Q0 to Qn of the switch circuit 60 to which the non-active column selection signals SB0 to SBn are input are turned off. Thus, the memory control circuit 70 turns off the transistors Q0 to Qn of the switch circuit 60 to make the drain of the transistor of the memory cell MC open (high impedance state), and applies the reference power supply potential VSS to the control gate. Thus, the word line drive circuit 40 (FIG. 1) is controlled, and the source line drive circuit 50 (FIG. 1) is controlled to apply the high power supply potential VPP to the source. As a result, when the negative charge is accumulated in the floating gate of the transistor of the memory cell MC, the negative charge accumulated in the floating gate is released to the source, and the threshold voltage of the transistor is lowered.

  On the other hand, inverter 52 receiving non-active row selection signals SW1 to SWm inverts reference power supply potential VSS to apply high power supply potential VPP to the gate of the P channel MOS transistor of transmission gate TG. Therefore, the transmission gate TG connected to the word lines WL1 to WLm is turned off. As a result, since the negative charge stored in the floating gate of the transistor of the memory cell MC not designated by the address signal is not discharged, the threshold voltage of the transistor does not change.

  In the read mode, memory control circuit 70 activates corresponding row selection signal and column selection signal to select the word line and bit line connected to the memory cell specified by the address signal, and other rows. The selection signal and the column selection signal are made non-active, and the source line drive signal SSL is made non-active. Hereinafter, as an example, the case where word line WL0 and bit line BL0 are selected will be described.

  The word line boosted potential VUP is supplied to the inverters 43 and 52, and the logic power supply potential VDD is supplied to the source line driver 51. The word line boosted potential VUP is supplied to the high potential side power supply terminal of the word line driver 41 by the inverter 43 to which the non-active erase mode signal ER is input. The word line driver 41 to which the active row selection signal SW0 is input outputs the word line boosted potential VUP to the word line WL0. In addition, the source line driver 51 to which the non-active source line drive signal SSL is input outputs the reference power supply potential VSS.

  Word line boosted potential VUP output from word line driver 41 is also applied to the gate of the N channel MOS transistor of transmission gate TG connected to word line WL0. Thereby, the N channel MOS transistor of the transmission gate TG is turned on, and the reference power supply potential VSS output from the source line driver 51 is applied to the source line SL0.

  Further, the transistor Q0 of the switch circuit 60 to which the active column selection signal SB0 is input is turned on, and the memory control circuit 70 applies the logic power supply potential VDD to the bit line BL0. Thus, the memory control circuit 70 controls the word line drive circuit 40 (FIG. 1) to apply the word line boosted potential VUP to the control gate of the transistor of the memory cell MC specified by the address signal. The source line drive circuit 50 (FIG. 1) is controlled to apply the reference power supply potential VSS, and the transistor Q0 of the switch circuit 60 is turned on to apply the logic power supply potential VDD to the drain.

  As a result, in the memory cell MC specified by the address signal, a drain current flows from the drain to the source of the transistor of the memory cell MC. Since the magnitude of the drain current differs depending on the amount of negative charge stored in the floating gate, the memory control circuit 70 can read data from the memory cell MC based on the magnitude of the drain current. In the memory cell verify mode, logic power supply potential VDD is supplied to inverters 43 and 52 instead of word line boosted potential VUP.

<Data readout circuit>
FIG. 3 is a circuit diagram showing a configuration example of the data read circuit shown in FIG. 1 and its periphery. Each of reference cells RC1 and RC2 includes an N-channel MOS transistor having a control gate, a floating gate, a source, and a drain.

  The transistor of the reference cell RC1 has a first threshold voltage, and the transistor of the reference cell RC2 has a second threshold voltage larger than the first threshold voltage. That is, the reference cell RC1 is in the erased state, and the reference cell RC2 is in the written state.

  The first drive potential WL is applied by the word line drive circuit 40 (FIG. 1) to the control gate of the transistor of the memory cell MC designated by the address signal. For example, the first drive potential WL is the word line boosted potential VUP in the read mode, the logic power supply potential VDD in the verify mode of the memory cell, and the reference power supply potential VSS in the verify mode of the reference cell.

  Further, the second drive potential RWL is applied to the control gates of the transistors of the reference cells RC1 and RC2 by the memory control circuit 70 (FIG. 1). For example, the second drive potential RWL is the word line boosted potential VUP in the read mode, and is the logic power supply potential VDD in the verify mode of the memory cell and the verify mode of the reference cell. The reference power supply potential VSS is supplied to the memory cells MC and the sources of the transistors of the reference cells RC1 and RC2.

  In the read mode and the memory cell verify mode, the data read circuit 71 generates a determination current based on the current flowing in the reference cell RC1 and the current flowing in the reference cell RC2, and compares the current flowing in the memory cell MC with the determination current By doing this, the data stored in the memory cell MC is read.

  Further, in the reference cell verify mode, the data read circuit 71 compares the current proportional to the current flowing to the reference cell RC2 with the current proportional to the current flowing to the reference cell RC1, and the verify circuit 72 (FIG. 1) It is confirmed whether the threshold voltage of the reference cell RC2 is appropriate. If the threshold voltage of the reference cell RC2 is not appropriate, the verify circuit 72 can correct the threshold voltage of the reference cell RC2.

  For example, as shown in FIG. 3, the data read circuit 71 includes P channel MOS transistors QP1 to QP10, N channel MOS transistors QN1 to QN5, an inverter IN1, and a sense amplifier 71a. Sense amplifier 71a includes P-channel MOS transistors QP11-QP14, N-channel MOS transistors QN6-QN8, inverters IN2 and IN3, and has an input terminal IN and an output terminal OUT.

  The logic power supply potential VDD is supplied to the sources of the transistors QP1 to QP3, and the gate is connected to the drain of the transistor QP1 and the drain of the transistor of the reference cell RC1. Here, the transistors QP1 to QP3 constitute a first current mirror circuit that supplies a current (four types of currents in FIG. 3) proportional to the current flowing to the reference cell RC1.

  The drain of the transistor QP2 is connected to the input terminal IN of the sense amplifier 71a via the transistor QP4. The drain of the transistor QP3 is connected to the input terminal IN of the sense amplifier 71a via the transistor QP5. The current setting signal E0 is applied to the gate of the transistor QP4, and the current setting signal E1 is applied to the gate of the transistor QP5. Here, the transistors QP4 and QP5 constitute a first selector circuit which selects the magnitude of the current supplied from the first current mirror circuit in accordance with the current setting signals E0 and E1.

  Memory control circuit 70 (FIG. 1) sets current setting signals E0 and E1 to low level (for example, reference power supply potential VSS) or high level according to the read mode, memory cell verify mode, and reference cell verify mode. (For example, it is set to the logic power supply potential VDD).

  When the current setting signal E0 is activated to a low level, the transistor QP4 is turned on to supply the current supplied from the drain of the transistor QP2 to the input terminal IN of the sense amplifier 71a. Further, when the current setting signal E1 is activated to a low level, the transistor QP5 is turned on to supply the current supplied from the drain of the transistor QP3 to the input terminal IN of the sense amplifier 71a.

  The logic power supply potential VDD is supplied to the sources of the transistors QP6 to QP8, and the gate is connected to the drain of the transistor QP6 and the drain of the transistor of the reference cell RC2. Here, the transistors QP6 to QP8 constitute a second current mirror circuit that supplies a current proportional to the current flowing to the reference cell RC2 (which may be a current substantially equal to the current flowing to the reference cell RC2).

  The drain of the transistor QP7 is connected to the input terminal IN of the sense amplifier 71a via the transistor QP9. The drain of the transistor QP8 is connected to the drain of the transistor QN1 via the transistor QP10. The verify signal VFY for setting the verify mode of the reference cell is applied to the gate of the transistor QP9, and the verify signal VFY inverted by the inverter IN1 is applied to the gate of the transistor QP10. Here, the transistors QP9 and QP10 and the inverter IN1 constitute a second selector circuit that selects the supply destination of the current supplied from the second current mirror circuit according to the verify signal VFY.

  The memory control circuit 70 (FIG. 1) sets the verify signal VFY to the low level in the read mode and the verify mode of the memory cell, and sets the verify signal VFY to the high level in the verify mode of the reference cell.

  Therefore, in the read mode and the verify mode of the memory cell, the transistor QP9 is turned on, and the current supplied from the drain of the transistor QP7 is supplied to the input terminal IN of the sense amplifier 71a. On the other hand, in the verify mode of the reference cell, the transistor QP10 is turned on, and the current supplied from the drain of the transistor QP8 is supplied to the drain of the transistor QN1.

  A verify signal VFY is applied to the gates of the transistors QN1 and QN2. The drain of the transistor QN3 is connected to the drain of the transistor QP8 via the transistors QN1 and QP10. The drain of the transistor QN4 is connected to the drain of the transistor QP12 via the transistor QN2.

  The gates of the transistors QN3 and QN4 are connected to the source of the transistor QN1 and the drain of the transistor QN3, and the source is supplied with the reference power supply potential VSS. Here, the transistors QN3 and QN4 constitute a third current mirror circuit that supplies a current proportional to the current supplied from the second current mirror circuit in the verify mode of the reference cell.

  In the read mode and the memory cell verify mode, the transistors QN1 and QN2 are turned off, so the third current mirror circuit does not operate. The data read circuit 71 generates a determination current by adding the current supplied from the first current mirror circuit and the current supplied from the second current mirror circuit, and the determination current is input to the input terminal of the sense amplifier 71a. Supply to IN.

  Further, in the verify mode of the reference cell, the transistors QN1 and QN2 are turned on, so the third current mirror circuit operates. The data read circuit 71 supplies the current supplied from the first current mirror circuit to the input terminal IN of the sense amplifier 71a, and the memory cell MC which turns off the current supplied from the third current mirror circuit. The voltage is supplied to the sense amplifier 71a in place of the transistor of FIG.

  The drain and gate of the transistor QN5 are connected to the input terminal IN of the sense amplifier 71a, and the reference power supply potential VSS is supplied to the source of the transistor QN5. Therefore, the current supplied to the input terminal IN of the sense amplifier 71a flows to the transistor QN5.

<Sense amplifier>
In the sense amplifier 71a, the gate of the transistor QN6 is connected to the input terminal IN, and the reference power supply potential VSS is supplied to the source. The transistor QN5 and the transistor QN6 constitute a current mirror circuit, and the determination current generated by the first current mirror circuit and the second current mirror circuit flows to the transistor QN6.

  The logic power supply potential VDD is supplied to the sources of the transistors QP11 and QP12, and the gate is connected to the drain of the transistor QP11 and the drain of the transistor QN6. Here, the transistors QP11 and QP12 have the same size, and constitute a current mirror circuit that supplies a current substantially equal to the current flowing through the transistor QN6. The drain of the transistor QP12 is connected to the drain of the transistor of the memory cell MC and the drain of the transistor QN2.

  In the read mode and the verify mode of the memory cell, a current flows to the transistor of the memory cell MC according to the first drive potential WL, and to the transistor QN6 based on the current flowing to the reference cell RC1 and the current flowing to the reference cell RC2. The generated determination current flows. The determination current also flows through the transistors QP11 and QP12.

  Therefore, if the current flowing to the memory cell MC is larger than the determination current, the drain potential of the transistor QP12 is lower than the drain potential of the transistor QP11. On the other hand, if the current flowing to the memory cell MC is smaller than the determination current, the drain potential of the transistor QP12 becomes higher than the drain potential of the transistor QP11.

  In the verify mode of the reference cell, a current proportional to the current flowing to the reference cell RC2 flows to the transistor QN2, and a current proportional to the current flowing to the reference cell RC1 flows to the transistor QN6. Also, a current proportional to the current flowing to the reference cell RC1 flows to the transistors QP11 and QP12.

  Therefore, if the current proportional to the current flowing to the reference cell RC2 is larger than the current proportional to the current flowing to the reference cell RC1, the drain potential of the transistor QP12 becomes lower than the drain potential of the transistor QP11. On the other hand, if the current proportional to the current flowing to the reference cell RC2 is smaller than the current proportional to the current flowing to the reference cell RC1, the drain potential of the transistor QP12 becomes higher than the drain potential of the transistor QP11.

  The logic power supply potential VDD is supplied to the sources of the transistors QP13 and QP14, and the gates are connected to the drain of the transistor QP11 and the drain of the transistor QP12, respectively. Therefore, transistors QP13 and QP14 flow respective currents according to the drain potentials of transistors QP11 and QP12.

  The drain of the transistor QN7 is connected to the drain of the transistor QP13, and the drain of the transistor QN8 is connected to the drain of the transistor QP14. The gates of the transistors QN7 and QN8 are connected to the drain of the transistor QP13 and the drain of the transistor QN7, and the source is supplied with the reference power supply potential VSS. Here, the transistors QN7 and QN8 have the same size, and constitute a current mirror circuit that supplies a current substantially equal to the current flowing through the transistor QP13.

  The drain of the transistor QN8 is connected to the input terminal of the inverter IN2. The output terminal of the inverter IN2 is connected to the input terminal of the inverter IN3, and the output terminal of the inverter IN3 is connected to the output terminal OUT of the sense amplifier. Therefore, if the drain potential of the transistor QP12 is lower than the drain potential of the transistor QP11, a high level determination signal Y is output from the output terminal OUT. On the other hand, if the drain potential of the transistor QP12 is higher than the drain potential of the transistor QP11, a low level determination signal Y is output from the output terminal OUT.

  As described above, in the read mode and the verify mode of the memory cell, the sense amplifier 71a causes the current flowing to the memory cell MC to be the current supplied from the first current mirror circuit and the current supplied from the second current mirror circuit. And a determination signal Y representing a comparison result is output. Further, in the verify mode of the reference cell, the sense amplifier 71a compares the current supplied from the third current mirror circuit with the current supplied from the first current mirror circuit, and outputs the determination signal Y indicating the comparison result. Output.

  Thereby, in the read mode, the sense amplifier 71a compares the current flowing to the memory cell MC with the determination current generated based on the current flowing to the reference cell RC1 and the current flowing to the reference cell RC2, and flows to the memory cell MC. When the current is larger than the determination current, a high level determination signal Y is output.

  Further, in the verify mode of the reference cell, the sense amplifier 71a compares the current proportional to the current flowing to the reference cell RC2 with the current proportional to the current flowing to the reference cell RC1, and transmits the current flowing to the reference cell RC2 to the reference cell RC1. When the current is larger than the flowing current, a high level determination signal Y is output.

  As described above, since the same sense amplifier 71a can be shared in the read mode and the verify mode of the reference cell, the threshold voltage of the reference cell can be accurately confirmed without increasing the circuit scale.

<Example of judgment level setting>
FIG. 4 is a diagram showing an example of setting of determination levels in the read mode of the data read circuit shown in FIG. In FIG. 4, the horizontal axis represents the drive potential applied to the control gate of the reference cell RC1 or RC2, and the vertical axis represents the current Icell flowing in the reference cell RC1 or RC2. The solid line (a) represents the current flowing to the reference cell RC1 in the erase (erasing) state, and the solid line (b) represents the current flowing to the reference cell RC2 in the programmed (writing) state.

  For example, by setting the current supplied from the first current mirror circuit to about one third of the current flowing to the reference cell RC1 by the current setting signals E0 and E1 shown in FIG. Judgment level is obtained. Furthermore, the current supplied from the second current mirror circuit is set to about one time the current flowing to the reference cell RC2, and the current supplied from the first current mirror circuit and the current supplied from the second current mirror circuit The determination level represented by the broken line (d) is obtained by adding the current.

  The determination level represented by the broken line (d) corresponds to a determination current to be compared when reading data stored in the memory cell in the read mode. As described above, by setting the determination level based on the current flowing in the reference cell RC1 and the current flowing in the reference cell RC2, the influence of the temperature and the power supply voltage when reading data from the memory cell MC can be reduced. .

  In the memory cell verify mode, different determination levels may be used for erase verify for verifying the memory cell MC in the erase state and for program verify for verifying the memory cell MC in the program state. Thereby, the determination level can be set more strictly than in the read mode, and the reliability of data stored in the memory cell MC can be enhanced.

  For example, in erase verify, the current supplied from the first current mirror circuit is set to about 1⁄2 times the current flowing to the reference cell RC1, and the current supplied from the second current mirror circuit is set to the reference cell RC2. The determination current may be generated by setting the current flowing in the first current mirror circuit to about one time and adding the current supplied from the first current mirror circuit and the current supplied from the second current mirror circuit. .

  On the other hand, in the program verify, the current supplied from the first current mirror circuit is set to about 1/10 of the current flowing to the reference cell RC1, and the current supplied from the second current mirror circuit is set to the reference cell RC2. The determination current may be generated by setting the current flowing in the first current mirror circuit to about one time and adding the current supplied from the first current mirror circuit and the current supplied from the second current mirror circuit. .

  As described above, according to the present embodiment, when the data stored in the memory cell MC is read, the determination current to be compared is based on the current flowing to the reference cell RC1 and the current flowing to the reference cell RC2. It can be set appropriately. Further, the determination current can be changed in the read mode and the verify mode of the memory cell.

  However, due to the variation of the threshold voltage of the reference cell RC2, an error may occur when reading data stored in the memory cell MC. Therefore, in order to confirm or correct the threshold voltage of the reference cell RC2, a verify mode of the reference cell is provided.

<Verify circuit>
FIG. 5 is a circuit diagram showing a configuration example of the verify circuit shown in FIG. FIG. 6 is a timing chart showing an operation example of the verify circuit shown in FIG. The verify circuit 72 sets the threshold voltage of the reference cell RC2 based on the threshold voltage of the reference cell RC1 shown in FIG. In the verify mode of the reference cell, only the reference cell RC2 is to be verified. Therefore, the decoding circuit for selecting the reference cell is not necessary, and the threshold voltage of the reference cell is not increased. Can be set accurately.

  For example, in the verify mode of the reference cell, the data read circuit 71 compares the current proportional to the current flowing to the reference cell RC2 with the current proportional to the current flowing to the reference cell RC1. The verify circuit 72 raises the threshold voltage of the reference cell RC2 when the current proportional to the current flowing to the reference cell RC2 is larger than the current proportional to the current flowing to the reference cell RC1. Thus, the threshold voltage of the reference cell RC2 can be accurately set in accordance with the ratio of the current flowing to the reference cell RC1 and the current flowing to the reference cell RC2.

  As shown in FIG. 5, the verify circuit 72 includes inverters IN4 and IN5, a NAND circuit 81, flip flops 82 and 83, AND circuits 84 to 86, and an OR circuit 87. The inverter IN4 inverts the determination signal Y and outputs the inverted determination signal. The inverter IN5 inverts the chip enable signal XCE of negative logic and outputs a chip enable signal of positive logic.

  The NAND circuit 81 inverts the clock signal CK and outputs an inverted clock signal when the chip enable signal XCE is at low level (L) and the verify signal VFY is at high level (H). The clock signal CK may be supplied to the semiconductor integrated circuit device from an LSI tester or the like.

  The flip flops 82 and 83 are reset when the verify signal VFY is inactivated to low level, and the reset is released when the verify signal VFY is activated to high level. The flip-flop 82 divides the clock signal CK in synchronization with the falling of the clock signal CK, and outputs a divided clock signal CK2. Flip-flop 83 latches inverted determination signal Y in synchronization with the rising of divided clock signal CK2. Therefore, from the inverted data output terminal X of the flip flop 83, the determination signal Y latched in synchronization with the rising of the divided clock signal CK2 is output.

  The AND circuit 84 outputs a high level output signal when the divided clock signal CK2 and the determination signal Y output from the inverted data output terminal X of the flip flop 83 are at high level, and in the other cases, Output a low level output signal.

  Since the program mode signal PRG is activated to the high level in the write mode, it is inactivated to the low level in the verify mode of the reference cell. When the program mode signal PRG is at the high level and the verify signal VFY is at the low level, the AND circuit 85 having a single-sided inverting input outputs an output signal at the high level. In the verify mode of the reference cell, since the verify signal VFY is at high level, the AND circuit 85 outputs a low level output signal.

  The AND circuit 86 outputs a high level output signal when the verify signal VFY is high level and the output signal of the AND circuit 84 is high level, and otherwise outputs a low level output signal. Do. Further, OR circuit 87 activates internal program mode signal INTPRG to high level when the output signal of AND circuit 85 or 86 is at high level, and otherwise makes internal program mode signal INTPRG to low level. Deactivate. Therefore, in the verify mode of the reference cell, the internal program mode signal INTPRG is the same as the divided clock signal CK2 when the determination signal Y is high level, and becomes low level after the determination signal Y becomes low level. .

  In the verify mode of the reference cell, the memory control circuit 70 (FIG. 1) operates the sense amplifier 71a shown in FIG. 3 while the internal program mode signal INTPRG is at the low level. The sense amplifier 71a compares the current proportional to the current flowing to the reference cell RC2 (which may be a current substantially equal to the current flowing to the reference cell RC2) with the current proportional to the current flowing to the reference cell RC1 to determine the comparison result Output signal Y.

  At that time, for example, the determination level represented by the broken line (c) in FIG. 4 is used. The determination level can be adjusted by changing the mirror ratio by the current setting signal E0 and the current setting signal E1 of the first current mirror circuit shown in FIG. Further, as shown in FIG. 4, the determination level changes depending on the logic power supply potential VDD. Therefore, a finer determination level adjustment is possible by adjusting the logic power supply potential VDD using an LSI tester or the like. It becomes.

  If the determination signal Y is high, the reference cell RC2 is programmed in synchronization with the clock signal C while the internal program mode signal INTPRG is high. That is, the high power supply potential VPP is applied to the control gate and the source of the transistor of the reference cell RC2, the reference power supply potential VSS is applied to the drain, and the reference cell RC2 is set to the write mode. As a result, the threshold voltage of the reference cell RC2 is increased.

  Next, while internal program mode signal INTPRG is at a low level, sense amplifier 71a again compares the current proportional to the current flowing to reference cell RC2 with the current proportional to the current flowing to reference cell RC1. , And outputs a determination signal Y representing a comparison result.

  If the determination signal Y is high level, the program of the reference cell RC2 is repeated, and the threshold voltage of the reference cell RC2 is further increased. At that time, the high power supply potential VPP for data writing may be supplied from the LSI tester to the semiconductor integrated circuit device, and the high power supply potential VPP may be raised according to the number of times of programming of the reference cell RC2. Alternatively, the clock signal CK may be supplied from the LSI tester to the semiconductor integrated circuit device, and the cycle of the clock signal CK may be increased according to the number of times of programming of the reference cell RC2.

  When the threshold voltage of the reference cell RC2 rises, the current flowing to the reference cell RC1 decreases, and the determination signal Y goes low, the internal program mode signal INTPRG goes low even if the divided clock signal CK2 goes high. Maintain the level. In such a case, the memory control circuit 70 (FIG. 1) ends the verification mode of the reference cell.

<Electronic equipment>
Next, an electronic device according to an embodiment of the present invention will be described with reference to FIG.
FIG. 7 is a block diagram showing a configuration example of an electronic device according to an embodiment of the present invention. The electronic device 100 includes a semiconductor integrated circuit device 110 according to an embodiment of the present invention, a CPU 120, an operation unit 130, a ROM (read only memory) 140, a RAM (random access memory) 150, and a communication unit. A display unit 170 and an audio output unit 180 may be included. Note that some of the components shown in FIG. 7 may be omitted or changed, or other components may be added to the components shown in FIG.

  The semiconductor integrated circuit device 110 includes a non-volatile memory, and performs various processes in response to a command from the CPU 120. For example, the semiconductor integrated circuit device 110 corrects the input data or converts the data format based on the parameters stored in the non-volatile memory.

  The CPU 120 performs various arithmetic processing and control processing using data and the like supplied from the semiconductor integrated circuit device 110 according to a program stored in the ROM 140 or the like. For example, the CPU 120 performs various data processing in accordance with the operation signal supplied from the operation unit 130, controls the communication unit 160 to perform data communication with the outside, or performs various operations on the display unit 170. It generates an image signal for displaying an image, and generates an audio signal for causing the audio output unit 180 to output various types of audio.

  The operation unit 130 is an input device including, for example, operation keys and a button switch, and outputs an operation signal according to an operation by the user to the CPU 120. The ROM 140 stores programs, data, and the like for the CPU 120 to perform various types of arithmetic processing and control processing. In addition, the RAM 150 is used as a work area of the CPU 120, and temporarily stores programs and data read from the ROM 140, data input using the operation unit 130, or an operation result executed by the CPU 120 according to the program. Do.

  The communication unit 160 includes, for example, an analog circuit and a digital circuit, and performs data communication between the CPU 120 and an external device. The display unit 170 includes, for example, an LCD (liquid crystal display device) and the like, and displays various types of information based on a display signal supplied from the CPU 120. Further, the audio output unit 180 includes, for example, a speaker, and outputs audio based on an audio signal supplied from the CPU 120.

  The electronic device 100 may be, for example, a smart card, a calculator, an electronic dictionary, an electronic game device, a mobile terminal such as a mobile phone, a digital still camera, a digital movie, a television, a videophone, a television monitor for crime prevention, a head mounted display, personal Computers, printers, network devices, car navigation devices, measuring devices, and medical devices (for example, electronic thermometers, sphygmomanometers, blood glucose meters, electrocardiogram measuring devices, ultrasound diagnostic devices, electronic endoscopes, etc.) .

  According to the present embodiment, when the data stored in the non-volatile memory incorporated in the semiconductor integrated circuit device 110 is read, the determination current to be compared is appropriately determined based on the current flowing through the two reference cells. An electronic device that can be set can be provided. For example, the ROM 140 can be omitted by storing the program in the nonvolatile memory of the semiconductor integrated circuit device 110, or the RAM 150 can be omitted by storing data in the nonvolatile memory of the semiconductor integrated circuit device 110.

  In the above embodiments, the case where the threshold voltage of the reference cell is set has been described. However, the present invention may be applied to the case where the threshold voltage of the memory cell for level detection used when boosting the control gate voltage The invention can be applied. As described above, the present invention is not limited to the embodiments described above, and many modifications can be made within the technical concept of the present invention by those skilled in the art.

  DESCRIPTION OF SYMBOLS 10 memory cell array 20 power circuit 30 word line booster circuit 40 word line drive circuit 41 word line driver 42 N channel MOS transistor 43 inverter 50 source line drive circuit 51 Source line driver, 52: inverter, 60: switch circuit, 70: memory control circuit, 71: data read circuit, 71: sense amplifier, 72: verify circuit, 81: NAND circuit, 82, 83: flip flop, 84 to 86 ... AND circuit, 87 ... OR circuit, 100 ... electronic equipment, 110 ... semiconductor integrated circuit device, 120 ... CPU, 130 ... operation unit, 140 ... ROM, 150 ... RAM, 160 ... communication unit, 170 ... display unit, 180 ... Voice output unit, WL0 to WLm: Word line, SL0 to SLm: Source line, BL ~ BLn ... Bit line, TG ... Transmission gate, MC ... Memory cell, Q0-Qn ... N channel MOS transistor, QP1-QP14 ... P channel MOS transistor, RC1, RC2 ... Reference cell, QN1 to QN8 ... N channel MOS transistor, IN1 to IN5: Inverter

Claims (4)

A memory cell including a transistor for storing data,
A first reference cell including a transistor having a first threshold voltage;
A second reference cell comprising a transistor having a second threshold voltage greater than the first threshold voltage;
A determination current is generated based on the current flowing in the first reference cell and the current flowing in the second reference cell, and stored in the memory cell by comparing the current flowing in the memory cell with the determination current. A data readout circuit that reads out the current data,
In the read mode, the data read circuit compares the current flowing in the memory cell with the determination current, and in the verify mode of the reference cell, the current proportional to the current flowing in the second reference cell and the current flowing in the first reference cell A sense amplifier that compares a current proportional to the current and outputs a determination signal representing a comparison result;
Equipped with
The data readout circuit includes a first current mirror circuit that supplies a current proportional to the current flowing to the first reference cell, and a second current that supplies a current proportional to the current flowing to the second reference cell. A mirror circuit, a selector circuit for selecting a supply destination of current supplied from the second current mirror circuit according to a signal for setting a verify mode of a reference cell, and the second current mirror in the verify mode of the reference cell A third current mirror circuit supplying a current proportional to the current supplied from the circuit;
The sense amplifier is configured such that, in the read mode, a determination current which is a sum of a current flowing through the memory cell, a current supplied from the first current mirror circuit, and a current supplied from the second current mirror circuit. , And comparing the current supplied from the third current mirror circuit with the current supplied from the first current mirror circuit in a verify mode of a reference cell .   The semiconductor integrated circuit device according to claim 1, further comprising a verify circuit that sets a threshold voltage of said second reference cell based on a threshold voltage of said first reference cell. The data read circuit compares a current proportional to the current flowing to the second reference cell with a current proportional to the current flowing to the first reference cell in the verify mode of the reference cell,
The verify circuit raises the threshold voltage of the second reference cell when the current proportional to the current flowing to the second reference cell is larger than the current proportional to the current flowing to the first reference cell. ,
The semiconductor integrated circuit device according to claim 2. An electronic device comprising the semiconductor integrated circuit device according to any one of claims 1 to 3 .

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