JP6515607B2 - Semiconductor integrated circuit device and electronic device using the same - Google Patents

Description

  The present invention relates to a semiconductor integrated circuit device incorporating an electrically rewritable nonvolatile memory such as a flash memory or an EEPROM (Electrically Erasable Programmable Read-Only Memory). Furthermore, the present invention relates to an electronic device and the like using such a semiconductor integrated circuit device.

  In recent years, electrically rewritable non-volatile memories such as flash memories and EEPROMs (Electrically Erasable Programmable Read-Only Memories) have become widespread. In such non-volatile memory, when the program (data writing) is performed and the data stored in the memory cell in the state of high threshold voltage is read, the judgment current to be compared is set to a small value. The thing is done.

  As a related technique, Patent Document 1 discloses that, in a nonvolatile semiconductor memory device for identifying memory information by comparing a read signal from a memory element with a reference signal, when reading data from the memory element in a write verify mode. It is disclosed that the value of the reference signal is automatically made higher by a predetermined value than the value of the reference signal at the time of reading of the normal reading operation. That is, in the write verify mode, since the determination current to be compared is set to a smaller value than that in the normal read, high reliability for storage retention of the memory element is ensured.

  Further, Patent Document 2 discloses a nonvolatile semiconductor memory device capable of strictly setting a reference level in the case of performing EEPROM verification. In this nonvolatile semiconductor memory device, the gate voltage of the memory cell is set to be relatively higher than the gate voltage of the reference cell at the time of write verify. As a result, at the time of write verification, determination is made more rigorous than at the time of normal reading.

  Furthermore, in Patent Document 3, the reference driving power of the reference transistor at the program verify time is made lower than that at the time of reading, thereby making the standard for determining the data "0" written in the memory cell transistor strict. It is disclosed to ensure the injection of a sufficient amount of charge into the floating gate.

JP-A-59-104796 (claims, FIG. 5) Unexamined-Japanese-Patent No. 11-306785 (Paragraphs 0008, 0015) JP-A 5-36288 (paragraph 0023)

  As described above, in Patent Documents 1 to 3, the criterion for reading out the data stored in the memory cell in which the threshold voltage is high when the program is performed at the program verify time is higher than that at the time of the normal reading. Set strictly. However, when the leak current flowing to the non-selected memory cell is increased due to overerasing or the like, the magnitude of the determination current to be compared is approached, and the normal determination is made when reading data stored in the memory cell in the write state. May not be able to

  Therefore, in view of the above points, a first object of the present invention is a semiconductor integrated circuit capable of accurately reading data stored in a memory cell by reducing the influence of a leak current flowing to a non-selected memory cell. It is providing a device. A second object of the present invention is to provide an electronic device and the like using such a semiconductor integrated circuit device.

  In order to solve at least a part of the above problems, a semiconductor integrated circuit device according to one aspect of the present invention includes a memory cell including a transistor for storing data according to charges accumulated in the floating gate, and a floating gate. A determination current is generated based on a current flowing through at least one reference cell including a transistor and at least one reference cell transistor whose drive potential is applied to the control gate, and a memory cell where the drive potential is applied to the control gate The data read out circuit reads out the data stored in the memory cell by comparing the current flowing in the transistor with the determination current, and is supplied to the data read out circuit at least in the verify mode of the memory cell in the write state. And a drive voltage generation circuit for generating a driving potential higher than the power supply potential on the high potential side.

  According to one aspect of the present invention, at least in the verify mode of the memory cell in the write state, the drive higher than the high potential power supply potential supplied to the data read circuit is applied to the control gates of the memory cell and reference cell transistors. Potentials are commonly applied. Therefore, it is not necessary to separately generate drive potentials supplied to the memory cell and the reference cell. In addition, since the current flowing to the memory cell and the reference cell is increased, the influence of the leak current flowing to the non-selected memory cell can be reduced, and the data stored in the memory cell can be read correctly. In addition, more stringent criteria can be applied in memory cell verification.

  Here, in the verify mode of the memory cell in the write state, the value of the ratio of the determination current to the current flowing through one reference cell may be larger in the data read circuit than in the read mode. As a result, when verifying the memory cell in the write state, the determination current generated based on the current flowing to the reference cell can be increased, and the influence of the leakage current flowing to the non-selected memory cell can be reduced.

  Further, the drive potential generation circuit may include a booster circuit that boosts the power supply voltage supplied to the data read circuit to generate the drive potential at least in the verify mode of the memory cell in the write state. Thus, a drive potential higher than the high potential power supply potential supplied to the data read circuit can be generated without increasing the type of power supply voltage supplied to the semiconductor integrated circuit device.

  Alternatively, the drive potential generation circuit may include a step-down circuit that steps down the power supply voltage larger than the power supply voltage supplied to the data read circuit to generate the drive potential at least in the verify mode of the memory cell in the write state. As a result, a drive potential higher than the power supply potential on the high potential side supplied to the data read out circuit can be accurately generated based on the reference potential.

  In the above, at least one reference cell includes a first reference cell including a transistor having a first threshold voltage and a second reference cell including a transistor having a second threshold voltage greater than the first threshold voltage. And the data read out circuit includes a first current mirror circuit supplying a current proportional to the current flowing to the first reference cell, and a second current supplying circuit proportional to the current flowing to the second reference cell. Comparing the current flowing to the memory cell in the read mode with the current mirror circuit and the determination current which is the sum of the current supplied from the first current mirror circuit and the current supplied from the second current mirror circuit You may do it.

  Thus, in the read mode, the data read circuit causes the determination current to be compared when reading data stored in the memory cell, the current flowing to the first reference cell and the current flowing to the second reference cell. It can be set appropriately based on

  In that case, the data read circuit further includes a switch circuit for operating or stopping the second current mirror circuit, and in the verify mode of the memory cell in the write state, the current flowing to the memory cell is output from the first current mirror circuit. It may be compared with the supplied current. Thus, the data read circuit can change the determination current in the read mode and the verify mode of the memory cell in the write state.

  An electronic device according to one aspect of the present invention includes any one of the semiconductor integrated circuit devices described above. Thus, it is possible to provide an electronic device capable of accurately reading data stored in a memory cell by reducing the influence of a leak current flowing to a non-selected memory cell.

FIG. 1 is a block diagram showing an example of the configuration of a non-volatile memory according to an embodiment of the present invention. FIG. 2 is a circuit diagram showing a configuration example of a drive potential generation circuit and a memory cell array shown in FIG. 1. FIG. 2 is a circuit diagram showing a configuration example of a booster circuit included in the drive potential generation circuit shown in FIG. 1. FIG. 5 is a waveform chart showing voltage waveforms of respective parts in the booster circuit shown in FIG. 3; FIG. 2 is a circuit diagram showing a configuration example of a step-down circuit included in the drive potential generation circuit shown in FIG. 1. FIG. 2 is a circuit diagram showing a configuration example of a data read circuit shown in FIG. 1 and the periphery thereof. The figure for demonstrating the influence which the leak current which flows into an unselected cell gives. FIG. 7 is a view showing an example of setting determination levels in the data read circuit shown in FIG. 6; FIG. 1 is a block diagram showing an example of the configuration of an electronic device according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same reference numerals are given to the same components, and the overlapping description is omitted.
<Non-volatile memory>
FIG. 1 is a block diagram showing a configuration example of a non-volatile memory built in a semiconductor integrated circuit device according to an embodiment of the present invention. The semiconductor integrated circuit device according to one embodiment of the present invention may incorporate only an electrically rewritable nonvolatile memory such as a flash memory or an EEPROM, or has a predetermined function in addition to the nonvolatile memory. A functional block such as a circuit block or a CPU (central processing unit) may be incorporated. In the following, a flash memory will be described as an example of the non-volatile memory.

  As shown in FIG. 1, the non-volatile memory includes a memory cell array 10, a power supply circuit 20, a drive potential generation circuit 30, a word line drive circuit 40, a source line drive circuit 50, a switch circuit 60, and a memory. And a control circuit 70. The memory control circuit 70 controls the power supply circuit 20 to the switch circuit 60 so that the plurality of memory cells included in the memory cell array 10 perform the erase operation, the write operation, or the read operation.

  The plurality of memory cells of the memory cell array 10 are arranged in a matrix of m rows and n columns (m and n are integers of 2 or more). For example, the memory cell array 10 includes 2048 rows of memory cells. In addition, one row of memory cells includes 1024 memory cells, and can store 128 8-bit data.

  The memory cell array 10 includes a plurality of word lines WL0, WL1,..., WLm, a plurality of source lines SL0, SL1,..., SLm and a plurality of bit lines BL0, BL1,. And contains. Each of those word lines is connected to a plurality of memory cells arranged in each row. Also, each of those bit lines is connected to a plurality of memory cells arranged in each column.

  For example, a reference power supply potential VSS, a high power supply potential VPP for data erasing and data writing, and a logic power supply potential VDD for a logic circuit are supplied to the power supply circuit 20 from the outside. Alternatively, the power supply circuit 20 may generate another power supply potential by stepping up or down one power supply potential of a plurality of externally supplied power supply potentials.

  The reference power supply potential VSS is a reference potential that is a reference relative to other potentials, and in the following, the case where the reference power supply potential VSS is the ground potential (0 V) will be described. The high power supply potential VPP is a predetermined potential higher than the reference power supply potential VSS, and is, for example, about 5V to 10V. The logic power supply potential VDD is a potential higher than the reference power supply potential VSS and lower than the high power supply potential VPP, and is, for example, about 1.2 V to 1.8 V. Logic power supply potential VDD may be shared with the power supply potential of a functional circuit used together with nonvolatile memory in the semiconductor integrated circuit device.

  The power supply circuit 20 supplies the logic power supply potential VDD to the memory control circuit 70 and, under the control of the memory control circuit 70, the high power supply potential VPP and the logic power supply potential VDD to each part of the non-volatile memory as necessary. Supply. In FIG. 1, the power supply potential supplied from power supply circuit 20 to drive potential generation circuit 30 is shown as word line power supply potential VWL, and the power supply potential supplied from power supply circuit 20 to source line drive circuit 50 is the source line. It is shown as power supply potential VSL.

  For example, in the erase mode in which the memory cell is brought into the erase state, the power supply circuit 20 supplies the high power supply potential VPP to the drive potential generation circuit 30 and the source line drive circuit 50. Drive potential generation circuit 30 supplies high power supply potential VPP to word line drive circuit 40.

  In the write mode for writing data to the memory cell, the power supply circuit 20 supplies the high power supply potential VPP to the drive potential generation circuit 30 and the source line drive circuit 50. Drive potential generation circuit 30 supplies high power supply potential VPP to word line drive circuit 40.

  In the read mode in which data is read from the memory cell, the power supply circuit 20 supplies the logic power supply potential VDD to the drive potential generation circuit 30 and the source line drive circuit 50. Drive potential generation circuit 30 generates a drive potential (for example, drive potential VUP) higher than the high potential side power supply potential (logic power supply potential VDD) supplied to data read circuit 71, and generates the drive potential as a word line drive circuit. Supply 40

  In the memory cell verify mode, power supply circuit 20 supplies logic power supply potential VDD to drive potential generation circuit 30 and source line drive circuit 50. Drive potential generation circuit 30 generates a drive potential (for example, drive potential VUP) higher than the high potential side power supply potential (logic power supply potential VDD) supplied to data read circuit 71, and generates the drive potential as a word line drive circuit. Supply 40

  In the verify mode of the reference cell, power supply circuit 20 supplies high power supply potential VPP and logic power supply potential VDD to drive potential generation circuit 30, and supplies high power supply potential VPP to source line drive circuit 50. Drive potential generation circuit 30 supplies high power supply potential VPP and drive potential VUP to word line drive circuit 40.

  The word line drive circuit 40 is connected to the plurality of word lines WL 0, WL 1,..., WLm, and drives the word lines connected to the memory cells selected by the memory control circuit 70. The source line drive circuit 50 is connected to the plurality of source lines SL1, SL2,..., SLm, and drives the source line connected to the memory cell selected by the memory control circuit 70.

  Switch circuit 60 includes, for example, a plurality of transistors respectively connected to a path of a plurality of bit lines BL0, BL1,..., BLn, which are turned on or off under control of memory control circuit 70. Do. The memory control circuit 70 can be connected to the memory cells connected to the plurality of bit lines BL0, BL1,..., BLn via the switch circuit 60.

  The memory control circuit 70 includes, for example, a logic circuit including a combinational circuit and a sequential circuit, an analog circuit, etc., and at least one reference cell (in FIG. 1, reference cells RC1 and RC2 are shown) and a data read circuit 71 and a verify circuit 72. The memory control circuit 70 is supplied with a chip select signal CS, a mode select signal MS, an operation clock signal CK, and an address signal AD.

  When the nonvolatile memory is selected by the chip select signal CS, the memory control circuit 70 performs the erase mode, the write mode, the read mode, the memory cell verify mode, or the reference according to the mode select signal MS. Set to cell verify mode.

  In the write mode, the read mode, and the verify mode of the memory cell, the memory control circuit 70 accesses each part of the non-volatile memory to access the memory cell designated by the address signal AD in synchronization with the operation clock signal CK. Control.

  In the write mode, the memory control circuit 70 inputs write data, and controls each part of the non-volatile memory to write data in the memory cell designated by the address signal AD. In the read mode and the memory cell verify mode, the memory control circuit 70 controls each part of the non-volatile memory to read data from the memory cell designated by the address signal AD, and outputs read data.

  For example, in the read mode and the verify mode of the memory cell, the memory control circuit 70 turns on the transistor of the switch circuit 60 connected to the memory cell specified by the address signal AD, based on the read current flowing to the memory cell. Read out the data.

  At this time, the data read circuit 71 generates a determination current based on the current flowing to at least one reference cell. In addition, the data read circuit 71 compares the current flowing in the memory cell designated by the address signal AD with the determination current, so that the data stored in the designated memory cell is “0” or “1”. Determine if it is.

FIG. 2 is a circuit diagram showing a configuration example of the drive potential generation circuit, the memory cell array, etc. shown in FIG.
<First Example of Drive Potential Generating Circuit>
FIG. 2 shows a configuration example of a booster circuit included in the drive potential generation circuit 30. As shown in FIG. In the first example, drive potential generation circuit 30 boosts the power supply voltage (VDD-VSS) supplied to data read circuit 71 by performing the bootstrap operation in at least the verify mode of the memory cell in the write state. And a booster circuit for generating the drive potential VUP.

  As shown in FIG. 2, drive potential generation circuit 30 includes an inverter 31, a P channel MOS transistor QP30, a P channel MOS transistor QP31 and an N channel MOS transistor QN31 constituting an inverter, a capacitor C0 and a power supply line SPL1. Contains.

  The inverter 31 inverts the boot pulse enable signal BPE and outputs an inverted boot pulse enable signal BPE. The boot pulse enable signal BPE is applied to the gate of the transistor QP30. The word line power supply potential VWL is supplied to the source of the transistor QP30. The power supply line SPL1 is connected to the drain of the transistor QP30.

  The memory control circuit 70 activates the erase mode signal ER to the high level in the erase mode, and deactivates the erase mode signal ER to the low level in the read mode and the verify mode. In the read mode and the verify mode, when boot pulse enable signal BPE is inactivated to a low level, transistor QP30 is turned on to supply word line power supply potential VWL to power supply line SPL1. Here, the word line power supply potential VWL is the same potential as the logic power supply voltage VDD.

  The word line power supply potential VWL is supplied to the source of the transistor QP31 forming the inverter, the drains of the transistors QP31 and QN31 are connected to the node N1, and the reference power supply potential VSS is supplied to the source of the transistor QN31. The inverted boot pulse enable signal BPE is applied to the gates of the transistors QP31 and QN31. Capacitor C0 is formed of, for example, a P-channel MOS transistor, and is connected between node N1 and power supply line SPL1.

  In the read mode and the verify mode, when the boot pulse enable signal BPE is inactivated to low level, the inverted boot pulse enable signal BPE becomes high level. Therefore, the transistor QP31 is turned off, the transistor QN31 is turned on, and the reference power supply potential VSS is supplied to the node N1.

  Next, when the boot pulse enable signal BPE is activated to a high level, the transistor QP30 is turned off. At this time, word line power supply potential VWL is supplied to power supply line SPL1. Further, the transistor QP31 is turned on, the transistor QN31 is turned off, and the word line power supply potential VWL is supplied to the node N1. Thereby, capacitor C0 performs a discharge operation, and the potential of power supply line SPL1 rises to approximately twice word line power supply potential VWL.

<Memory cell array>
Each memory cell MC includes an N-channel MOS transistor having a control gate, a floating gate, a source, and a drain. The transistor of the memory cell MC stores one bit of data according to the charge stored in the floating gate.

  Each of the word lines WL0, WL1,... Is connected to the control gate of the transistor of the plurality of memory cells MC arranged in the respective row. Each of the source lines SL0, SL1,... Is connected to the sources of the transistors of the plurality of memory cells MC arranged in each row. Further, each of the bit lines BL0, BL1,... Is connected to the drains of the transistors of the plurality of memory cells MC arranged in each column.

  Word line drive circuit 40 (FIG. 1) comprises a plurality of word line drivers 41 for driving control gates of the transistors of memory cells MC connected to word lines WL0, WL1,. And an inverter 43 for supplying the high potential side power supply of the word line driver 41. Each word line driver 41 is configured by, for example, a level shifter, a buffer circuit, or an inverter. The word line power supply potential VWL or the drive potential VUP is supplied from the inverter 43 to each word line driver 41.

  A high active row selection signal activated to a high level when selecting one or more rows of memory cells from among the plurality of memory cells constituting the memory cell array is input to the input terminals of the plurality of word line drivers 41. SW0, SW1,... Are input from the memory control circuit 70. Word line driver 41 outputs word line power supply potential VWL or drive potential VUP to the word line when the row selection signal is active, and the word line of reference power supply potential VSS when the row selection signal is non-active. Output to

  Source line drive circuit 50 (FIG. 1) includes a source line driver 51, a plurality of transmission gates TG, and the like to drive the sources of the transistors of memory cells MC connected to source lines SL0, SL1,. A plurality of inverters 52 are included. The source line driver 51 is configured by, for example, a level shifter, a buffer circuit, or an inverter. The plurality of transmission gates TG are connected between the output terminal of the source line driver 51 and the source lines SL0, SL1,.

  The source line power supply potential VSL is supplied to the source line driver 51 from the power supply circuit 20 (FIG. 1). A high active source line drive signal SSL, which is activated to a high level when applying a high power supply potential to the source line, is input from the memory control circuit 70 to the input terminal of the source line driver 51. The source line driver 51 outputs the source line power supply potential VSL when the source line drive signal SSL is active, and outputs the reference power supply potential VSS when the source line drive signal SSL is non-active.

  Each transmission gate TG is formed of an N channel MOS transistor and a P channel MOS transistor, and functions as a switch circuit that opens and closes the connection between the output terminal of the source line driver 51 and the source line. In the transmission gate TG, the gate of the N channel MOS transistor is connected to the output terminal of the word line driver 41, and the gate of the P channel MOS transistor is connected to the output terminal of the inverter 52.

  Word line power supply potential VWL or word line boosted potential VUP is supplied to inverter 52 from word line drive circuit 40 (FIG. 1). Row selection signals SW0 to SWm are input to input terminals of the inverter 52. The inverter 52 inverts the row selection signals SW0 to SWm, and applies the inverted signal to the gate of the P-channel MOS transistor of the transmission gate TG.

  Switch circuit 60 includes N channel MOS transistors Q0, Q1,... Connected between the memory control circuit 70 and the drains of the transistors of memory cells MC connected to bit lines BL0, BL1,. It is. The gates of the transistors Q0, Q1,... Are high active column selection which is activated to high level when one or more memory cells are selected from a plurality of memory cells constituting the memory cell array. Signals SB 0, SB 1,... Are applied from memory control circuit 70.

  In the write mode, memory control circuit 70 activates corresponding row selection signal and column selection signal to select the word line and bit line connected to memory cell MC designated by the address signal, and other than that. The row selection signal and the column selection signal are made inactive, and the source line drive signal SSL is made active. Hereinafter, as an example, the case where word line WL0 and bit line BL0 are selected will be described.

  The high power supply potential VPP is supplied to the inverter 43, the source line driver 51, and the inverter 52. The high power supply potential VPP is supplied to the high potential side power supply terminal of the word line driver 41 by the inverter 43 to which the non-active erase mode signal ER is input. The word line driver 41 to which the active row selection signal SW0 is input outputs the high power supply potential VPP to the word line WL0. Further, the source line driver 51 to which the active source line drive signal SSL is input outputs the high power supply potential VPP.

  The inverter 52 to which the active row selection signal SW0 is input inverts the high power supply potential VPP, and applies the reference power supply potential VSS to the gate of the P-channel MOS transistor of the transmission gate TG. Thereby, transmission gate TG is turned on, and high power supply potential VPP output from source line driver 51 is applied to source line SL0.

  Further, the transistor Q0 of the switch circuit 60 to which the active column selection signal SB0 is input is turned on, and the memory control circuit 70 applies the reference power supply potential VSS to the bit line BL0. Thus, memory control circuit 70 applies word line drive circuit 40 (FIG. 1) and source line drive circuit to apply high power supply potential VPP to the control gate and source of the transistor of memory cell MC specified by the address signal. While controlling 50 (FIG. 1), the reference power supply potential VSS is applied to the drain.

  As a result, current flows from the source to the drain of the transistor of the memory cell MC specified by the address signal. The hot carriers (electrons in this embodiment) generated by the current are injected into the floating gate, so that negative charges are accumulated in the floating gate, and thus the threshold voltage of the transistor is increased.

  On the other hand, the word line driver 41 to which non-active row selection signals SW1 to SWm are input outputs the reference power supply potential VSS to the word lines WL1 to WLm. The inverter 52 receiving the non-active row selection signals SW1 to SWm inverts the reference power supply potential VSS and applies the high power supply potential VPP to the gate of the P channel MOS transistor of the transmission gate TG. Therefore, the transmission gate TG connected to the word lines WL1 to WLm is turned off. Further, the transistors Q1 to Qn of the switch circuit 60 to which the non-active column selection signals SB1 to SBn are input are turned off. As a result, since no current flows between the source and drain of the transistor of the memory cell MC not designated by the address signal, the threshold voltage of the transistor does not change.

  In the erase mode, memory control circuit 70 activates the corresponding row select signal to select the word line connected to memory cell MC designated by the address signal, and makes the other row select signals non-active. At the same time, the column selection signals SB0 to SBn are deactivated, and the source line drive signal SSL is activated. Hereinafter, the case where word line WL0 is selected will be described as an example.

  The high power supply potential VPP is supplied to the inverter 43, the source line driver 51, and the inverter 52. The reference power supply potential VSS is applied to the high potential side power supply terminal of the word line driver 41 by the inverter 43 to which the active erase mode signal ER is input. The word line driver 41 to which the active row selection signal SW0 is input is not activated, but the reference power supply potential VSS is applied to the word line WL0 by the N channel MOS transistor 42 having the gate to which the active erase mode signal ER is applied. Ru. Further, the source line driver 51 to which the active source line drive signal SSL is input outputs the high power supply potential VPP.

  The inverter 52 to which the active row selection signal SW0 is input inverts the high power supply potential VPP, and applies the reference power supply potential VSS to the gate of the P-channel MOS transistor of the transmission gate TG. As a result, the P-channel MOS transistor of transmission gate TG is turned on, and high power supply potential VPP output from source line driver 51 is applied to source line SL0.

  In addition, the transistors Q0 to Qn of the switch circuit 60 to which the non-active column selection signals SB0 to SBn are input are turned off. Thus, the memory control circuit 70 turns off the transistors Q0 to Qn of the switch circuit 60 to make the drain of the transistor of the memory cell MC open (high impedance state), and applies the reference power supply potential VSS to the control gate. Thus, the word line drive circuit 40 (FIG. 1) is controlled, and the source line drive circuit 50 (FIG. 1) is controlled to apply the high power supply potential VPP to the source. As a result, when the negative charge is accumulated in the floating gate of the transistor of the memory cell MC, the negative charge accumulated in the floating gate is released to the source, and the threshold voltage of the transistor is lowered.

  On the other hand, inverter 52 receiving non-active row selection signals SW1 to SWm inverts reference power supply potential VSS to apply high power supply potential VPP to the gate of the P channel MOS transistor of transmission gate TG. Therefore, the transmission gate TG connected to the word lines WL1 to WLm is turned off. As a result, since the negative charge stored in the floating gate of the transistor of the memory cell MC not designated by the address signal is not discharged, the threshold voltage of the transistor does not change.

  In the read mode and the memory cell verify mode, memory control circuit 70 activates corresponding row selection signal and column selection signal to select the word line and bit line connected to the memory cell specified by the address signal. And non-active the other row selection signal and column selection signal and non-activation of the source line drive signal SSL. Hereinafter, as an example, the case where word line WL0 and bit line BL0 are selected will be described.

  The word line boosted potential VUP is supplied to the inverters 43 and 52, and the logic power supply potential VDD is supplied to the source line driver 51. The word line boosted potential VUP is supplied to the high potential side power supply terminal of the word line driver 41 by the inverter 43 to which the non-active erase mode signal ER is input. The word line driver 41 to which the active row selection signal SW0 is input outputs the word line boosted potential VUP to the word line WL0. In addition, the source line driver 51 to which the non-active source line drive signal SSL is input outputs the reference power supply potential VSS.

  Drive potential VUP output from word line driver 41 is also applied to the gate of the N channel MOS transistor of transmission gate TG connected to word line WL0. Thereby, the N channel MOS transistor of the transmission gate TG is turned on, and the reference power supply potential VSS output from the source line driver 51 is applied to the source line SL0.

  Further, the transistor Q0 of the switch circuit 60 to which the active column selection signal SB0 is input is turned on, and the memory control circuit 70 applies the logic power supply potential VDD to the bit line BL0. Thus, the memory control circuit 70 controls the word line drive circuit 40 (FIG. 1) to apply the drive potential VUP to the control gate of the transistor of the memory cell MC specified by the address signal. The source line drive circuit 50 (FIG. 1) is controlled to apply the power supply potential VSS, and the transistor Q0 of the switch circuit 60 is turned on to apply the logic power supply potential VDD to the drain.

  As a result, in the memory cell MC specified by the address signal, a drain current flows from the drain to the source of the transistor of the memory cell MC. Since the magnitude of the drain current differs depending on the amount of negative charge stored in the floating gate, the memory control circuit 70 can read data from the memory cell MC based on the magnitude of the drain current.

<Second Example of Drive Potential Generating Circuit>
FIG. 3 is a circuit diagram showing another configuration example of the booster circuit included in the drive potential generation circuit shown in FIG. In the second example, the drive potential generation circuit 30 boosts the power supply voltage (VDD-VSS) supplied to the data read circuit 71 by performing a charge pump operation at least in the verify mode of the memory cell in the write state. And a booster circuit for generating the drive potential VUP. Here, the case where the step-up ratio of the step-up circuit is twice will be described.

  As shown in FIG. 3, the booster circuit includes an N channel MOS transistor QN32, P channel MOS transistors QP33 to QP35, capacitors C1 and C2, and level shifters 33 and 34. When the booster circuit is built in the semiconductor integrated circuit device, the capacitors C1 and C2 may be provided outside the semiconductor integrated circuit device.

  The reference power supply potential VSS is supplied to the node N1, and the logic power supply potential VDD is supplied to the node N2. The booster circuit performs charge pump operation according to boosted clock signals CK1 and CK2 generated by the memory control circuit 70 (FIG. 1) or the like to set the difference between the logic power supply potential VDD and the reference power supply potential VSS to the logic power supply potential VDD. The addition is performed to generate the drive potential VUP, and the drive potential VUP is output to the node N3.

  The level shifters 33 and 34 respectively generate boosted clock signals CK4 and CK3 by shifting the high level of the boosted clock signals CK1 and CK2 from the logic power supply potential VDD to the drive potential VUP. The low level of the boosting clock signals CK1 to CK4 is the reference power supply potential VSS.

  By repeating the operation of turning on the transistors QP33 and QP35 and turning off the transistors QN32 and QP34 according to the boosted clock signals CK1, CK3 and CK4, and the operation of turning off the transistors QP33 and QP35 and turning on the transistors QN32 and QP34, Charging and discharging of the capacitor C1 are repeated.

  Along with this, the charge moves and charge pump operation is performed. As a result, the drain of the transistor QP4 charges the capacitor C2, and the drive potential VUP at the node N3 gradually rises and reaches approximately twice the logic power supply potential VDD in the steady state.

  FIG. 4 is a waveform diagram showing voltage waveforms of respective parts in the booster circuit shown in FIG. In FIG. 4, a voltage waveform after reaching a steady state is shown. The boosting clock signals CK1 and CK2 are signals in reverse phase to each other, and shift between the reference power supply potential VSS (0 V) and the logic power supply potential VDD. The level shifters 33 and 34 shift the high level of the boosted clock signals CK1 and CK2 to obtain boosted clock signals CK4 and CK3 shifted between the reference power supply potential VSS (0 V) and the drive potential VUP.

  Boosted clock signals CK1, CK3 and CK4 are applied to the gates of the transistors QN32 and QP33 to QP35, and the transistors QN32 and QP33 to QP35 perform switching operations. As a result, the potentials VP1 and VM1 across the capacitor C1 change as shown in FIG. As a result, at node N3, a drive potential VUP of about twice that of logic power supply potential VDD is obtained.

  According to the first or second example of the drive potential generation circuit, the power supply potential on the high potential side supplied to data read out circuit 71 is not increased without increasing the type of power supply voltage supplied to the semiconductor integrated circuit device. A high drive potential can be generated.

<Third Example of Drive Potential Generating Circuit>
FIG. 5 is a circuit diagram showing a configuration example of a step-down circuit included in the drive potential generation circuit shown in FIG. In the third example, drive potential generation circuit 30 steps down and drives a power supply voltage larger than the power supply voltage (VDD-VSS) supplied to data read circuit 71 in at least the verify mode of the memory cell in the write state. It includes a step-down circuit that generates a potential.

  For example, based on the high power supply potential VPP supplied from the power supply circuit 20 shown in FIG. 1 to the drive potential generation circuit 30, a power supply voltage larger than the power supply voltage (VDD-VSS) supplied to the data read circuit 71 can be obtained. . Alternatively, when a power supply potential (for example, 3 V) higher than the logic power supply potential VDD is supplied to the analog circuit incorporated in the semiconductor integrated circuit device, the power supply voltage (VDD) supplied to the data read circuit 71 based thereon. A power supply voltage larger than -VSS) can be obtained.

  The step-down circuit shown in FIG. 5 is a regulator and includes an operational amplifier 35, a constant voltage source 36, a P-channel MOS transistor QP36, and resistors R1 and R2. The source of the transistor QP36 is connected to the input terminal of the step-down circuit, the gate is connected to the output terminal of the operational amplifier 35, and the drain is connected to the output terminal of the step-down circuit. Resistors R1 and R2 are connected in series between the drain of the transistor QP36 and the wiring of the reference power supply potential VSS.

  The input potential Vin is input to the input terminal of the step-down circuit. The transistor QP36 causes current to flow from the source to the drain in accordance with a signal applied to the gate. The reference potential Vref generated by the constant voltage source 36 is input to the inverting input terminal of the operational amplifier 35. Further, a feedback potential obtained by dividing the voltage at the output terminal of the step-down circuit by the resistors R1 and R2 is fed back to the non-inverting input terminal of the operational amplifier 35. The operational amplifier 35 amplifies the difference between the feedback potential input to the noninverting input terminal and the reference potential Vref input to the inverting input terminal, and applies the amplified signal to the gate of the transistor QP36.

Therefore, the output potential Vout of the step-down circuit is expressed by the following equation using the reference potential Vref.
Vout = Vref (1 + R1 / R2)
Here, Vout> VDD. According to the third example of the drive potential generation circuit, a drive potential higher than the power supply potential (logic power supply potential VDD) on the high potential side supplied to the data read out circuit 71 is accurately generated based on the reference potential. Can.

<Data readout circuit>
FIG. 6 is a circuit diagram showing a configuration example of the data read circuit shown in FIG. 1 and the periphery thereof. In this example, two reference cells RC1 and RC2 are used. Each of reference cells RC1 and RC2 includes an N-channel MOS transistor having a control gate, a floating gate, a source, and a drain.

  The transistor of the reference cell RC1 has a first threshold voltage, and the transistor of the reference cell RC2 has a second threshold voltage larger than the first threshold voltage. That is, the reference cell RC1 is in the erased state, and the reference cell RC2 is in the written state.

  The first drive potential WL is supplied by the word line drive circuit 40 to the control gate of the transistor of the memory cell MC specified by the address signal. The memory control circuit 70 supplies the second drive potential RWL to the control gates of the transistors of the reference cells RC1 and RC2.

  Conventionally, the first drive potential WL and the second drive potential RWL are higher than the logic power supply potential VDD in the read mode, and are the logic power supply potential VDD in the verify mode. In the present embodiment, at least in the verify mode of the memory cell in the write state, the first drive potential WL and the second drive potential RWL are supplied to the data read circuit 71 at the high potential side power supply potential (logic power supply potential The potential is higher than VDD).

  Hereinafter, a case where the first drive potential WL and the second drive potential RWL are the drive potential VUP in the read mode and the verify mode will be described. The reference power supply potential VSS is supplied to the memory cells MC and the sources of the transistors of the reference cells RC1 and RC2.

  In the read mode, the data read circuit 71 generates a determination current based on the current flowing in the reference cell RC1 and the current flowing in the reference cell RC2, and compares the current flowing in the memory cell MC with the determination current. Read the data stored in MC.

  In the memory cell verify mode, the data read circuit 71 generates a determination current based on at least one of the current flowing in the reference cell RC1 and the current flowing in the reference cell RC2, and determines the current flowing in the memory cell MC. The data stored in the memory cell MC is read out by comparing with.

  Further, in the verify mode of the reference cell, the data read circuit 71 compares the current proportional to the current flowing to the reference cell RC2 with the current proportional to the current flowing to the reference cell RC1. It may be checked whether the threshold voltage is appropriate. If the threshold voltage of the reference cell RC2 is not appropriate, the verify circuit 72 can correct the threshold voltage of the reference cell RC2.

  For example, as shown in FIG. 6, the data read circuit 71 includes P channel MOS transistors QP1 to QP8, an N channel MOS transistor QN1, and a sense amplifier 71a. Sense amplifier 71a includes P-channel MOS transistors QP11-QP14, N-channel MOS transistors QN2-QN4 and inverters IN1 and IN2, and has an input terminal IN and an output terminal OUT.

  The logic power supply potential VDD is supplied to the sources of the transistors QP1 to QP3, and the gate is connected to the drain of the transistor QP1 and the drain of the transistor of the reference cell RC1. Here, the transistors QP1 to QP3 constitute a first current mirror circuit that supplies a current (four types of currents in FIG. 6) proportional to the current flowing to the reference cell RC1.

  The drain of the transistor QP2 is connected to the input terminal IN of the sense amplifier 71a via the transistor QP4. The drain of the transistor QP3 is connected to the input terminal IN of the sense amplifier 71a via the transistor QP5. The current setting signal E0 is applied to the gate of the transistor QP4, and the current setting signal E1 is applied to the gate of the transistor QP5. Here, the transistors QP4 and QP5 constitute a selector circuit that selects the magnitude of the current supplied from the first current mirror circuit according to the current setting signals E0 and E1.

  Memory control circuit 70 sets current setting signals E0 and E1 to low level (for example, reference power supply potential VSS) or high level (for example, logic) according to the read mode, the verify mode of the memory cell, and the verify mode of the reference cell. Set to the power supply potential VDD).

  When the current setting signal E0 is activated to a low level, the transistor QP4 is turned on to supply the current supplied from the drain of the transistor QP2 to the input terminal IN of the sense amplifier 71a. Further, when the current setting signal E1 is activated to a low level, the transistor QP5 is turned on to supply the current supplied from the drain of the transistor QP3 to the input terminal IN of the sense amplifier 71a.

  The logic power supply potential VDD is supplied to the sources of the transistors QP6 and QP7, and the gate is connected to the drain of the transistor QP6 and the drain of the transistor of the reference cell RC2. Here, the transistors QP6 and QP7 constitute a second current mirror circuit that supplies a current proportional to the current flowing to the reference cell RC2.

  The drain of the transistor QP7 is connected to the input terminal IN of the sense amplifier 71a via the transistor QP8. A program cell invalidation signal P0 is applied to the gate of the transistor QP8 to invalidate the output of the reference cell RC2 in the program state. Here, the transistor QP8 configures a switch circuit that operates or stops the second current mirror circuit in accordance with the programmed cell invalidation signal P0.

  For example, the memory control circuit 70 sets the program cell invalidation signal P0 to the low level in the read mode and the verify mode of the memory cell in the erase state. Thereby, the transistor QP8 is turned on, and the current supplied from the drain of the transistor QP7 is supplied to the input terminal IN of the sense amplifier 71a.

  Therefore, the data read circuit 71 generates a determination current by adding the current supplied from the first current mirror circuit and the current supplied from the second current mirror circuit, and the determination current is generated by the sense amplifier 71a. Supply to the input terminal IN. Thereby, the data read circuit 71 appropriately determines the determination current to be compared when reading the data stored in the memory cell MC based on the current flowing to the reference cell RC1 and the current flowing to the reference cell RC2. It can be set.

  On the other hand, the memory control circuit 70 sets the program cell invalidation signal P0 to the high level in the verify mode of the memory cell in the write state. Thereby, the transistor QP8 is turned off, and a current is not supplied from the drain of the transistor QP7 to the input terminal IN of the sense amplifier 71a.

  Therefore, the data read circuit 71 supplies the current supplied from the first current mirror circuit to the input terminal IN of the sense amplifier 71a. Thus, the data read circuit 71 can change the determination current in the read mode and the verify mode of the memory cell in the write state.

  The drain and gate of the transistor QN1 are connected to the input terminal IN of the sense amplifier 71a, and the reference power supply potential VSS is supplied to the source of the transistor QN1. Therefore, the current supplied to the input terminal IN of the sense amplifier 71a flows to the transistor QN1.

<Sense amplifier>
In the sense amplifier 71a, the gate of the transistor QN2 is connected to the input terminal IN, and the source is supplied with the reference power supply potential VSS. The transistor QN1 and the transistor QN2 constitute a current mirror circuit, and the determination current generated by the first current mirror circuit and the second current mirror circuit flows to the transistor QN2.

  The logic power supply potential VDD is supplied to the sources of the transistors QP11 and QP12, and the gate is connected to the drain of the transistor QP11 and the drain of the transistor QN2. Here, the transistors QP11 and QP12 have the same size, and constitute a current mirror circuit that supplies a current substantially equal to the current flowing through the transistor QN2. The drain of the transistor QP12 is connected to the drain of the transistor of the memory cell MC and the drain of the transistor QN2.

  In the read mode and the verify mode of the memory cell in the erased state, a current flows to the transistor of the memory cell MC according to the first drive potential WL, and a current flowing to the reference cell RC1 and a current flowing to the reference cell RC2 to the transistor QN2 The judgment current flows based on. Further, in the verify mode of the memory cell in the write state, a current flows to the transistor of the memory cell MC according to the first drive potential WL, and a determination current based on the current flowing to the reference cell RC1 flows to the transistor QN2.

  The above determination current also flows through the transistors QP11 and QP12. Therefore, if the current flowing to the memory cell MC is larger than the determination current, the drain potential of the transistor QP12 is lower than the drain potential of the transistor QP11. On the other hand, if the current flowing to the memory cell MC is smaller than the determination current, the drain potential of the transistor QP12 becomes higher than the drain potential of the transistor QP11.

  The logic power supply potential VDD is supplied to the sources of the transistors QP13 and QP14, and the gates are connected to the drain of the transistor QP11 and the drain of the transistor QP12, respectively. Therefore, transistors QP13 and QP14 flow respective currents according to the drain potentials of transistors QP11 and QP12.

  The drain of the transistor QN3 is connected to the drain of the transistor QP13, and the drain of the transistor QN4 is connected to the drain of the transistor QP14. The gates of the transistors QN3 and QN4 are connected to the drain of the transistor QP13 and the drain of the transistor QN3, and the source is supplied with the reference power supply potential VSS. Here, the transistors QN3 and QN4 have the same size, and constitute a current mirror circuit that supplies a current substantially equal to the current flowing through the transistor QP13.

  The drain of the transistor QN4 is connected to the input terminal of the inverter IN1. The output terminal of the inverter IN1 is connected to the input terminal of the inverter IN2, and the output terminal of the inverter IN2 is connected to the output terminal OUT of the sense amplifier. Therefore, if the drain potential of the transistor QP12 is lower than the drain potential of the transistor QP11, a high level determination signal Y is output from the output terminal OUT. On the other hand, if the drain potential of the transistor QP12 is higher than the drain potential of the transistor QP11, a low level determination signal Y is output from the output terminal OUT.

  As described above, in the read mode and the verify mode of the memory cell in the erase state, the sense amplifier 71a supplies the current flowing to the memory cell MC from the current supplied from the first current mirror circuit and the second current mirror circuit. In comparison with the judgment current which is the sum of the current and the current to be outputted, the judgment signal Y representing the comparison result is outputted. Further, in the verify mode of the memory cell in the write state, sense amplifier 71a compares the current flowing through memory cell MC with the determination current which is the current supplied from the first current mirror circuit, and indicates the comparison signal Output Y For example, the sense amplifier 71a outputs the determination signal Y at high level when the current flowing to the memory cell MC is larger than the determination current, and low level when the current flowing to the memory cell MC is smaller than the determination current. The determination signal Y is output.

<Example of judgment level setting>
FIG. 7 is a diagram for explaining the influence of the leak current flowing to the non-selected cell on the reading of the data of the selected cell. Conventionally, in the memory cell verify mode, the logic power supply potential VDD is applied to the word line connected to the control gate of the selected memory cell, and 0 V is applied to the other word lines.

  Also, the logic power supply potential VDD is applied to the bit line connected to the drain of the selected memory cell, and the other bit lines are in the open state (high impedance state: HiZ). Furthermore, 0 V was applied to the source line connected to the source of the selected memory cell, and the other source lines were in the open state (high impedance state: HiZ).

  However, as shown by a broken line in FIG. 7, a leak current flows in the non-selected memory cell, and the leak current is superimposed on the drain current of the selected memory cell. Therefore, if data is read from the memory cell in a state where the current flowing to the selected memory cell and reference cell is small, a normal determination can not be performed due to the influence of the leak current.

  FIG. 8 is a diagram showing an example of setting of determination levels in the data read circuit shown in FIG. In FIG. 8, the horizontal axis represents the drive potential, and the vertical axis represents the current Icell flowing to the reference cell or the memory cell. The solid line (a) represents the current flowing to the reference cell RC1 or memory cell MC in the erased (erasing) state, and the solid line (b) represents the current flowing to the reference cell RC2 or memory cell MC in the programmed (writing) state. It represents.

  In the memory cell verify mode, different determination levels may be used in the erase verify for verifying the memory cell MC in the erase state and for the program verify for verifying the memory cell MC in the program state. Thereby, the determination level can be set more strictly than in the read mode, and the reliability of data stored in the memory cell MC can be enhanced.

  For example, in the erase verify, the memory control circuit 70 (FIG. 1) sets the program cell invalidation signal P0 shown in FIG. 6 to low level, and the current supplied from the first current mirror circuit flows to the reference cell RC1. The current setting signals E0 and E1 are generated such that the current is set to about 1⁄2 times and the current supplied from the second current mirror circuit is set to about 1 times the current flowing to the reference cell RC2. Thus, the current supplied from the first current mirror circuit and the current supplied from the second current mirror circuit are added to generate a determination current (determination level).

  On the other hand, in the program verify, the memory control circuit 70 (FIG. 1) sets the program cell invalidation signal P0 to high level, and the current supplied from the first current mirror circuit is set to a predetermined current flowing in the reference cell RC1. The current setting signals E0 and E1 are generated to be set to a ratio. Thus, a determination current (determination level) is generated by the current supplied from the first current mirror circuit.

  The broken lines (c) and (d) show the current supplied from the first current mirror circuit. In program verify, it is determined whether the data stored in the selected memory cell MC is “1”, using the determination level shown by the broken line (c) or (d). Circles shown in FIG. 8 indicate positions where the current flowing to the memory cell MC in the programmed state is equal to the determination level.

  The broken line (c) shows a case where the value of the ratio of the current supplied from the first current mirror circuit to the current flowing in the reference cell RC1 (hereinafter also referred to as "mirror ratio") is reduced. Here, if the drive potential is equal to the logic power supply potential VDD, the current flowing to the memory cell MC in the programmed state is smaller than the determination level, so it can be determined that the operation of the memory cell MC is normal. However, since the current flowing to the memory cell MC and the reference cell RC1 is small, it is susceptible to the leak current flowing to the non-selected memory cell.

  By raising the drive potential to a potential higher than the logic power supply potential VDD (for example, the drive potential VUP), the current flowing to the memory cell MC and the reference cell RC1 increases. However, this alone causes the current flowing to the programmed memory cell MC to be larger than the determination level. Therefore, in the present embodiment, as indicated by the broken line (d), the data read circuit 71 makes the mirror ratio larger than in the conventional case to increase the drive potential. Thereby, the influence of the leak current flowing to the non-selected memory cell can be reduced while the determination criterion of whether the operation of the memory cell MC in the programmed state is normal is equal to or stricter than the conventional one. it can.

  Further, in the verify mode of the memory cell MC in the write state, the data read circuit 71 may make the value of the ratio of the determination current to the current flowing in the reference cell RC1 larger than in the read mode. Thereby, when verifying the memory cell MC in the write state, the determination current generated based on the current flowing to the reference cell RC1 can be increased to reduce the influence of the leakage current flowing to the non-selected memory cell. . The change of the mirror ratio is performed by the memory control circuit 70 (FIG. 1) changing the current setting signals E0 and E1.

  In the read mode, the memory control circuit 70 (FIG. 1) sets the program cell invalidation signal P0 to the high level, and the current supplied from the first current mirror circuit is approximately equal to the current flowing in the reference cell RC1. The current setting signals E0 and E1 may be generated such that the current supplied from the second current mirror circuit is set to about one time the current flowing to the reference cell RC2 while being set to 1/3. As a result, the current supplied from the first current mirror circuit and the current supplied from the second current mirror circuit are added to generate a determination current.

  According to the present embodiment, at least in the verify mode of the memory cell in the write state, driving higher than the high potential power supply potential supplied to the data read circuit 71 to the control gates of the transistors of the memory cell MC and the reference cell RC1. Potentials are commonly applied. Therefore, it is not necessary to separately generate drive potentials supplied to the memory cell MC and the reference cell RC1. Further, since the current flowing to the memory cell MC and the reference cell RC1 increases, the influence of the leak current flowing to the non-selected memory cell can be reduced, and the data stored in the memory cell MC can be read correctly. In addition, in the verification of the memory cell MC, more stringent criteria can be applied.

<Electronic equipment>
Next, an electronic device according to an embodiment of the present invention will be described with reference to FIG.
FIG. 9 is a block diagram showing an example of the configuration of an electronic device according to an embodiment of the present invention. The electronic device 100 includes a semiconductor integrated circuit device 110 according to an embodiment of the present invention, a CPU 120, an operation unit 130, a ROM (read only memory) 140, a RAM (random access memory) 150, and a communication unit. A display unit 170 and an audio output unit 180 may be included. Note that some of the components shown in FIG. 9 may be omitted or changed, or other components may be added to the components shown in FIG.

  The semiconductor integrated circuit device 110 includes a non-volatile memory, and performs various processes in response to a command from the CPU 120. For example, the semiconductor integrated circuit device 110 corrects the input data or converts the data format based on the parameters stored in the non-volatile memory.

  The CPU 120 performs various arithmetic processing and control processing using data and the like supplied from the semiconductor integrated circuit device 110 according to a program stored in the ROM 140 or the like. For example, the CPU 120 performs various data processing in accordance with the operation signal supplied from the operation unit 130, controls the communication unit 160 to perform data communication with the outside, or performs various operations on the display unit 170. It generates an image signal for displaying an image, and generates an audio signal for causing the audio output unit 180 to output various types of audio.

  The operation unit 130 is an input device including, for example, operation keys and a button switch, and outputs an operation signal according to an operation by the user to the CPU 120. The ROM 140 stores programs, data, and the like for the CPU 120 to perform various types of arithmetic processing and control processing. In addition, the RAM 150 is used as a work area of the CPU 120, and temporarily stores programs and data read from the ROM 140, data input using the operation unit 130, or an operation result executed by the CPU 120 according to the program. Do.

  The communication unit 160 includes, for example, an analog circuit and a digital circuit, and performs data communication between the CPU 120 and an external device. The display unit 170 includes, for example, an LCD (liquid crystal display device) and the like, and displays various types of information based on a display signal supplied from the CPU 120. Further, the audio output unit 180 includes, for example, a speaker, and outputs audio based on an audio signal supplied from the CPU 120.

  The electronic device 100 may be, for example, a smart card, a calculator, an electronic dictionary, an electronic game device, a mobile terminal such as a mobile phone, a digital still camera, a digital movie, a television, a videophone, a television monitor for crime prevention, a head mounted display, personal Computers, printers, network devices, car navigation devices, measuring devices, and medical devices (for example, electronic thermometers, sphygmomanometers, blood glucose meters, electrocardiogram measuring devices, ultrasound diagnostic devices, electronic endoscopes, etc.) .

  According to the present embodiment, in the non-volatile memory incorporated in the semiconductor integrated circuit device 110, it is possible to accurately read the data stored in the memory cell while reducing the influence of the leak current flowing to the non-selected memory cell. It is possible to provide an electronic device that can For example, the ROM 140 can be omitted by storing the program in the nonvolatile memory of the semiconductor integrated circuit device 110, or the RAM 150 can be omitted by storing data in the nonvolatile memory of the semiconductor integrated circuit device 110.

  Although the above embodiment has described the case where the present invention is applied to a flash memory, the present invention is not limited to the above-described embodiment, and can be applied by those skilled in the art. Many modifications are possible within the scope of the inventive concept.

  DESCRIPTION OF SYMBOLS 10 memory cell array 20 power supply circuit 30 drive potential generation circuit 31 inverter 33, 34 level shifter 35 op amp 36 constant voltage source 40 word line drive circuit 41 word line driver , 42: N channel MOS transistor, 43: inverter, 50: source line drive circuit, 51: source line driver, 52: inverter, 60: switch circuit, 70: memory control circuit, 71: data read circuit, 71a: sense amplifier , 72: verify circuit, 100: electronic device, 110: semiconductor integrated circuit device, 120: CPU, 130: operation unit, 140: ROM, 150: RAM, 160: communication unit, 170: display unit, 180: audio output unit , WL0 to WLm: word lines, SL0 to SLm: source lines, BL0 to BL ... bit line, RC1, RC2 ... reference cell, MC ... memory cell, TG ... transmission gate, C0-C2 ... capacitor, R1, R2 ... resistance, Q0, Q1 ... N channel MOS transistor, QP1-QP36 ... P channel MOS Transistors, QN1 to QN32: N channel MOS transistors, IN1 to IN3: inverters

Claims (4)

A memory cell including a transistor for storing data,
A first reference cell including bets lunge star having a first threshold voltage,
A second reference cell comprising a transistor having a second threshold voltage greater than the first threshold voltage;
Wherein the first reference cell second based on the current flowing through the transistor of the reference cell to generate a determination current, previous SL by comparing the current flowing through the transistor of the memory cell and the determination current, stored in said memory cell a data reading circuit for reading the data being,
In verify mode of the memory cell of the writing can lump state, a drive voltage generating circuit for generating a potentiodynamic drive not higher than the power supply potential on the high potential side is supplied to the data reading circuit,
Equipped with
The drive potential generation circuit includes a booster circuit that boosts a power supply voltage supplied to the data read circuit to generate the drive potential in a verify mode of a memory cell in a write state.
A first current mirror circuit that supplies a current proportional to the current flowing to the first reference cell, and a second current that supplies a current proportional to the current flowing to the second reference cell; A mirror circuit and a switch circuit for operating or stopping the second current mirror circuit, and in a read mode, a current flowing through the memory cell, a current supplied from the first current mirror circuit, and Current flowing through the memory cell in the verify mode of the memory cell in the write state, and the first current mirror. A semiconductor integrated circuit device comparing the current supplied from the circuit. A memory cell including a transistor for storing data;
A first reference cell including a transistor having a first threshold voltage;
A second reference cell comprising a transistor having a second threshold voltage greater than the first threshold voltage;
A determination current is generated based on the current flowing through the transistors of the first reference cell and the second reference cell, and the current flowing through the transistor of the memory cell is compared with the determination current to be stored in the memory cell A data reading circuit for reading out the data;
A drive potential generation circuit generating a drive potential higher than a power supply potential on the high potential side supplied to the data read circuit in a verify mode of the memory cell in the write state;
Equipped with
The drive potential generation circuit includes a step-down circuit that steps down a power supply voltage larger than a power supply voltage supplied to the data read circuit to generate the drive potential in a verify mode of a memory cell in a write state.
A first current mirror circuit that supplies a current proportional to the current flowing to the first reference cell, and a second current that supplies a current proportional to the current flowing to the second reference cell; A mirror circuit and a switch circuit for operating or stopping the second current mirror circuit, and in a read mode, a current flowing through the memory cell, a current supplied from the first current mirror circuit, and Current flowing through the memory cell in the verify mode of the memory cell in the write state, and the first current mirror. A semiconductor integrated circuit device comparing the current supplied from the circuit. The data read circuit, in verify mode of said memory cell in the written state, is larger than in the first reference cell or ratio reads the value mode of the current flowing through the second reference cell and the determination current The semiconductor integrated circuit device according to claim 1 or 2 .   An electronic apparatus comprising the semiconductor integrated circuit device according to any one of claims 1 to 3.

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