JP7050658B2 - Manufacturing method of semiconductor chip - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor chip.

After forming a plurality of semiconductor elements on a semiconductor wafer, a product is manufactured by dicing a plurality of semiconductor chips from the semiconductor wafer by dicing with a dicing blade (see, for example, Patent Document 1).

In the conventional technique, when a plurality of semiconductor chips are separated from a warped or distorted semiconductor wafer, it is premised that the semiconductor wafer is flatly crimped and fixed in a wafer mounting and dicing process.

JP-A-2017-228660

Warpage and strain are corrected by crimping flat, but the stress at that time is inherent in the semiconductor wafer. In the early stage of the dicing process, in the vicinity where the dicing blade first cuts into the semiconductor wafer, the stress of the internal semiconductor wafer is dissipated, so that there is a problem that chipping occurs from the side surface to the back surface of the semiconductor chip which is a product. .. Therefore, it was a potential defect of the product.

However, Patent Document 1 does not disclose a method of suppressing chipping generated by releasing the stress of the internal semiconductor wafer.

Therefore, an object of the present invention is to provide a technique for suppressing chipping that occurs from the side surface to the back surface of a semiconductor chip due to the release of stress from the internal semiconductor wafer.

The method for manufacturing a semiconductor chip according to the present invention is a method for manufacturing a plurality of semiconductors from a semiconductor wafer having an effective chip region which is a region where a plurality of semiconductor chips are formed and a wafer outer peripheral invalid region which is a region on the outer peripheral side of the effective chip region. A method for manufacturing a semiconductor chip in which chips are separated into individual pieces, that is, a discard dicing step (a) in which the ineffective region on the outer periphery of the wafer is cut at a predetermined pitch, and the effective chip region is cut at a predetermined pitch. This includes a dicing step (b) for separating the plurality of semiconductor chips into individual pieces.

According to the present invention, in the discard dicing step (a), since the wafer outer peripheral invalid region is cut at a predetermined pitch, the stress of the internal semiconductor wafer can be dissipated before the dicing step (b). This makes it possible to suppress chipping that occurs from the side surface to the back surface of the semiconductor chip.

It is a top view which shows the manufacturing method of the semiconductor chip which concerns on Embodiment 1. FIG. It is an enlarged plan view which shows the manufacturing method of the semiconductor chip which concerns on Embodiment 1. FIG. It is a figure for demonstrating the dicing line in the manufacturing method of the semiconductor chip which concerns on Embodiment 1. FIG. It is a top view which shows the manufacturing method of the semiconductor chip which concerns on Embodiment 2. FIG. It is a top view which shows the manufacturing method of the semiconductor chip which concerns on Embodiment 3. FIG. It is a top view which shows the manufacturing method of the semiconductor chip which concerns on Embodiment 4. FIG. It is a top view which shows the manufacturing method of the semiconductor chip which concerns on the modification 1 of Embodiment 4. It is a top view which shows the manufacturing method of the semiconductor chip which concerns on the modification 2 of Embodiment 4. It is a top view which shows the manufacturing method of the semiconductor chip which concerns on the modification 3 of Embodiment 4. It is a top view which shows the manufacturing method of the semiconductor chip which concerns on the modification 4 of Embodiment 4. It is a top view which shows the manufacturing method of the semiconductor chip which concerns on the modification 5 of Embodiment 4. It is a schematic plan view of the semiconductor wafer which concerns on Embodiment 5. FIG. It is a top view of the semiconductor wafer which concerns on Embodiment 5. FIG. It is a top view which shows the manufacturing method of the semiconductor chip which concerns on Embodiment 6. It is a top view which shows the manufacturing method of the semiconductor chip which concerns on the modification 1 of Embodiment 6. It is a top view which shows the manufacturing method of the semiconductor chip which concerns on the modification 2 of Embodiment 6. It is a top view which shows the manufacturing method of the semiconductor chip which concerns on the modification 3 of Embodiment 6. It is a top view which shows the manufacturing method of the semiconductor chip which concerns on the modification 4 of Embodiment 6. It is a top view which shows the order of dicing in the manufacturing method of the semiconductor chip which concerns on the modification 4 of Embodiment 6.

<Embodiment 1>
Embodiment 1 of the present invention will be described below with reference to the drawings. FIG. 1 is a plan view showing a method of manufacturing the semiconductor chip 1a according to the first embodiment. Specifically, FIG. 1A is a plan view showing Ch (1) ′ and Ch (1) of dicing in the semiconductor wafer 1. FIG. 1B is a plan view showing Ch (2) of dicing in the semiconductor wafer 1. FIG. 1 (c) is a plan view showing the post-execution states of Dicing Ch (1)', Ch (1), and Ch (2) in the semiconductor wafer 1. FIG. 2 is an enlarged plan view showing a method of manufacturing the semiconductor chip 1a according to the first embodiment. FIG. 3 is a diagram for explaining a dicing line in the method for manufacturing the semiconductor chip 1a according to the first embodiment.

As shown in FIG. 1A, the semiconductor wafer 1 includes an effective chip region 2 and a wafer outer peripheral invalid region 3. The base material of the semiconductor wafer 1 is a thinned compound semiconductor such as Si, SiC, or GaN.

The effective chip region 2 is a circular region in a plan view, and is a region in which a plurality of semiconductor chips 1a (see FIG. 2) are formed. The semiconductor chip 1a formed in the effective chip region 2 has a relatively small chip size of, for example, less than 5.0 mm × 5.0 mm. The wafer outer peripheral invalid region 3 is an annular region formed on the outer peripheral side of the effective chip region 2 in a plan view, and is a region in which the semiconductor chip 1a is not formed.

Next, a method for manufacturing the semiconductor chip 1a will be described. As shown in FIG. 1 (a), first, in the dicing Ch (1)', several lines of the wafer outer peripheral invalid region 3 are cut at a predetermined pitch by a dicing blade. Specifically, after cutting several lines from the orientation flat (OF) side of the wafer outer peripheral invalid region 3 at the same pitch X as the product by the dicing blade, as shown in FIG. 2, the wafer outer peripheral invalid region 3 is combined with the OF. Cut several lines from the opposite side at the same pitch X as the product. In FIGS. 1 (a) and 2 (a), a long arrow indicates a discard dicing which is a dicing Ch (1) ′, and a short arrow indicates a position of the first dicing in each direction of each Ch.

Next, in the dicing Ch (1), the effective chip region 2 is cut from the OF side to the side facing the OF side by the dicing blade at the pitch X of the product having a predetermined pitch.

Next, as shown in FIG. 1 (b), in the dicing Ch (2) whose angle is rotated by 90 °, the wafer outer peripheral invalid region 3 and the effective chip region 2 are used from the upper side in FIG. 1 (b) by the dicing blade. Is continuously cut at the pitch Y of the product. As a result, as shown in FIG. 1 (c), the semiconductor wafer 1 is in a state of being cut in a grid pattern. In FIG. 1 (c), the portion cut by Ch (1)'is shown by a dotted line.

At this time, as shown in FIG. 3, when the end face of the semiconductor wafer 1 is cut at the limit regardless of whether it is on the OF side or not, the dicing blade may be slightly bent and damaged. In order to suppress this, a few mm from the end face of the semiconductor wafer 1 is cut from the inner peripheral side. Here, the dicing Ch (1)'corresponds to the discard dicing step (a), and the step of cutting the effective chip region 2 in the dicing Ch (1) and Ch (2) corresponds to the dicing step (b). do.

As described above, in the method for manufacturing the semiconductor chip 1a, in the discard dicing step (a), the wafer outer peripheral ineffective region 3 is cut into a plurality of pieces at a predetermined pitch, so that the internal stress of the semiconductor wafer 1 is used in the dicing step (a). b) Can be diverged before. This makes it possible to suppress chipping that occurs from the side surface to the back surface of the semiconductor chip 1a.

The predetermined pitch in the discard dicing step (a) is the same as the predetermined pitch in the dicing step (b). Therefore, by applying this to the case of the semiconductor wafer 1 in which the semiconductor chip 1a having a relatively small chip size of less than 5.0 mm × 5.0 mm is formed, chipping generated from the side surface to the back surface of the semiconductor chip 1a can be generated. It can be effectively suppressed.

The base material of the semiconductor wafer 1 is a thinned compound semiconductor such as Si, SiC, or GaN. Further, the semiconductor wafer 1 is warped or distorted. Therefore, in the semiconductor wafer 1 whose base material is a thinned compound semiconductor such as Si, SiC, or GaN in which warpage or distortion is likely to occur, it is possible to suppress the progress of dicing in an unstable state. As a result, it is possible to suppress the frequent occurrence of chipping on the semiconductor chip 1a, which is a product.

<Embodiment 2>
Next, the second embodiment will be described. FIG. 4 is a plan view showing a method of manufacturing the semiconductor chip 1a according to the second embodiment. Specifically, FIG. 4A is a plan view showing Ch (1)'of dicing in the semiconductor wafer 1. FIG. 4B is a plan view showing Ch (1) and Ch (2) of dicing in the semiconductor wafer 1. In the second embodiment, the same components as those described in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIGS. 4A and 4B, in the second embodiment, the predetermined pitch in the discard dicing step (a) is smaller than the predetermined pitch in the dicing step (b). The second embodiment is applied to the semiconductor wafer 1 on which a semiconductor chip having a medium to large chip size of 5.0 mm × 5.0 mm or more is formed, for example.

Next, a method for manufacturing the semiconductor chip 1a will be described. As shown in FIG. 4A, first, in the dicing Ch (1)', several lines of the wafer outer peripheral invalid region 3 are cut at a predetermined pitch by the dicing blade. Specifically, after cutting two lines from the OF side of the wafer outer peripheral invalid region 3 with a dicing blade at a pitch smaller than the pitch X of the product, two lines are cut from the side facing the OF of the wafer outer peripheral invalid region 3 into the product. Cut at a pitch smaller than the pitch X of.

Next, as shown in FIG. 4 (b), in the dicing Ch (1), a product having a predetermined pitch across the effective chip region 2 from the OF side to the side facing the OF side by the dicing blade. Cut at the pitch X of.

Next, in the dicing Ch (2) whose angle is rotated by 90 °, the wafer outer peripheral invalid region 3 and the effective chip region 2 are continuously cut at the pitch Y of the product from the upper side in FIG. 4 (b) by the dicing blade. do. In FIG. 4B, the solid straight line indicates the cutting point in Ch (1) and Ch (2), and the dotted straight line indicates the cutting point in Ch (1)'.

As described above, in the method for manufacturing the semiconductor chip 1a, the predetermined pitch in the discard dicing step (a) is smaller than the predetermined pitch in the dicing step (b). Therefore, by applying this to the semiconductor wafer 1 on which the semiconductor chip 1a having a medium to large chip size of 5.0 mm × 5.0 mm or more is formed, the frequency of performing the discard dicing step (b), that is, the number of lines Therefore, the stress of the internal semiconductor wafer 1 can be more effectively dissipated before the dicing step (b).

<Embodiment 3>
Next, the third embodiment will be described. FIG. 5 is a plan view showing a method of manufacturing the semiconductor chip 1a according to the third embodiment. FIG. 5A is a plan view showing Ch (1) ′ and Ch (2) ′ of dicing in the semiconductor wafer 1. FIG. 5B is a plan view showing Ch (1) and Ch (2) of dicing in the semiconductor wafer 1. In the third embodiment, the same components as those described in the first and second embodiments are designated by the same reference numerals and the description thereof will be omitted.

In the third embodiment, all the portions of the semiconductor wafer 1 where the warp is steep are discarded and the dicing step is performed. The cutting in the discard dicing step is performed over a range of 20 mm from the outer peripheral end of the wafer outer peripheral invalid region 3 where the rise of the warp is considered to be steep. The width of the wafer outer peripheral invalid region 3 is 20 mm. Further, the third embodiment can be applied regardless of the chip size of the semiconductor chip 1a.

Next, a method for manufacturing the semiconductor chip 1a will be described. As shown in FIG. 5A, first, in the dicing Ch (1)', the range from the OF side of the wafer outer peripheral invalid region 3 to the inner peripheral side 20 mm from the outer peripheral end of the wafer outer peripheral invalid region 3 by the dicing blade. After cutting several lines at a pitch smaller than the pitch X of the product, the wafer outer peripheral invalid region 3 extends from the side facing the OF to the inner peripheral side 20 mm from the outer peripheral end of the wafer outer peripheral invalid region 3. Cut several lines at a pitch smaller than the pitch X of the product.

Next, in the dicing Ch (2)', from the position where the angle is rotated by 90 ° with respect to the OF by the dicing blade (upper side in FIG. 5B), the inner circumference from the outer peripheral end of the wafer outer peripheral invalid region 3 After cutting several lines at a pitch smaller than the pitch X of the product over a range of 20 mm on the side, the outer circumference of the wafer is rotated by −90 ° with respect to the OF (lower side in FIG. 5 (b)). Several lines are cut at a pitch smaller than the pitch X of the product over a range of 20 mm on the inner peripheral side from the outer peripheral end of the invalid region 3.

Next, in the dicing Ch (1), the effective chip region 2 is cut from the OF side to the side facing the OF by the dicing blade at the pitch X of the product having a predetermined pitch.

Next, in the dicing Ch (2), the position where the effective tip region 2 is rotated by -90 ° from the position where the angle of the effective tip region 2 is rotated by 90 ° with respect to the OF (upper side in FIG. 5 (b)) by the dicing blade ( Cut at the pitch Y of the product over the lower side in FIG. 5 (b).

As described above, in the method for manufacturing the semiconductor chip 1a, the cutting in the discard dicing step (a) is performed over a range of 20 mm from the outer peripheral end of the wafer outer peripheral invalid region 3 to the inner peripheral side. Therefore, the stress of the internal semiconductor wafer 1 can be more effectively dissipated before the dicing step (b) by discarding all the portions where the warp and strain are considered to be steep and cutting in the dicing step (a). can.

<Embodiment 4>
Next, the fourth embodiment will be described. FIG. 6 is a plan view showing a method of manufacturing the semiconductor chip 1a according to the fourth embodiment. FIG. 7 is a plan view showing a method of manufacturing the semiconductor chip 1a according to the first modification of the fourth embodiment. FIG. 8 is a plan view showing a method of manufacturing the semiconductor chip 1a according to the second modification of the fourth embodiment. FIG. 9 is a plan view showing a method of manufacturing the semiconductor chip 1a according to the third modification of the fourth embodiment. FIG. 10 is a plan view showing a method of manufacturing the semiconductor chip 1a according to the modified example 4 of the fourth embodiment. FIG. 11 is a plan view showing a method of manufacturing the semiconductor chip 1a according to the fifth modification of the fourth embodiment. In the fourth embodiment, the same components as those described in the first to third embodiments are designated by the same reference numerals and the description thereof will be omitted.

The amount of warpage and strain that correlates greatly with chipping tends to be larger for products with higher withstand voltage or smaller theoretical numbers, that is, larger chip sizes. As shown in FIG. 6, in the fourth embodiment, the effective chip region 2 in the semiconductor wafer 1A is reduced by providing the effective chip region 2 in the effective chip region 2, and the cutting in the discard dicing step (b) is performed. , It is performed for the wafer outer peripheral invalid area 3 and the effective chip area ineffective area 4.

As shown in FIG. 6, the semiconductor wafer 1A includes an effective chip region 2 and a wafer outer peripheral invalid region 3, and the effective chip region 2 is provided with an ineffective chip region 4 in the effective chip region. The invalid region 4 in the effective chip region is a monitor pattern that serves as a mark when the semiconductor wafer 1 is manufactured, and is provided on the OF side of the effective chip region 2. The length in the lateral direction (length in the left-right direction in FIG. 6) of the invalid region 4 in the effective chip region is the same as the pitch X of the product.

The base material of the semiconductor wafer 1A is a thinned compound semiconductor such as Si, SiC or GaN. The same applies to the semiconductor wafers 1B to 1F described below.

The monitor patterns are, for example, recognition marks, length measurement patterns, alignment marks, alignment marks, TEG marks, and the like. Since the monitor patterns are unnecessary after the dicing step (b), there is no problem even if they are cut.

A method for manufacturing the semiconductor wafer 1A will be briefly described. The semiconductor wafer 1A is manufactured through a step (e) of forming an effective chip region 2 and an ineffective region 3 on the outer periphery of the wafer, and a step (f) of forming an ineffective region 4 in the effective chip region in the effective chip region 2. Since the other steps are the same as in the case of the conventional semiconductor wafer, the description thereof will be omitted.

Next, a method for manufacturing the semiconductor chip 1a will be described. First, in the dicing Ch (1)', the wafer outer peripheral invalid region 3 and the effective chip inward invalid region 4 are cut at the pitch X of the product from the OF side of the wafer outer peripheral invalid region 3 by the dicing blade, and then the wafer outer peripheral invalid region 3 is invalidated. The wafer outer peripheral invalid region 3 is cut at the pitch X of the product from the side of the region 3 facing the OF. Since the dicing Ch (1) and subsequent steps are the same as in the case of the first embodiment, the description thereof will be omitted.

As shown in FIG. 7, the invalid region 4 in the effective chip region of the semiconductor wafer 1B may be provided on the side of the effective chip region 2 facing the OF. In this case, the dicing Ch (1)'is performed from the side where the invalid region 4 in the effective chip region is provided. The ineffective region 4 in the effective chip region shown in FIGS. 6 and 7 can be applied to the semiconductor wafer 1 on which a semiconductor chip having a medium to large chip size of 5.0 mm × 5.0 mm or more is formed, for example. ..

Further, as shown in FIG. 8, the ineffective region 4 in the effective chip region of the semiconductor wafer 1C may be provided on the OF side of the effective chip region 2 and the side facing the OF. The ineffective region 4 in the effective chip region shown in FIG. 8 can be applied to the semiconductor wafer 1 on which the semiconductor chip 1a having a relatively small chip size of, for example, less than 5.0 mm × 5.0 mm is formed.

Further, as shown in FIG. 9, the ineffective region 4 in the effective chip region of the semiconductor wafer 1D is provided so as to extend from a position rotated by ± 90 ° with respect to the OF of the effective chip region 2 to the central portion. May be good.

Further, as shown in FIG. 10, the OF side of the effective chip region 2 of the semiconductor wafer 1E may be increased, and the invalid region 4 in the effective chip region may be provided on the side facing the OF. The two-dot chain line in FIG. 10 shows the inner circumference of the wafer outer peripheral invalid region 3 when the invalid region 4 in the effective chip region is not provided.

Further, as shown in FIG. 11, the ineffective region 4 in the effective chip region of the semiconductor wafer 1F may be provided over the entire inner peripheral portion of the ineffective region 3 on the outer periphery of the wafer. The two-dot chain line in FIG. 11 shows the inner circumference of the wafer outer peripheral invalid region 3 when the invalid region 4 in the effective chip region is not provided.

As described above, the semiconductor wafers 1A to 1F include an effective chip region 2 which is a region where a plurality of semiconductor chips 1a are formed, and a wafer outer peripheral invalid region 3 which is a region on the outer peripheral side of the effective chip region 2. The effective chip area 2 is provided with the ineffective chip area 4 in the effective chip area. Further, in the method for manufacturing the semiconductor chip 1a, the effective chip region 2 is provided with the invalid region 4 in the effective chip region, and the cutting in the discard dicing step (a) is performed with respect to the wafer outer peripheral invalid region 3 and the invalid region 4 in the effective chip region. Will be done.

Therefore, the stress of the internal semiconductor wafer 1 is diced by providing the ineffective region 4 in the effective chip region in the peripheral portion or the central portion of the outer peripheral portion of the semiconductor wafers 1A to 1F where the stress due to warpage and strain is likely to be inherent. It can be more effectively diverged before step (b).

Further, in the method of manufacturing the semiconductor wafers 1A to 1F, an effective chip region 2 which is a region where a plurality of semiconductor chips 1a are formed and a wafer outer peripheral invalid region 3 which is a region on the outer peripheral side of the effective chip region 2 are formed. The step (e) and the step (f) of forming the ineffective region 4 in the effective chip region in the effective chip region 2 are provided.

Therefore, since it is only necessary to form the ineffective region 4 in the effective chip region in the effective chip region 2 with respect to the conventional semiconductor wafer, the stress of the internal semiconductor wafer 1 is more effectively dissipated before the dicing step (b). The possible semiconductor wafer 1 can be easily manufactured.

The base material of the semiconductor wafers 1A to 1F is a thinned compound semiconductor such as Si, SiC or GaN. Further, the semiconductor wafers 1A to 1F are warped or distorted. Therefore, it is possible to suppress the progress of dicing in an unstable state in the semiconductor wafers 1A to 1F whose base material is a thinned compound semiconductor such as Si, SiC or GaN in which warpage or distortion is likely to occur. As a result, it is possible to suppress the frequent occurrence of chipping of the semiconductor chip 1a, which is a product.

<Embodiment 5>
Next, the fifth embodiment will be described. FIG. 12 is a schematic plan view of the semiconductor wafer 1G according to the fifth embodiment. FIG. 13 is a plan view of the semiconductor wafer 1G according to the fifth embodiment. In the fifth embodiment, the same components as those described in the first to fourth embodiments are designated by the same reference numerals and the description thereof will be omitted.

As shown in FIGS. 12 and 13, in the fifth embodiment, the effective chip region 2 is increased by reducing the wafer outer peripheral invalid region 3 of the semiconductor wafer 1G to 3.0 mm or more and 5.0 mm or less, and the semiconductor. The wafer 1G is provided with a marking 5 as a mark for removing it as a defective product in the portion on the OF side in the effective chip region 2. The base material of the semiconductor wafer 1G is a thinned compound semiconductor such as Si, SiC or GaN.

More specifically, the marking 5 is provided on the portion of the effective chip region 2 that becomes the two semiconductor chips 1a in contact with the wafer outer peripheral invalid region 3 on the OF side. The portion where the marking 5 is provided is a portion that was conventionally the wafer outer peripheral invalid region 3, and the semiconductor chip 1a formed in the OF-side portion of the effective chip region 2 where stress due to warpage and strain is likely to be present is provided. , The marking 5 is provided for the purpose of removing in advance. The two-dot chain line in FIG. 12 shows the inner circumference of the wafer outer peripheral invalid region 3 when the marking 5 is not provided.

A method for manufacturing the semiconductor wafer 1G will be briefly described. The semiconductor wafer 1G is manufactured through a step (g) of forming an effective chip region 2 and a wafer outer peripheral invalid region 3 and a step (h) of forming a marking 5 on the OF side portion of the effective chip region 2. ing. Since the other steps are the same as in the case of the conventional semiconductor wafer, the description thereof will be omitted.

Next, a method for manufacturing the semiconductor chip 1a will be described. First, in the dicing Ch (1), the effective chip area 2 is cut at the pitch X of the product, which is a predetermined pitch, from the OF side of the effective chip area 2 to the side facing the OF.

Next, in the dicing Ch (2), the angle is rotated by 90 ° with respect to the OF of the effective tip region 2 (upper side in FIG. 13) to the position rotated by −90 ° (lower side in FIG. 13). A plurality of semiconductor chips 1a are separated into individual pieces by cutting the effective chip area 2 at the pitch X of the product having a predetermined pitch.

Next, the semiconductor chip provided with the marking 5 is removed from the plurality of semiconductor chips 1a that have been fragmented (step (d)). Here, the dicing Ch (1) and Ch (2) correspond to the dicing step (c).

As described above, the semiconductor wafer 1G includes an effective chip region 2 which is a region where a plurality of semiconductor chips 1a are formed, and a wafer outer peripheral invalid region 3 which is a region on the outer peripheral side of the effective chip region 2 and is an effective chip. A marking 5 is provided on the OF side portion of the region 2 as a mark for removing it as a defective product. Further, in the method for manufacturing the semiconductor chip 1a, a marking 5 is provided on the OF side portion of the effective chip area 2 as a mark for removing it as a defective product, and the effective chip area 2 is cut into a plurality of pieces at a predetermined pitch. This comprises a dicing step (c) in which the plurality of semiconductor chips 1a are fragmented, and a step (d) in which the semiconductor chip 1a provided with the marking 5 is removed from the fragmented semiconductor chips 1a.

Therefore, it is possible to remove in advance the semiconductor chip 1a on the outer peripheral portion of the effective chip region 2 where chipping is likely to occur due to the internal stress due to warpage and strain. Further, unlike the first to fourth embodiments, it is not necessary to perform the discard dicing step (a), which simplifies dicing. The fifth embodiment is mainly applied to the semiconductor wafer 1G on which the rectangular semiconductor chip 1a is formed.

The base material of the semiconductor wafer 1G is a thinned compound semiconductor such as Si, SiC or GaN. Further, the semiconductor wafer 1G is warped or distorted. Therefore, it is possible to suppress the progress of dicing in an unstable state in the semiconductor wafer 1G whose base material is a thinned compound semiconductor such as Si, SiC or GaN in which warpage or distortion is likely to occur. As a result, it is possible to suppress the frequent occurrence of chipping of the semiconductor chip 1a, which is a product.

<Embodiment 6>
Next, the sixth embodiment will be described. FIG. 14 is a plan view showing a method of manufacturing the semiconductor chip 1a according to the sixth embodiment. FIG. 15 is a plan view showing a method of manufacturing the semiconductor chip 1a according to the first modification of the sixth embodiment. FIG. 16 is a plan view showing a method of manufacturing the semiconductor chip 1a according to the second modification of the sixth embodiment. FIG. 17 is a plan view showing a method of manufacturing the semiconductor chip 1a according to the third modification of the sixth embodiment. FIG. 18 is a plan view showing a method of manufacturing the semiconductor chip 1a according to the fourth modification of the sixth embodiment. FIG. 19 is a plan view showing the order of dicing in the method for manufacturing the semiconductor chip 1a according to the fourth modification of the sixth embodiment. In the sixth embodiment, the same components as those described in the first to fifth embodiments are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIGS. 14 and 15, in the sixth embodiment, the cutting in the discard dicing step (a) is performed at a different angle with respect to the OF than the cutting in the dicing step (b). Mainly in the dicing Ch (1)', the angle is rotated in the range of 1 ° or more and 45 ° or less with respect to the OF. FIG. 14 is an example of cutting by rotating the angle by 45 ° with respect to the OF, and FIG. 15 is an example of cutting by rotating the angle by 1 ° or more and 3 ° or less with respect to the OF.

Alternatively, as shown in FIG. 16, it is also possible to cut to the middle (about 1/2) of the dicing line at Ch (1)'of dicing.

Alternatively, as shown in FIG. 17, it is also possible to cut within the range of the wafer outer peripheral invalid region 3 in the dicing Ch (1)'and Ch (2)'. First, in the dicing Ch (1)', the position where the angle is rotated by −90 ° with respect to the OF (lower side in FIG. 17) and the position where the angle is rotated by 90 ° with respect to the OF (upper side in FIG. 17). ) Is cut in this order. Next, in the dicing Ch (2)', cutting is performed in the order of the OF side of the wafer outer peripheral invalid region 3 and the side facing the OF of the wafer outer peripheral invalid region 3. However, cut so that it does not overlap with the dicing line of the product.

Alternatively, as shown in FIG. 18, the cutting in the discard dicing step (a) can be performed in the direction from the outer peripheral edge of the wafer outer peripheral invalid region 3 toward the center of the semiconductor wafer 1. In this case, the semiconductor wafer 1 is cut diagonally in the order in which the numbers in single brackets shown in FIG. 19 are attached.

As described above, in the method for manufacturing the semiconductor chip 1a, the cutting in the discard dicing step (a) is performed at a different length or an angle with respect to the OF as compared with the cutting in the dicing step (b). Alternatively, the cutting in the discard dicing step (a) is performed in the direction from the outer peripheral edge of the wafer outer peripheral invalid region 3 toward the center of the semiconductor wafer 1.

Therefore, even when the cutting length, angle, or direction in the discard dicing step (a) is changed, chipping that occurs from the side surface to the back surface of the semiconductor chip 1a can be suppressed.

In the present invention, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted within the scope of the invention.

1,1A, 1B, 1C, 1D, 1E, 1F, 1G semiconductor wafer, 1a semiconductor chip, 2 effective chip area, 3 wafer outer circumference invalid area, 4 effective chip area invalid area, 5 marking.

Claims (9)

A method for manufacturing a semiconductor chip in which a plurality of semiconductor chips are individualized from a semiconductor wafer having an effective chip region which is a region in which a plurality of semiconductor chips are formed and a wafer outer peripheral invalid region which is a region on the outer peripheral side of the effective chip region. And
(A) A discard dicing step of cutting the wafer outer peripheral invalid region at a predetermined pitch, and a discard dicing step.
(B) A dicing step of cutting a plurality of the semiconductor chips into individual pieces by cutting the effective chip area at a predetermined pitch.
A method for manufacturing a semiconductor chip. The method for manufacturing a semiconductor chip according to claim 1, wherein the predetermined pitch in the discard dicing step (a) is the same as the predetermined pitch in the dicing step (b). The method for manufacturing a semiconductor chip according to claim 1, wherein the predetermined pitch in the discard dicing step (a) is smaller than the predetermined pitch in the dicing step (b). The method for manufacturing a semiconductor chip according to claim 1, wherein the cutting in the discard dicing step (a) is performed over a range of 20 mm from the outer peripheral end of the wafer outer peripheral invalid region to the inner peripheral side. An invalid area within the effective chip area is provided in the effective chip area, and the effective chip area is provided.
The method for manufacturing a semiconductor chip according to claim 1, wherein the cutting in the discard dicing step (a) is performed for the ineffective region in the outer peripheral region of the wafer and the ineffective region in the effective chip region. The method for manufacturing a semiconductor chip according to claim 1, wherein the cutting in the discard dicing step (a) is performed at a different angle with respect to a different length or an orientation flat from the cutting in the dicing step (b). The method for manufacturing a semiconductor chip according to claim 1, wherein the cutting in the discard dicing step (a) is performed in a direction from the outer peripheral edge of the wafer outer peripheral invalid region toward the center of the semiconductor wafer. The method for manufacturing a semiconductor chip according to any one of claims 1 to 7 , wherein the base material of the semiconductor wafer is a thinned Si or a compound semiconductor. The method for manufacturing a semiconductor chip according to claim 8 , wherein the semiconductor wafer is warped or distorted.

Images