JP2021118233A - Manufacturing method of semiconductor device - Google Patents

Abstract

To provide a technique for suppressing the occurrence of chipping and cracking in a semiconductor device.SOLUTION: A manufacturing method of a semiconductor device includes a first step of dicing a semiconductor wafer such that a dicing blade is tilted with respect to the thickness direction of the semiconductor wafer, and a second step of dicing the semiconductor wafer such that the dicing blade is inclined to the side opposite to the first step with respect to the thickness direction of the semiconductor wafer. A first pass region through which the dicing blade passes through the semiconductor wafer in the first step intersects with a second pass region through which the dicing blade passes through the semiconductor wafer in the second step.SELECTED DRAWING: Figure 4

Description

The techniques disclosed herein relate to methods of manufacturing semiconductor devices.

Patent Document 1 discloses a method for manufacturing a semiconductor device. In this manufacturing method, two notches (grooves) along the dicing line are formed on the upper surface of the semiconductor wafer. These two notches are formed so as to be inclined to opposite sides with respect to the thickness direction of the semiconductor wafer. That is, the two notches are formed so as to separate from each other as they proceed downward from the upper surface of the semiconductor wafer. Then, the semiconductor wafer is thinned by polishing from the lower surface side thereof. When the polished surface reaches the notch, the semiconductor wafer is divided into a plurality of semiconductor devices.

Japanese Unexamined Patent Publication No. 2006-108254

In the manufacturing method of Patent Document 1, a notch inclined with respect to the thickness direction of the semiconductor wafer is formed along the dicing line. Therefore, the corner portion formed by the upper surface and the side surface of the manufactured semiconductor device forms an acute angle. Therefore, when handling a semiconductor device (that is, a chip), chipping or cracks are likely to occur at the corner portion due to vibration or external stress. The present specification provides a technique for suppressing the occurrence of chipping or cracking in a semiconductor device.

The method for manufacturing a semiconductor device disclosed in the present specification includes a first step of dicing the semiconductor wafer so that the dicing blade is tilted with respect to the thickness direction of the semiconductor wafer, and a method of manufacturing the semiconductor wafer with respect to the thickness direction of the semiconductor wafer. It has a second step of dicing the semiconductor wafer so that the dicing blade is inclined to the side opposite to the first step. The first passing region through which the dicing blade passes through the semiconductor wafer in the first step intersects with the second passing region through which the dicing blade passes through the semiconductor wafer in the second step.

In this manufacturing method, in the first step, the semiconductor wafer is diced so that the dicing blade is tilted in the thickness direction of the semiconductor wafer, and in the second step, the dicing blade is first in the thickness direction of the semiconductor wafer. The semiconductor wafer is diced so as to be inclined to the side opposite to the process. In the first step and the second step, the first pass region through which the dicing blade passes through the semiconductor wafer in the first step and the second pass region through which the dicing blade passes through the semiconductor wafer in the second step intersect. Will be done. Therefore, the acute-angled corners formed in the first step are cut in the second step. Therefore, each corner portion of the manufactured semiconductor device (the corner portion composed of the upper surface and the side surface and the corner portion composed of the lower surface and the side surface) forms an obtuse angle. As described above, in this manufacturing method, since the acute-angled corners are removed, it is possible to suppress the occurrence of chipping and cracks in the semiconductor device.

A plan view of a semiconductor wafer. The figure for demonstrating the preparation process in the manufacturing process of embodiment. The figure for demonstrating the 1st dicing process in the manufacturing process of embodiment. The figure for demonstrating the 2nd dicing process in the manufacturing process of embodiment. The perspective view which shows typically the appearance of the manufactured semiconductor device. The figure for demonstrating the 3rd dicing process in the manufacturing process of the modification.

The method for manufacturing the semiconductor device of the present embodiment will be described with reference to the drawings. In the following, only the steps that are the features of this embodiment will be described. Therefore, the actual manufacturing method may include one or more steps not included in the following description, if necessary. The manufacturing method of the present embodiment includes a preparatory step, a first dicing step, and a second dicing step.

(Preparation process)
In the preparation step, first, the semiconductor wafer 12 shown in FIG. 1 is prepared. The semiconductor wafer 12 is made of SiC (silicon carbide). However, the semiconductor wafer 12 may be made of another semiconductor material. A plurality of semiconductor devices 10 are integrally formed on the semiconductor wafer 12. Each semiconductor device 10 is a power semiconductor element such as a MOSFET. Each semiconductor device 10 is regularly arranged on the semiconductor wafer 12 in the x-direction and the y-direction. The broken line 16 shown in FIG. 1 indicates a line to be diced later (hereinafter, referred to as a dicing line 16).

Next, as shown in FIG. 2, the dicing tape 18 is attached so as to cover the lower surface 12b of the semiconductor wafer 12. The dicing tape 18 is attached so as to cover substantially the entire lower surface 12b of the semiconductor wafer 12.

(1st dicing process)
The dicing of the semiconductor wafer 12 is first carried out along the dicing line 16 extending in the x direction of FIG. In the first dicing step, as shown in FIG. 3, the semiconductor wafer 12 to which the dicing tape 18 is attached is arranged on the dicing stage 20. In the first dicing step, the dicing stage 20 is tilted by an angle θ1 with respect to the horizontal plane. More specifically, the dicing stage 20 is tilted by an angle θ1 with respect to the horizontal plane about the direction in which the dicing line 16 extends (that is, the x direction). Therefore, the semiconductor wafer 12 arranged on the dicing stage 20 is also tilted by an angle θ1 with respect to the horizontal plane.

Next, the dicing blade 22 dices the semiconductor wafer 12 along the dicing line 16. In this step, dicing is performed along all the dicing lines 16 extending in the x direction. Since the semiconductor wafer 12 is tilted by an angle θ1 with respect to the horizontal plane, the dicing blade 22 is tilted by an angle θ1 with respect to the thickness direction of the semiconductor wafer 12 and passes through the semiconductor wafer 12. That is, the semiconductor wafer 12 is diced at an angle θ1 inclined with respect to the thickness direction thereof. The semiconductor wafer 12 is divided by the first dicing step. Each divided portion is supported by the dicing tape 18.

(Second dicing process)
Subsequently, the second dicing step is carried out. As shown in FIG. 4, in the second dicing step, the dicing stage 20 is tilted with respect to the horizontal plane about the x direction by an angle θ1 opposite to the first dicing step. Therefore, the semiconductor wafer 12 arranged on the dicing stage 20 is also tilted by an angle θ1 with respect to the horizontal plane on the side opposite to the first dicing step. The angle at which the semiconductor wafer 12 is tilted in the first dicing step and the second dicing step is not particularly limited. In the first dicing step and the second dicing step, the semiconductor wafer 12 may be tilted at the same angle with respect to the horizontal plane, or may be tilted at different angles.

Next, the dicing blade 22 dices the semiconductor wafer 12 again along the dicing line 16. In this step, as in the first dicing step, dicing is performed along all the dicing lines 16 extending in the x direction. Since the semiconductor wafer 12 is tilted by an angle θ1 on the side opposite to the first dicing step with respect to the horizontal plane, the dicing blade 22 is inclined at an angle θ1 on the side opposite to the first dicing step with respect to the thickness direction of the semiconductor wafer 12. It is inclined by only and passes through the semiconductor wafer 12. That is, the semiconductor wafer 12 is diced at an angle θ1 inclined to the side opposite to the first dicing step with respect to the thickness direction thereof. In the second dicing step, the second passing region 32 through which the dicing blade 22 passes through the semiconductor wafer 12 intersects with the first passing region 30 through which the dicing blade 22 passes through the semiconductor wafer 12 in the first dicing step. Dicing is done. Therefore, a corner portion 34 is formed on the dicing surface (the surface cut by the dicing blade 22) at an intermediate position in the thickness direction thereof.

After that, the above-mentioned first dicing step and second dicing step are carried out in the same manner along all the dicing lines 16 extending in the y direction of FIG. By the above steps, the semiconductor wafer 12 is divided into a plurality of semiconductor devices 10 shown in FIG.

In the present embodiment, in the first dicing step, the semiconductor wafer 12 is inclined with respect to its thickness direction for dicing. Therefore, as shown in FIG. 3, an acute-angled corner portion 36 is formed on the lower surface 12b side of the semiconductor wafer 12. Therefore, as shown in FIG. 3, cracks 37 are likely to occur in the vicinity of the corner portion 36, which has an acute angle, due to vibration or blurring during dicing. However, in the present embodiment, the second dicing step is carried out after the first dicing step. In the second dicing step, the semiconductor wafer 12 is inclined in the thickness direction opposite to the first dicing step to perform dicing. Further, the second dicing step is carried out so that the first passing region 30 and the second passing region 32 intersect. Therefore, as shown in FIG. 4, the acute-angled corner portion 36 is removed in the second dicing step. That is, in the second dicing step, the corner portion 36 where cracks may occur is removed. Therefore, in the present embodiment, chipping caused by dicing can be suppressed.

Further, in the present embodiment, as shown in FIG. 5, since the corner portions 34, 38, and 40 of the semiconductor device 10 that have been separated from each other have obtuse angles, when the semiconductor device 10 is picked up from the dicing tape 18, the semiconductor device 10 is picked up. After that, chipping and cracking are unlikely to occur due to the external stress applied when the semiconductor device 10 is mounted.

After the second dicing step is carried out, the third dicing step described below may be carried out. In the third dicing step, first, as shown in FIG. 6, the dicing stage 20 is leveled. Then, the semiconductor wafer 12 is diced along the dicing line 16 by the dicing blade 24 having a width wider than that of the dicing blade 22. As a result, the corner portion 34 (see FIGS. 4 and 5) is chamfered. In this way, when the third dicing step is carried out, the corners 42 and 44 of the fragmented semiconductor device have an obtuse angle than the corners 34, so that the semiconductor device is less likely to chip due to external stress. Can be manufactured.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described herein or in the drawings exhibit their technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in this specification or drawings achieve a plurality of objectives at the same time, and achieving one of the objectives itself has technical usefulness.

10: Semiconductor device 12: Semiconductor wafer 12b: Bottom surface 16: Dicing line 18: Dicing tape 20: Dicing stage 22, 24: Dicing blade 30: First passage region 32: Second passage region 34, 36, 38, 40: Square Department

Claims (1)

It is a manufacturing method of semiconductor devices.
The first step of dicing the semiconductor wafer so that the dicing blade is inclined with respect to the thickness direction of the semiconductor wafer, and
A second step of dicing the semiconductor wafer so that the dicing blade is inclined to the side opposite to the first step with respect to the thickness direction of the semiconductor wafer.
Have,
A manufacturing method in which a first passing region through which the dicing blade passes through the semiconductor wafer in the first step intersects with a second passing region through which the dicing blade passes through the semiconductor wafer in the second step.

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