JPS6142931A - Dividing method for semiconductor wafer - Google Patents

Dividing method for semiconductor wafer

Info

Publication number
JPS6142931A
JPS6142931A JP59165860A JP16586084A JPS6142931A JP S6142931 A JPS6142931 A JP S6142931A JP 59165860 A JP59165860 A JP 59165860A JP 16586084 A JP16586084 A JP 16586084A JP S6142931 A JPS6142931 A JP S6142931A
Authority
JP
Japan
Prior art keywords
wafer
sheet
semiconductor wafer
dividing
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59165860A
Other languages
Japanese (ja)
Inventor
Mitsuo Sakamoto
光男 坂本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP59165860A priority Critical patent/JPS6142931A/en
Publication of JPS6142931A publication Critical patent/JPS6142931A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To remove defective chips easily by dividing a wafer into each chip and making the defective chips adhere to a composite resin sheet on the upper side for removal thereof after making an ink mark having a strong adhesion adhere onto a defective chip member and applying the composite resin sheet to both faces of a wafer for vacuum seal. CONSTITUTION:After sol-like silicon resin is made to adhere to the surface of a chip member 1a which has been defective, it is dried to strengthen adhesion thereof to a vinyl chloride sheet. Next, cut-grooves 3 for division which are partitioned into each chip member 1a and provided on the surface of a wafer 1 like a square on a go board. A No.1 vinyl sheet 4 and a No.2 vinyl sheet 5 are overlapped on the wafer 1 in this state from the back and the surface respectively to exhaust air between the vinyl sheets 4 and 5. Thus, the space therebetween is brought into a vacuum seal state. Next, the wafer 1 is pushed up from the back of the vinyl sheet 4 by a roller to divide thereof into each chip 6 clong cut-grooves chips 6 are removed by an ink mark 3 with the defective chips 6 made to adhere to the vinyl sheet 5.

Description

【発明の詳細な説明】 〔発明の技術分野〕 この発明は1表面に碁盤目に入れられた切込み溝に沿っ
て多数の半導体チップに分割する。半導体ウエーノ〜の
分割方法に関する。
DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] This invention divides one surface into a number of semiconductor chips along cut grooves cut into a grid pattern. This invention relates to a method for dividing semiconductor wafers.

〔゛従来技術〕[Conventional technology]

所要の能動領域が形成された半導体ウェーハ(以下「ウ
ェーハ」と称する)を分割し、多数個の半導1体チップ
(以下「チップ」と称する)を得る方法として1次の工
程によっている。(a)薄板状に形成されたウェーハの
表面に、所要のチップに分割するための切込み溝(スク
ライプライン)を碁盤目に入れる。(b)この状態のウ
エーノ・裏面側から押上刃を加えることによシ、切込み
溝に沿って割れ目を生じさせ個々のチップに分割する。
A first step is used as a method of dividing a semiconductor wafer (hereinafter referred to as "wafer") on which a required active region is formed to obtain a large number of integrated semiconductor chips (hereinafter referred to as "chips"). (a) Cut grooves (scribe lines) for dividing into required chips are cut in a grid pattern on the surface of a wafer formed into a thin plate shape. (b) By applying a push-up blade to the wafer in this state from the back side, a crack is created along the cutting groove and the chip is divided into individual chips.

(c)所要のチップを選び出す。(c) Select the required chips.

このうち、 (b) 、 (c)の工程において1個々
のチップを簡単に、しかも歩留シよく得るため、従来。
Among these, in order to easily obtain individual chips in steps (b) and (c) with a high yield, conventional methods are used.

次の方法によっていた。It was done by the following method.

(A)  表面だ碁盤目の切込み溝が入れられたウェー
ハの裏面に第1の塩化ビニールシートを当て。
(A) A first vinyl chloride sheet is applied to the back side of the wafer, which has cut grooves in a grid pattern on the front side.

表面に第2の塩化ビニールシートを当て、双方のシート
間にウェーハを真空封止(真空パック)する。
A second vinyl chloride sheet is applied to the surface, and the wafer is vacuum sealed (vacuum packed) between both sheets.

(B)  所要のチップの大きさに応じたローラを用い
、下方からウェーハに押上刃を加え、個々のチップに分
割する。
(B) Using a roller corresponding to the required chip size, a push-up blade is applied to the wafer from below to divide it into individual chips.

(0)  表面側の第2の塩化ビニールシート(以下「
ビニールシート」と称する)をはぎ取る。このとき、各
チップは第1の塩化ビニールシート(以下「ビニールシ
ート」と称する)上に付着したままであるっ (D)  この状態の第1のビニールシートを四方に伸
長し、この伸長状態に維持しておく。
(0) Second vinyl chloride sheet on the front side (hereinafter “
(referred to as "vinyl sheet"). At this time, each chip remains attached to the first vinyl chloride sheet (hereinafter referred to as "vinyl sheet").(D) The first vinyl sheet in this state is stretched in all directions, and Keep it.

このように、シート伸長法により、各チップが所要の間
隔を保ち整然と配列された状態になシ。
In this way, by using the sheet stretching method, each chip can be arranged in an orderly manner with the required spacing.

所要のチップを容易に選び出すことができる:1″!!
た。吸着具を用いてチップを吸着し取出すことができ、
半導体装置の組立てが容易になるようにしている。
You can easily select the desired chip: 1″!!
Ta. Chips can be sucked and removed using a suction tool.
This makes it easier to assemble semiconductor devices.

上記従来方法では1個々のチップが適当な間隔を保ち整
列状態にされるが、不良品チップが良品チップに混在し
て整列されておシ、チップを取出し組立てるのに、良品
と不良品を何らかの方法で区別する必要があシ1面倒で
あった。
In the conventional method described above, individual chips are aligned at appropriate intervals, but defective chips are mixed with good chips and are aligned. It was troublesome to have to differentiate by method.

〔発明の概要〕[Summary of the invention]

この発明は、ウエーノ1の不良のチップ部上に、付着力
の強いインクマークを付着し、ウエーノ・の表面に碁盤
目状に切込み溝を入れ、ウェーI・の裏面及び表面に第
1及び第2の合成樹脂シートを重ねて覆い、真空封止し
て後、ウエーノ・を切込み溝に沿って各チップに分割し
、第2の合成樹脂シートを引きはがすことにより、イン
クマークで付着している不良チップをともに取除き、良
品のチップのみが第1の合成樹脂シート上に残るように
し。
In this invention, a highly adhesive ink mark is attached on the defective chip part of the wafer 1, grooves are cut in a checkerboard pattern on the surface of the wafer 1, and first and second marks are placed on the back and front surfaces of the wafer 1. After overlapping and covering the second synthetic resin sheet and vacuum sealing, the Ueno® is divided into chips along the cut grooves, and by peeling off the second synthetic resin sheet, the chips are adhered with ink marks. Both defective chips are removed so that only good chips remain on the first synthetic resin sheet.

不良チップが容易に取除かれ、vk工程での組立の作業
性が大幅に向上される半導体ウェーハの分割方法を提供
することを目的としている。
It is an object of the present invention to provide a semiconductor wafer dividing method in which defective chips are easily removed and assembly workability in the VK process is greatly improved.

〔発明の実施例〕[Embodiments of the invention]

以下、この発明の一実施例によるウェーハの分割方法を
1図によシ説明する。
Hereinafter, a method for dividing a wafer according to an embodiment of the present invention will be explained with reference to FIG.

第1図はウェーハの平面図で、ウェーハ(1)は例えば
、ガリウムひ素からなる基板に電界効果トランジスタの
チップ部(1a)が多数形成されである。
FIG. 1 is a plan view of a wafer, and the wafer (1) is a substrate made of, for example, gallium arsenide, on which a large number of chip portions (1a) of field effect transistors are formed.

各チップ部(1a)全数にわたり順次特性検査を行い。Characteristic tests were sequentially performed on all chip parts (1a).

不良のチップa(la)K対しては、不良品を表示する
インクマーク(3)をインク付着装@(図示は略す)に
よシ付着する。このインクマーク(2)の大きさは。
For defective chips a(la)K, an ink mark (3) indicating a defective product is attached by an ink adhering device (not shown). What is the size of this ink mark (2)?

チップ部(1a)の大きさよシ小さくしておく。このイ
ンクマーク(2)のインク材としては1例えば、トーン
・ボッティングレジンSH−1840(シリコン樹脂、
東しシリコーン社製商品名)に硬化剤を適当な粘度にな
るように十分混合して使用する。この混合後のシリコン
樹脂はゾル状態である。なお。
Make it smaller than the size of the chip part (1a). The ink material for this ink mark (2) is 1, for example, Tone Botting Resin SH-1840 (silicone resin,
(trade name, manufactured by Toshi Silicone Co., Ltd.) and a curing agent are sufficiently mixed to obtain an appropriate viscosity. The silicone resin after this mixing is in a sol state. In addition.

このシリコン樹脂は透明であり、m別に支障があれば、
必要によシ着色用のインクを混合してもよいり 上記のように、ゾル状のシリコン樹脂を、特性検査で不
良となったチップ部(1a)の表面に付着した後、清浄
な空調雰囲気中で、乾燥(例えば90°Cで10分間)
させる。すると1点状のインクマーク(2)がゾル状に
なシ、粘着力が大きく、塩化ビニールシートに対し付着
力が強くなる。
This silicone resin is transparent, so if there is any problem,
If necessary, coloring ink may be mixed in.As described above, after adhering the sol-like silicone resin to the surface of the chip part (1a) that failed in the characteristic test, it was placed in a clean air-conditioned atmosphere. Dry (e.g. 90°C for 10 minutes) in
let Then, the dot-shaped ink mark (2) becomes sol-like and has a large adhesive force, and has a strong adhesion force to the vinyl chloride sheet.

つづいて、ウェーハ(1)表面に、各チップ部(1a)
に区分し分割用の切込み溝(3)を碁盤目に入れる。
Next, each chip part (1a) is placed on the surface of the wafer (1).
Divide into sections and cut grooves (3) for division into a grid pattern.

この切込み溝(3)加工には、ダイヤモンドスクライバ
、グイシングンーなどの装置を用いる。
To process this cut groove (3), a device such as a diamond scriber or a guising gun is used.

この状態のウエーノ直1)に、第2図に示すように、第
1のビニールシート(4)を裏面から、第2のビニール
シート(5)を表面から重ね合わす、これらのビニール
シート(4) 、 (5)は、伸展性に富む材質を用い
る。
As shown in Figure 2, the first vinyl sheet (4) is superimposed on the Ueno straight 1) in this state, and the second vinyl sheet (5) is superimposed on the front surface. , (5) uses a material with high extensibility.

第3図に断面図で示すように、ビニールシート(4)上
にウェーハ(1)を裏面で接して置き、このウェーハ(
1) 表面及びビニールシー) (4)上にビニールシ
ー ) (5)を重ねる。こうして、真空ポンプ(図面
は略ス)によシビニールシー) 、(4)及び(5)間
の空気を排気し、真空封止状態にする。
As shown in the cross-sectional view in Figure 3, the wafer (1) is placed on the vinyl sheet (4) with its back side in contact with the wafer (1).
1) Overlay the vinyl sheet (5) on top of the surface and vinyl sheet (4). In this way, the air between the cylinder seats (4) and (5) is evacuated by a vacuum pump (not shown in the drawings), and a vacuum seal is created.

この際、ビニールシート(5)はウェーハ(1)全体を
覆い1周縁側がビニールシート(4)に重なる広さが必
要であシ、その材質は、付着され処理されたインクマー
ク(3)と適当な付着力を有するものを用いである。
At this time, the vinyl sheet (5) must be wide enough to cover the entire wafer (1) and overlap the vinyl sheet (4) on its periphery, and its material must be compatible with the attached and processed ink marks (3). Use a material with appropriate adhesion.

つぎに、ビニールシート(4)の裏面から、チップ部(
1a)の大きさに応じたローラ(図示は略す)を用い、
ウェーハ(1)を押上げてゆき、第4図のように、切込
み溝(2) K沿って各チップ(6)に分割する。
Next, from the back side of the vinyl sheet (4), insert the chip part (
Using a roller (not shown) according to the size of 1a),
The wafer (1) is pushed up and divided into chips (6) along the cut grooves (2) K as shown in FIG.

ついで、第5図に示すように、ビニールシート(5)の
端をピンセット(7)で挾み引きはがしていくと。
Next, as shown in Figure 5, the end of the vinyl sheet (5) is pinched with tweezers (7) and pulled off.

不良のチップ(6)はインクマーク(3)によシビニー
ルシート(5)に付着したまま取除かれていく。
The defective chip (6) is removed with the ink mark (3) still attached to the vinyl sheet (5).

こうして、第6図に示すように、ビニールシート(4)
上に良品のチップ(6)のみが整列されたまま残る。
In this way, as shown in Figure 6, the vinyl sheet (4)
Only the good chips (6) remain aligned on the top.

この後、ビニールシート(4)を伸長手段により四方に
伸長すると、第7図のように、残っている良品の各チッ
プ(6)は、相互の間隔が広げられる。このようにビニ
ールシート(4)を伸長した状態に保持しておけば、所
要のチップ(6)が容易に選び出される。とのとき、整
列しているチップ(6)は良品だけであシ、後工程での
組立てにおいて1作業性が大幅に向上される。
Thereafter, when the vinyl sheet (4) is stretched in all directions by the stretching means, the remaining non-defective chips (6) are spaced apart from each other, as shown in FIG. By holding the vinyl sheet (4) in an expanded state in this way, the desired chips (6) can be easily selected. In this case, only non-defective chips (6) are aligned, and work efficiency is greatly improved in assembly in the subsequent process.

インクマーク(3)の材質としては、ビニールシート(
5)との付着力が、ウェーハ(1)裏面とビニールシー
) (4)との付着力よシ強いものを選び、tた。チッ
プ(6)及びビニールシート(5)に悪影響を与えない
ものを用いる。
The material for the ink mark (3) is vinyl sheet (
A material with stronger adhesion to the wafer (1) and the vinyl sheet (5) than the adhesive (4) was selected and tested. Use a material that does not adversely affect the chip (6) and vinyl sheet (5).

なお、上記実施例では、インクマーク(3)としてシリ
コン樹脂系を用いたが、これに限らず、上記条件を満た
すものであれば、他の材質であってもよい。
In the above embodiment, the ink mark (3) is made of silicone resin, but is not limited to this, and may be made of other materials as long as it satisfies the above conditions.

また、上記実施例では、ウェーハ(1)はガリウムひ素
を基板としたが、他の材料の半導体基板であってもよい
Further, in the above embodiment, the wafer (1) is made of gallium arsenide, but it may be a semiconductor substrate made of other materials.

さらに、ウェーハ(1)を挾付けるシートとして。Furthermore, as a sheet for holding the wafer (1).

上記実施例では、塩化ビニールシー) (4) 、 (
5)を用いたが、伸展性に富みウェーハを容易に付着し
In the above example, (vinyl chloride sea) (4), (
5) was used, but it has excellent extensibility and wafers can be easily attached to it.

引きはがしが容易であれが、他の種の合成樹脂シートで
あってもよい。
Other types of synthetic resin sheets may be used as long as they are easy to peel off.

〔発明の効果) 以上のように、この発明の方法によれば、ウェーハの不
良のチップ部上に、付着力の強いインクマークを付着し
、ウェーハの裏面に第1の゛合成樹脂シートを当て1表
面に第2の合成樹脂シートを□重ねて覆い、真空封止後
、ウェーハを切込み溝に沿って各チップに分割し、第2
の合成樹脂シートを引きはがし、不良チップをこの第2
の合成樹脂シートにインクマークによシ付着させたまま
取除くようにしたので、不良チップが容易に除かれて良
品のチップのみが第1の合成樹脂シート上に残され、後
工程での組立の作簗性が大幅に向上され、自動化が容易
になる。
[Effects of the Invention] As described above, according to the method of the present invention, a highly adhesive ink mark is attached on the defective chip portion of a wafer, and a first synthetic resin sheet is applied to the back surface of the wafer. 1 surface is covered with a second synthetic resin sheet, and after vacuum sealing, the wafer is divided into each chip along the cut grooves, and the second
Peel off the synthetic resin sheet and remove the defective chip from this second
Since the ink mark is removed with the ink mark still attached to the first synthetic resin sheet, defective chips are easily removed and only good chips are left on the first synthetic resin sheet for assembly in the subsequent process. This greatly improves the efficiency of gleaning and facilitates automation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ないし第7図はこの発明の一実施例による半導体
ウェーハの分割方法を工程@に示し、第1図は不良チッ
プ部にインクマークを付着し切込み溝を入れた状態のウ
ェーハの平面図、第2図は第1図のウェーハを裏1表か
らビニ−/I/ シー トチ覆わんとする状態の斜視図
、第3図は第2図の状態からウェーハをビニールシート
で覆い真空封止した状態の断面図、第4因は第3図のウ
ェーハを各チップに分割した状態の断面図、第5図は第
4図の表側のビニールシートを引きはがし不良チップを
ともに@除いている状態の断面図、第6図は第5図の状
態から裏側のビニールシート上に良品チップのみが残さ
れた状態の断面図、第7図は第6図の裏側のビニールシ
ートを伸長し各良品チップの間隔を広げた状態の断面図
である。 l・・・半導体ウェーハ、la・・・チップ部、2・・
・インクマーク、3・・・切込み溝、4・・・第1の塩
化ビニールシート(合成樹脂シート)、5・・・第2の
塩化ビニールシート(合成樹脂シート)、6・・・半導
体チップ なお1図中同一行号は同−又は相当部分を示す。
Figures 1 to 7 show a method of dividing a semiconductor wafer according to an embodiment of the present invention in steps @, and Figure 1 is a plan view of the wafer with ink marks attached to defective chip parts and cut grooves made. , Figure 2 is a perspective view of the wafer in Figure 1 being covered with a vinyl sheet from the front to the back, and Figure 3 is a perspective view of the wafer in Figure 2 covered with a vinyl sheet and vacuum sealed. The fourth factor is a cross-sectional view of the wafer in Figure 3 divided into chips, and Figure 5 is the state in which the vinyl sheet on the front side of Figure 4 is removed and all defective chips are removed. Figure 6 is a cross-sectional view of the state shown in Figure 5 with only good chips remaining on the back side vinyl sheet, and Figure 7 is a cross-sectional view of the state shown in Figure 5 with only good chips remaining on the back side vinyl sheet. FIG. l...Semiconductor wafer, la...Chip part, 2...
・Ink mark, 3... Cut groove, 4... First vinyl chloride sheet (synthetic resin sheet), 5... Second vinyl chloride sheet (synthetic resin sheet), 6... Semiconductor chip The same line numbers in Figure 1 indicate the same or equivalent parts.

Claims (3)

【特許請求の範囲】[Claims] (1)半導体ウェーハに形成された多数配列のチップ部
を全数にわたり特性検査をし、不良のチップ部上に付着
力の大きいインクマークを付着する工程と、上記半導体
ウェーハの表面に上記各チップ部を区分し分割するため
の切込み溝を碁盤目状に入れる工程と、伸展性に富む第
1及び第2の合成樹脂シートにより上記半導体ウェーハ
を裏面及び表向から覆つて真空封止する工程と、この状
態の半導体ウェーハに裏側から押上刃を加え、上記切込
み溝に沿つて多数個の半導体チップに分割する工程と、
上記表面の第2の合成樹脂シートを引きはがすことによ
り、上記インクマークによりこの第2の合成樹脂シート
に付着している上記不良の半導体チップをともに取除く
工程と、上記第1の合成樹脂シートを四方に伸長し、付
着して残つている良品の上記各半導体チップの相互の間
隔を広げておく工程とからなる半導体ウェーハの分割方
法。
(1) A process of inspecting the characteristics of all the chip parts in multiple arrays formed on the semiconductor wafer, and attaching an ink mark with strong adhesion on the defective chip part, and marking each of the chip parts on the surface of the semiconductor wafer. a step of making cut grooves in a checkerboard pattern for dividing and dividing the semiconductor wafer, and a step of vacuum-sealing the semiconductor wafer by covering it from the back side and front side with highly extensible first and second synthetic resin sheets; Adding a push-up blade to the semiconductor wafer in this state from the back side and dividing it into a large number of semiconductor chips along the cut grooves,
removing the defective semiconductor chips attached to the second synthetic resin sheet by the ink marks by peeling off the second synthetic resin sheet on the surface; A method for dividing a semiconductor wafer comprising the steps of stretching the semiconductor wafer in all directions and widening the mutual spacing between the remaining good semiconductor chips.
(2)インクマークはシリコン樹脂系のインクを用いる
ことを特徴とする特許請求の範囲第1項記載の半導体ウ
ェーハの分割方法。
(2) The method for dividing a semiconductor wafer according to claim 1, wherein the ink mark uses silicone resin ink.
(3)合成樹脂シートは塩化ビニールシートからなる特
許請求の範囲第1項又は第2項記載の半導体ウェーハの
分割方法。
(3) The method for dividing a semiconductor wafer according to claim 1 or 2, wherein the synthetic resin sheet is a vinyl chloride sheet.
JP59165860A 1984-08-06 1984-08-06 Dividing method for semiconductor wafer Pending JPS6142931A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59165860A JPS6142931A (en) 1984-08-06 1984-08-06 Dividing method for semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59165860A JPS6142931A (en) 1984-08-06 1984-08-06 Dividing method for semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS6142931A true JPS6142931A (en) 1986-03-01

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP59165860A Pending JPS6142931A (en) 1984-08-06 1984-08-06 Dividing method for semiconductor wafer

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Country Link
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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089874A (en) * 1989-03-08 1992-02-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with infrared mapping markers
JP2020098859A (en) * 2018-12-18 2020-06-25 三菱電機株式会社 Semiconductor chip manufacturing method, semiconductor wafer, and semiconductor wafer manufacturing method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5359363A (en) * 1976-11-10 1978-05-29 Hitachi Ltd Adsorbed component removing method from flexible magnetic plate surface

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5359363A (en) * 1976-11-10 1978-05-29 Hitachi Ltd Adsorbed component removing method from flexible magnetic plate surface

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5089874A (en) * 1989-03-08 1992-02-18 Mitsubishi Denki Kabushiki Kaisha Semiconductor device with infrared mapping markers
JP2020098859A (en) * 2018-12-18 2020-06-25 三菱電機株式会社 Semiconductor chip manufacturing method, semiconductor wafer, and semiconductor wafer manufacturing method

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