JPS58142543A - Dicing method for semiconductor substrate - Google Patents

Dicing method for semiconductor substrate

Info

Publication number
JPS58142543A
JPS58142543A JP57026211A JP2621182A JPS58142543A JP S58142543 A JPS58142543 A JP S58142543A JP 57026211 A JP57026211 A JP 57026211A JP 2621182 A JP2621182 A JP 2621182A JP S58142543 A JPS58142543 A JP S58142543A
Authority
JP
Japan
Prior art keywords
semiconductor
substrate
sheet
semiconductor wafer
chips
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP57026211A
Other languages
Japanese (ja)
Inventor
Nobutoshi Takehashi
信逸 竹橋
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP57026211A priority Critical patent/JPS58142543A/en
Publication of JPS58142543A publication Critical patent/JPS58142543A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Dicing (AREA)

Abstract

PURPOSE:To dice an Si substrate into chips without producing cracks by a method wherein an adhesive sheet is adhered on the Si substrate and the substrate is bent. CONSTITUTION:An adhesive sheet 23 whereon a substrate 30 to be diced is adhered is fixed by holders 21 and 22, then a hollow part 24 is evacuated, and a gas is introduced into a hollow part 25 to a high pressure. Thereat, a force whereby the sheet 23 becomes a ball form generates thereon, then this force is applied on the bottom of grooves formed on the substrate 30, and accordingly it is diced into individual chips 32. Thereafter, the chips 32 are removed from the holders 21 and 22, and selected by a magnifier, etc. By this method, the substrate can be splitted with good yield.

Description

【発明の詳細な説明】 本発明は半導体@板の分割方法に関する。[Detailed description of the invention] The present invention relates to a method for dividing a semiconductor@board.

半導体装置の製造工程において、半導体ウエノ・上に形
成された各半導体装置は第1図に示すように1ダイシン
グ(スクライビング)1、分割2、ダイポンディング3
、ワイヤボンディング4、封止6および特性試験6の各
工程を経てパッケージされる。このような工程において
、従来の半導体ウニ・・の分割方法はまず半導体ウニ・
・表面に形成されたスクライブライン上に、ダイシング
、およびスクライビングにより切り溝を形成させる。次
に第2図(a)に示すようにこれら切り溝18が形成さ
れた半導体ウェハ10を表面保護シート12をしいた硬
質ラバーゴム13上に四半導体ウエノ・の裏面が上を向
くように置く。そして、半導ウエノ・1o上に、静電性
シート11を置き、前記半導体ウェハ1o1およびその
周辺の保護シート12と密着せしめる。
In the manufacturing process of semiconductor devices, each semiconductor device formed on a semiconductor wafer is processed through 1 dicing (scribing) 1, division 2, and die-ponding 3 as shown in Figure 1.
, wire bonding 4, sealing 6, and characteristic testing 6 before packaging. In such a process, the conventional method of dividing semiconductor sea urchins...
- Cut grooves are formed on the scribe lines formed on the surface by dicing and scribing. Next, as shown in FIG. 2(a), the semiconductor wafer 10 on which these grooves 18 have been formed is placed on a hard rubber 13 covered with a surface protection sheet 12 so that the back side of the four semiconductor wafers faces upward. Then, an electrostatic sheet 11 is placed on the semiconductor wafer 1o, and brought into close contact with the semiconductor wafer 1o1 and the protective sheet 12 around it.

次に、第2図(b)に示すように半導体ウエノ・10カ
硬質ラバーゴム13上の保護シート12と静電性シート
11とに密着された状態において、前記半導体ウェハ1
0の裏面にローラ14を当接させて半導体ウェハ1oの
裏面に加重を加える。前記半導体ウェハ10の裏面に加
重を加えると、硬質ラバーシート13の加重が加わった
箇所が陥没し、これにより前記半導ウェハ10に形成さ
れた溝底14に加重が集中し割れる。このように、前記
半導体ウニ・・10の裏面に加重を加え、第2図(C)
に示すように個々の半導体チップ16に分割する。
Next, as shown in FIG. 2(b), the semiconductor wafer 1 is placed in close contact with the protective sheet 12 on the hard rubber rubber 13 and the electrostatic sheet 11.
A roller 14 is brought into contact with the back surface of the semiconductor wafer 1o to apply a load to the back surface of the semiconductor wafer 1o. When a load is applied to the back surface of the semiconductor wafer 10, the portion of the hard rubber sheet 13 where the load is applied collapses, and as a result, the load concentrates on the groove bottom 14 formed in the semiconductor wafer 10, causing it to crack. In this way, a load is applied to the back surface of the semiconductor sea urchin 10, as shown in FIG. 2(C).
It is divided into individual semiconductor chips 16 as shown in FIG.

しかし、このような従来の半導体基板の分割方法におい
ては、半導体ウェハ10の裏面に加重を加えた時発生す
る半導体ウェハのカケラ16が、前記半導体チップ16
の表面に損傷を与えたり、前記半導体チップ同志が互い
に接触し合い、クラック17が起き歩留りを低下させる
おそれがあった。
However, in such a conventional semiconductor substrate dividing method, the chips 16 of the semiconductor wafer that are generated when a load is applied to the back surface of the semiconductor wafer 10 are
There is a risk that the surface of the semiconductor chips may be damaged or the semiconductor chips may come into contact with each other, causing cracks 17 and reducing the yield.

本発明は、前記従来の方法のように半導体ウェー・表面
からローラ等により集中的な加重を加えるのではなく、
気圧差による圧力を半導体ウエノ・の裏面全体に均一に
加えて半導体チップに分割する半導体基板の分割方法を
提供するものであり、半導体チップ上の回路素子をSi
カケラにより損傷すること及び半導体チップがクラック
することなく個々の半導体チップに分割することを目的
とする0 本発明の半導体基板の分割方法の実施例を図面を用いて
詳しく説明する。第3図は、本発明の半導体基板の分割
方法を達成すべく構成された装置の構成を示す。同図の
装置において、中空部24゜26を有する二つの保持具
21,22間には収縮性粘着性シート23に接着された
ダイシングずみ半導体ウエノ・30が収納されている。
The present invention does not apply intensive load from the surface of the semiconductor wafer to a roller, etc., as in the conventional method.
This method provides a method for dividing semiconductor substrates into semiconductor chips by uniformly applying pressure due to a pressure difference to the entire back surface of a semiconductor substrate.
DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the method for dividing a semiconductor substrate according to the present invention, which aims to divide the semiconductor chips into individual semiconductor chips without causing damage due to fragmentation and without cracking the semiconductor chips, will be described in detail with reference to the drawings. FIG. 3 shows the configuration of an apparatus configured to accomplish the semiconductor substrate dividing method of the present invention. In the apparatus shown in the figure, a diced semiconductor wafer 30 bonded to a shrinkable adhesive sheet 23 is housed between two holders 21 and 22 having hollow portions 24 and 26.

保持具21の中空部内24を真空にするため、その真空
度を判断する真空計26と開閉弁28が保持具21に接
続されている。保持具22と中空部内26を高圧にする
ため、その高圧度を判断する高圧針27とその開閉弁2
9が保持具22に接続されている。
In order to create a vacuum inside the hollow portion 24 of the holder 21, a vacuum gauge 26 and an on-off valve 28 for determining the degree of vacuum are connected to the holder 21. In order to make the holder 22 and the inside of the hollow part 26 high pressure, a high pressure needle 27 and its opening/closing valve 2 are used to judge the high pressure level.
9 is connected to the holder 22.

次に本発明の半導体基板の分割方法を第4図(&)。Next, FIG. 4 (&) shows a method for dividing a semiconductor substrate according to the present invention.

(b)、 (0)を用いて説明する。This will be explained using (b) and (0).

まず第4図(&)において、ダイシングずみ半導体ウェ
ハ3oを接着固定した、粘着性収縮シート23を上部保
持具21と下部保持具22との間に固定する。この時、
上部保持具21、粘着性収縮シート23、下部保持具2
2は互いに密着した状態である。次に第4図(b)にお
いて、以上の状態により上部保持具21の中空部24を
真空状態にし、−劣下部保持具22の中空部26に加圧
気体を導入することにより高圧状態にする操作をそれぞ
れ同時に行う。そうすることにより、上部保持具21と
下部保持具22との間に固定された粘着性収縮シート2
3が気圧差により、上部保持具21の中空部内24に引
きよせられる。この時、粘着性収縮シート23に接着固
定された、前記半導体ウニ・・30により初期において
、平面状に上部保持具21の中空部内24に引きよせら
れる。しかし、第4図(c)において、上部保持具21
の中空部24に引きよせられた粘着性収縮シート23は
、球状による状態になろうとする力が発生し、これによ
り、接着固定された前記半導体ウェハ30により粘着性
収縮シート23が平面状を保っていたが、前記半導体ウ
ェハ30に形成された溝の底に前記により発生した力が
加わり割れ、個々の半導体チップ32に分割される。そ
して、粘着性収縮シート23は、個々の半導体チップ3
2とわずかな間隔をもって球状の形状を形成する。この
後上部保持具21と下部保持具22から半導体チップ3
2を取りはずし、拡張機等により半導体チップ32の選
別を行う。
First, in FIG. 4(&), an adhesive shrink sheet 23 on which a diced semiconductor wafer 3o is adhesively fixed is fixed between an upper holder 21 and a lower holder 22. As shown in FIG. At this time,
Upper holder 21, adhesive shrink sheet 23, lower holder 2
2 is in a state where they are in close contact with each other. Next, in FIG. 4(b), the hollow part 24 of the upper holder 21 is made into a vacuum state under the above conditions, and pressurized gas is introduced into the hollow part 26 of the inferior part holder 22 to make it into a high pressure state. Perform each operation simultaneously. By doing so, the adhesive shrink sheet 2 fixed between the upper holder 21 and the lower holder 22
3 is drawn into the hollow portion 24 of the upper holder 21 due to the pressure difference. At this time, the semiconductor sea urchin . However, in FIG. 4(c), the upper holder 21
A force is generated in the adhesive shrink sheet 23 pulled toward the hollow part 24 to make it into a spherical shape, and as a result, the adhesive shrink sheet 23 maintains its flat shape due to the semiconductor wafer 30 that is adhesively fixed. However, the force generated as described above is applied to the bottom of the groove formed in the semiconductor wafer 30, causing it to crack and be divided into individual semiconductor chips 32. Then, the adhesive shrink sheet 23 is attached to each semiconductor chip 3.
2 and form a spherical shape with a slight interval. After this, the semiconductor chip 3 is removed from the upper holder 21 and the lower holder 22.
2 is removed, and the semiconductor chips 32 are sorted using an expansion machine or the like.

なお、ここで粘着性収縮シート23は全く通気性のない
膜であってもよいし、ある程度通気性のある膜であって
もよい。粘着性収縮シート23に通気性がある場合には
、同シートがわん曲して半導体ウェハが分割されたとき
そのカケラが発生したとしても下部保持具22の中空部
26から上部保持具21の中空部25の方へ空気の流れ
が生じ、この空気の流れによって前記カケラは上部保持
具21の真空口31から効果的に排出される。
Note that the adhesive shrink sheet 23 may be a film with no air permeability at all, or may be a film with some degree of air permeability. If the adhesive shrink sheet 23 has air permeability, even if the sheet is bent and chips are generated when the semiconductor wafer is divided, the hollow part 26 of the lower holder 22 will be removed from the hollow part of the upper holder 21. A flow of air is generated towards the section 25 , which effectively ejects the debris from the vacuum port 31 of the upper holder 21 .

以上の説明により明らかなように、半導体ウェハ分割時
には、半導体ウェー・表面は無接触状態であり又、分割
時発生する半導体ウェハのカケラによる半導体チップ表
面に形成される回路素子の損傷やクラック等が生じるこ
とはない。たとえ、半導体ウニ・・のカケラが発生した
としても、粘着シートに通気性を持たせておけば上部保
持具の真空口から排出され、前記半導体チップ上に付着
することなく、前記半導体チップ上に形成された素子の
配線間の短絡等がない。又、下部保持具の中空部に高温
加圧気体を導入することにより、粘着性収縮シートの収
縮性を抑制させ、半導体ウェハの分割を、円滑に行うこ
とができる。
As is clear from the above explanation, when the semiconductor wafer is divided, the semiconductor wafer surface is in a non-contact state, and the circuit elements formed on the semiconductor chip surface may be damaged or cracked due to the fragmentation of the semiconductor wafer that occurs during the division. It will never occur. Even if a piece of a semiconductor sea urchin occurs, if the adhesive sheet is made breathable, it will be discharged from the vacuum port of the upper holder and will not adhere to the semiconductor chip. There is no short circuit between wiring lines of the formed elements. Moreover, by introducing high temperature pressurized gas into the hollow part of the lower holder, the shrinkability of the adhesive shrink sheet can be suppressed, and the semiconductor wafer can be divided smoothly.

以上説明したように本発明の半導体基板の分割方法は歩
留りよく半導体基板を分割できるもので工業上の利用価
値が高い。
As explained above, the semiconductor substrate dividing method of the present invention can divide semiconductor substrates with a high yield, and has high industrial utility value.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は半導体冬板の製造工程の手順を示す図、第2図
(a) 、 (b) 、 (c)は従来の半導体甚擺の
分割方法を示す図、第3図は本発明の半導体冬板の分割
方法を実施する装置の構成を示す図、第4図(4)、(
b)。 (c)は本発明の実施例における半導体冬板の分割方法
を示す図である。 21・・・・・・上部保持具、22・・・・・・下部保
持具、23・・・・・・粘着性収縮シート、3o・・・
・・・半導体ウェハ、32・・・・・・半導体チップ。 代理人の氏名 弁理士 中 尾 敏 男 にか1名第1
図 112図 2 ←175− !!I3図
Fig. 1 is a diagram showing the steps of the manufacturing process of a semiconductor winter board, Figs. 2 (a), (b), and (c) are diagrams showing a conventional method of dividing a semiconductor board, and Fig. 3 is a diagram showing the method of dividing a semiconductor board according to the present invention. Figures 4 (4) and 4 (4) are diagrams illustrating the configuration of an apparatus for carrying out the semiconductor winter board dividing method.
b). (c) is a diagram showing a method of dividing a semiconductor winter plate in an embodiment of the present invention. 21... Upper holder, 22... Lower holder, 23... Adhesive shrink sheet, 3o...
... Semiconductor wafer, 32 ... Semiconductor chip. Name of agent: Patent attorney Toshio Nakao (1st person)
Figure 112 Figure 2 ←175-! ! Figure I3

Claims (1)

【特許請求の範囲】[Claims] 半導体基板を張付けた粘着シートを圧力差によりわん曲
させて前記半導体基板を分割することを特徴とする半導
体基板の分割方法。
1. A method for dividing a semiconductor substrate, which comprises dividing the semiconductor substrate by bending an adhesive sheet to which the semiconductor substrate is attached due to a pressure difference.
JP57026211A 1982-02-19 1982-02-19 Dicing method for semiconductor substrate Pending JPS58142543A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57026211A JPS58142543A (en) 1982-02-19 1982-02-19 Dicing method for semiconductor substrate

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57026211A JPS58142543A (en) 1982-02-19 1982-02-19 Dicing method for semiconductor substrate

Publications (1)

Publication Number Publication Date
JPS58142543A true JPS58142543A (en) 1983-08-24

Family

ID=12187097

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57026211A Pending JPS58142543A (en) 1982-02-19 1982-02-19 Dicing method for semiconductor substrate

Country Status (1)

Country Link
JP (1) JPS58142543A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5238876A (en) * 1989-07-21 1993-08-24 Mitsubishi Denki Kabushiki Kaisha Method of dividing semiconductor wafer using ultraviolet sensitive tape
US6165813A (en) * 1995-04-03 2000-12-26 Xerox Corporation Replacing semiconductor chips in a full-width chip array

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5238876A (en) * 1989-07-21 1993-08-24 Mitsubishi Denki Kabushiki Kaisha Method of dividing semiconductor wafer using ultraviolet sensitive tape
US5332406A (en) * 1989-07-21 1994-07-26 Mitsubishi Denki Kabushiki Kaisha Apparatus for producing semiconductor device
US6165813A (en) * 1995-04-03 2000-12-26 Xerox Corporation Replacing semiconductor chips in a full-width chip array

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