JP7046212B2 - 表面mesfet - Google Patents
表面mesfet Download PDFInfo
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- JP7046212B2 JP7046212B2 JP2020548974A JP2020548974A JP7046212B2 JP 7046212 B2 JP7046212 B2 JP 7046212B2 JP 2020548974 A JP2020548974 A JP 2020548974A JP 2020548974 A JP2020548974 A JP 2020548974A JP 7046212 B2 JP7046212 B2 JP 7046212B2
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Description
図3a~図3iは、第1の実施形態による金属-半導体電界効果トランジスタ構成を製造する方法を示す。この実施形態では、第1の底部ソース電極はまた、第1の半導体チャネル層によって覆われ、第1のソース領域内の第1の金属接点を覆う第1の界面接点を含み、第1の底部ドレイン電極はまた、第1の半導体チャネル層によって覆われ、第1のドレイン領域内の第1の金属接点を覆う第1の界面接点を含み、結果、第1の界面接点は、第1のソース領域およびドレイン領域内の第1の半導体チャネル層への界面を形成する。半導体チャネル層は、ナノ結晶、ナノプレートレット、量子ドット、または薄膜を用いて、単層として、または半導体要素の多くの層を備えたスタックとして形成することができる。
図4a~図4dは、第2の実施形態による金属-半導体電界効果トランジスタ構成を製造する方法を示す。第2の実施形態では、第1の底部ゲート電極はまた、第1の半導体チャネル層によって覆われ、かつ第1のゲート領域内の第1の金属接点を覆う第2の界面接点も含み、結果、第2の界面接点は第1のゲート領域内の第1の半導体チャネル層への界面を形成する。
上部ゲート電極は、本開示に提示される他の実施形態のいずれかに追加され得る。上部ゲートは、半導体チャネル層内のショットキー接合の垂直深さを増加させることができ、当該増大は、非常に厚いアクティブMESFETチャネル層(例えば、ナノ結晶またはナノプレートレット)が使用されている場合に有用であり得る。したがって、上部ゲートは、MESFETトランジスタの感光応答を変化させ、安定させることができる。
配線層の第1のゲート領域の金属接点が、第1のソース領域および第1のドレイン領域の金属接点とは異なる金属を含む場合、半導体チャネル631は、上記領域内のすべての金属接点上に直接堆積することができる。図6aおよび図6bは、第1のソース領域61Sおよびドレイン領域61Dの金属接点が第1の金属材料から作製され、ゲート領域61Gの金属接点が第2の金属材料から作製される構成を示す。再び例として、チャネルがPbSから作製され、ソース電極61Sおよびドレイン電極61Dに適切に選択された材料、例えばインジウムまたは金が使用されていると仮定すると、底部ソース電極61Sとチャネル631との間の接合はオーミックになり、底部ドレイン電極61Dとチャネル631との間の接合は、オーミックになる。例えば、アルミニウムまたはチタンがゲート電極61Gに使用される場合、底部ゲート電極61Gとチャネル631との間の接合は、ショットキー接合になる。
MESFET閾値電圧に応じて、MESFETトランジスタは、エンハンスメント型(E型)MESFET(ノーマリー「オフ」)またはデプレッション型(D型)MESFET(ノーマリー「オン」)として特徴付けることができる。MESFET閾値電圧は、半導体チャネル層のドーピング、当該層の厚さ、および、ゲート電極と半導体チャネルとの間の仕事関数の差などの材料パラメータに依存する。
図8aは、本開示において説明されるMESFETトランジスタの、光センサとして使用されるときのピクセルジオメトリを示す。同じジオメトリを、前述の実施形態のいずれにも使用することができる。当該例では、参照符号80S、80Gおよび80Dは、それぞれ第1の実施形態の参照符号30S、30Gおよび30Dに対応する。
Claims (10)
- 金属-半導体電界効果トランジスタ構成であって、前記金属-半導体電界効果トランジスタ構成が、
水平基板表面上に少なくとも1つの配線層がある、前記水平基板表面上の第1のMESFETトランジスタであって、最上部の前記配線層は、第1の底部ソース電極を有する第1のソース領域、第1の底部ドレイン電極を有する第1のドレイン領域、および第1の底部ゲート電極を有する第1のゲート領域を備え、前記第1の底部ソース電極、前記第1の底部ドレイン電極および前記第1の底部ゲート電極の各々は、少なくとも導電性の第1の金属接点を備える、第1のMESFETトランジスタと、
前記第1の底部ソース電極、前記第1の底部ドレイン電極、および前記第1の底部ゲート電極を少なくとも部分的に覆う第1の半導体チャネル層と
を備え、
前記第1の底部ソース電極と前記第1の半導体チャネル層の間の界面がオーミック接合であり、前記第1の底部ドレイン電極と前記第1の半導体チャネル層の間の界面がオーミック接合であり、前記第1の底部ゲート電極と前記第1の半導体チャネル層との間の界面がショットキー接合であり、
前記水平基板がCMOS基板であることを特徴とする、
金属-半導体電界効果トランジスタ構成。 - 前記第1の底部ソース電極がまた、前記第1の半導体チャネル層によって覆われ、前記第1のソース領域内の前記第1の金属接点を覆う第1の界面接点を備え、前記第1の底部ドレイン電極がまた、前記第1の半導体チャネル層によって覆われ、かつ前記第1のドレイン領域内の前記第1の金属接点を覆う第1の界面接点を備え、結果、前記第1の界面接点が、前記第1のソース領域および前記第1のドレイン領域内の前記第1の半導体チャネル層への前記界面を形成することを特徴とする、
請求項1に記載の金属-半導体電界効果トランジスタ構成。 - 前記第1の底部ゲート電極がまた、前記第1の半導体チャネル層によって覆われ、前記第1のゲート領域内の前記第1の金属接点を覆う第2の界面接点を備え、結果、前記第2の界面接点が前記第1のゲート領域内の前記第1の半導体チャネル層への前記界面を形成することを特徴とする、
請求項1または2に記載の金属-半導体電界効果トランジスタ構成。 - 前記金属-半導体電界効果トランジスタ構成が、前記第1のゲート領域内の前記第1の半導体チャネル層を少なくとも部分的に覆う第1の上部ゲート電極をさらに備えることを特徴とする、
請求項1~3のいずれか一項に記載の金属-半導体電界効果トランジスタ構成。 - 前記金属-半導体電界効果トランジスタ構成が、前記第1のソース領域内の前記第1の半導体チャネル層を少なくとも部分的に覆う第1の上部ソース電極、および、前記第1のドレイン領域内の前記第1の半導体チャネル層を少なくとも部分的に覆う第1の上部ドレイン電極をさらに備えることを特徴とする、
請求項1~4のいずれか一項に記載の金属-半導体電界効果トランジスタ構成。 - 前記金属-半導体電界効果トランジスタ構成が、
前記第1のMESFETトランジスタと同じ基板表面上の第2のMESFETトランジスタであって、最上部の配線層は、第2の底部ソース電極を有する第2のソース領域、第2の底部ドレイン電極を有する第2のドレイン領域、および第2の底部ゲート電極を有する第2のゲート領域を備え、前記第2の底部ソース電極、前記第2の底部ドレイン電極および前記第2の底部ゲート電極の各々は、少なくとも導電性の第2の金属接点を備える、第2のMESFETトランジスタと、
前記第2の底部ソース電極、前記第2の底部ドレイン電極、および前記第2の底部ゲート電極を少なくとも部分的に覆う第2の半導体チャネル層と
を備え、
前記第2の底部ソース電極と前記第2の半導体チャネル層の間の界面がオーミック接合であり、前記第2の底部ドレイン電極と前記第2の半導体チャネル層の間の界面がオーミック接合であり、前記第2の底部ゲート電極と前記第2の半導体チャネル層との間の界面がショットキー接合であり、
前記第1のMESFETトランジスタおよび前記第2のMESFETトランジスタのうちの一方はエンハンスメント型MESFETであり、前記第1のMESFETトランジスタおよび前記第2のMESFETトランジスタのうちの他方はデプレッション型MESFETであることを特徴とする、
請求項1~5のいずれか一項に記載の金属-半導体電界効果トランジスタ構成。 - 前記第2の底部ソース電極がまた、前記第2の半導体チャネル層によって覆われ、かつ前記第2のソース領域内の前記第2の金属接点を覆う第3の界面接点を備え、前記第2の底部ドレイン電極がまた、前記第2の半導体チャネル層によって覆われ、かつ前記第2のドレイン領域内の前記第2の金属接点を覆う第3の界面接点を備え、結果、前記第3の界面接点が、前記第2のソース領域および前記第2のドレイン領域内の前記第2の半導体チャネル層への前記界面を形成することを特徴とする、
請求項6に記載の金属-半導体電界効果トランジスタ構成。 - 前記第2の底部ゲート電極がまた、前記第2の半導体チャネル層によって覆われ、かつ前記第2のゲート領域内の前記第2の金属接点を覆う第4の界面接点を備え、結果、前記第4の界面接点が前記第2のゲート領域内の前記第2の半導体チャネル層への前記界面を形成することを特徴とする、
請求項6または7に記載の金属-半導体電界効果トランジスタ構成。 - 前記金属-半導体電界効果トランジスタ構成が、前記第2のゲート領域内の前記第2の半導体チャネル層を少なくとも部分的に覆う第2の上部ゲート電極をさらに備えることを特徴とする、
請求項6~8のいずれか一項に記載の金属-半導体電界効果トランジスタ構成。 - 前記金属-半導体電界効果トランジスタ構成が、前記第2のソース領域内の前記第2の半導体チャネル層を少なくとも部分的に覆う第2の上部ソース電極、および、前記第2のドレイン領域内の前記第2の半導体チャネル層を少なくとも部分的に覆う第2の上部ドレイン電極をさらに備えることを特徴とする、
請求項6~9のいずれか一項に記載の金属-半導体電界効果トランジスタ構成。
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US20190288123A1 (en) | 2019-09-19 |
JP2021517738A (ja) | 2021-07-26 |
EP3766102B1 (en) | 2022-08-31 |
US11296239B2 (en) | 2022-04-05 |
KR20210010438A (ko) | 2021-01-27 |
WO2019175471A1 (en) | 2019-09-19 |
EP3766102A1 (en) | 2021-01-20 |
CA3093954C (en) | 2023-09-05 |
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