JP7043768B2 - Through Electrode Substrate and Its Manufacturing Method - Google Patents

Description

The present disclosure relates to a through electrode substrate and a method for manufacturing the same.

With the widespread use of mobile information terminals in recent years, technology for mounting semiconductor components at high density has been attracting attention. Technologies for mounting semiconductor components at high density include, for example, technology for three-dimensionally stacking semiconductor components and high-density relay boards for semiconductor components (also called wiring boards, multilayer wiring boards, through silicon via boards, interposers, etc.). There is a technology to electrically connect to the printed circuit board after mounting it on the top.

For example, Patent Document 1 discloses a technique for mounting a semiconductor chip on a multilayer wiring board (interposer).

Japanese Unexamined Patent Publication No. 2009-260255

However, in the technique disclosed in Patent Document 1, wiring is provided on the projection surface of the through electrode provided on the multilayer wiring board. When the multilayer wiring board is subjected to high temperature treatment, cracks may occur in the wiring due to thermal expansion of the through electrodes.

In view of such problems, one of the objects in the embodiment of the present disclosure is to provide a through electrode substrate having high reliability for high temperature treatment. Further, one of the objects in the embodiment of the present disclosure is to provide a method for manufacturing a through electrode substrate having high reliability for high temperature treatment.

The through electrode substrate, which is one of the embodiments of the present disclosure, is provided in a substrate having a first surface, a second surface, and a through hole penetrating the first surface and the second surface, and in the through hole. The through electrode and the first wiring provided on the first surface having a first opening whose center line substantially coincides with the center line of the through hole and whose hole diameter is larger than the hole diameter of the through hole, and the center line are the first. It has a second opening that substantially coincides with the center line of the first opening and has a hole diameter larger than the hole diameter of the first opening, and is provided on the first surface and the first wiring, and on the insulating film. It has a second wiring that is provided and is electrically connected to the first wiring through an opening different from the second opening.

The thickness of the first wiring included in the through electrode substrate may be equal to or thinner than the thickness of the second wiring.

The thickness of the first wiring included in the through electrode substrate may be 1 μm or less.

The position of the opening end of the first opening of the through electrode substrate may be inside the position of the opening end of the second opening and outside the through hole or the through electrode.

It may further have a third wiring that is electrically connected to the first wiring through the first opening and the second opening of the through electrode substrate.

In the method for manufacturing a through electrode substrate, which is one of the embodiments of the present disclosure, a through hole is provided to penetrate the first surface of the substrate and the second surface of the substrate, and the through hole is filled with a conductor to penetrate. An electrode is provided, the first wiring is provided in contact with the first surface, the center line substantially coincides with the center line of the through hole, and the hole diameter is larger than the hole diameter of the through hole. An insulating film is provided so as to be in contact with the wiring, and the insulating film is provided with a second opening having a center line substantially matching the center line of the first opening and larger than the hole diameter of the first opening. An opening provided on the insulating film, which is different from the second opening, and a second wiring are provided so as to be in contact with the first wiring.

The thickness of the first wiring in the method for manufacturing the through electrode substrate may be equal to or thinner than the thickness of the second wiring.

The thickness of the first wiring in the method for manufacturing the through electrode substrate may be 1 μm or less.

The position of the opening end of the first opening in the method for manufacturing the through electrode substrate may be inside the position of the opening end of the second opening and outside the through hole or the through electrode.

As for the method for manufacturing the through electrode substrate, the process at a high temperature may be performed after the second wiring is provided.

In the method for manufacturing the through silicon via substrate, after the treatment at the above high temperature, a third wiring electrically connected to the first wiring may be provided via the first opening and the second opening.

The other through-electrode substrate, which is one of the embodiments of the present disclosure, includes a substrate having a first surface, a second surface, and a through hole penetrating the first surface and the second surface, and a through hole. A first insulating film provided with a through electrode provided, a first insulating film provided on the first surface, a first opening whose center line substantially coincides with the center line of the through hole and whose hole diameter is larger than the hole diameter of the through hole, and the first. A first wiring provided on one surface and the first insulating film, having a second opening whose center line substantially coincides with the center line of the first opening and whose hole diameter is smaller than the hole diameter of the first opening. A second insulating film provided on the first insulating film and the first wiring and having a third opening and a fourth opening, and a first wiring provided on the second insulating film and via the third opening. It has a second wiring that is electrically connected to the.

The thickness of the first wiring of the other through silicon via substrate may be equal to or thinner than the thickness of the second wiring.

The thickness of the first wiring of the other through silicon via substrate may be 1 μm or less.

The position of the opening end of the first opening of the other through electrode substrate may be inside the position of the opening end of the second opening and outside the through hole or the through electrode.

It may further have a third wiring that is electrically connected to the first wiring through the first opening and the fourth opening of the other through silicon via substrate.

It is a top view explaining the semiconductor device which concerns on one Embodiment of this disclosure. FIG. 3 is a cross-sectional view taken along the line A1-A2 of the semiconductor device shown in FIG. It is a top view explaining the semiconductor device which concerns on one Embodiment of this disclosure. It is sectional drawing along the C1-C2 line of the semiconductor device which concerns on one Embodiment of this disclosure. It is a flowchart explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is a top view explaining the semiconductor device which concerns on one Embodiment of this disclosure. It is sectional drawing along the C1-C2 line of the semiconductor device which concerns on one Embodiment of this disclosure. It is a flowchart explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure. It is sectional drawing explaining the manufacturing method of the through electrode substrate which concerns on one Embodiment of this disclosure.

Hereinafter, each embodiment of the present disclosure will be described with reference to the drawings and the like. However, the present disclosure can be carried out in various aspects without departing from the gist thereof, and is not construed as being limited to the description contents of the embodiments exemplified below.

The drawings may schematically represent the width, thickness, shape, etc. of each part as compared to the actual embodiment in order to clarify the explanation, but this is merely an example and the interpretation of the present disclosure is limited. It's not something to do. In this specification and each figure, elements having the same functions as those described with respect to the above-mentioned figures may be designated by the same reference numerals to omit duplicate explanations.

In the present specification and the scope of patent claims, when expressing an aspect of arranging another structure on one structure, when the term "above" is simply used, the structure shall be used unless otherwise specified. It includes both the case where another structure is placed directly above the structure so as to be in contact with each other and the case where another structure is placed above one structure via another structure. Further, in the present specification and claims, U and its arrow represent up and up in the cross section, and D and its arrow represent down and down in the cross section.

In the present specification and claims, the expression that one structure overlaps with another means that at least a part of these structures overlap in a plan view. In other words, it means that one of these structures is located above or below the other, and at least some of these structures overlap each other when viewed from above or below. do.

(First Embodiment)
(1-1. Structure of semiconductor device)
FIG. 1 shows a top view showing an example of a semiconductor device 100, which is one of the embodiments of the present disclosure. The semiconductor device 100 includes a printed circuit board 102, a through silicon via substrate 104, an integrated circuit 106a, an integrated circuit 106b, a wiring layer 108, and a wiring layer 110.

The integrated circuit 106a and the integrated circuit 106b are electrically connected to each other via the wiring layer 110 or the wiring layer 108. Further, the integrated circuit 106a and the integrated circuit 106b are electrically connected to the through electrode substrate 104 via the wiring layer 110 and the wiring layer 108. The through electrode substrate 104 is electrically connected to the printed circuit board 102 via a through electrode described later.

FIG. 1 shows an example in which two integrated circuits having four terminals electrically connected to the four wiring layers 110 are mounted on the through silicon via substrate 104, but the present invention is not limited to the examples shown here. The integrated circuit may have, for example, five or more terminals, or may have less than four terminals. Further, the number of integrated circuits mounted on the through electrode substrate 104 may be three or more, or may be one. Further, a plurality of integrated circuits having different numbers of terminals may be mounted on the integrated circuit mounted on the through silicon via substrate 104. It can be appropriately selected depending on the application of the semiconductor device. Note that FIG. 1 shows an example in which a through silicon via substrate is mounted on a printed circuit board, but the present invention is not limited to this example. The through electrode substrate may be mounted on, for example, a glass substrate or a flexible material such as FPC. It can be appropriately selected depending on the application of the semiconductor device.

FIG. 2 shows a cross-sectional view taken along the line of A1-A2 shown in FIG. The through electrode substrate 104 is provided in the multilayer wiring layer 116, the first surface 140a, the second surface 140b, the glass substrate 120 having the through holes 126, and the through holes penetrating the first surface 140a and the second surface 140b. It has a through electrode 118. The multilayer wiring layer 116 is provided on the first surface 140a. Although the details will be described later, the wiring layer included in the multilayer wiring layer 116 is electrically connected to the through electrode 118. The through silicon via 118 is electrically connected to the bump 114. The integrated circuit 106b is electrically connected to the multilayer wiring layer 116 via the bump 114. The through electrode substrate 104 is electrically connected to the printed circuit board 102 via the bump 104. The first surface 140a and the second surface 140b have an upper and lower relationship or a front and back relationship with respect to the through electrode substrate 104.

FIG. 3 shows an enlarged plan view of the region 112 shown in FIG. An integrated circuit 106b, a wiring layer 108, a wiring layer 110, a wiring layer 122, an opening 123 provided in the wiring layer 122, an opening 124a, and an opening 124b are provided on the first surface 140a side of the through electrode substrate 104. Has been done. Further, in FIG. 3, a through hole 126 is shown for facilitating understanding.

D1 is the hole diameter of the through hole 126. D2 is the hole diameter of the opening 123. D3 is the hole diameter of the opening 124a. D4 is the pattern diameter of the circular portion of the wiring layer 108. D5 is the hole diameter of the opening 124b. D6 is the pattern diameter of the circular portion of the wiring layer 110. In the present specification, the hole diameter of the through hole 126 is defined as the larger diameter of the hole diameters of the first surface 140a and the second surface 140b. The hole diameter of the through hole 126 does not necessarily have to be the larger diameter of the hole diameters of the first surface 140a and the second surface 140b. For example, the hole diameter of the through hole 126 may be defined as the hole diameter of the 140a surface for the opening of the wiring layer or the insulating layer laminated on the 140a surface, and the hole diameter of the through hole 126 may be defined as the hole diameter of the wiring layer laminated on the 140b surface. The hole diameter of the 140b surface may be defined for the opening of the layer or the insulating layer. Further, the hole diameter of the opening 123, the hole diameter of the opening 124a, and the hole diameter of the opening 124b are defined as the diameter of the largest portion of the opening. Here, the diameter of the smallest portion of the opening 123 is larger than the diameter of the through hole 126. Further, the pattern diameter of the circular portion of the wiring layer 108 and the pattern diameter of the circular portion of the wiring layer 110 are defined as the diameter of the circle when each pattern is regarded as a circle. When the hole of the through hole 126 cannot be regarded as a circle, the diameter of the circle whose circumference is the circumference of the hole of the through hole 126 is defined as the width of the through hole 126, that is, the hole diameter. The definition of the hole diameter when the pattern of the opening 123, the opening 124a, the opening 124b, the wiring layer 108, and the circular portion of the wiring layer 110 cannot be regarded as a circle is the same as the definition of the hole diameter of the through hole 126. do.

FIG. 4 shows a cross-sectional view taken along the line of C1-C2 shown in FIG. The through electrode substrate 104 is provided in the multilayer wiring layer 116, the first surface 140a, the second surface 140b, the glass substrate 120 having the through holes 126, and the through holes penetrating the first surface 140a and the second surface 140b. It has a through electrode 118. The multilayer wiring layer 116 is provided on the first surface 140a. The multilayer wiring layer 116 has a wiring layer 122, an inorganic insulating film 130, a wiring layer 108, and a wiring layer 110. The wiring layer 122 is provided with an opening 123. The wiring layer 108 is electrically connected to the wiring layer 122 and the through silicon via 118 via the opening 124a and the opening 123. The wiring layer 110 is electrically connected to the wiring layer 122 via the opening 124b, and is electrically connected to the wiring layer 108 and the through silicon via 118 via the opening 124a and the opening 123. The through silicon via 118 is electrically connected to the bump 114. The integrated circuit 106b is electrically connected to the multilayer wiring layer 116 via the bump 114. The through electrode substrate 104 is electrically connected to the printed circuit board 102 via the bump 104.

The hole diameter D2 of the opening 123 provided in the wiring layer 122 is larger than the hole diameter D1 of the through hole 126. The region where the wiring layer 122 and the first surface 140a overlap is inside the region where the inorganic insulating film 130 and the wiring layer 122 overlap, and is outside the through hole 126 or the through electrode 118. That is, the position of the opening end of the opening 123 is inside the position of the opening end of the opening 124a and outside the through hole 126 or the through electrode 118. Further, the inorganic insulating film 130 and the through hole 126 or the through electrode 118 do not overlap, and the wiring layer 122 and the through hole 126 or the through electrode 118 do not overlap. In addition, in this specification, the opening end is defined as the end portion of a vacant hole in the top view of the opening. For example, as shown in FIG. 3, the portion shown by the dotted line of the opening 123 is the opening end, and the same applies to the opening 124a, the opening 124b, and the through hole 126.

In FIG. 4, in the side view, the center line extending up and down from the center of the diameter of the hole diameter D2 of the opening 123 and the center line extending up and down from the center of the diameter of the hole diameter D1 of the through hole 126 are both center lines. An example that matches 200a is shown, but the present invention is not limited to this example. For example, in the side view, the opening 123 may be shifted to the right, and the center line extending vertically from the center of the hole diameter D2 of the opening 123 may be shifted to the right. The region where the wiring layer 122 and the first surface 140a overlap and the through hole 126 or the through electrode 118 do not overlap each other, that is, the position of the opening end of the opening 123 is from the position of the opening end of the opening 124a. Also inside, and in the range outside the through hole 126 or the through electrode 118, the center line extending up and down from the center of the diameter of the hole diameter D2 of the opening 123 and up and down from the center of the diameter of the hole diameter D1 of the through hole 126. It suffices if it substantially coincides with the extending center line. The center line extending up and down from the center of the diameter of the hole diameter D3 of the opening 124a also coincides with the center line 200a, but is not limited to this example. The region where the inorganic insulating film 130 and the wiring layer 122 overlap is outside the region where the wiring layer 122 and the first surface 140a overlap, that is, the position of the opening end of the opening 124a is the opening end of the opening 123. A center line extending up and down from the center of the diameter of the hole diameter D3 of the opening 124a and the through hole 126 in the range outside the position of the opening 124a and outside the through hole 126 or the through electrode 118, as in the opening 123. It suffices if it substantially coincides with the center line extending vertically from the center of the diameter of the hole diameter D1. In the side view, the center line extending vertically from the center of the hole diameter D5 of the opening 124b is the center line 200b.

The wiring layer 122 is, for example, the first wiring. The wiring layer 110 is, for example, a second wiring. The wiring layer 108 is, for example, a third wiring. The opening 123 is, for example, a first opening. The opening 124a is, for example, a second opening. The opening 124b is, for example, an opening different from the second opening.

(1-2. Manufacturing method of through silicon via substrate)
FIG. 5 shows a flowchart illustrating a method for manufacturing the through silicon via substrate 104.

When the production of the through electrode substrate 104 is started, first, the through hole 126 penetrating the first surface and the second surface of the glass substrate 120 is opened, and the through hole 126 is formed (step 41 (S41)). ).

Next, a through electrode 126 is formed by filling the through hole 126 with a conductor (step 42 (S42)).

Next, the wiring layer 122 is provided so as to be in contact with the first surface 140a, and the first wiring is formed (step 43 (S43)). The wiring layer 122 is provided with an opening 123. Here, the opening 123 has a center line that substantially coincides with the center line of the through hole 126, and has a hole diameter larger than the hole diameter of the through hole 126. The wiring layer 122 may be a wiring having an island-shaped pattern called a land, a wiring having a linear pattern, or a wiring in which a circular pattern and a linear pattern are connected.

Next, the inorganic insulating film 130 is provided so as to be in contact with the first surface 140a and the wiring layer 122, and the opening 124a and the opening 124b are formed (step 44 (S44)). Here, the opening 124a has a center line that substantially coincides with the center line of the opening 123, and has a hole diameter larger than the hole diameter of the opening 123. Here, the opening 124a is a second opening formed in the inorganic insulating film 130. Further, the opening 124b is an opening different from the second opening formed in the inorganic insulating film 130.

Next, the wiring layer 110 is provided so as to be in contact with the inorganic insulating film 130 and the wiring layer 122 exposed by the opening 124b, and the second wiring is formed (step 45 (S45)).

Next, the through electrode substrate 104 is subjected to high temperature treatment (step 46 (S46)). The high temperature means, for example, a temperature of 400 to 600 degrees. For example, in the high temperature treatment after forming the second wiring of the through electrode substrate 104, a plurality of thin film transistors, capacitive elements, resistance elements, and the like may be formed. An integrated circuit can be provided by forming a plurality of thin film transistors, capacitive elements, resistance elements, and the like.

Finally, the wiring layer 108 is provided so as to be in contact with the wiring layer 122 exposed by the opening 124a of the inorganic insulating film 130, the first surface 124a, and the through silicon via 118, and the third wiring is formed (step 47 (step 47). S47)).

The through electrode substrate 104 can be manufactured by the above manufacturing method.

The manufacturing method of the through electrode substrate 104 shown in the flowchart of FIG. 5 will be described in detail with reference to FIGS. 6 to 12. 6 to 10 and 12 are cross-sectional views taken along line C1-C2 of the through electrode substrate 104 in the enlarged drawing of the region 112 of the semiconductor device 100 shown in FIG. 3, as in FIG. show. FIG. 11 is a cross-sectional view taken along line B1-B2 shown in FIG. 1 when, for example, an integrated circuit 106a is formed by using a thin film transistor in a step of applying a high temperature treatment to the through electrode substrate 104 in step 46. Is shown.

First, as shown in FIG. 6, a through hole 126 penetrating the first surface 140a and the second surface 140b is formed on the glass substrate 120.

In one embodiment of the present disclosure, the through electrode substrate 104 shows an example in which the glass substrate 120 is used, but the present invention is not limited to this example. As the through electrode substrate 104, for example, a substrate having high rigidity such as a quartz substrate, a Si wafer whose surface is insulated with an oxide film or the like may be used. The thickness of the glass substrate 120 is not particularly limited, but is preferably 300 μm or more and 700 μm or less, for example. Further, by using a glass substrate, for example, processing at a high temperature of 400 degrees or more becomes possible.

The through hole 126 is formed, for example, by irradiating the glass substrate 120 with a high-power laser beam and melting the glass substrate 120. Specifically, when a glass substrate 140 is used for the through electrode substrate 104 as in one embodiment of the present disclosure, the through hole 1226 is formed by using a CO2 laser, an excimer laser, and an Nd: YAG laser. To.

Further, the through hole 126 may be formed by dry etching. Examples of the dry etching include a reactive ion etching (RIE) method and a DRIE (Deep Reactive Ion Etching) method using a Bosch process.

Next, as shown in FIG. 7, a through electrode 118 is formed in the through hole 126. The through electrode 118 is formed, for example, by a plating method. For example, when the through electrode 118 is formed using copper (Cu), a thin film of copper (Cu) is first formed on the first surface 140a, the second surface 140b, and the through hole 126 of the glass substrate 120 by a sputtering method. It is formed. Next, using the copper (Cu) thin film as a seed layer, copper (Cu) is plated in the through holes 126 by an electrolytic plating method. At this time, the through electrode 118 may be filled and plated. Finally, the through electrode 118 is formed by removing the copper (Cu) film formed on the first surface 140a and the second surface 140b of the glass substrate 120 by a chemical mechanical polishing (CMP) method. Will be done.

Further, the through electrode 118 may be formed by first forming a conductive film on the through hole 126, the first surface 140a and the second surface 140b, and then performing patterning by a photolithography method. As a method for forming the conductive film, for example, a sputtering method can be used. In addition to copper (Cu), the material used for the through electrode 118 may be a metal such as aluminum (Al), nickel (Ni), titanium (Ti), tungsten (W), or an alloy obtained by combining these metals. can.

Subsequently, as shown in FIGS. 8 to 12, the multilayer wiring layer 116 is formed.

First, as shown in FIG. 8, a conductive film is formed on the first surface 140a of the glass substrate 120 by a sputtering method, and then patterning is performed by a photolithography method to form a wiring layer 122 and an opening 123. Form. The material used for the wiring layer 122 shall be the same material as that used for forming the through electrode 118, such as copper (Cu), aluminum (Al), nickel (Ni), titanium (Ti), and tungsten (W). Can be done. The wiring layer 122 is, for example, the first wiring. The opening 123 is, for example, a first opening. The shape of the wiring layer 122 is such that it surrounds the first opening in a ring shape. The wiring layer 122 does not overlap with the through electrodes 118 and the through holes 126.

The wiring layer 122 is preferably a thin film. Specifically, the thickness of the wiring layer 122 is preferably 1 μm or less. For example, when the through electrode substrate 104 is subjected to high temperature treatment, the through electrode 118 thermally expands. Through electrodes 118 and wiring layer 122 also become hot. When the wiring layer 122 is not a thin film, the wiring layer 122 undergoes thermal expansion, which causes cracks in the inorganic insulating film 130 described later, which lowers the reliability of the through electrode substrate 104. However, since the wiring layer 122 is a thin film, the volume of the wiring layer 122 is sufficiently smaller than that of the through silicon via 118, so that the volume expansion of the wiring layer 122 is suppressed and the inorganic insulating film 130 described later is cracked. It can be suppressed. Further, in one embodiment of the present disclosure, since the wiring layer 122 and the through electrode 118 do not overlap and are physically separated from each other, the wiring layer 122 may be cracked due to the thermal expansion of the through electrode 118. do not have.

Next, as shown in FIG. 9, the inorganic insulating film 130 is formed on the first surface 140a and the wiring layer 122. As a method for forming the inorganic insulating film 130, for example, a CVD method or a sputtering method can be used. As the material of the inorganic insulating film 130, for example, an inorganic compound such as silicon oxide, silicon nitride, silicon nitride, or silicon nitride can be used. Further, in FIG. 9, an example in which the inorganic insulating film 130 is formed from one layer is shown, but the present invention is not limited to this example. For example, the inorganic insulating film 130 may have a two-layer structure by laminating two of the above-mentioned materials. Further, the surface of the inorganic insulating film 130 may be polished and flattened by a chemical mechanical polishing (CMP) method. By flattening the inorganic insulating film 130, the film formed thereafter is formed on a surface having no unevenness and having high adhesion.

Next, the opening 124a and the opening 124b that open the inorganic insulating film 130 are formed. The opening 124a and the opening 124b are formed by patterning by a photolithography method. The openings 124a and 124b expose the wiring layer 122, the first surface 140a, and the through silicon via 118. The region where the inorganic insulating film 130 and the wiring layer 122 overlap is outside the region where the wiring layer 122 and the first surface 140a overlap, the region where the inorganic insulating film 130 and the wiring layer 122 overlap, and the wiring layer 122. The region where the first surface 140a overlaps does not overlap with each other. Further, the region where the inorganic insulating film 130 and the wiring layer 122 overlap and the region where the wiring layer 122 and the first surface 140a overlap do not overlap each other with the through electrode 118 and the through hole 126. That is, the position of the opening end of the opening 124a is outside the position of the opening end of the opening 123 and outside the through hole 126 or the through electrode 118. Further, the inorganic insulating film 130 is provided on the outside of the through electrode 118 and the through hole 126, and the hole diameter of the opening 124a is larger than the hole diameter of the through hole 126. The opening 124a is, for example, a second opening. The opening 124b is, for example, an opening different from the second opening in the inorganic insulating film 130.

Next, as shown in FIG. 10, a conductive film is formed by a sputtering method, and then patterning is performed by a photolithography method to form a wiring layer 110. As the material used for the wiring layer 110, the same material as the material used at the time of forming the through electrode 118 can be used. The wiring layer 110 may be formed by a plating method. The thickness of the wiring layer 110 is equal to or thicker than the thickness of the wiring layer 122 (the thickness of the wiring layer 122 is equal to or thinner than the thickness of the wiring layer 110). The wiring layer 110 is in contact with the exposed portion of the inorganic insulating film 130, the opening 124a, and the wiring layer 122, and is electrically connected to the wiring layer 122. The wiring layer 110 is, for example, a second wiring, and electrically connects the integrated circuit 106a and the integrated circuit 106b. When the thickness of the wiring layer 110 is equivalent to the thickness of the wiring layer 122, the covering property of the insulating film formed on the wiring layer 110 covering the layer below the insulating film is improved, and the reliability of the through electrode substrate 104 is improved. Can be improved. Further, when the thickness of the wiring layer 110 is equivalent to the thickness of the wiring layer 122, the flatness at the time of forming the multilayer wiring can be improved in the multi-layer wiring of the through electrode substrate 104. Further, when the thickness of the wiring layer 110 is the same as the thickness of the wiring layer 122, even if the wiring layer 110 is thermally expanded by the high temperature treatment, the insulating film formed on the wiring layer 110 may be cracked, for example. However, the stress associated with thermal expansion can be reduced. When the thickness of the wiring layer 110 is thicker than the thickness of the wiring layer 122, by using the wiring layer 110 as wiring between the integrated circuits, for example, the signal delay can be reduced or the amount of current flowing through the wiring can be reduced. Can be increased.

The through electrode substrate 104 is subjected to high temperature treatment after forming the wiring layer 110. FIG. 11 shows an example when the integrated circuit 106a is formed by using a thin film transistor.

As shown in FIG. 11, the semiconductor film 150 is formed on the inorganic insulating film 130. The semiconductor film 150 is formed, for example, by forming a semiconductor layer by a CVD method and patterning it by a photolithography method. As the material of the semiconductor film 150 and the semiconductor film, for example, silicon or an oxide semiconductor can be used. Examples of the oxide semiconductor include a mixed oxide of indium, gallium, and zinc (IGZO). Further, the crystallinity of the semiconductor film 150 and the semiconductor film may be any of amorphous, microcrystal, polycrystal, single crystal, or a mixture thereof, and can be appropriately selected according to the purpose and application. ..

Next, the insulating layer 152 is formed on the inorganic insulating film 130 and the semiconductor film 150. As the method and material for forming the insulating layer 152, the same forming method and material as the inorganic insulating film 130 can be used. The inorganic insulating film 130 is a gate insulating film.

Next, the wiring layer 153 is formed on the insulating layer 152. As the method and material for forming the wiring layer 153, the same forming method and material as the wiring layer 110 can be used. The wiring layer 153 is, for example, a gate electrode. The gate electrode is also called a gate, a gate terminal, or the like.

Next, the insulating layer 154 is formed on the insulating layer 152 and the wiring layer 153. As the method and material for forming the insulating layer 154, the method and material for forming the inorganic insulating film 130 can be used as in the case of the insulating layer 152.

Next, an opening for opening the insulating layer 152 and the insulating layer 154 is formed. The opening is formed by patterning by a photolithography method. The opening exposes the semiconductor film 150 or the wiring layer 110. In the present disclosure, an example in which the formation of the openings for opening the insulating layer 152 and the insulating layer 154 is performed collectively is described, but the present invention is not limited to this example. For example, after forming the opening for opening the insulating layer 152, the opening for opening the insulating layer 154 may be formed.

Next, the wiring layer 155 is formed on the insulating layer 154 at the opening that opens the insulating layer 152 and the insulating layer 154, the portion where the semiconductor film 150 is exposed, and the portion where the through electrode 110 is exposed. As the method and material for forming the wiring layer 155, the same forming method and material as the wiring layer 110 can be used. The wiring layer 155 is, for example, wiring for electrically connecting the source electrode or drain electrode of the thin film transistor 124, the thin film transistor 124, the capacitive element, the resistance element, and the like. The source electrode is also called a source or a source terminal. The drain electrode is also called a drain or a drain terminal.

Next, the insulating layer 156 is formed on the insulating layer 154 and the wiring layer 155. As the method and material for forming the insulating layer 156, the same forming method and material as the insulating layer 152 can be used. Further, as the material of the insulating layer 156, an organic resin such as polyimide or acrylic may be used. When an organic resin is used as the material of the insulating layer 156, for example, a spin coating method or a dipping method can be applied to the method of forming the insulating layer 156 by using a liquid material. As the insulating layer 156, a resin film made of a film material can also be used.

From the above, the thin film transistor 124 can be formed. In the thin film transistor 124, the conduction between the source and the drain is controlled by the gate electrode. An integrated circuit 106a can be formed by electrically connecting a plurality of thin film transistors 124, a capacitive element, a resistance element, and the like.

The method of forming the integrated circuit 106a using the thin film transistor shown in FIG. 11 is an example of the method of forming the integrated circuit 106a according to the embodiment of the present disclosure. For example, as the method for forming the integrated circuit 106a using the thin film transistor of the present disclosure, the thin film transistor forming method usually used in the technical field of the display device may be adopted. Known structures, manufacturing methods and materials can be adopted as the structures of thin film transistors, capacitive elements, resistance elements and the like, and the manufacturing methods and materials of the films and layers forming the respective structures.

Next, as shown in FIG. 12, the wiring layer 108 is formed. As the method and material for forming the wiring layer 108, the same forming method and material as the wiring layer 110 can be used. The wiring layer 108 may be formed by a vapor deposition method, a plating method, a solder, or a solder and a metal wire. The wiring layer 108 is in contact with the opening 124a, the portion where the wiring layer 122 is exposed, the portion where the first surface 140a is exposed, the opening 123, and the through electrode 118, and is in contact with the opening 124a and the opening 123. It is electrically connected to 122 and through silicon via 118. The thickness of the wiring layer 108 may be thicker than the thickness of the wiring layer 122 and the wiring layer 110. The wiring layer 108 is, for example, a third wiring. Similar to the wiring layer 110, the wiring layer 108 electrically connects the integrated circuit 106a and the integrated circuit 106b. Further, since the thickness of the wiring layer 108 is thicker than the thickness of the wiring layer 122, the resistance value of the wiring is small. Therefore, by using the wiring layer 108 as the wiring between the integrated circuits, for example, it is possible to reduce the signal delay or increase the amount of current flowing through the wiring.

By the above manufacturing method, the multilayer wiring layer 116 can be formed on the first surface 140a of the glass substrate 120, and the through electrode substrate 104 can be manufactured.

(1-3. Manufacturing method of semiconductor device)
In the semiconductor device 100, the integrated circuit 106b and the wiring layer 110 included in the through electrode substrate 104 are electrically connected via the bump 114, and further, the through electrode substrate 104 and the printed circuit board 102 on which the integrated circuit 106b is mounted are connected. Is electrically connected via the bump 114. The bump 114 is, for example, a solder ball. The integrated circuit 106a may be electrically connected to the wiring layer 110 of the through electrode substrate 104 via the bump 114, as in the integrated circuit 106b, without being formed by using the thin film transistor.

As described above, in the through electrode substrate according to the embodiment of the present disclosure, the wiring layer provided on the first surface and having a shape surrounding the circumference of the first opening in a ring shape and the through electrode are The wiring layers are not overlapped and are provided outside the through electrodes or through holes. Therefore, in the formation of the through electrode wiring, even if the through electrode substrate is subjected to high temperature treatment and the through electrode thermally expands, according to the present disclosure, the wiring layer and the through electrode are separated from each other without contacting each other. The occurrence of cracks in the wiring layer can be suppressed. Further, since the thickness of the wiring layer is thinner than the thickness of other wiring layers used in the multilayer wiring layer, the volume of the wiring layer is smaller than the volume of the through electrode. Therefore, in the formation of the through electrode wiring, even if the through electrode substrate is subjected to high temperature treatment and the through electrode thermally expands, according to the present disclosure, the wiring layer can suppress the volume expansion, so that the wiring can be used. It is possible to suppress the occurrence of cracks. Further, even if the through electrode substrate is subjected to high temperature treatment and the through electrode thermally expands, the wiring layer can suppress the volume expansion according to the present disclosure. Therefore, the inorganic insulation provided on the wiring layer is provided. The generation of cracks in the film can be suppressed. Therefore, according to the present disclosure, it is possible to provide a through electrode substrate having high reliability for high temperature treatment. Further, according to the present disclosure, it is possible to manufacture a through electrode substrate having high reliability for high temperature treatment.

(Second Embodiment)
In the embodiment of the present disclosure, a structure different from the semiconductor device 100 described in the first embodiment will be described with reference to FIGS. 13 to 21. The description of the same configuration as that of the first embodiment may be omitted.

(2-1. Structure of semiconductor device)
FIG. 13 shows an enlarged plan view of the region 112 shown in FIG. FIG. 13 is the same as that of FIG. 3, except that the opening 132 is increased. Here, the description of the same configuration as in FIG. 3 will be omitted.

Since D1 to D6 are the same as the description of FIG. 3, the description here will be omitted. D7 is the hole diameter of the opening 132. In the present specification, the definition of the hole diameter of the opening 132 is the same as the definition of the opening 124a, and the description thereof is omitted here. Further, the definition of the hole diameter when the opening 132 cannot be regarded as a circle is the same as the definition of the hole diameter of the through hole 126, and the description thereof is omitted here. Further, the definition of the opening end of the opening 132 is the same as the definition of the opening end such as the opening 123, the opening 124a, the opening 124b, and the through hole 126, and the description thereof is omitted here.

FIG. 14 shows a cross-sectional view taken along the line of C1-C2 shown in FIG. FIG. 14 is the same as that of FIG. 4, except that the inorganic insulating film 134 and the opening 132 are increased. Here, the description of the same configuration as in FIG. 4 will be omitted. The multilayer wiring layer 116 has an inorganic insulating film 134 in addition to the configuration described in FIG. The inorganic insulating film 134 is provided with an opening 132. The wiring layer 122 is provided with an opening 123. The wiring layer 122 is provided so as to be in contact with the opening 132. The wiring layer 108 is electrically connected to the wiring layer 122 and the through silicon via 118 via the opening 124a and the opening 123. The wiring layer 110 is electrically connected to the wiring layer 122 via the opening 124b, and is electrically connected to the wiring layer 108 and the through silicon via 118 via the opening 124a and the opening 123. The through silicon via 118 is electrically connected to the bump 114. The integrated circuit 106b is electrically connected to the multilayer wiring layer 116 via the bump 114. The through electrode substrate 104 is electrically connected to the printed circuit board 102 via the bump 104. In FIG. 14, the hole diameter D7 of the opening 132 is smaller than the hole diameter D3 of the opening 124a, but the hole diameter D7 of the opening 132 may be substantially the same as the hole diameter D3 of the opening 124a. The hole diameter D7 of the opening 132 may be larger than the hole diameter D3 of the opening 124a.

(2-2. Manufacturing method of through silicon via substrate, manufacturing method of semiconductor device)
FIG. 15 shows a flowchart illustrating a method for manufacturing the through silicon via substrate 104.

When the production of the through electrode substrate 104 is started, steps 51 (S51) and 52 (S52) are performed. Since step 51 (S51) and step 52 (S52) are the same as step 41 (S41) and step 42 (S42) described with reference to FIG. 5, the description thereof is omitted here.

Next, the inorganic insulating film 134 is provided so as to be in contact with the first surface 140a, and the opening 132 is formed (step 53 (S53)). Here, the opening 132 has a center line that substantially coincides with the center line of the through hole 126, and has a hole diameter larger than the hole diameter of the through hole 126. The inorganic insulating film 134 is the first insulating film. The opening 132 is the first opening.

Next, the wiring layer 122 is provided so as to be in contact with the first surface 140a exposed by the inorganic insulating film 134 and the opening 132, and the first wiring is formed (step 54 (S54)). The wiring layer 122 is provided with an opening 123. Here, the opening 123 has a center line that substantially coincides with the center line of the through hole 126, and has a hole diameter larger than the hole diameter of the through hole 126. The wiring layer 122 and the through electrode 118 or the through hole 126 do not overlap. The wiring layer 122 may be a wiring having an island-shaped pattern called a land, a wiring having a linear pattern, or a wiring in which a circular pattern and a linear pattern are connected. The opening 123 is a second opening.

Next, the inorganic insulating film 130 is provided so as to be in contact with the first surface 140a and the wiring layer 122, and the opening 124a and the opening 124b are formed (step 55 (S55)). The opening 124a has a center line that substantially coincides with the center line of the opening 123, and has a hole diameter larger than the hole diameter of the opening 123. Here, the opening 124a is a fourth opening formed in the inorganic insulating film 130. Further, the opening 124b is a third opening formed in the inorganic insulating film 130.

Next, the wiring layer 110 is provided so as to be in contact with the inorganic insulating film 130 and the wiring layer 122 exposed by the opening 124b, and the second wiring is formed (step 56 (S56)).

Next, the through electrode substrate 104 is subjected to high temperature treatment (step 57 (S57)). Since step 57 (S57) is the same as step 46 (S46) described with reference to FIG. 5, the description thereof is omitted here.

Finally, step 58 (S58) is performed. Since step 58 (S58) is the same as step 47 (S47) described with reference to FIG. 5, the description thereof is omitted here.

The through electrode substrate 104 can be manufactured by the above manufacturing method.

The manufacturing method of the through electrode substrate 104 shown in the flowchart of FIG. 15 will be described in detail with reference to FIGS. 6, 7, 16 to 21. 6 and 7, FIGS. 16 to 19 and 21 are the C1-C2 lines of the through electrode substrate 104 in the enlarged drawing of the region 112 of the semiconductor device 100 shown in FIG. 3, similarly to FIG. The cross-sectional view along with is shown. FIG. 20 is a cross-sectional view taken along line B1-B2 shown in FIG. 1 when, for example, an integrated circuit 106a is formed by using a thin film transistor in a step of applying a high temperature treatment to the through electrode substrate 104 in step 57. Is shown.

First, as shown in FIG. 6, a through hole 126 penetrating the first surface 140a and the second surface 140b is formed in the glass substrate 120. Next, as shown in FIG. 7, a through electrode 118 is formed in the through hole 126. Since FIGS. 6 and 7 are described in the first embodiment, the description thereof is omitted here.

Subsequently, as shown in FIGS. 16 to 21, the multilayer wiring layer 116 is formed.

As shown in FIG. 16, the inorganic insulating film 134 is formed so as to be in contact with the first surface 140a. After that, an opening 132 that opens the inorganic insulating film 134 is formed. As the method and material for forming the inorganic insulating film 134, the same forming method and material as the inorganic insulating film 130 shown in FIG. 9 can be used. Further, as a method for forming the opening 132 for opening the inorganic insulating film 134, the same forming method as the method for forming the opening 124a and the opening 124b of the inorganic insulating film 130 shown in FIG. 9 can be used. The inorganic insulating film 134 is, for example, the first insulating film. The opening 132 is, for example, a first opening. The inorganic insulating film 134 does not overlap with the through electrode 118 and the through hole 126, and is provided on the outside of the through electrode 118 and the through hole 126.

Next, as shown in FIG. 17, the wiring layer 122 is formed. Since the method and material for forming the wiring layer 122 are the same as those described in FIG. 8, the description thereof will be omitted here. The wiring layer 122 is, for example, the first wiring. The opening 123 is, for example, a second opening. The shape of the wiring layer 122 is such that it surrounds the second opening in a ring shape. The region where the wiring layer 122 and the first surface 140a overlap is inside the region where the wiring layer 122 and the inorganic insulating film 134 overlap, and is outside the through electrode 118 or the through hole 126. That is, the position of the opening end of the opening 123 is inside the position of the opening end of the opening 124a and outside the through hole 126 or the through electrode 118. Further, the region where the wiring layer 122 and the first surface 140a overlap, and the through electrodes 118 and the through holes 126 do not overlap each other. Further, the region where the wiring layer 122 and the inorganic insulating film 134 overlap, and the through electrodes 118 and the through holes 126 do not overlap each other.

Also in the second embodiment, as in the first embodiment, the wiring layer 122 is preferably a thin film. Specifically, the thickness of the wiring layer 122 is preferably 1 μm or less. For example, when the through electrode substrate 104 is subjected to high temperature treatment, the through electrode 118 thermally expands. Through electrodes 118 and wiring layer 122 also become hot. When the wiring layer 122 is not a thin film, the thermal expansion of the wiring layer 122 causes cracks in the inorganic insulating film 134 and the inorganic insulating film 130 described later, which lowers the reliability of the through silicon via substrate 104. However, since the wiring layer 122 is a thin film, the volume of the wiring layer 122 is sufficiently smaller than that of the through electrode 118, so that the volume expansion of the wiring layer 122 is suppressed, and the inorganic insulating film 134 and the inorganic insulating described later are described. It is possible to prevent cracks from entering the film 130. Further, in one embodiment of the present disclosure, since the wiring layer 122 and the through electrode 118 do not overlap and are physically separated from each other, the wiring layer 122 may be cracked due to the thermal expansion of the through electrode 118. do not have.

Next, as shown in FIG. 18, the inorganic insulating film 130 is formed on the inorganic insulating film 134 and the wiring layer 122. Since the method and material for forming the inorganic insulating film 130 are the same as those described in FIG. 9, the description thereof is omitted here. Further, since the method of forming the opening 124a and the opening 124b for opening the inorganic insulating film 130 is the same as the description of FIG. 9, the description here will be omitted. The inorganic insulating film 130 is, for example, a second insulating film. Further, the opening 124a is the fourth opening, and the opening 124b is the third opening.

The opening 124a exposes the wiring layer 122. The opening 124b exposes the wiring layer 122, the first surface 140a, and the through silicon via 118. The region where the inorganic insulating film 134 and the wiring layer 122 overlap is outside the region where the wiring layer 122 and the first surface 140a overlap, and the region where the inorganic insulating film 134 and the wiring layer 122 overlap and the wiring layer 122 The region where the first surface 140a overlaps does not overlap with each other. That is, the inorganic insulating film 134 is provided on the outside of the through electrode 118 and the through hole 126.

Next, as shown in FIG. 19, the wiring layer 110 is formed on the inorganic insulating film 130 at the opening 124b that opens the inorganic insulating film 130 and the portion where the wiring layer 122 is exposed. Since the method and material for forming the wiring layer 110 are the same as those described in FIG. 10, the description thereof will be omitted here.

Also in the second embodiment, as in the first embodiment, the thickness of the wiring layer 110 is equal to or thicker than the thickness of the wiring layer 122 (the thickness of the wiring layer 122 is the thickness of the wiring layer 110). Equivalent to or thinner than). The wiring layer 110 is in contact with the opening 124b that opens the inorganic insulating film 130 and the exposed portion of the wiring layer 122, and is electrically connected to the wiring layer 122 via the opening 124b that opens the inorganic insulating film 130. To. The wiring layer 110 is, for example, a second wiring, and electrically connects the integrated circuit 106a and the integrated circuit 106b. When the thickness of the wiring layer 110 is equivalent to the thickness of the wiring layer 122, the covering property of the insulating film formed on the wiring layer 110 covering the layer below the insulating film is improved, and the reliability of the through electrode substrate 104 is improved. Can be improved. Further, when the thickness of the wiring layer 110 is equivalent to the thickness of the wiring layer 122, the flatness at the time of forming the multilayer wiring can be improved in the multi-layer wiring of the through electrode substrate 104. Further, when the thickness of the wiring layer 110 is the same as the thickness of the wiring layer 122, even if the wiring layer 110 is thermally expanded by the high temperature treatment, the insulating film formed on the wiring layer 110 may be cracked, for example. However, the stress associated with thermal expansion can be reduced. When the thickness of the wiring layer 110 is thicker than the thickness of the wiring layer 122, by using the wiring layer 110 as wiring between the integrated circuits, for example, the signal delay can be reduced or the amount of current flowing through the wiring can be reduced. Can be increased.

The through electrode substrate 104 is subjected to high temperature treatment after forming the wiring layer 110. FIG. 20 shows an example when the integrated circuit 106a is formed by using a thin film transistor. Since the description of FIG. 20 is the same as that of FIG. 11, the description here will be omitted.

Finally, as shown in FIG. 21, the wiring layer 108 is formed. Since the method and material for forming the wiring layer 108 are the same as those described in FIG. 12, the description thereof will be omitted here.

The wiring layer 108 is in contact with the opening 124a, the portion where the wiring layer 122 is exposed, the portion where the first surface 140a is exposed, the opening 123, and the through electrode 118, and is in contact with the opening 124a and the opening 123. It is electrically connected to 122 and through silicon via 118. The wiring layer 108 is, for example, a third wiring. Further, the opening 124a is a fourth opening. Similar to the wiring layer 110, the wiring layer 108 electrically connects the integrated circuit 106a and the integrated circuit 106b. Further, also in the second embodiment, as in the first embodiment, the thickness of the wiring layer 108 is thicker than the thickness of the wiring layer 122, so that the resistance value of the wiring is small and the wiring layer 108 is placed between the integrated circuits. By using the wiring, for example, it is possible to reduce the signal delay and increase the amount of current flowing through the wiring.

By the above manufacturing method, the multilayer wiring layer 116 is formed on the first surface 140a of the glass substrate 120, and the through electrode substrate 104 is manufactured. Further, the integrated circuit 106b is electrically connected to the wiring layer 110 of the through electrode substrate 104, and the through electrode substrate 104 on which the integrated circuit 106b is mounted is electrically connected to the printed circuit board 102 to form a semiconductor device. 100 is made. The bump 114 is, for example, a solder ball.

As described above, in the through electrode substrate according to the embodiment of the present disclosure, the inorganic insulating film provided on the first surface and the through electrode or through hole do not overlap, and the first insulating film is the through electrode. And is provided on the outside of the through hole. Further, in the through electrode substrate according to the embodiment of the present disclosure, the first wiring having a shape that surrounds the circumference of the first opening provided in the first insulating film in a ring shape and the through electrode overlap each other. However, the first wiring is provided on the outside of the through electrode or the through hole. Therefore, in the formation of the through electrode wiring, even if the through electrode substrate is subjected to high temperature treatment and the through electrode thermally expands, according to the present disclosure, the through electrode and the first insulating film are separated from each other without contacting each other. Since the through silicon via is separated from the first wiring without contacting it, it is possible to suppress the occurrence of cracks in the first wiring and the first insulating film. Further, the through silicon via according to the embodiment of the present disclosure is subjected to high temperature treatment, and even if the through electrode thermally expands, the volume expansion of the first wiring can be suppressed, so that the first insulating film and the through electrode substrate can be suppressed. The generation of cracks in the second insulating film can be suppressed. Therefore, the present disclosure provides a through electrode substrate having high reliability for high temperature treatment. The present disclosure also provides a method for manufacturing a through electrode substrate having high reliability for high temperature treatment.

Each of the above-described embodiments as the embodiments of the present disclosure can be appropriately combined and implemented as long as they do not contradict each other. In addition, those skilled in the art who have appropriately added, deleted, or changed the design of components based on each embodiment are also included in the scope of the present disclosure as long as the gist of the present disclosure is provided.

In addition, even if the effects are different from the effects brought about by each of the above-described embodiments, those that are clear from the description of the present specification or those that can be easily predicted by those skilled in the art are of course. It is understood to be brought about by this disclosure.

100: Semiconductor device, 102: Printed circuit board, 104: Wiring board (through electrode board), 106a: Integrated circuit, 106b: Integrated circuit, 108: Wiring layer, 110: Wiring layer, 112: Region, 114: Bump, 116: Multilayer wiring layer, 118: through electrode, 120: glass substrate, 122: wiring layer, 123: opening, 124a: opening, 124b: opening, 126: through hole, 130: inorganic insulating film, 132: opening, 134: Inorganic insulating film, 140a: 1st surface, 140b: 2nd surface, 150: Semiconductor film, 152: Insulation film, 153: Wiring film, 154: Insulation film, 155: Wiring film, 156: Insulation film, 200a: Center line, 200b: Center line

Claims (16)

A substrate having a first surface, a second surface, and a through hole penetrating the first surface and the second surface.
Through electrodes provided in the through holes and
A first wiring having a first opening whose center line substantially coincides with the center line of the through hole and whose hole diameter is larger than the hole diameter of the through hole, and which is in contact with the first surface.
With an insulating film having a second opening whose center line substantially coincides with the center line of the first opening and whose hole diameter is larger than the hole diameter of the first opening, and which is in contact with the first surface and the first wiring. ,
An opening provided on the insulating film and different from the second opening , and a second wiring in contact with the first wiring.
Through electrode substrate with. The through electrode substrate according to claim 1, wherein the thickness of the first wiring is thinner than the thickness of the second wiring. The through electrode substrate according to claim 1, wherein the thickness of the first wiring is 1 μm or less. The through electrode according to claim 1, wherein the position of the opening end of the first opening is inside the position of the opening end of the second opening and outside the through hole or the through electrode. substrate. The through electrode substrate according to claim 1, further comprising a third wiring that is electrically connected to the first wiring through the first opening and the second opening. A through hole is provided so as to penetrate the first surface of the substrate and the second surface of the substrate.
A through electrode is provided by filling the through hole with a conductor.
A first wiring having a first opening which is in contact with the first surface, whose center line substantially coincides with the center line of the through hole, and whose hole diameter is larger than the hole diameter of the through hole is provided.
An insulating film is provided so as to be in contact with the first surface and the first wiring.
The insulating film is provided with a second opening whose center line substantially coincides with the center line of the first opening and whose hole diameter is larger than the hole diameter of the first opening .
An opening provided on the insulating film and different from the second opening, and a second wiring provided in contact with the first wiring.
Manufacturing method of through silicon via substrate. The method for manufacturing a through electrode substrate according to claim 6, wherein the thickness of the first wiring is equal to or thinner than the thickness of the second wiring. The method for manufacturing a through electrode substrate according to claim 7, wherein the thickness of the first wiring is 1 μm or less. The through electrode according to claim 6 , wherein the position of the opening end of the first opening is inside the position of the opening end of the second opening and outside the through hole or the through electrode. Substrate manufacturing method. The method for manufacturing a through electrode substrate according to claim 6, wherein the processing at a high temperature is performed after the second wiring is provided. The through electrode according to claim 10, wherein a third wiring electrically connected to the first wiring is provided via the first opening and the second opening after the treatment at the high temperature. Substrate manufacturing method. A substrate having a first surface, a second surface, and a through hole penetrating the first surface and the second surface.
Through electrodes provided in the through holes and
A first insulating film provided on the first surface, having a first opening whose center line substantially coincides with the center line of the through hole and whose hole diameter is larger than the hole diameter of the through hole.
It is in contact with the first surface in the first opening, is provided on the first insulating film, the center line substantially coincides with the center line of the first opening, and the hole diameter is larger than the hole diameter of the first opening. With a first wiring having a small second opening,
A second insulating film provided on the first insulating film and the first wiring and having a third opening and a fourth opening, and a second insulating film.
A second wiring provided on the second insulating film and electrically connected to the first wiring through the third opening,
Through electrode substrate with. The through electrode substrate according to claim 12, wherein the thickness of the first wiring is equal to or thinner than the thickness of the second wiring. The through electrode substrate according to claim 12, wherein the thickness of the first wiring is 1 μm or less. The through electrode according to claim 12, wherein the position of the opening end of the second opening is inside the position of the opening end of the first opening and outside the through hole or the through electrode. Board . A substrate having a first surface, a second surface, and a through hole penetrating the first surface and the second surface.
Through electrodes provided in the through holes and
A first insulating film provided on the first surface, having a first opening whose center line substantially coincides with the center line of the through hole and whose hole diameter is larger than the hole diameter of the through hole.
It has a second opening provided on the first surface and the first insulating film, the center line substantially coincides with the center line of the first opening, and the hole diameter is smaller than the hole diameter of the first opening. The first wiring and
A second insulating film provided on the first insulating film and the first wiring and having a third opening and a fourth opening, and a second insulating film.
A second wiring provided on the second insulating film and electrically connected to the first wiring through the third opening,
A through silicon via substrate having a third wiring that is electrically connected to the first wiring through the first opening and the fourth opening.

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