JP2013165099A - Semiconductor device, semiconductor device manufacturing method, circuit device, circuit device manufacturing method and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has high reliability while including densely-arranged through electrodes.SOLUTION: A semiconductor device 10 comprises: a semiconductor substrate 11 including a first principal surface 11a on which an element circuit layer 30 is provided and a second principal surface 11b on the opposite side to the first principal surface 11a; a through hole 20 penetrating from the first principal surface 11a to the second principal surface 11b; a through electrode 50 which is formed inside the through hole 20 and connected to an element wiring layer 32 of the element circuit layer 30, and which continues into a rewiring layer 51 formed on the second principal surface 11b; and an air gap G provided between an inner peripheral surface of the through hole 20 and between the rewiring layer 51 and the second principal surface 11b. The sizes of each part of the air gap G are in a relation represented as (the size of the air gap between the rewiring layer 51 and the second principal surface 11b)>(the size of the air gap between the through electrode 50 and an inner peripheral wall of the through hole 20 on the second principal surface 11b side)>(the size of the air gap between the through electrode 50 and the inner peripheral wall of the through hole 20 on the first principal surface 11a side).

Description

  The present invention relates to a semiconductor device, a method for manufacturing the semiconductor device, a circuit device having the semiconductor device, a method for manufacturing the circuit device, and an electronic apparatus.

  In recent years, portable electronic devices have become widespread, and in these portable electronic devices, highly functional circuit devices on which a plurality of semiconductor devices are mounted are often used with the advancement of functions. In addition, portable electronic devices are also required to be smaller and lighter. Therefore, a manufacturing method has been proposed in which a plurality of through-electrodes called TSV (Throu Si Via) are formed on a semiconductor substrate, and the distance between the through-electrodes is reduced to increase the density, while miniaturizing the semiconductor device. Yes.

  In such a circuit device, a through electrode for connecting the semiconductor device and the wiring substrate is formed on the semiconductor substrate, and a recess is formed around the through electrode of the semiconductor substrate between the through electrode and the semiconductor substrate. The structure which provided the space | gap is proposed (for example, refer patent document 1 and patent document 2).

JP 2010-267805 A JP 2010-267830 A

  In Patent Document 1 and Patent Document 2 described above, when a circuit device to which a semiconductor device or a wiring board is connected is used in an environment in which a temperature change such as a temperature cycle is applied, the connection between the through electrode and the wiring layer of the semiconductor device. The insulating layer provided around the through-electrode, the connecting portion between the through-electrode and the wiring substrate, and the through-electrode is likely to crack due to the stress generated due to the difference in the coefficient of thermal expansion between them, and the reliability may be lowered.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

  Application Example 1 A semiconductor device according to this application example includes a semiconductor substrate having a first main surface on which an element circuit layer is provided and a second main surface opposite to the first main surface. In the semiconductor device, the through hole penetrating the first main surface and the second main surface, the inside of the through hole, and connected to the element wiring layer of the element circuit layer, A through electrode continuous with the rewiring layer formed on the surface of the second main surface, between the inner peripheral surface of the through hole and the through electrode, and between the rewiring layer and the second main surface A gap between the rewiring layer and the second main surface> a size of the through electrode on the second main surface side and the through hole. The size of the gap between the peripheral wall> the size of the gap between the through electrode on the first main surface side and the inner peripheral wall of the through hole. , Characterized by.

  According to this application example, by relaxing the stress generated due to the difference between the thermal expansion coefficients of the through electrode, the element wiring layer, and the semiconductor substrate connected to each other by the gap between the through electrode and the semiconductor substrate, The occurrence of cracks at the connection portion between the through electrode and the element circuit layer can be suppressed, and the reliability can be improved.

  When the semiconductor substrate is a conductor, it is necessary to ensure insulation between the through electrode and the semiconductor substrate. In the through electrode, the tip of the rewiring layer side tends to be inclined with the connection portion with the element circuit layer as a base portion. Therefore, the size of the gap is defined as the size of the gap between the redistribution layer and the second main surface> the size of the gap between the through electrode on the second main surface side and the inner peripheral wall of the through hole> first. The size of the gap between the through electrode on the main surface side and the inner peripheral wall of the through hole is set. As a result, the gap at the tip of the penetrating electrode becomes larger than the others, and insulation can be ensured even if the penetrating electrode is inclined.

  For example, when an electronic device such as a circuit board including another semiconductor device or circuit element is connected to the semiconductor device, rewiring is performed by providing a gap between the second main surface and the rewiring layer. The stress generated due to the difference in the coefficient of thermal expansion between the through electrode and the connection portion of the electronic device including the layer and the connection pressure can be relaxed.

  Application Example 2 In the semiconductor device according to the application example described above, it is preferable that the through electrode has a tapered shape that gradually decreases from the element wiring layer side toward the rewiring layer side.

  Thus, by making the through electrode into a tapered shape, the stress generated in the through electrode itself and the connecting portion between the through electrode and the element circuit layer can be reduced.

  Application Example 3 In the semiconductor device according to the application example described above, it is preferable that an insulating layer that fills the gap between the inner peripheral surface of the through hole and the through electrode is further formed.

  In such a configuration, an insulating layer is formed between the inner peripheral surface of the through hole and the through electrode, and on the second main surface side, a gap is provided between the second main surface and the rewiring layer. ing. If it does in this way, stress relaxation of the tip side of a penetration electrode can be aimed at, ensuring insulation of a penetration electrode and a semiconductor substrate.

  Application Example 4 In the semiconductor device according to the application example described above, it is preferable that the insulating layer is formed between the element wiring layer and a part of the thickness of the semiconductor substrate.

  In such a configuration, the insulating layer is formed between the inner peripheral surface of the through hole and the base portion side of the through electrode, and between the tip portion of the through electrode on the second main surface side and the through hole, and the first A gap is provided between the two principal surfaces and the rewiring layer. In this way, since the gap between the front end portion of the through electrode and the inner peripheral surface of the through hole is larger than the intermediate portion while ensuring insulation between the base portion of the through electrode and the semiconductor substrate, the front end of the through electrode It is possible to secure the insulation on the side and relieve stress.

  Application Example 5 A semiconductor device manufacturing method according to this application example includes a semiconductor substrate having a first main surface on which an element circuit layer is provided and a second main surface opposite to the first main surface. A step of opening a through-hole, a step of forming an insulating layer on the inner peripheral surface of the through-hole and the second main surface, and an element wiring layer on the first main surface side of the element circuit layer, A step of exposing in the through-hole, a through-electrode filling the inside of the insulating layer formed on the inner peripheral surface of the through-hole, and the insulation formed on the second main surface continuous with the through-electrode. Forming a rewiring layer extending on the surface of the layer; patterning the rewiring layer into a predetermined shape; and removing the insulating layer.

  According to this application example, after forming the insulating layer on the inner peripheral surface of the through hole and the second main surface and forming the through electrode, the inner peripheral surface of the through hole and the through electrode are removed by removing the insulating layer. And a gap is formed between the second main surface and the rewiring layer. Such a manufacturing method can form a void if the insulating layer is removed as compared with a method of forming a recess (gap) in the semiconductor substrate around the through electrode by etching as in the prior art described above. The through electrodes and the semiconductor substrate accompanying the formation of the recesses by etching in the semiconductor substrate are not damaged, and the reliability of the semiconductor device can be improved.

  In addition, the gap between the through electrode and the semiconductor substrate reduces the stress generated due to the difference in thermal expansion coefficient between the through electrode, the element wiring layer, and the semiconductor substrate in the temperature cycle during the process. The occurrence of cracks at the connection portion with the element circuit layer can be suppressed, and the reliability can be further improved.

  In addition, since the insulation between the through electrode and the semiconductor substrate can be ensured as described above, the distance (pitch) between the through electrodes can be reduced, and the density of the through electrodes can be increased and the semiconductor device can be downsized.

  Application Example 6 In the semiconductor device manufacturing method according to the application example described above, the thickness of the insulating layer is greater than the thickness between the redistribution layer and the second main surface> the through electrode on the second main surface side. The thickness between the inner peripheral surface of the through hole and the thickness between the through electrode on the first main surface side and the inner peripheral surface of the through hole is preferable.

  Although details will be described in the embodiment, when the insulating layer is formed from the second main surface side by the CVD method (chemical vapor deposition method), the insulating layer is located behind the through hole (close to the element circuit layer). The thickness of the portion) tends to be smaller than the thickness in the vicinity of the entrance to the through hole (second main surface side). Therefore, the gap formed by removing the insulating layer is such that the size of the gap between the rewiring layer and the second main surface> the distance between the through electrode on the second main surface side and the inner peripheral wall of the through hole. The relationship between the size of the gap> the size of the gap between the through electrode on the first main surface side and the inner peripheral wall of the through hole can be established.

Application Example 7 In the semiconductor device manufacturing method according to the application example described above, in the step of removing the insulating layer, the removal range of the insulating layer is between the rewiring layer and the second main surface, A range from the second main surface to a part of the thickness of the semiconductor substrate is preferable.
As a method for removing the insulating layer, for example, dry etching, wet etching, or the like can be used.

When the above-described etching method is used as a method for removing the insulating layer, the removal range of the insulating layer can be controlled by the etching processing time. Therefore, the removal range of the insulating layer in the through hole can be arbitrarily controlled by controlling the etching processing time. By removing the insulating layer in this manner, an insulating layer is formed between the inner peripheral surface of the through hole and the base portion side of the through electrode, and the distal end portion of the through electrode on the second main surface side and the inner peripheral surface of the through hole And a space provided between the second main surface and the redistribution layer.
In this way, since the gap between the front end portion of the through electrode and the inner peripheral surface of the through hole is larger than the intermediate portion while ensuring insulation between the base portion of the through electrode and the through hole, the front end of the through electrode It is possible to secure the insulation on the side and relieve stress.

  Application Example 8 In the method of manufacturing a semiconductor device according to the application example, in the step of removing the insulating layer, the removal range of the insulating layer is between the rewiring layer and the second main surface. Are preferred.

As described above, the removal range of the insulating layer can be controlled by the etching processing time. Therefore, the removal range of the insulating layer in the through hole can be arbitrarily controlled by controlling the etching processing time. As a result, it is possible to realize a configuration in which an insulating layer is formed between the inner peripheral surface of the through hole and the through electrode, and a gap is provided between the second main surface and the rewiring layer.
If it does in this way, stress relaxation of the tip side of a penetration electrode can be aimed at, ensuring insulation between a penetration electrode and a penetration hole.

Application Example 9 In the method for manufacturing a semiconductor device according to the application example, it is preferable that the insulating layer is SiO ₂ .

When the insulating layer is SiO ₂ , for example, a process gas such as C ₂ F ₆ , CF ₄ , or CHF ₃ is used for dry etching. These process gases can remove the insulating layer without damaging Si used as a semiconductor substrate, Cu used as a through electrode, or the like.

  Application Example 10 A circuit device according to this application example includes a semiconductor substrate having a first main surface on which an element circuit layer is provided, and a second main surface opposite to the first main surface, A through hole penetrating between the first main surface and the second main surface; and formed in the through hole and connected to the element wiring layer of the element circuit layer; and A through electrode continuous with the rewiring layer formed on the surface, a gap provided between the inner peripheral surface of the through hole and the through electrode, and between the rewiring layer and the second main surface, And the size of the gap is larger than the size of the gap between the rewiring layer and the second main surface> between the through electrode on the second main surface side and the inner peripheral wall of the through hole. The size of the gap> The semiconductor device in the relationship of the size of the gap between the through electrode on the first main surface side and the inner peripheral wall of the through hole, and the second Characterized in that it comprises an electronic device wiring layer on the surface opposite to the surface is exposed, the re-wiring layer and the connection terminals for connecting the wiring layer of the electronic device, the.

  According to this application example, the gap is formed between the through electrode provided in the semiconductor device and the inner peripheral surface of the through hole opened in the semiconductor substrate. By providing the gap, the semiconductor device can relieve the stress generated due to the difference in the thermal expansion coefficient between the connection portions of the through electrode, the element wiring layer, and the semiconductor substrate. Since the occurrence of cracks in the connecting portion can be suppressed, the reliability can be improved.

  In addition, insulation must be ensured between the through electrode (including the rewiring layer) and the semiconductor substrate. In the through electrode, the tip of the rewiring layer side tends to be inclined with the connection portion with the element circuit layer as a base portion. Therefore, the size of the gap is defined as the size of the gap between the redistribution layer and the second main surface> the size of the gap between the through electrode on the second main surface side and the inner peripheral wall of the through hole> first. The size of the gap between the through electrode on the main surface side and the inner peripheral wall of the through hole is set. As a result, the semiconductor device can ensure insulation even when the gap at the tip of the through electrode is larger than the others and the through electrode is inclined.

  In the circuit device configured by connecting the semiconductor device configured as described above and an electronic device such as a circuit board including another semiconductor device or a circuit element, between the second main surface of the semiconductor device and the redistribution layer In addition, by providing the voids, it is possible to enhance the insulation and to relieve the stress generated by the difference in thermal expansion coefficient between the through electrode (including the rewiring layer) and the electronic device and the connection pressure. Therefore, the reliability of the circuit device can be increased.

  In addition, since the above-described semiconductor device can secure the insulation between the through electrode and the semiconductor substrate, the distance between the through electrodes can be reduced, so that the circuit device can be increased in density and reduced in size.

  Application Example 11 A method of manufacturing a circuit device according to this application example connects the rewiring layer of the semiconductor device according to any one of the above application examples and the wiring layer of an electronic device facing the rewiring layer. And a step of connecting by terminals.

  According to this application example, the above-described semiconductor device has a gap between the through electrode and the semiconductor substrate, and ensures insulation even when the through electrode is inclined when connected to the electronic device. Can do. Moreover, the stress which generate | occur | produces by the difference of the thermal expansion coefficient of a penetration electrode (a rewiring layer is included) and an electronic device, and a connection pressure can be relieved. Therefore, the reliability of the circuit device can be increased.

  Application Example 12 A method for manufacturing a circuit device according to this application example includes a semiconductor substrate having a first main surface on which an element circuit layer is provided and a second main surface opposite to the first main surface. A step of opening a through hole between the first main surface and the second main surface, a step of forming an insulating layer on the inner peripheral surface of the through hole and the second main surface, and the circuit The element wiring layer of the element layer is exposed in the through hole, the through electrode filling the inside of the insulating layer formed on the inner peripheral surface of the through hole, the second electrode is continuous with the second electrode, A step of forming a rewiring layer extending on the surface of the insulating layer formed on the main surface, and a step of patterning the rewiring layer into a predetermined shape. A step of connecting the rewiring layer and the wiring layer of the electronic device facing the rewiring layer by a connection terminal; After connecting the semiconductor device and said electronic device, characterized in that it comprises a step of removing the insulating layer.

  In the circuit device manufacturing method according to this application example, after the semiconductor device and the electronic device are connected, the insulating layer formed on the semiconductor device is removed. Therefore, when connecting the semiconductor device and the electronic device, the space between the through electrode and the semiconductor substrate is filled with an insulating layer. Therefore, it is possible to prevent the insulating layer from being broken due to the inclination of the through electrode or the bonding pressure in the connection process between the semiconductor device and the electronic device. Then, by removing the insulating layer after the connection between the semiconductor device and the electronic device, the reliability of the circuit device can be improved by ensuring the insulation as the circuit device.

  Application Example 13 In the method of manufacturing a circuit device according to the application example, in the step of forming the insulating layer, the thickness of the insulating layer is a thickness between the rewiring layer and the second main surface> the above It is preferable that the relationship between the thickness between the through electrode on the second main surface side and the through hole is greater than the thickness between the through electrode on the first main surface side.

  By making the thickness of the insulating layer as described above, the size of the gap formed after removing the insulating layer is such that the size of the gap between the rewiring layer and the second main surface> the second main surface side. The size of the gap between the through electrode and the inner peripheral wall of the through hole is larger than the size of the gap between the through electrode on the first main surface side and the inner peripheral wall of the through hole. As a result, the gap at the tip of the penetrating electrode becomes larger than the others, and insulation can be ensured even if the penetrating electrode is inclined.

  Further, when connecting the semiconductor device and the electronic device, by providing a gap between the second main surface and the rewiring layer, the coefficient of thermal expansion of the connection portion between the through electrode and the electronic device including the rewiring layer is provided. The stress generated by the difference and the connection pressure can be relaxed.

  Further, by setting the thickness of the insulating layer to the relationship described above, the through electrode is tapered gradually from the element wiring layer side (first main surface side) toward the rewiring layer side (second main surface side). It becomes a shape. Thus, by making the through electrode into a tapered shape, the stress generated in the through electrode itself and the connecting portion between the through electrode and the element circuit layer can be reduced.

  Application Example 14 In the circuit device manufacturing method according to the application example, in the step of removing the insulating layer, the removal range of the insulating layer is between the rewiring layer and the second main surface, A range from the second main surface to a part of the thickness of the semiconductor substrate is preferable.

In the case where an etching method is used as a method for removing the insulating layer, the removal range of the insulating layer can be controlled by the etching processing time. Therefore, the removal range of the insulating layer in the through hole can be arbitrarily controlled by controlling the etching processing time. By removing the insulating layer in this way, an insulating layer is formed between the inner peripheral surface of the through hole and the base portion side of the through electrode, and between the tip portion of the through electrode on the second main surface side and the through hole. And the structure by which the space | gap is provided between the 2nd main surface and the rewiring layer is realizable.
Accordingly, since the gap between the front end portion of the through electrode and the inner peripheral surface of the through hole is larger than the intermediate portion while ensuring the insulation between the base portion of the through electrode and the through hole, the insulating property on the front end side of the through electrode is increased. And stress relaxation can be achieved.

  Application Example 15 In the method of manufacturing a circuit device according to the application example, in the step of removing the insulating layer, the removal range of the insulating layer is between the rewiring layer and the second main surface. Are preferred.

As described above, the removal range of the insulating layer can be controlled by the etching processing time. Therefore, the removal range of the insulating layer in the through hole can be arbitrarily controlled by controlling the etching processing time. By removing the insulating layer in this way, an insulating layer is formed between the inner peripheral surface of the through hole and the through electrode, and a gap is provided between the second main surface and the rewiring layer. realizable.
Therefore, stress relaxation at the tip of the through electrode can be achieved while ensuring insulation between the through electrode and the through hole.

  Application Example 16 An electronic apparatus according to this application example includes the semiconductor device or the circuit device according to any one of the application examples described above.

  The electronic apparatus according to this application example can increase the reliability while realizing high density, small size, and light weight by using the above-described semiconductor device or circuit device.

1A and 1B show a semiconductor device according to a first example of Embodiment 1, wherein FIG. 3A is a cross-sectional view showing a part of a main part, and FIG. FIG. 4 is a cross-sectional view showing a part of a semiconductor device according to a second example of the first embodiment. FIG. 4 is a cross-sectional view showing a part of a semiconductor device according to a third example of the first embodiment. FIG. 4 is a partial cross-sectional view showing main processes in the method for manufacturing a semiconductor device according to the first embodiment. FIG. 4 is a partial cross-sectional view showing main processes in the method for manufacturing a semiconductor device according to the first embodiment. FIG. 4 is a partial cross-sectional view showing main processes in the method for manufacturing a semiconductor device according to the first embodiment. FIG. 3 is a partial cross-sectional view illustrating the circuit device according to the first embodiment. FIG. 9 is a cross-sectional view showing a part of the method for manufacturing the circuit device according to the second embodiment. The perspective view which shows roughly the external appearance of the terahertz camera which concerns on one specific example of an electronic device. The block diagram which shows the structure of a terahertz camera roughly.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The drawings referred to in the following description are schematic views in which the vertical and horizontal scales of each member or part are different from actual ones in order to make each member a recognizable size.
(Embodiment 1)
(Semiconductor device / first embodiment)

1A and 1B show a semiconductor device according to a first example of Embodiment 1, wherein FIG. 1A is a cross-sectional view showing a part of a main part, and FIG. 1B is a cross-sectional view showing details of a gap. A large number of through electrodes 50 are formed on the semiconductor substrate 11, and one of them will be described as an example. As shown to (a), the semiconductor device 10 has the 1st main surface 11a in which the element circuit layer 30 is provided, and the 2nd main surface 11b on the opposite side to the 1st main surface 11a. 11, a through hole 20 passing between the first main surface 11 a and the second main surface 11 b, and one end portion inside the through hole 20 is connected to the element wiring layer 32 of the element circuit layer 30. The through electrode 50 is formed so as to penetrate the second main surface 11b, and the rewiring layer 51 is formed at the end of the through electrode 50 on the second main surface 11b side.
In the present embodiment, the semiconductor substrate 11 is exemplified as a Si substrate.

  The element circuit layer 30 is an integrated circuit (IC), a sensor circuit, or the like, and a plurality of circuit elements, wiring layers, and insulating layers are laminated. 1 illustrates a configuration in which an insulating layer 31, an element wiring layer 32, an insulating layer 33, a second element wiring layer 34, and an insulating layer 35 are stacked in this order. The insulating layer 31 is between the first main surface 11a of the semiconductor substrate 11 and the element wiring layer 32, and is in close contact with the first main surface 11a. The element wiring layer 32 and the second element wiring layer 34 are connected by a through electrode 36 (sometimes referred to as a via). The through electrode 50 is sometimes called a via in the semiconductor device.

  As shown in the figure, the through electrode 50 has a columnar shape having a tapered shape that gradually decreases from the element wiring layer 32 side toward the rewiring layer 51 side. The through electrode 50 shown in FIG. 1A is exaggerated. A barrier layer 41 and a seed layer 42 are laminated on the outer peripheral surface of the through electrode 50 and the surface of the rewiring layer 51 on the second main surface 11b side. The through electrode 50 is connected to the element wiring layer 32 through the barrier layer 41 and the seed layer 42. The through electrode 50 is made of a metal material such as Cu.

As shown in FIG. 1A, a barrier layer 41 and a seed layer 42 are interposed between the through electrode 50 and the inner peripheral surface of the through hole 20 and between the rewiring layer 51 and the second main surface. A gap G is formed. Next, the gap G will be described in detail with reference to FIG. The size of the gap G is G1, the size of the gap between the rewiring layer 51 and the second main surface 11b, and the gap between the through electrode 50 on the second main surface 11b side and the inner peripheral wall of the through hole 20. Is G2, the size of the gap between the through electrode 50 at the intermediate thickness position of the semiconductor substrate 11 and the inner peripheral wall of the through hole 20 is G3, and the through electrode 50 and the through hole 20 on the first main surface 11a side. When the size of the gap between the inner wall and the inner wall is G4, the relationship is G1>G2>G3> G4. In the following, the size of each gap is subtracted by the thickness of the barrier layer 41 and the seed layer 42. However, the thickness of the barrier layer 41 and the seed layer 42 is very thin relative to the size of each gap. These thicknesses are omitted for explanation.
Subsequently, a second embodiment will be described.

  According to the first embodiment described above, in an environment where a temperature cycle is applied during the manufacturing process or the like, the stress generated due to the difference in thermal expansion coefficient between the through electrode 50, the element wiring layer 32, and the semiconductor substrate 11 is reduced. 50 can be mitigated by the gap G provided between the semiconductor substrate 11 and the semiconductor substrate 11, and cracks can be prevented from occurring at the connection portion between the through electrode 50 and the element wiring layer 32, thereby improving reliability. Can be made.

  In addition, the penetrating electrode 50 has a tip end portion on the rewiring layer 51 side that is easily inclined with respect to the connection portion with the element wiring layer 32. Therefore, by setting the size of the gap G to a relationship of G1> G2> G3> G4, the gap at the tip of the through electrode 50 becomes larger than the others, and insulation is ensured even if the through electrode 50 is inclined. Can do.

  For example, when the semiconductor device 10 and an electronic device such as a circuit board including another semiconductor device or circuit element are connected by the through electrode 50, a gap is also formed between the second main surface 11 b and the rewiring layer 51. By providing, it is possible to relieve the difference in the coefficient of thermal expansion between the through electrode 50 and the connection portion of the electronic device including the rewiring layer 51 and the stress associated with the connection.

The through electrode 50 has a columnar shape with a taper that gradually decreases from the element wiring layer 32 side toward the rewiring layer 51 side. In this way, by forming the through electrode 50 in a tapered shape, it is possible to relieve stress generated in the through electrode 50 itself and the connection portion between the through electrode 50 and the element circuit layer 30.
(Semiconductor device / second embodiment)

FIG. 2 is a cross-sectional view illustrating a part of the semiconductor device 10 according to the second example of the first embodiment. In addition, description is abbreviate | omitted about the common part with 1st Example (refer FIG. 1) mentioned above, and attaches | subjects and demonstrates the same code | symbol to the same location. In FIG. 2, the semiconductor device 10 includes a semiconductor substrate 11 provided with an element circuit layer 30, one end connected to the element wiring layer 32 of the element circuit layer 30 inside the through hole 20, and a second It has a through electrode 50 penetrating the main surface 11b and a rewiring layer 51 formed at the end of the through electrode 50 on the second main surface 11b side. The configuration of the element circuit layer 30, the semiconductor substrate 11, the through hole 20, and the through electrode is the same as that of the first embodiment described above. In the second embodiment, the insulating layer 40 that fills the gap between the inner peripheral surface of the through hole 20 and the through electrode 50 is formed. The insulating layer 40 is made of SiO ₂ or SiN.

  The insulating layer 40 is formed in the total thickness range of the semiconductor substrate 11 in the through hole 20. Therefore, the insulating layer 40 is formed in the through hole 20, and a gap G is formed between the rewiring layer 51 and the second main surface 11 b.

According to the second embodiment as described above, it is possible to relieve stress on the front end side of the through electrode 50 while ensuring insulation between the through electrode 50 and the semiconductor substrate 11.
(Semiconductor device / third embodiment)

Next, a third embodiment will be described.
FIG. 3 is a cross-sectional view illustrating a part of the semiconductor device 10 according to the third example of the first embodiment. In addition, description is abbreviate | omitted about the common part with 1st Example (refer FIG. 1) mentioned above, and attaches | subjects and demonstrates the same code | symbol to the same location. In FIG. 3, the semiconductor device 10 includes a semiconductor substrate 11 provided with an element circuit layer 30, one end connected to the element wiring layer 32 of the element circuit layer 30 inside the through hole 20, and a second It has a through electrode 50 penetrating the main surface 11b and a rewiring layer 51 formed at the end of the through electrode 50 on the second main surface 11b side. The configuration of the element circuit layer 30, the semiconductor substrate 11, the through hole 20, and the through electrode is the same as that of the first embodiment described above. In the third embodiment, the insulating layer 40 that fills a part of the gap between the inner peripheral surface of the through hole 20 and the through electrode 50 is formed.

As shown in FIG. 3, the insulating layer 40 is formed between the position of the element wiring layer 32 and a part of the thickness of the semiconductor substrate 11 (in FIG. 3, an example of an intermediate position of the thickness of the semiconductor substrate 11). Is shown).
That is, the insulating layer 40 is formed between the inner peripheral surface of the through hole 20 and the base portion side of the through electrode 50, and the tip of the through electrode 50 on the second main surface 11 b side and the semiconductor substrate 11 are formed. A gap G is provided between the second main surface 11 b and the rewiring layer 51.

In this way, while ensuring the insulation between the base portion of the through electrode 50 and the inner peripheral surface of the through hole 20, the gap G (see FIG. 1) between the tip portion of the through electrode 50 and the inner peripheral surface of the through hole 20. Since the gap G (corresponding to G2) is larger than the gap G (corresponding to G3 in FIG. 1) in the intermediate portion, it is possible to ensure insulation and stress relaxation on the tip side of the through electrode 50.
(Method for manufacturing semiconductor device)

Next, a method for manufacturing the semiconductor device described above will be described. In addition, since the manufacturing method of 1st Example-3rd Example mentioned above can be demonstrated in the same process, the case of 1st Example is illustrated and demonstrated. Further, a large number of through electrodes 50 are formed on the semiconductor substrate 11, and these are formed in a batch by batch processing in the state of a wafer substrate, and one of them will be described as an example.
4, 5, and 6 are partial cross-sectional views illustrating main processes in the method for manufacturing the semiconductor device 10. As shown in FIG. 4A, the semiconductor substrate 11 having the element circuit layer 30 formed on the first main surface 11a is prepared. The element circuit layer 30 is an integrated circuit, a sensor circuit, or the like, and a plurality of circuit elements, wiring layers, and insulating layers are laminated. FIG. 4A illustrates a configuration in which the insulating layer 31, the element wiring layer 32, the insulating layer 33, the second element wiring layer 34, and the insulating layer 35 are stacked in this order from the surface of the first main surface 11a. . The element wiring layer 32 and the second element wiring layer 34 are connected by a through electrode 36. A case where a Si substrate is used as the semiconductor substrate 11 will be described as an example.

  First, as shown in FIG. 4A, a support substrate 60 is attached to the formation surface of the element circuit layer 30 using an adhesive 61 or the like. The support substrate 60 is used in order to prevent cracking in the subsequent process flow and to improve the handleability, and preferably has a thermal expansion coefficient close to that of the semiconductor substrate 11, for example, Pyrex (registered trademark). Glass or quartz glass is used. After the support substrate 60 is attached, the upper surface 12 of the semiconductor substrate 11 is ground to the second main surface 11b by grinding or the like.

Next, as shown in FIG. 4B, the through hole 20 is formed in the semiconductor substrate 11. The through hole 20 penetrates between the first main surface 11a where the element circuit layer 30 is formed and the second main surface 11b opposite to the first main surface 11a, and the second main surface 11b side is The insulating layer 31 (exposed surface 31a) is exposed on the first main surface 11a side. The opening process of the through hole 20 is performed by dry etching such as RIE (Reactive Ion Etching) and ICP (Inductive Coupled Plasma Etching). In these dry etching processes, a bushing process in which etching and deposition are alternately repeated can be applied. SF ₆ or O ₂ is used as an etching process gas, and C ₄ F ₆ or O ₂ is used for deposition. _{Use 2} . Specifically, a hole having a large aspect ratio can be opened by repeating the process of covering and protecting a portion except where a hole is desired to be opened with a resist and removing the resist after the etching process.

In the present embodiment, the opening diameter of the through hole 20 is 10 μm to 20 μm, and the depth of the through hole is 50 μm to 100 μm. In this case, the aspect ratio is 3 to 7.
The through holes 20 may be arranged in an array in the wafer, or may be a peripheral arrangement, and the distance (pitch) between the through holes 20 can be about 20 μm to 30 μm.

Next, as shown in FIG. 4C, the exposed surface 31a exposed in the through hole 20 of the insulating layer 31 is removed by dry etching, and the connection surface 32a of the element wiring layer 32 is exposed. The material of the insulating layer 31 is SiO ₂ .

Next, as illustrated in FIG. 5D, an insulating layer 40 that is continuous with the inner peripheral surface of the through hole 20 and the surface of the second main surface 11 b is formed. The insulating layer 40 is also formed on the connection surface 32 a of the element wiring layer 32. The insulating layer 40 is made of SiO ₂ , SiN or the like by a CVD method. A resin material can be used as the material of the insulating layer 40. Even if it forms in the same process, the thickness of the insulating layer 40 changes with places to form. This will be described with reference to FIG.

  The thickness of the insulating layer 40 becomes thinner as the through hole 20 becomes deeper as shown in FIG. The thickness formed on the surface of the second main surface 11b is t1, the thickness of the opening of the through hole 20 (position of the second main surface 11b) is t2, and the thickness of the bottom is t3.

  As shown in Table 1, the thickness of the insulating layer 40 has a relationship of t1> t2> t3. That is, it becomes thinner as the through hole 20 becomes deeper. The thickness of each part of the insulating layer 40 varies depending on the hole diameter (μm), the hole depth (μm), and the aspect ratio of the through hole 20, but the larger the aspect ratio, the greater the thickness of the insulating layer 40 between the parts. The difference tends to increase. This indicates that if the aspect ratio is increased, the taper of the through electrode 50 described later can be increased.

  This data is obtained when the CVD processing time is 30 minutes, and the thickness of the insulating layer 40 increases in proportion to the CVD processing time when the CVD processing conditions are constant. I know that.

Table 1 shows the relationship between the thicknesses of the respective portions of the insulating layer 40. From the actual management, CVD processing conditions (t2> 5 μm, 2 μm <t3 <5 μm, t1> 10 μm are satisfied). It is preferable to control (including processing time). In particular, t1 is preferably set to t1> 10 μm from the viewpoint of reducing parasitic capacitance.
Note that the insulating layer 40 may also be formed on the insulating layer 31 on the bottom surface of the through-hole 20 and it is necessary to remove this.

Subsequently, as shown in FIG. 5F, the insulating layer 31 in the through hole 20 is removed by dry etching, and the connection surface 32a of the element wiring layer 32 is exposed. This insulating layer removal step is performed using an oxide film etcher after resist-protecting a portion where the insulating layer 40 is not desired to be removed. As the process gas, C ₂ F ₆ , CF ₄ , CHF ₃ or the like is used.

  Next, as shown in FIG. 5G, a barrier layer 41 and a seed layer 42 are formed on the surface of the insulating layer 40 by a CVD method or a sputtering method. Both the barrier layer 41 and the seed layer 42 are formed on the inner peripheral wall of the insulating layer 40 in the through hole 20, the connection surface 32a of the element wiring layer 32, and the surface of the insulating layer 40 on the second main surface 11b. The barrier layer 41 uses Ti, TiW, TiN throat, and the seed layer 42 uses Cu. The thickness of the barrier layer 41 was 100 nm, and the thickness of the seed layer 42 was 300 nm.

  Next, as shown in FIG. 5 (h), the through electrode 50 filling the inside of the insulating layer 40 formed on the inner peripheral surface of the through hole 20 and the through electrode 50 are continuous with the second main surface 11b. A rewiring layer 51 is formed on the surface of the insulating layer 40 to be formed. The through electrode 50 and the rewiring layer 51 are formed by a series of Cu plating. The through electrode 50 and the rewiring layer 51 may be formed in separate steps. The thickness of the rewiring layer 51 is about 6 μm.

  Next, as shown in FIG. 6I, the insulating layer 40, the barrier layer 41, the seed layer 42, and the rewiring layer 51 on the second main surface 11b are patterned into a predetermined shape. This patterning step is performed by etching using a resist mask. In this patterning step, after forming the insulating layer 40, the barrier layer 41, the seed layer 42, the through electrode 50, and the rewiring layer 51 may be formed in this order using a resist mask. Thereafter, the resist mask is removed.

Next, as shown in FIG. 6J, the insulating layer 40 is removed. When the insulating layer 40 is SiO ₂ , dry etching using a hydrofluoric acid vapor or wet etching using hydrofluoric acid is performed.
Through such a series of steps, the semiconductor device 10 having the gap G between the through electrode 50 and the semiconductor substrate 11 is formed (see also FIG. 1). A layer of a low melting point metal such as SnAg or a noble metal such as Au may be formed on the surface of the rewiring layer 51.
Thereafter, the support substrate 60 is peeled and separated into individual semiconductor devices 10. Further, when the semiconductor device 10 is connected to another electronic device, bumps may be formed on the surface of the rewiring layer 51.

  According to the method for manufacturing the semiconductor device 10 described above, the insulating layer 40 is formed on the inner peripheral surface of the through hole 20 and the second main surface 11b, and the insulating layer is formed after the through electrode 50 and the rewiring layer 51 are formed. By removing 40, gaps are formed between the inner peripheral surface of the through hole 20 and the through electrode 50, and between the second main surface 11b and the rewiring layer 51. In such a manufacturing method, a void is formed by removing the insulating layer 40 as compared with the method of forming a recess (gap) around the through electrode 50 of the semiconductor substrate 11 by etching as in the conventional technique described above. Is possible. Therefore, it is possible to improve the reliability of the semiconductor device 10 without damaging the through electrode 50 and the semiconductor substrate 11 due to the formation of the recesses in the semiconductor substrate 11 by etching.

  Further, due to the gap G between the through electrode 50 and the semiconductor substrate 11, the gap G is generated in accordance with the difference in thermal expansion coefficient between the through electrode 50, the element wiring layer 32, and the semiconductor substrate 11 in an environment where a temperature cycle during the manufacturing process is applied. It is possible to relieve the stress to be generated, to suppress the occurrence of cracks at the connection portion between the through electrode 50 and the element wiring layer 32, and to further improve the reliability.

  Further, since the insulation between the through electrode 50 and the semiconductor substrate 11 can be secured, the distance (pitch) between the through electrodes 50 can be reduced, and the semiconductor device 10 can be increased in density and downsized.

  The thickness of the insulating layer 40 is set such that the thickness t1 between the rewiring layer 51 and the second main surface 11b> the thickness t2 between the through electrode 50 on the second main surface 11b side and the inner peripheral surface of the through hole 20. > Thickness t3 between the through electrode 50 on the first main surface 11a side and the inner peripheral surface of the through hole 20 is established. Therefore, the gap G formed by removing the insulating layer 40 is equal to the size G1 of the gap between the rewiring layer 51 and the second main surface 11b> the through electrode 50 and the through hole on the second main surface 11b side. The size of the gap G2 between the inner peripheral wall 20 and the size G3 of the gap between the through electrode 50 on the first main surface 11a side and the inner peripheral wall of the through hole 20 can be made.

  Further, according to such a manufacturing method, the through electrode 50 has a tapered shape that gradually becomes thinner from the element wiring layer 32 side toward the rewiring layer 51 side. By forming the through electrode 50 in a tapered shape, it is possible to reduce the stress generated in the through electrode 50 itself and the connection portion between the through electrode 50 and the element circuit layer 30.

  The removal range of the insulating layer 40 can be arbitrarily set by controlling the etching processing time. For example, in the semiconductor device 10 described in the second embodiment (see FIG. 2), in the step of removing the insulating layer 40, the removal range of the insulating layer is set between the rewiring layer 51 and the second main surface 11b. By providing only the gap, the insulating layer 40 is filled between the inner peripheral surface of the through hole 20 and the through electrode 50, and the semiconductor device has a gap G between the rewiring layer 51 and the second main surface 11 b. 10 can be formed.

  According to such a manufacturing method, stress relaxation on the front end side of the through electrode 50 can be achieved while ensuring insulation between the through electrode 50 and the semiconductor substrate 11.

Further, in the step of removing the insulating layer 40, by controlling the etching processing time, the removal range of the insulating layer 40 can be reduced between the rewiring layer 51 and the second main surface 11b, and from the second main surface 11b to the semiconductor. The range can be up to a part of the thickness of the substrate 11. In this way, the insulating layer 40 is formed between the inner peripheral surface of the through hole 20 and the base portion side of the through electrode 50, and the front end portion of the through electrode 50 on the second main surface 11 b side, the through hole 20, and the like. A gap G can be formed between the second main surface 11 b and the rewiring layer 51.
Further, since the gap G between the front end portion of the through electrode 50 and the inner peripheral surface of the through hole 20 is larger than the intermediate portion while ensuring insulation between the base portion of the through electrode 50 and the through hole 20, the through electrode It is possible to ensure insulation and relieve stress on the front end side of 50.
(Circuit device)

Subsequently, a circuit device 100 using the semiconductor device 10 described above will be described.
FIG. 7 is a partial cross-sectional view showing the circuit device 100 according to the first embodiment. The circuit device 100 includes the semiconductor device 10 described above, the electronic device 80 in which a part of the wiring layer 83 is exposed on the surface facing the second main surface 11b of the semiconductor device 10, and the rewiring layer 51 of the semiconductor device 10. And a connection terminal 85 that connects the wiring layer 83 of the electronic device 80. The semiconductor device 10 is the same as that described in the first to third embodiments. Therefore, the description of the semiconductor device 10 is omitted, and the same reference numerals as those in the first embodiment (see FIG. 1) are given.

The semiconductor device 10 is, for example, an integrated circuit (IC) or a sensor circuit. As the sensor circuit, for example, a so-called MEMS (Micro Electro Mechanical Systems) in which an inertial sensor, a temperature sensor, and the like are formed on a substrate together with an electronic circuit may be used.
The electronic device 80 is, for example, an integrated circuit (IC) or a sensor circuit. As the sensor circuit, for example, a so-called MEMS (Micro Electro Mechanical Systems) in which an inertial sensor, a temperature sensor, and the like are formed on a substrate together with an electronic circuit may be used. Further, it may be a circuit board on which other electronic elements are mounted.

  The electronic device 80 is formed by laminating an insulating layer 82, a wiring layer 83, and an insulating layer 84 in this order on one surface of the circuit board 81. A part of the wiring layer 83 is a connection surface 83a exposed to the semiconductor device 10 side.

  In the semiconductor device 10 and the electronic device 80, the rewiring layer 51 on the semiconductor device 10 side and the wiring layer 83 on the electronic device 80 side are connected by a connection terminal 85. The connection terminal 85 is made of solder, a low melting point metal such as SnAg, Au, or a conductive adhesive. A bump may be formed on the rewiring layer 51 or the wiring layer 83 as the connection terminal 85. In such a case, it is preferable to form a connection electrode such as SnAg on the wiring layer facing the bump formation side. FIG. 7 illustrates a case where the connection electrode 52 made of SnAg is provided on the rewiring layer 51 side.

  In the circuit device 100 described above, by providing a gap between the second main surface 11b of the semiconductor device 10 and the rewiring layer 51, the insulation is improved and the through electrode 50 (including the rewiring layer 51) is provided. The difference in the thermal expansion coefficient of the electronic device 80 and the stress generated with the connection can be relaxed. Therefore, the reliability of the circuit device can be increased.

  In addition, since the through electrode 50 has a tapered shape, even when a pressing force is applied when the electronic device 80 is joined and the through electrode 50 is inclined, the insulating property is impaired because a gap is provided at the tip. There is no.

  In addition, since the semiconductor device 10 described above can ensure the insulation between the through electrode 50 and the semiconductor substrate 11, the distance between the through electrodes 50 can be reduced, and thus the circuit device 100 can be increased in density and size.

Note that. The circuit device 100 using the semiconductor device 10 according to the second embodiment or the third embodiment described above can achieve the same effect.
(Embodiment 2)

  Next, a method for manufacturing the circuit device according to the second embodiment will be described. The configuration of the circuit device of the second embodiment is the same as the configuration of the circuit device 100 of the first embodiment described above. In the first embodiment, the semiconductor device 10 from which the insulating layer 40 is removed and the electronic device 80 are connected. In the second embodiment, after the semiconductor device 10 and the electronic device 80 are connected, the insulating layer 40 is changed. It is characterized by removing. Therefore, the same parts as those in the first embodiment will be described by assigning the same reference numerals to the differences from the first embodiment.

  8A to 8C are cross-sectional views illustrating main processes of the method for manufacturing the circuit device 100 according to the second embodiment. FIG. 8A shows a form of the semiconductor device 10. The semiconductor device 10 is performed up to the step shown in FIG. 6I using the semiconductor device manufacturing method of the first embodiment described above. That is, the barrier layer 41, the seed layer 42, and the rewiring layer 51 on the second main surface 11b are patterned into a predetermined shape, and the insulating layer 40 is not removed.

  Next, as shown in FIG. 8B, the electronic device 80 is connected to the semiconductor device 10 by a connection terminal 85. The method for connecting the electronic device 80 and the semiconductor device 10 can be the same as that of the first embodiment (see FIG. 7).

  Subsequently, as illustrated in FIG. 8C, the insulating layer 40 is removed in a state where the electronic device 80 and the semiconductor device 10 are connected. The method for removing the insulating layer 40 can be the same as that of the first embodiment.

  The removal range of the insulating layer may be only between the rewiring layer 51 and the second main surface 11b as in the second embodiment, and the rewiring layer 51 and the second main surface as in the third embodiment. 11b (see FIG. 2) and the range up to the middle of the thickness of the semiconductor substrate 11 (see FIG. 3).

In the method for manufacturing the circuit device 100 according to the second embodiment described above, after the semiconductor device 10 and the electronic device 80 are connected, the insulating layer 40 formed on the semiconductor device 10 is removed. Accordingly, when the semiconductor device 10 and the electronic device 80 are connected, the insulating layer 40 is filled between the through electrode 50 and the semiconductor substrate 11 and between the rewiring layer 51 and the second main surface 11b. If the semiconductor device 10 and the electronic device 80 are connected in a state where the insulating layer 40 remains in this way, it is possible to prevent the insulating layer 40 from being broken due to the inclination of the through electrode 50 or the bonding pressure. Then, after connecting the semiconductor device 10 and the electronic device 80, the insulating layer 40 is removed to ensure insulation as the circuit device 100, and the thermal expansion of the through electrode 50 (including the rewiring layer 51) and the electronic device 80. The stress accompanying the difference in rate can be relaxed. Therefore, the reliability of the circuit device 100 can be improved.
(Electronics)

Next, an electronic apparatus including the circuit device 100 described above will be described using a terahertz camera as an example.
FIG. 9 is a perspective view schematically showing an appearance of a terahertz camera according to a specific example of the electronic apparatus. The terahertz camera 200 includes a housing 201. A slit 202 is formed on the front surface of the housing 201, and a lens 203 is mounted on the front surface. From the slit 202, a terahertz band electromagnetic wave is irradiated toward an object (not shown). Such electromagnetic waves include radio waves called terahertz waves and light such as infrared rays. The terahertz band includes a frequency band of 100 GHz to 30 THz. The lens 203 receives a terahertz band electromagnetic wave reflected from the object.

The configuration of the terahertz camera 200 will be described in more detail.
FIG. 10 is a block diagram schematically showing the configuration of the terahertz camera 200. As shown in FIG. 10, the terahertz camera 200 includes an irradiation source (electromagnetic wave source) 210. A drive circuit 211 is connected to the irradiation source 210. The drive circuit 211 supplies a desired drive signal to the irradiation source 210. The irradiation source 210 radiates terahertz band electromagnetic waves in response to receipt of the drive signal. As the irradiation source 210, for example, a laser light source can be used.

  The lens 203 constitutes the optical system 212. The optical system 212 may include an optical component in addition to the lens 203. On the optical axis 213 of the lens 203, the circuit device 100 including the semiconductor device 10 described above is disposed. In the present embodiment, the circuit device 100 is a photodetector. Therefore, hereinafter, the circuit device 100 will be described as the photodetector 100. Note that the photodetector 100 includes a thermal detection element (not shown). The surface of the semiconductor substrate 11 is orthogonal to the optical axis 213, for example. An analog / digital conversion circuit 214 is connected to the photodetector 100. The analog-to-digital conversion circuit 214 is supplied with the output of a thermal detection element (not shown) from the photodetector 100 in time series. The analog-digital conversion circuit 214 converts the output analog signal into a digital signal.

  An arithmetic processing circuit (processing circuit) 215 is connected to the analog-digital conversion circuit 214. Digital image data is supplied from the analog-digital conversion circuit 214 to the arithmetic processing circuit 215. The arithmetic processing circuit 215 processes the image data and generates pixel data for each pixel of the display screen. A drawing processing circuit 216 is connected to the arithmetic processing circuit 215. The drawing processing circuit 216 generates drawing data based on the pixel data. A display device 217 is connected to the drawing processing circuit 216. As the display device 217, for example, a flat panel display such as a liquid crystal display can be used. The display device 217 displays an image on the screen based on the drawing data. The drawing data can be stored in the storage device 218. The terahertz camera 200 can be used as an inspection apparatus based on permeability to paper, plastic, fibers, and other objects, and an absorption spectrum unique to the substance.

  In addition, the terahertz camera 200 can be used for qualitative analysis and quantitative analysis of substances. For such use, for example, a filter having a specific frequency can be disposed on the optical axis 213 of the lens 203. The filter blocks electromagnetic waves other than a specific wavelength. Therefore, only electromagnetic waves having a specific wavelength can reach the photodetector 100. Thus, the presence or amount of a specific substance can be detected.

The electronic apparatus to which the present invention is applied is not limited to the terahertz camera 200 as described above, but can be applied to an infrared camera or the like.
Further, when the circuit device 100 includes an inertial sensor, the circuit device 100 can be applied to a navigation device, an electronic camera, an in-vehicle camera, a motion sensor device, a game machine controller, a robot device, and the like.
Further, when the circuit device 100 includes a physical quantity sensor, it can be applied to an inclinometer, a weight / gravity meter, a flow meter, and the like, and is particularly suitable for a portable electronic device that requires a reduction in size and a high density. .

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 11 ... Semiconductor substrate, 11a ... 1st main surface, 11b ... 2nd main surface, 20 ... Through-hole, 30 ... Element circuit layer, 32 ... Element wiring layer, 50 ... Through electrode, 51 ... Rewiring layer.

Claims (16)

A semiconductor device comprising a semiconductor substrate having a first main surface provided with an element circuit layer and a second main surface opposite to the first main surface,
A through hole penetrating the first main surface and the second main surface;
A through electrode formed inside the through hole and connected to the element wiring layer of the element circuit layer and continuing to the rewiring layer formed on the second main surface;
A gap provided between the inner peripheral surface of the through hole and the through electrode, and between the redistribution layer and the second main surface,
The size of the air gap is the size of the air gap between the redistribution layer and the second main surface> the size of the air gap between the through electrode on the second main surface side and the inner peripheral wall of the through hole. > The size of the gap between the through electrode on the first main surface side and the inner peripheral wall of the through hole,
A semiconductor device characterized by the above. The through electrode has a tapered shape that gradually decreases from the element wiring layer side toward the rewiring layer side;
The semiconductor device according to claim 1. An insulating layer filling the gap between the inner peripheral surface of the through hole and the through electrode is further formed;
The semiconductor device according to claim 1, wherein: The insulating layer is formed between the element wiring layer and a part of the thickness of the semiconductor substrate;
The semiconductor device according to claim 3. Opening a through hole in a semiconductor substrate having a first main surface provided with an element circuit layer and a second main surface opposite to the first main surface;
Forming an insulating layer on the inner peripheral surface of the through hole and the second main surface;
Exposing the element wiring layer on the first main surface side of the element circuit layer in the through hole;
A through-electrode filling the inside of the insulating layer formed on the inner peripheral surface of the through-hole, and a re-extending on the surface of the insulating layer formed in the second main surface, continuous with the through-electrode. A step of forming a wiring layer;
Patterning the rewiring layer into a predetermined shape;
Removing the insulating layer;
A method for manufacturing a semiconductor device, comprising: The thickness of the insulating layer is the thickness between the rewiring layer and the second main surface> the thickness between the through electrode on the second main surface side and the inner peripheral surface of the through hole> the first main The thickness between the through electrode on the surface side and the inner peripheral surface of the through hole,
A method for manufacturing a semiconductor device according to claim 5. In the step of removing the insulating layer,
The removal range of the insulating layer is between the redistribution layer and the second main surface, and a range from the second main surface to a part of the thickness of the semiconductor substrate;
The method for manufacturing a semiconductor device according to claim 5, wherein: In the step of removing the insulating layer,
The removal range of the insulating layer is between the rewiring layer and the second main surface;
The method for manufacturing a semiconductor device according to claim 5, wherein: The insulating layer is SiO ₂ ;
The method for manufacturing a semiconductor device according to claim 5, wherein: A semiconductor substrate having a first main surface on which an element circuit layer is provided, a second main surface opposite to the first main surface, and between the first main surface and the second main surface A through-hole penetrating through and a through-electrode formed inside the through-hole and connected to the element wiring layer of the element circuit layer and continuing to the rewiring layer formed on the surface of the second main surface; A gap provided between the inner peripheral surface of the through hole and the through electrode and between the rewiring layer and the second main surface, and the size of the gap is the rewiring The size of the gap between the layer and the second main surface> The size of the gap between the through electrode on the second main surface side and the inner peripheral wall of the through hole> The through on the first main surface side A semiconductor device in the relationship of the size of the gap between the electrode and the inner peripheral wall of the through hole, and
An electronic device having a wiring layer exposed on a surface facing the second main surface; a connection terminal connecting the rewiring layer and the wiring layer of the electronic device;
A circuit device comprising: Including a step of connecting the rewiring layer of the semiconductor device according to any one of claims 1 to 4 and the wiring layer of an electronic device facing the rewiring layer by a connection terminal;
The method of manufacturing a circuit device according to claim 10. A semiconductor substrate having a first main surface on which an element circuit layer is provided and a second main surface opposite to the first main surface, between the first main surface and the second main surface. A step of opening a through hole; a step of forming an insulating layer on the inner peripheral surface of the through hole and the second main surface;
Exposing the element wiring layer of the element circuit layer in the through hole;
A through electrode filling the inside of the insulating layer formed on the inner peripheral surface of the through hole, and a rewiring layer that is continuous with the through electrode and extends to the surface of the insulating layer formed on the second main surface And a step of forming
Patterning the rewiring layer into a predetermined shape;
A semiconductor device using
Connecting the rewiring layer and the wiring layer of the electronic device facing the rewiring layer by a connection terminal;
Removing the insulating layer after connecting the semiconductor device and the electronic device;
A method for manufacturing a circuit device, comprising: In the step of forming the insulating layer,
The thickness of the insulating layer is such that the thickness between the redistribution layer and the second main surface> the thickness between the through electrode on the second main surface side and the through hole> the side on the first main surface side. The thickness is in a relationship with the through electrode,
The method of manufacturing a circuit device according to claim 12. In the step of removing the insulating layer,
The removal range of the insulating layer is between the redistribution layer and the second main surface, and a range from the second main surface to a part of the thickness of the semiconductor substrate;
14. The method for manufacturing a circuit device according to claim 12 or 13, wherein: In the step of removing the insulating layer,
The removal range of the insulating layer is between the rewiring layer and the second main surface;
14. The method for manufacturing a circuit device according to claim 12 or 13, wherein:   An electronic apparatus comprising the semiconductor device according to claim 1 or the circuit device according to claim 10.

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