JP2001127242A - Semiconductor chip, multi-chip package, semiconductor device, electronic device, and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To surely realize an electrical connection between electrodes of a semiconductor chip to be stacked and a conduction means set in a through hole for interlayer connection, and to join in a case of stacking to form a multi-chip. Realize work efficiently. SOLUTION: Through holes 16 penetrating through a chip substrate are provided above and below a signal input / output electrode pad 20 portion. A corrosion-resistant conductive metal film 28 that is electrically connected to the electrode pad and reaches the opening edge of the through hole is formed. A conductive pin 30 including a head flange 32 joined to the corrosion-resistant conductive metal film 28 and a shaft portion 34 inserted into the through hole and having a tip protruding from the chip back surface is mounted, and the conductive pin is used to form the electrode pad. The semiconductor chip 14 has a conductive path to the semiconductor chip 14 arranged on the back surface of the chip.
A multi-chip package is formed by laminating them, and a semiconductor device and an electronic device using the multi-chip package are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor chip for a multichip package, a multichip package formed by stacking and integrating the semiconductor chips, a semiconductor device manufactured by mounting the multichip package, and an electronic device. The present invention relates to devices and methods for manufacturing them.

[0002]

2. Description of the Related Art In recent years, with the increase in performance and miniaturization of electronic equipment, a plurality of semiconductor chips are arranged in one package to form a multi-chip package (Multi Chip Package), thereby achieving high performance of a semiconductor device. And miniaturization are achieved. The multi-chip package includes a package in which a plurality of semiconductor chips are arranged in a plane and a package in which a plurality of semiconductor chips are stacked in a thickness direction. A multi-chip package in which semiconductor chips are arranged in a plane requires a large mounting area, so that the contribution to miniaturization of electronic devices is small. Therefore, a stacked M in which semiconductor chips are stacked
CP is being actively developed.

As this type of package structure, as disclosed in Japanese Patent No. 2870530, a module in which a semiconductor chip is mounted on an interposer is formed, and these modules are stacked by electrically connecting each other with solder bumps. In general, the structure is as follows. Further, as a configuration example not using an interposer, there is a configuration disclosed in Japanese Patent No. 2871636. In this method, chips are stacked with an insulating resin interposed, holes are formed by irradiating laser on the electrode portions of this stacked body, holes are filled with conductive resin, and the lowermost chip portion is mounted on a printed circuit board by solder bumps. It has such a structure.

[0004]

However, in any of the above cases, since the chip is directly mounted on the motherboard by solder bumps, the difference in the coefficient of thermal expansion between the motherboard and the package due to the thermal expansion due to the temperature cycle of the chip. There is a high possibility of disconnection due to relative displacement. As a countermeasure, it is necessary to fill the resin between the board and the chip package with an underfill to absorb the stress, but it is extremely difficult to perform the underfill after mounting, and this is not a general package. Therefore, as in the former case, the mounting method using the solder bumps can be realized only in the chip size package (CSP) by interposing an interposer and having the same role as the underfill. In the case of the latter package in which the chips are directly bonded, it is still extremely difficult to mount them on a board, and there is a feasibility problem.

[0005] In particular, in the latter type in which the chips are directly joined, a configuration is used in which a conductive resin is injected into the through holes to connect the chip electrodes in each layer. It is difficult to reliably establish an electrical connection with the conductive resin. Particularly, the resin is not properly filled within several tens of μm, which may cause a connection failure.

The present invention has been made in view of the above-mentioned conventional problems, and reliably realizes electrical connection between the electrodes of the semiconductor chips to be stacked and the conducting means provided in the through holes for interlayer connection. It is an object of the present invention to provide a semiconductor chip capable of efficiently performing a bonding operation in the case of stacking to form a multichip, and a multichip package, a semiconductor device, and an electronic device using the semiconductor chip. It is another object of the present invention to provide a semiconductor device and an electronic device with good electrical characteristics, which can reduce a wiring distance when a multichip package is mounted on a motherboard.

[0007]

In order to achieve the above object, a semiconductor chip for a multi-chip package according to the present invention is a semiconductor chip for a multi-chip package on which signal input / output electrode pads are formed, A head having a through-hole vertically penetrating the chip substrate at the electrode pad portion, a corrosion-resistant conductive metal film which is electrically connected to the electrode pad and reaches an opening edge of the through-hole, and a head joined to the conductive metal film; Mounting a conductive pin comprising a shaft portion inserted into the through-hole and the through hole, the tip of which protrudes from the back surface of the chip, and a conductive path to the electrode pad is arranged on the back surface of the chip by the conductive pin. It is a feature. In this case, the corrosion-resistant conductive metal film can be formed of gold or platinum, and the conduction pin can be formed of a tin material. By doing so, the joining portions of the two can be eutectic joined, and the formation of the conductive pin is extremely easy. In addition, an insulation resin may be molded in the through-hole to insulate the conductive pin. Thereby, insulation with the substrate silicon can be ensured.

The multichip package according to the present invention has through-holes vertically penetrating the chip substrate at signal input / output electrode pad portions, and is electrically connected to the electrode pads at an opening edge of the through-hole. A conductive pin having a corrosion-resistant conductive metal film that reaches, a head flange joined to the conductive metal film and a shaft portion that is inserted into the through hole and has a tip protruding from the back surface of the chip is attached,
A plurality of semiconductor chips having conductive paths to the electrode pads arranged on the back surface of the chip are stacked by the conductive pins, and the conductive pins mounted on through holes arranged on a straight line of the stacked semiconductor chips are connected to each other. By doing so, conduction between the common electrode pads of the stacked semiconductor chips is achieved. Also in this case, an insulation resin may be molded in the through-hole to maintain insulation of the conduction pin. Further, an insulating film can be formed on the inner wall surface of the through-hole to maintain insulation. Furthermore, the semiconductor chips may be stacked with an adhesive layer having an electrode pad portion opened between the stacked semiconductor chips. As a result, the bonding of the stacked chips can be made firm.

Further, a semiconductor device according to the present invention includes a semiconductor chip or a multi-chip package configured as described above, and an electronic apparatus according to the present invention includes a semiconductor chip, a multi-chip package, or a semiconductor chip according to the present invention. It is characterized by comprising a device.

In the method of manufacturing a semiconductor chip for a multichip package according to the present invention, a corrosion-resistant conductive metal film is formed on an electrode pad portion of a semiconductor chip to reach an opening edge of a through hole that is to be electrically connected to the electrode pad. After that, a through-hole penetrating the semiconductor chip is formed, and a conduction pin having a head flange joined to the conductive metal film and a shaft portion penetrated through the through-hole is projected from the back surface of the chip. A configuration is adopted in which the shaft portion penetrating through is welded and fixed to the back surface of the chip.

In addition, after forming a corrosion-resistant conductive metal film reaching the opening edge of the through hole that is to be electrically connected to the electrode pad, a through hole penetrating the semiconductor chip is formed in the electrode pad portion of the semiconductor chip. After attaching a conductive pin having a head flange joined to the conductive metal film and a shaft portion passing through the through hole, an insulating resin may be molded into the through hole and cured.

In a method of manufacturing a semiconductor chip for a multi-chip package, a corrosion-resistant conductive metal film is formed on an electrode pad portion of a semiconductor chip so as to reach an opening edge of a through hole to be electrically connected to the electrode pad. Thereafter, a through-hole penetrating the semiconductor chip is formed, an insulating resin is filled in the through-hole, a through-hole penetrating the insulating resin is formed, and then the head is pressed against the corrosion-resistant conductive metal film. It is also possible to adopt a configuration in which a conductive pin having a shaft flange penetrating through the inside of the through-hole is provided. In this case, if the through hole is filled with an insulating resin, the back surface of the semiconductor chip is wrapped to be thinner, whereby a thinner chip is manufactured.

Further, according to a method of manufacturing a semiconductor multi-chip package according to the present invention, semiconductor chips manufactured by any of the above-described methods are stacked so that conductive pins of each electrode pad portion are arranged in a straight line. The common pins of the laminated semiconductor chip are electrically connected by crimping the conductive pins to each other.

Further, according to a method of manufacturing a semiconductor device according to the present invention, a plurality of semiconductor chips manufactured by any of the above-described methods are prepared, and external electrodes arranged in the same arrangement pattern as the electrode pads of the semiconductor chip are provided. The semiconductor chip is aligned and stacked on a motherboard having pads, and conductive pins arranged in a straight line are pressure-bonded to the external electrode pads so that the electrodes are electrically connected and mounted. In this configuration, mounting on the motherboard is performed by pressing a conductive pin projecting from a lower layer of a multi-chip package in which semiconductor chips are stacked and integrated in advance onto external electrode pads, or mounting on the lowermost layer is performed. After the conductive pins of the semiconductor chip are mounted on the external electrode pads by crimping, the required number of semiconductor chips may be sequentially stacked.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, specific embodiments of a semiconductor chip, a multi-chip package, a semiconductor device, an electronic device, and a method of manufacturing the same according to the present invention will be described in detail with reference to the drawings.

FIG. 1 is a schematic diagram of a semiconductor device 12 on which a semiconductor multi-chip package 10 according to the embodiment is mounted. The semiconductor chip 14 constituting the semiconductor multi-chip package 10 is formed by laminating and integrating a plurality of chips (four in the illustrated example). When each chip 14 is configured as a memory element, the power supply line, data line, address line, and chip select electrode can be shared. Therefore, since these chip electrodes can be arranged in common on the chip plane, by stacking the chips 14, the common electrodes are arranged on the same vertical line in the vertical direction, and the upper and lower chip electrodes are electrically connected. Thus, the mounting density can be increased up to the number of stacked chips.

In this embodiment, a through hole 16 is formed in each semiconductor chip 14 having chip electrodes arranged in common, and penetrates vertically through each electrode portion. This is Figure 3
As shown in FIG. 2, an electrode pad 20 made of an aluminum film surrounds a silicon oxide film 22 on a silicon single crystal substrate 18 having a (100) azimuthal plane on which various elements such as a transistor, a resistance element, and a wiring are formed. It is formed to be covered by. The electrode pad 20 is formed in advance as a plane rectangular or circular pad body having a hole opened in the center (FIG. 3A). Silicon single crystal substrate 1
In the state where the silicon oxide film 24 is formed on the back surface of the substrate 8, a laser beam is irradiated toward the center hole of the pad to form a preceding hole 26 that penetrates the center portion of the electrode pad 20 (FIG. 2B). Thereafter, a corrosion-resistant conductive metal film (gold bump) 28 made of gold or platinum is formed on the electrode pad 20 by a sputtering method or the like (FIG. 3C). Then
The diameter of the preceding hole 26 is increased by anisotropic etching (FIG. 4D). At this time, since the electrode pad 20 made of aluminum is protected by the corrosion-resistant conductive metal film 28 formed on the surface, the electrode pad 20 itself is prevented from being corroded. In this anisotropic etching, the etching stops at the azimuthal (111) plane where the silicon single crystal substrate 18 has an inclination angle of 54.7 degrees, and when the etching proceeds further, the plane perpendicular to the substrate surface recedes to the inner part. Then, the corrosion-resistant conductive metal film 28 faces the opening edge of the through hole 16. In the silicon single crystal substrate 18, by adjusting the etching time, first, a straight portion is formed, and when the time further advances, a spindle shape is formed.
The diameter of the spindle-shaped through hole 16 is gradually increased from the end as shown in FIG.
Is formed. A silicon oxide film 29 is formed as necessary on the inner wall surface of the through hole 16 whose diameter has been increased by anisotropic etching. By forming the corrosion-resistant conductive metal film 28 on the electrode pad 20 before the etching process of the through hole 16 in this manner, the corrosion-resistant conductive metal film 28 that is electrically connected to the electrode pad 20 is exposed on the surface, and this is exposed. A state in which the opening edge of the through hole 16 protrudes is obtained.

Since the through-holes 16 are formed in the respective chip electrode pads 20 in this manner, when the semiconductor chips 14 diced from the wafer are aligned and superposed, the through-holes 16 on the common electrode portion are on a vertical line. They will be arranged in a straight line. Therefore, the conductive pins 30 are attached to the through holes 16 of each chip 14, and the signal input / output conductive paths of the electrode pads 20 are led to the back side of the chip, and then a plurality of semiconductor chips 14 are stacked. The multi-chip package 10 can be manufactured.

A configuration example in which the conductive pins 30 are mounted in the through holes 16 of the semiconductor chip 14 will be described with reference to FIG. FIG. 2 is an enlarged sectional view of the through hole 16 of the semiconductor chip 14. As shown in the figure, a through hole 16 is formed in the semiconductor chip 14 by the method shown in FIG. 3, and the silicon oxide film 21 for interlayer insulation and the protective silicon oxide film 24 on the back surface are formed in the opening portions of the through hole 16. As a result, the single crystal silicon substrate 18 is etched so as to be recessed from the opening edges of the silicon oxide films 21 and 24, and as a result, the through hole 16 is formed in a spindle shape. The electrode pad 20 is located outside the opening edge of the through hole 16 by the silicon oxide film 21 in an overhang state. However, the corrosion-resistant conductive metal film 28 provided on the surface layer is It is formed in a state that has rushed to Therefore, even if the conductive pin 30 is mounted in the through hole 16 with a simple T-shaped cross section, the single crystal silicon substrate 18 can be electrically connected to the electrode pad 20 by the openings of the silicon oxide films 21 and 24. The conductive path to the electrode pad 20 can be guided to the back surface of the chip without contact.

For this reason, the conduction pin 30 is formed as follows. That is, a cross section T in which a head flange 32 that can be joined to the corrosion-resistant conductive metal film 28 is provided, and a shaft portion 34 having an outer diameter that can be inserted into the through hole 16 is formed at the center of the head flange 32. It is shaped like a letter. The opening diameter of the through hole 16 is 50-100 μm.
m, so that the shaft portion 34 may be set to a size having a diameter that can be inserted through the through hole opening. The length of the shaft portion 34 is such that the tip 14
The length protrudes from the back surface of. Since the chip thickness in this embodiment is about 500 μm, it is set to be longer. The head flange 32 may be manufactured according to the exposed shape of the corrosion-resistant conductive metal film 28.

FIG. 4 shows a manufacturing process of such a conductive pin 30.
Shown in Although a conductive material having a diameter of 50 to 100 μm is used, aluminum, tungsten, copper, or the like can be used as the conductive material. In this embodiment, a wire 36 made of a tin material is used as a material. This uses a material that is eutectic bonded to the corrosion-resistant conductive metal film 28 formed on the electrode pad 20. In the embodiment, gold is used as the corrosion-resistant conductive metal film 28. The conduction pin 30 is manufactured. In the manufacturing process, the bell wire material is divided into two crimping jigs 38.
And a press device for holding by crimping. This apparatus is provided with a fixed mold 40 composed of a pair of crimping jigs 38 and a movable mold 42 that can be moved toward and away from the fixed mold 40. A material length necessary for forming the head flange 32 is protruded from the swaged portion of the fixed die 40, and the cavity 44 for forming the head flange 32 by crushing the protruding tip by the fixed die 40 is formed in the movable die 4.
2 is formed. The wire 36 is fed by a fixed amount by a wire feeder (FIG. 4 (1)), the crimping jig 38 holds the wire 36 by caulking, and the fixed die 40 feeds out the tip of the wire 36 by a fixed amount. 42 is joined to the fixed mold 40 (FIG. 4 (2)). As a result, the tip of the wire 36 is crushed, and is formed so as to follow the shape of the cavity 44. After the forming process of the head flange 32 is completed, the movable mold 42 is retracted. At this time, the crimping jig 38 is once separated to allow the wire 36 to be pulled out, and the movable mold 42 is adjusted to the retracted state. Then, it is pulled out and moved together with the head flange 32 (FIG. 4 (3)). The negative pressure may be generated through the suction passage 46 provided in the movable mold 42. After this, the cutter 48 along the end face of the fixed mold 40
The shaft portion 34 is separated by using
(4)). In this way, the conductive pins 30 can be manufactured continuously.

The conductive pin 30 can be made of an insulating material. In this case, as shown in FIG. 4 (5), the head flange 32 of the conductive pin 30 and the tip of the shaft portion 34, Alternatively, the whole may be plated with a conductive molten metal such as gold plating (FIG. 4).
(5)).

The conduction pin 30 manufactured as described above is
A head flange 32 mounted in the through hole 16 from the active surface side of the semiconductor chip 14 and formed in a flange shape
Can be conductively joined to the corrosion-resistant conductive metal film 28,
The tip of the shaft portion 34 penetrating the through hole 16 is projected from the back surface of the chip while being held in position by the openings of the silicon oxide layers 21 and 24. At this time, the through-hole 16 is formed by the method shown in FIG.
Never be contacted. Solder welding 50 is performed on the shaft portion 34 of the conductive pin 30 protruding from the back surface of the semiconductor chip 14 to fix the conductive pin 30 in place.

As shown in FIG. 2, the through holes 16 formed in the semiconductor chip 14 are inserted from the active surface side where the electrode pads 20 are formed, from the shaft portion 34 side of the conductive pins 30. Usually one semiconductor chip 14
Has a power supply line and a data / address line, and in this embodiment, there are also terminal electrodes forming a chip select. Therefore, through holes 16 are formed in a number corresponding to the number of the electrode lines. Therefore, as shown in FIG. 5, a multi-handling device 54 having a plurality of robot hands 52 that are arranged corresponding to the arrangement pattern of the electrode pads 20 and that can grip the head flange 32 of the conduction pin 30 is provided. In addition, all the through holes 16 of each semiconductor chip 14 are collectively mounted. Of course, it may be mounted in divided zone units.
Then, the solder may be welded collectively from the back side.

Here, the conduction pin 30 is connected to the through hole 16.
When mounted on the shaft, the shaft portion 34 and the through hole 1
6 is a gap. For this reason, an insulating resin may be molded inside. It is desirable to perform resin molding in order to secure insulation and stably hold the conduction pin 30. In this case, the solder welding 58 to the tip of the shaft portion 34 of the conductive pin 30 penetrating the chip 14 can be omitted.

As described above, the corrosion-resistant conductive metal film 28 that can be electrically connected to the electrode pad 20 of each semiconductor chip 14 is formed so as to reach the opening edge of the planned through hole 16, and then the through hole 16 is formed. After the semiconductor chip 14 having the holes 16 opened and the conductive pins 30 mounted thereon is manufactured, the semiconductor chips 14 are stacked and integrated with each other as shown in FIG. This step will be described with reference to FIG. FIG. 6 omits an insulating layer for simplicity. First, a corrosion-resistant conductive metal film 28 is formed on the semiconductor chip 14 on which the aluminum electrode pads 20 are formed, on the exposed regions of the electrode pads 20. For this, a gold film is formed by sputtering or the like, and is extended to reach the opening of the central hole of the electrode pad 20 (FIG. 6A). A through hole 16 is formed through the center hole (corresponding to the electrode pad 20 of the semiconductor chip 14) of the corrosion-resistant conductive metal film 28 by the method shown in FIG. 3 (FIG. 6 (2)). Through hole 1
6, anisotropic wet etching is performed, but the aluminum electrode pad 20 is protected by the corrosion-resistant conductive metal film 28 on the surface. Multi-handling device 54
(See FIG. 5), conductive pins 30 are attached to through holes 16 provided in each semiconductor chip 14, and their head flanges 32 are pressed to establish conduction with the corrosion-resistant conductive metal film 28 (FIG. 5). 6 (3)). At this time, by forming the corrosion-resistant conductive metal film 28 from a gold material and forming the conduction pin 30 from a tin material, the joint surface between the two becomes eutectic. The tip of the shaft portion 34 of the conductive pin 30 that protrudes from the back surface of the chip through the through hole 16 is solder-welded 50 (see FIG. 2) or, as shown in FIG. The conductive insulating resin 56 is molded (FIG. 6D). Thus, conductive pin 30 is stably held without contacting silicon single crystal substrate 18 in the through hole. A plurality of semiconductor chips 14 that have been subjected to the same processing are stacked and aligned, and are arranged so that the through holes 16 of the common electrode pad 20 are aligned. In this state, the portions of the conductive pins 30 arranged in a straight line are pressurized, and the leading end of the penetrating shaft portion of the upper conductive pin 30 is crushed and connected to the head flange of the lower conductive pin 30 to establish conduction. Thereby, the plurality of semiconductor chips 14
Are manufactured to produce a multi-chip package 10 in which the components are stacked. At this time, if necessary, the semiconductor chips 14 may be integrated with an adhesive layer 57 (see FIG. 1) such as polyimide interposed therebetween.

The multi-chip package 10 is formed by stacking and integrating a plurality of semiconductor chips 14 as described above.
The tip electrode of the conduction pin 30 protrudes from the back surface. The tip electrode of the shaft portion 34 of the conductive pin 30 becomes an external connection terminal 34Fout as a package. Therefore, FIG.
As shown in FIG. 6 (5), the external electrode pads 6 on the motherboard 58 on which the multi-chip package 10 is mounted
0 is connected to the external connection terminal 34Fout. On the motherboard 58 side, external electrode pads 60 are formed in the same arrangement pattern as the electrode pads 20 as common electrodes of the semiconductor chip 14. Therefore, by positioning the multi-chip package 10 with respect to the motherboard 58, the external connection terminals 34F
out and the external electrode pad 60 are aligned. Since the solder balls 62 are mounted on the mother board 58, the external connection terminals 3 are connected to the solder balls 72.
The multichip package 10 can be mounted on the motherboard 58 by abutting and welding the tip of 4Fout.

As described above, the multi-chip package 10 is mounted on the motherboard 58. As described above, the conductive pins 30 having the external connection terminals 34Fout protruding from the package back surface are used as connection terminals to the motherboard 58, and the external connection terminals A space 64 is formed between the package 10 and the motherboard 58 by the length of the protrusion of 34Fout. The space 64 allows the multi-chip package 10
Of motherboard 58
And the stress can be relaxed.

According to such an embodiment, the corrosion-resistant conductive metal film 28 is formed on the electrode pad 20 provided on the semiconductor chip 14 in advance, and this is made to face the opening edge of the through hole 16. In this state, the conductive pins 30 are attached to each of them, so that the conductive pins 30 can guide the conductive path to the electrode pad 20 to the back surface of the chip. At this time, since the corrosion-resistant conductive metal film 28 faces the opening of the through hole with being interposed on the pad, the shape of the conductive pin 30 can have a simple T-shaped cross-sectional shape. The formation of the road is very easy. In particular, when the corrosion-resistant conductive metal film 28 is made of gold and the conductive pins 30 are formed of a tin material, the two become a eutectic bond of gold and tin, and the conductivity can be secured. Such semiconductor chips 14 are aligned and stacked one above the other, and this is
The multi-chip package 10 can be easily manufactured by performing the pressure bonding of the members and by laminating and integrating them with each other. The conductive pins 3 protruding from the back surface of the lower chip as external connection terminals of the package 10
Since 0 is used, the connection wiring distance with the external electrode pad 60 of the motherboard 58 can be set to the shortest.
The external connection terminal 34Fout of the package 10 has a predetermined length, and can be provided with a space 64 when mounted on the motherboard 58.
The thermal stress between the multi-chip package 8 and the multi-chip package 10 can be relaxed, thereby preventing the electrical characteristics from deteriorating.

FIG. 7 shows a manufacturing process when a semiconductor chip 14 is thinned to produce a multichip package and a semiconductor device on which the multichip package is mounted. The corrosion-resistant conductive metal film 28 is formed on the electrode pads 20 of the semiconductor chip 14.
Is formed (FIG. 7 (1)), the through-hole 16 is pierced by the method shown in FIG. 3 (FIG. 7 (2)), and then a thermosetting insulating resin 56 is placed inside the through-hole 16. Fill and cure (FIG. 7 (3)). As a result, the through holes 16 are filled, and the occurrence of cracks due to lapping can be prevented, so that the backside of the semiconductor chip 14 can be wrapped. Therefore, the semiconductor chip 14 is thinned by performing back lapping until the required thickness is obtained (FIG. 7D). Thinned semiconductor chip 14H
The insulating resin 56 of each through hole 16 is irradiated with a laser beam to open a through hole 66 of 50 to 100 μm (FIG. 7 (5)). As a result, the conduction pin 30 can be mounted, and the conduction pin 30 is connected to the multi-handling device 54.
Is mounted on each of the laser through holes 66 of the semiconductor chip 14H at a time (FIG. 7 (6)). Thereafter, as in the embodiment shown in FIG. 6, the plurality of semiconductor chips 14H are stacked and aligned, and the common electrode pads 20 are arranged such that the through holes 16 are aligned. In this state, the portions of the conductive pins 30 arranged in a straight line are pressurized, and the leading end of the penetrating shaft portion of the upper conductive pin 30 is crushed and connected to the head flange of the lower conductive pin 30 to establish conduction. Thereby, the multi-chip package 10 in which the plurality of semiconductor chips 14H are stacked is manufactured. Then, a shaft tip electrode of the conductive pin 30 protruding from the lowermost semiconductor chip 14 with respect to the external electrode 60 of the motherboard 58 on which it is mounted is connected to the external connection terminal 34Fou as a package.
The connection may be made using t (FIG. 7 (7)).

In the case of forming the through holes 66 by the laser, the semiconductor chips 14 to be stacked can be collectively formed in a stacked state. Thereby, the through-holes 66 arranged in a straight line in the state where the conductive pins 30 are chip-aligned are more accurately aligned, and there is an advantage that the rate of occurrence of poor connection between the conductive pins 30 can be reduced.

FIG. 8 shows a circuit board 1000 on which a semiconductor device 1100 according to an embodiment of the present invention is mounted. For the circuit board 1000, an organic substrate such as a glass epoxy substrate is generally used. On the circuit board 1000, a bonding portion made of, for example, copper is formed so as to form a desired circuit. Then, by electrically connecting the bonding portion and the external electrode of the semiconductor device 1100, their electrical continuity is achieved.

Since the mounting area of the semiconductor device 1100 can be reduced to the area for mounting with bare chips, the use of this circuit board 1000 for electronic equipment can reduce the size of the electrical equipment itself. Further, in the same area, more mounting space can be secured, and higher functionality can be achieved.

FIG. 9 shows a notebook personal computer 1200 as an electronic apparatus having the circuit board 1000. The notebook personal computer 1200 has a highly functional circuit board 1000.
, The performance can be improved.

[0035]

As described above, the present invention relates to a semiconductor chip for a multi-chip package in which signal input / output electrode pads are formed, and a multi-chip package in which signal input / output electrode pads are formed. A semiconductor chip for use, having a through-hole vertically penetrating the chip substrate at the electrode pad portion, and having a corrosion-resistant conductive metal film which is conducted to the electrode pad and reaches an opening edge of the through-hole. A conductive pin consisting of a head flange joined to a metal film and a shaft portion inserted into the through hole and having a tip protruding from the back surface of the chip is attached, and the conductive pin connects a conductive path to the electrode pad to the back surface of the chip. A multi-chip package is formed by stacking the semiconductor chips, and a semiconductor device using the multi-chip package. In addition, the electrical connection between the electrodes of the semiconductor chip to be laminated and the conducting means set in the through hole that forms the interlayer connection can be reliably realized through the corrosion-resistant conductive metal film and the conductive pin, and the electronic device can be stacked. In this case, the effect of efficiently realizing the joining operation when forming a multi-chip is obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device mounted with a multi-chip package in which semiconductor chips according to an embodiment are stacked.

FIG. 2 is an enlarged sectional view of a through-hole portion of the semiconductor chip according to the embodiment.

FIG. 3 is an explanatory diagram of a step of forming a through hole in a semiconductor chip.

FIG. 4 is a manufacturing process diagram of a conduction pin.

FIG. 5 is an explanatory diagram showing an example of mounting conductive pins.

FIG. 6 is an explanatory diagram showing steps of a method for manufacturing a multi-package according to the embodiment.

FIG. 7 is an explanatory view showing steps of a method for manufacturing a multi-package according to another embodiment.

FIG. 8 is an explanatory diagram of an application example of the multichip package according to the embodiment to a circuit board.

FIG. 9 is an explanatory diagram of an application example of the multichip package according to the embodiment to an electronic device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Semiconductor multi-package 12 Semiconductor device 14 Semiconductor chip (memory chip) 16 Through hole 18 Silicon single crystal substrate 20 Electrode pad (chip electrode) 21 Silicon oxide film for interlayer insulation 22, 24 Silicon oxide film 26 Lead hole 28 Corrosion-resistant conductive metal film (Gold Bump) 30 Conducting Pin 32 Head Flange 34 Shaft 36 Wire 38 Crimping Jig 40 Fixed 42 Movable 44 Cavity 46 Suction Path 48 Cutter 50 Solder Welding 52 Robot Hand 54 Multi-Handling Device 56 Insulating Resin 57 Adhesive Layer 58 Motherboard 60 External electrode pad 62 Solder ball 64 Void 66 Laser through hole

Claims (16)

[Claims] 1. A semiconductor chip for a multi-chip package in which signal input / output electrode pads are formed, wherein said electrode pads have through holes vertically penetrating a chip substrate at upper and lower sides, and are electrically connected to said electrode pads. A conductive pin having a corrosion-resistant conductive metal film reaching the opening edge of the through hole, and a head flange joined to the conductive metal film and a shaft portion inserted into the through hole and having a tip protruding from the back surface of the chip. Wherein a conductive path to the electrode pad is arranged on the back surface of the chip by the conductive pin. 2. The semiconductor chip for a multi-chip package according to claim 1, wherein said corrosion-resistant conductive metal film is formed of gold or platinum, and said conductive pins are formed of a tin material. 3. The semiconductor chip for a multi-chip package according to claim 1, wherein an insulating resin is molded in the through-hole to keep the conductive pins insulated. 4. An electrode pad portion for signal input / output has through holes vertically penetrating the chip substrate, and a corrosion-resistant conductive metal film which is conducted to the electrode pads and reaches an opening edge of the through hole. Then, a conductive pin including a head flange joined to the conductive metal film and a shaft portion inserted into the through hole and having a tip protruding from the back surface of the chip is mounted, and a conductive path to the electrode pad is provided by the conductive pin. A plurality of semiconductor chips arranged on the back side of the chip are stacked, and the conductive pins mounted in through holes arranged on a straight line of the stacked semiconductor chips are connected to each other to connect the conductive pins to each other, so that the stacked semiconductor chips have a common property. A multi-chip package characterized by conduction between electrode pads. 5. The semiconductor device according to claim 4, wherein an insulating film is formed on an inner wall surface of the through hole, or an insulating resin is molded in the through hole to insulate and hold the conductive pin and the chip substrate silicon. A multi-chip package according to item 1. 6. The multi-chip package according to claim 4, wherein the semiconductor chips are stacked with an adhesive layer having an electrode pad portion opened between the stacked semiconductor chips. 7. A semiconductor device comprising the semiconductor chip or the multi-chip package according to claim 1. 8. The semiconductor chip according to claim 1, wherein:
An electronic device comprising a multichip package or a semiconductor device. 9. After forming a corrosion-resistant conductive metal film that reaches an opening edge of a through hole that is to be electrically connected to the electrode pad, a through hole penetrating the semiconductor chip is formed in an electrode pad portion of the semiconductor chip. After projecting a conduction pin having a shaft portion penetrating through the through-hole and a head flange joined to the conductive metal film from the back surface of the chip, the shaft portion penetrating through the through-hole is welded and fixed to the back surface of the chip. A method for manufacturing a semiconductor chip for a multi-chip package, comprising: 10. After forming a corrosion-resistant conductive metal film on an electrode pad portion of a semiconductor chip to reach an opening edge of a through hole to be electrically connected to the electrode pad,
After forming a through hole penetrating the semiconductor chip, mounting a conductive pin having a head flange joined to the conductive metal film and a shaft portion penetrating the through hole, molding an insulating resin in the through hole. And producing a semiconductor chip for a multi-chip package. 11. After forming a corrosion-resistant conductive metal film on an electrode pad portion of a semiconductor chip to reach an opening edge of a through hole that is to be electrically connected to the electrode pad,
After forming a through hole penetrating the semiconductor chip, filling the through hole with an insulating resin, forming a through hole penetrating the insulating resin, and then crimping the head flange to the corrosion-resistant conductive metal film. And a conductive pin having a shaft portion penetrated inside the through hole. 12. The method for manufacturing a semiconductor chip for a multi-chip package according to claim 11, wherein after filling the through hole with the insulating resin, the back surface of the semiconductor chip is wrapped to be thinned. 13. The semiconductor chips manufactured by the method according to claim 9 are stacked such that the shaft portions of the respective conductive pins are arranged in a straight line, and the conductive pins are press-bonded to each other. A method of manufacturing a semiconductor multi-chip package, characterized in that a common electrode portion of a semiconductor chip is conducted. 14. A motherboard having a plurality of semiconductor chips manufactured by the method according to claim 9 and having external electrode pads arranged in the same arrangement pattern as the electrode pads of the semiconductor chips. A method of manufacturing a semiconductor device, comprising: aligning and stacking the semiconductor chips; and bonding conductive pins arranged in a straight line to the external electrode pads so that the electrodes are electrically connected and mounted. 15. The semiconductor according to claim 14, wherein the mounting on the motherboard is performed by pressing a conductive pin projecting from a lower layer of a multi-chip package in which semiconductor chips are stacked and integrated in advance on an external electrode pad. Device manufacturing method. 16. The semiconductor device according to claim 14, wherein a necessary number of semiconductor chips are sequentially stacked on the motherboard after the conductive pins of the lowermost semiconductor chip are mounted on the external electrode pads by pressure bonding. Of manufacturing a semiconductor device.