JP7020981B2 - Semiconductor device - Google Patents

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JP7020981B2
JP7020981B2 JP2018068043A JP2018068043A JP7020981B2 JP 7020981 B2 JP7020981 B2 JP 7020981B2 JP 2018068043 A JP2018068043 A JP 2018068043A JP 2018068043 A JP2018068043 A JP 2018068043A JP 7020981 B2 JP7020981 B2 JP 7020981B2
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wiring
power supply
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semiconductor device
mos transistor
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JP2019179840A (en
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健司 大貫
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Lapis Semiconductor Co Ltd
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Lapis Semiconductor Co Ltd
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Description

本発明は、半導体装置に関する。 The present invention relates to a semiconductor device.

従来、半導体装置１０Ｃの電源配線１４は、図３に示すように、行方向に複数の電源線と、列方向に複数の電源線とを備え、メッシュ状に配線されている。電源配線１４には、電源パッド１２と、複数の回路１６、１８とが接続されている（特許文献１）。このように電源配線１４がメッシュ状に配線されていると、ある特定の回路１６の動作によってノイズが発生すると、発生したノイズは、回路１６が接続される電源線１４Ａに伝播する。電源線１４Ａにノイズが伝搬すると、このノイズは、電源線１４Ａに接続される他の電源線１４Ｂを介して、他の電源線１４Ｂに接続され且つノイズを発生させた回路１６の付近に位置する他の回路１８に伝搬し、回路１８に誤動作を引き起こす場合がある。 Conventionally, as shown in FIG. 3, the power supply wiring 14 of the semiconductor device 10C includes a plurality of power supply lines in the row direction and a plurality of power supply lines in the column direction, and is wired in a mesh shape. A power supply pad 12 and a plurality of circuits 16 and 18 are connected to the power supply wiring 14 (Patent Document 1). When the power supply wiring 14 is wired in a mesh shape in this way, when noise is generated by the operation of a specific circuit 16, the generated noise propagates to the power supply line 14A to which the circuit 16 is connected. When noise propagates to the power supply line 14A, this noise is located in the vicinity of the circuit 16 connected to the other power supply line 14B and generating noise via the other power supply line 14B connected to the power supply line 14A. It may propagate to another circuit 18 and cause a malfunction in the circuit 18.

また、従来、図４に示すように、図３と同様に、メッシュ状に配線されている半導体装置１０Ｄの電源配線１４に接続される回路が、ｎ型ＭＯＳトランジスタ（ＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ－Ｆｉｅｌｄ－Ｅｆｅｃｔ－Ｔｒａｎｓｉｓｔｏｒ）２６の場合がある。ｎ型ＭＯＳトランジスタ２６にノイズが発生すると、発生したノイズは、電源線１４Ａ、１４Ｂ及び基板を経由して、他の回路１８に伝搬し、回路１８に誤動作を引き起こす場合がある。 Further, as shown in FIG. 4, conventionally, as in FIG. 3, the circuit connected to the power supply wiring 14 of the semiconductor device 10D, which is wired in a mesh shape, is an n-type MOS transistor (MOSFET (Metal-Oxide-Semiconductor ductor). -Field-Efect-Transistor) 26. When noise is generated in the n-type MOS transistor 26, the generated noise propagates to the other circuit 18 via the power supply lines 14A and 14B and the substrate, and the circuit 18 may cause a malfunction.

ところで、このようなノイズの伝搬を防止するため、配線を基板に直接接続させない発明（特許文献２）や、電源線と接地線とを分離する発明（特許文献３）が提案されている。 By the way, in order to prevent such noise propagation, an invention in which wiring is not directly connected to a substrate (Patent Document 2) and an invention in which a power supply line and a ground line are separated (Patent Document 3) have been proposed.

特開２００４－２６０２１８号公報Japanese Unexamined Patent Publication No. 2004-260218 特開平５－２５９３９２号公報Japanese Unexamined Patent Publication No. 5-259392 特開平７－７４２５９号公報Japanese Unexamined Patent Publication No. 7-74259

しかし、これらの発明（特許文献２、３）であっても、ノイズを発生させる回路１６、２６と、他の回路１８とが、電源線１４Ａ、１４Ｂにより接続されているので、ノイズは、電源線１４Ａ、１４Ｂを介して他の回路１８に伝搬する。 However, even in these inventions (Patent Documents 2 and 3), since the circuits 16 and 26 that generate noise and the other circuits 18 are connected by the power lines 14A and 14B, the noise is a power source. It propagates to another circuit 18 via the lines 14A and 14B.

本開示は、上記した点に鑑みてなされたものであり、ある回路で発生したノイズが他の回路に伝搬することを低減することができる半導体装置を提供することを目的とする。 The present disclosure has been made in view of the above points, and an object of the present invention is to provide a semiconductor device capable of reducing noise generated in one circuit from propagating to another circuit.

本開示の第１の態様の半導体装置は、ノイズの発生の要因となる第１の回路と、前記第１の回路の周辺に設けられた第２の回路と、一端が前記第１の回路と接続され且つ前記一端より他端の位置が前記第２の回路から遠ざかる位置に配設されると共に前記第２の回路とは接続されない第１の配線と、前記第１の配線の前記他端と、第２の配線を介して、接続される電源パッドと、を備える。 The semiconductor device of the first aspect of the present disclosure includes a first circuit that causes noise, a second circuit provided around the first circuit, and one end of the first circuit. The first wiring that is connected and the position of the other end from the one end is arranged at a position away from the second circuit and is not connected to the second circuit, and the other end of the first wiring. , A power pad, which is connected via a second wire.

本開示の第２の態様の半導体装置では、第１の態様において、前記電源パッドは、前記第２の配線に接続され、前記第１の配線の前記他端は、前記第２の配線における前記電源パッドが接続される部分の近傍に接続される。 In the semiconductor device of the second aspect of the present disclosure, in the first aspect, the power supply pad is connected to the second wiring, and the other end of the first wiring is the said in the second wiring. It is connected near the part where the power pad is connected.

本開示の第３の態様の半導体装置では、第２の態様において、前記第２の配線は、複数の線がメッシュ状に配線され且つ前記線が交差する交差点を有し、前記第１の配線の前記他端が前記第２の配線に接続される接続部分と前記交差点との距離は、前記接続部分と前記第２の配線における前記電源パッドが接続される部分との距離より長い。 In the semiconductor device of the third aspect of the present disclosure, in the second aspect, the second wiring has a plurality of lines wired in a mesh shape and has an intersection where the lines intersect, and the first wiring. The distance between the connection portion where the other end is connected to the second wiring and the intersection is longer than the distance between the connection portion and the portion of the second wiring to which the power supply pad is connected.

本開示の第４の態様の半導体装置では、第１の態様～第３の態様に何れかにおいて、前記電源パッドを複数備え、前記第１の配線の前記他端は、前記第２の配線を介して、前記複数の電源パッドの中で、前記第１の回路に最も近い位置に位置する電源パッドに接続される。 In the semiconductor device of the fourth aspect of the present disclosure, in any one of the first to third aspects, the power supply pad is provided in plurality, and the other end of the first wiring has the second wiring. It is connected to the power supply pad located at the position closest to the first circuit among the plurality of power supply pads.

本開示の第５の態様の半導体装置では、第１の態様～第４の態様に何れかにおいて、前記第１の回路は、ｎ型ＭＯＳトランジスタ又はｐ型ＭＯＳトランジスタであり、前記第１の配線の一端は、前記ｎ型ＭＯＳトランジスタのソース又は前記ｐ型ＭＯＳトランジスタのソースに接続される。 In the semiconductor device of the fifth aspect of the present disclosure, in any one of the first to fourth aspects, the first circuit is an n-type MOS transistor or a p-type MOS transistor, and the first wiring. One end of is connected to the source of the n-type MOS transistor or the source of the p-type MOS transistor.

本開示の第６の態様の半導体装置では、第５の態様において、前記第１の回路を複数備え、前記複数の第１の回路の各々は、ｎ型ＭＯＳトランジスタ又はｐ型ＭＯＳトランジスタである。 In the semiconductor device of the sixth aspect of the present disclosure, in the fifth aspect, the plurality of the first circuits are provided, and each of the plurality of first circuits is an n-type MOS transistor or a p-type MOS transistor.

本開示の第７の態様の半導体装置では、第１の態様～第６の態様に何れかにおいて、前記第１の回路は、前記第２の配線には接続されない。 In the semiconductor device of the seventh aspect of the present disclosure, in any one of the first to sixth aspects, the first circuit is not connected to the second wiring.

本開示の第８の態様の半導体装置では、第１の態様～第７の態様に何れかにおいて、前記第２の配線は、電源用の配線であり、前記第２の回路は、電源用に前記第２の配線にのみ直接接続され、前記第１の回路は、電源用に前記第１の配線にのみ直接接続される。 In the semiconductor device of the eighth aspect of the present disclosure, in any one of the first to seventh aspects, the second wiring is wiring for a power supply, and the second circuit is for a power supply. Directly connected only to the second wire, the first circuit is directly connected only to the first wire for power.

本開示によれば、ある回路で発生したノイズが他の回路に伝搬することを低減することができる。 According to the present disclosure, it is possible to reduce the noise generated in one circuit from propagating to another circuit.

第１実施形態の半導体装置の構成の一例を示す図である。It is a figure which shows an example of the structure of the semiconductor device of 1st Embodiment. 第２実施形態の半導体装置の構成の一例を示す図である。It is a figure which shows an example of the structure of the semiconductor device of 2nd Embodiment. 従来技術の半導体装置の構成を示す図である。It is a figure which shows the structure of the semiconductor device of the prior art. 従来技術の半導体装置の構成を示す図である。It is a figure which shows the structure of the semiconductor device of the prior art.

以下、開示の技術の実施形態の一例を図面を参照しつつ説明する。なお、各図面において同一または等価な構成要素及び部分には同一の参照符号を付与し、重複する説明は適宜省略する。 Hereinafter, an example of the disclosed technology will be described with reference to the drawings. The same reference numerals are given to the same or equivalent components and parts in each drawing, and duplicate description will be omitted as appropriate.

［第１実施形態］
図１には、第１の実施の形態の半導体装置（チップ）１０Ａが示されている。図１に示すように、半導体装置１０Ａの電源配線１４は、図３と同様に、行方向に複数の電源線と、列方向に複数の電源線とを備え、メッシュ状に配線されている。電源配線１４には、電源（ｖｓｓ）パッド１２と、複数の回路１６、１８とが接続されている。 [First Embodiment]
FIG. 1 shows the semiconductor device (chip) 10A of the first embodiment. As shown in FIG. 1, the power supply wiring 14 of the semiconductor device 10A includes a plurality of power supply lines in the row direction and a plurality of power supply lines in the column direction, and is wired in a mesh shape, as in FIG. A power supply (vss) pad 12 and a plurality of circuits 16 and 18 are connected to the power supply wiring 14.

所定の試験などにより、回路１６は、その動作によってノイズを発生させる回路であると発見されたとする。回路１６は、ノイズの発生の要因となる回路である。回路１８は、回路１６の周辺に設けられている。 It is assumed that the circuit 16 is found to be a circuit that generates noise by its operation by a predetermined test or the like. The circuit 16 is a circuit that causes noise to be generated. The circuit 18 is provided around the circuit 16.

回路１６からノイズが、電源線１４Ａ、１４Ｂにより、回路１８に伝搬しないようにするため、第１の実施の形態では、回路１６を、電源線１４Ａから切り離すことにより、メッシュ状に配線されている電源配線１４から切り離す。そして、電源パッド１２の近傍から分離させた電源線２０を、回路１６の専用の電源線として、回路１６に直結させる。つまり、電源線２０を他の回路１８には直接繋がない。 In order to prevent noise from the circuit 16 from propagating to the circuit 18 by the power lines 14A and 14B, in the first embodiment, the circuit 16 is wired in a mesh shape by being separated from the power line 14A. Disconnect from the power supply wiring 14. Then, the power supply line 20 separated from the vicinity of the power supply pad 12 is directly connected to the circuit 16 as a dedicated power supply line for the circuit 16. That is, the power line 20 is not directly connected to the other circuit 18.

より詳細には、電源線２０の一端４０は、回路１６と接続され且つ一端４０より他端４４の位置が回路１８から遠ざかる位置に配設されると共に回路１８とは接続されない。電源線２０の他端４４は、電源配線１４を介して、電源パッド１２に接続されている。電源パッド１２は、電源配線１４に接続され、電源線２０の他端４４は、電源配線１４における電源パッド１２が接続される部分４２の近傍に接続される。 More specifically, one end 40 of the power line 20 is connected to the circuit 16 and the position of the other end 44 from the one end 40 is arranged at a position away from the circuit 18 and is not connected to the circuit 18. The other end 44 of the power supply line 20 is connected to the power supply pad 12 via the power supply wiring 14. The power pad 12 is connected to the power supply wiring 14, and the other end 44 of the power supply line 20 is connected in the vicinity of the portion 42 to which the power supply pad 12 is connected in the power supply wiring 14.

半導体装置１０Ａの電源配線１４は、上記のようにメッシュ状に配線され、電源線が交差する複数の交差点４６を有する。電源線２０の他端４４が電源配線１４に接続される接続部分と、複数の交差点４６の中で最も電源パッド１２に近い交差点４６との距離Ｌ２は、電源線２０の他端４４が電源配線１４に接続される接続部分と、電源配線１４における電源パッド１２が接続される部分４２との距離Ｌ１より長い。 The power supply wiring 14 of the semiconductor device 10A is wired in a mesh shape as described above, and has a plurality of intersections 46 where the power supply lines intersect. The distance L2 between the connection portion where the other end 44 of the power supply line 20 is connected to the power supply wiring 14 and the intersection 46 closest to the power supply pad 12 among the plurality of intersections 46 is such that the other end 44 of the power supply line 20 is the power supply wiring. The distance between the connection portion connected to 14 and the portion 42 to which the power pad 12 in the power supply wiring 14 is connected is longer than the distance L1.

上記のように、回路１６は、回路１８が直接接続される電源線１４Ａ、１４Ｂには直接接続されない。詳細には、電源配線１４は、電源用の配線であり、回路１８は、電源用に電源配線１４にのみ直接接続される。回路１６は、電源用に電源線２０にのみ直接接続される。 As described above, the circuit 16 is not directly connected to the power lines 14A and 14B to which the circuit 18 is directly connected. Specifically, the power supply wiring 14 is wiring for power supply, and the circuit 18 is directly connected only to the power supply wiring 14 for power supply. The circuit 16 is directly connected only to the power line 20 for power.

このように、ノイズを発生させる回路１６の専用の電源線２０は他の回路１８等には直接接続されないので、回路１６により発生したノイズが回路１８に伝搬することを低減することができる。 As described above, since the dedicated power supply line 20 of the circuit 16 that generates noise is not directly connected to the other circuit 18 or the like, it is possible to reduce the noise generated by the circuit 16 from propagating to the circuit 18.

［第２実施形態］
次に、第２の実施の形態を説明する。 [Second Embodiment]
Next, a second embodiment will be described.

図２には、第２の実施の形態の半導体装置１０Ｂが示されている。図２の半導体装置１０Ｂの構成は、図１の半導体装置１０Ａと同様の構成であるので、同一部分には同一の符号を伏して、その部分の説明を省略し、異なる部分のみを説明する。 FIG. 2 shows the semiconductor device 10B of the second embodiment. Since the configuration of the semiconductor device 10B of FIG. 2 is the same as that of the semiconductor device 10A of FIG. 1, the same reference numerals are given to the same parts, the description of the parts is omitted, and only the different parts will be described.

図２に示すように、半導体装置１０Ｂは、図４と同様に、メッシュ状に配線されている電源配線１４に、ｎ型ＭＯＳトランジスタ２６のソースが接続される。ｎ型ＭＯＳトランジスタ２６がノイズを発生させるとする。 As shown in FIG. 2, in the semiconductor device 10B, the source of the n-type MOS transistor 26 is connected to the power supply wiring 14 which is wired in a mesh shape as in FIG. It is assumed that the n-type MOS transistor 26 generates noise.

ｎ型ＭＯＳトランジスタ２６により発生したノイズが電源線１４Ａ、１４Ｂ及び基板から回路１８に伝搬しないようにするため、第２の実施の形態では、ｎ型ＭＯＳトランジスタ２６のソースを、電源線１４Ａから切り離す。そして、電源パッド１２の近傍から分離させた電源線３０を、ｎ型ＭＯＳトランジスタ２６の専用の電源線として、ｎ型ＭＯＳトランジスタ２６のソースに直結させる。つまり、ｎ型ＭＯＳトランジスタ２６のソースは、電源線３０のみに直接接続し、他の回路１８には直接接続されていない。 In the second embodiment, the source of the n-type MOS transistor 26 is separated from the power supply line 14A so that the noise generated by the n-type MOS transistor 26 does not propagate from the power supply lines 14A and 14B and the substrate to the circuit 18. .. Then, the power supply line 30 separated from the vicinity of the power supply pad 12 is directly connected to the source of the n-type MOS transistor 26 as a dedicated power supply line for the n-type MOS transistor 26. That is, the source of the n-type MOS transistor 26 is directly connected only to the power supply line 30, and is not directly connected to the other circuits 18.

半導体装置１０Ｂの電源配線１４は、上記のようにメッシュ状に配線され、電源線が交差する複数の交差点４６を有する。電源線３０の他端４４が電源配線１４に接続される接続部分と、複数の交差点４６の中で最も電源パッド１２に近い交差点４６との距離Ｌ２２は、電源線３０の他端４４が電源配線１４に接続される接続部分と、電源配線１４における電源パッド１２が接続される部分４２との距離Ｌ１１より長い。 The power supply wiring 14 of the semiconductor device 10B is wired in a mesh shape as described above, and has a plurality of intersections 46 where the power supply lines intersect. The distance L22 between the connection portion where the other end 44 of the power supply line 30 is connected to the power supply wiring 14 and the intersection 46 closest to the power supply pad 12 among the plurality of intersections 46 is such that the other end 44 of the power supply line 30 is the power supply wiring. The distance between the connection portion connected to 14 and the portion 42 to which the power pad 12 in the power supply wiring 14 is connected is longer than the distance L11.

上記のように、型ＭＯＳトランジスタ２６は、回路１８が直接接続される電源配線１４には直接接続されない。詳細には、電源配線１４は、電源用の配線であり、回路１８は、電源用に電源配線１４にのみ直接接続される。ｎ型ＭＯＳトランジスタ２６のソースは、電源用に電源線３０にのみ直接接続される。 As described above, the type MOS transistor 26 is not directly connected to the power supply wiring 14 to which the circuit 18 is directly connected. Specifically, the power supply wiring 14 is wiring for power supply, and the circuit 18 is directly connected only to the power supply wiring 14 for power supply. The source of the n-type MOS transistor 26 is directly connected only to the power line 30 for power supply.

このように、ノイズを発生させるｎ型ＭＯＳトランジスタ２６のソースの専用の電源線３０は他の回路１８に直接繋がないので、ｎ型ＭＯＳトランジスタ２６により発生したノイズが電源線１４Ａ、１４Ｂを介して回路１８に伝搬することを低減することができる。特に、ｎ型ＭＯＳトランジスタ２６のソースを電源線３０に接続するので、ソースから基板へのノイズの回り込み経路を遮断することができるので、ノイズが基板を経由して回路１８に伝搬することを低減することができる。 As described above, since the dedicated power supply line 30 of the source of the n-type MOS transistor 26 that generates noise is not directly connected to the other circuit 18, the noise generated by the n-type MOS transistor 26 passes through the power supply lines 14A and 14B. Propagation to the circuit 18 can be reduced. In particular, since the source of the n-type MOS transistor 26 is connected to the power supply line 30, the noise wraparound path from the source to the board can be blocked, so that the noise propagates to the circuit 18 via the board is reduced. can do.

［変形例］
（第１の変形例）
第２の実施の形態では、ｎ型ＭＯＳトランジスタ２６がノイズを発生させる。本開示の技術は、ｎ型ＭＯＳトランジスタ２６に限定されず、ｐ型ＭＯＳトランジスタであっても、第２の実施の形態と同様に、ｐ型ＭＯＳトランジスタのソースを、電源(vcc)パッド１２の近傍から分離させた電源線３０に直結させる。 [Modification example]
(First modification)
In the second embodiment, the n-type MOS transistor 26 generates noise. The technique of the present disclosure is not limited to the n-type MOS transistor 26, and even if it is a p-type MOS transistor, the source of the p-type MOS transistor is used in the power supply (vcc) pad 12 as in the second embodiment. It is directly connected to the power supply line 30 separated from the vicinity.

第１の変形例でも、第２の実施の形態と同様に、ノイズが基板（Ｎ ｗｅｌｌ）を経由して回路１８に伝搬することを低減することができる。 Also in the first modification, as in the second embodiment, it is possible to reduce the noise propagating to the circuit 18 via the substrate (N well).

（第２の変形例）
第２の実施の形態では、ｎ型ＭＯＳトランジスタ２６が、第１の変形例では、ｐ型ＭＯＳトランジスタが、ノイズを発生させる。本開示の技術は、これらに限定されない。例えば、本開示の技術は、半導体装置に、少なくとも１つのｎ型ＭＯＳトランジスタ２６及び少なくとも１つのｐ型ＭＯＳトランジスタを備える場合にも、適用することができる。この場合には、ｎ型ＭＯＳトランジスタ２６及びｐ型ＭＯＳトランジスタの各々のソースを、電源パッド１２の近傍から分離させた電源線に直結させる。この場合、ｎ型ＭＯＳトランジスタ２６のソースを、電源(vss/vcc)パッド１２の近傍から分離させた第１の電源線に直結させ、ｐ型ＭＯＳトランジスタのソースを、電源パッド１２の近傍から分離させた第２の電源線に直結させるようにしてもよい。ここで、第１の電源線と第２の電源線とは接続されていなくともいいが、第１の電源線及び第２の電源線の一方が他方に接続したり、第１の電源線及び第２の電源線が、電源パッド１２の近傍から分離させた第３の電源線に接続したりしてもよい。なお、第１の電源線～第３の電源線は、回路１８には直接接続しない。 (Second modification)
In the second embodiment, the n-type MOS transistor 26 generates noise, and in the first modification, the p-type MOS transistor generates noise. The techniques of the present disclosure are not limited to these. For example, the technique of the present disclosure can also be applied when the semiconductor device includes at least one n-type MOS transistor 26 and at least one p-type MOS transistor. In this case, the sources of the n-type MOS transistor 26 and the p-type MOS transistor are directly connected to the power supply line separated from the vicinity of the power supply pad 12. In this case, the source of the n-type MOS transistor 26 is directly connected to the first power supply line separated from the vicinity of the power supply (vss / vcc) pad 12, and the source of the p-type MOS transistor is separated from the vicinity of the power supply pad 12. It may be directly connected to the second power line. Here, the first power line and the second power line do not have to be connected, but one of the first power line and the second power line may be connected to the other, or the first power line and the first power line and the like. The second power line may be connected to a third power line separated from the vicinity of the power pad 12. The first power line to the third power line are not directly connected to the circuit 18.

（第３の変形例）
第１の実施の形態、第２の実施の形態、第１の変形例、及び第２の変形例は、１つの電源パッド１２を備える。本開示の技術は、これらに限定されない。例えば、本開示の技術は、半導体装置に電源パッドを複数備える場合にも適用できる。この場合、電源線２０又は電源線３０の他端は、複数の電源パッドの中で、回路１６又はｎ型ＭＯＳトランジスタ２６（又はｐ型ＭＯＳトランジスタ）に最も近い位置に位置する電源パッドが電源線に接続する部分の近傍に接続されるようにしてもよい。 (Third modification example)
The first embodiment, the second embodiment, the first modification, and the second modification include one power supply pad 12. The techniques of the present disclosure are not limited to these. For example, the technique of the present disclosure can be applied to a case where a semiconductor device is provided with a plurality of power supply pads. In this case, at the other end of the power supply line 20 or the power supply line 30, the power supply pad located at the position closest to the circuit 16 or the n-type MOS transistor 26 (or p-type MOS transistor) among the plurality of power supply pads is the power supply line. It may be connected in the vicinity of the portion connected to.

１０Ａ、１０Ｂ、１０Ｃ、１０Ｄ 半導体装置
１２ 電源パッド
１４ 電源配線
１４Ａ 電源線
１４Ｂ 電源線
１６ 回路
１８ 回路
２０ 電源線
２６ ｎ型ＭＯＳトランジスタ２６
３０ 電源線
４０ 一端
４４ 他端
４６ 交差点 10A, 10B, 10C, 10D Semiconductor device 12 Power pad 14 Power wiring 14A Power line 14B Power line 16 Circuit 18 Circuit 20 Power line 26 n-type MOS transistor 26
30 Power line 40 One end 44 The other end 46 Intersection

Claims (8)

ノイズの発生の要因となる第１の回路と、
前記第１の回路の周辺に設けられた第２の回路と、
一端が前記第１の回路と接続され且つ前記一端より他端の位置が前記第２の回路から遠ざかる位置に配設されると共に前記第２の回路とは接続されない第１の配線と、
前記第１の配線の前記他端と、複数の線がメッシュ状に配線された第２の配線を介して、接続される電源パッドと、
を備え、
前記第１の回路は、前記複数の線がメッシュ状に配線された第２の配線から切り離されている
半導体装置。 The first circuit that causes noise,
The second circuit provided around the first circuit and
A first wiring in which one end is connected to the first circuit and the position of the other end from the one end is arranged at a position away from the second circuit and is not connected to the second circuit.
A power pad connected to the other end of the first wiring and a second wiring in which a plurality of wires are wired in a mesh shape .
Equipped with
The first circuit is separated from the second wiring in which the plurality of wires are wired in a mesh shape.
Semiconductor device. 前記電源パッドは、前記第２の配線に接続され、
前記第１の配線の前記他端は、前記第２の配線における前記電源パッドが接続される部分の近傍に接続される、
請求項１に記載の半導体装置。 The power pad is connected to the second wiring and is connected to the second wiring.
The other end of the first wire is connected in the vicinity of the portion of the second wire to which the power pad is connected.
The semiconductor device according to claim 1. 前記第２の配線は、前記線が交差する交差点を有し、
前記第１の配線の前記他端が前記第２の配線に接続される接続部分と前記交差点との距離は、前記接続部分と前記第２の配線における前記電源パッドが接続される部分との距離より長い、
請求項２に記載の半導体装置。 The second wiring has an intersection where the lines intersect.
The distance between the connection portion where the other end of the first wiring is connected to the second wiring and the intersection is the distance between the connection portion and the portion of the second wiring to which the power supply pad is connected. Longer,
The semiconductor device according to claim 2. 前記電源パッドを複数備え、
前記第１の配線の前記他端は、前記第２の配線を介して、前記複数の電源パッドの中で、前記第１の回路に最も近い位置に位置する電源パッドに接続される、
請求項１～請求項３の何れか１項に記載の半導体装置。 Equipped with multiple power pads
The other end of the first wiring is connected to the power supply pad located closest to the first circuit among the plurality of power supply pads via the second wiring.
The semiconductor device according to any one of claims 1 to 3. 前記第１の回路は、ｎ型ＭＯＳトランジスタ又はｐ型ＭＯＳトランジスタであり、
前記第１の配線の一端は、前記ｎ型ＭＯＳトランジスタのソース又は前記ｐ型ＭＯＳトランジスタのソースに接続される、
請求項１～請求項４の何れか１項に記載の半導体装置。 The first circuit is an n-type MOS transistor or a p-type MOS transistor.
One end of the first wiring is connected to the source of the n-type MOS transistor or the source of the p-type MOS transistor.
The semiconductor device according to any one of claims 1 to 4. 前記第１の回路を複数備え、
前記複数の第１の回路の各々は、ｎ型ＭＯＳトランジスタ又はｐ型ＭＯＳトランジスタである、
請求項５に記載の半導体装置。 A plurality of the first circuits are provided.
Each of the plurality of first circuits is an n-type MOS transistor or a p-type MOS transistor.
The semiconductor device according to claim 5. 前記第１の回路は、前記第２の配線には直接接続されない、
請求項１～請求項６の何れか１項に記載の半導体装置。 The first circuit is not directly connected to the second wiring.
The semiconductor device according to any one of claims 1 to 6. 前記第２の配線は、電源用の配線であり、
前記第２の回路は、電源用に前記第２の配線にのみ直接接続され、
前記第１の回路は、電源用に前記第１の配線にのみ直接接続される、
請求項１～請求項７の何れか１項に記載の半導体装置。 The second wiring is wiring for a power supply, and is
The second circuit is directly connected only to the second wiring for power supply.
The first circuit is directly connected only to the first wiring for power.
The semiconductor device according to any one of claims 1 to 7.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002373940A (en) 2001-06-15 2002-12-26 Denso Corp Semiconductor integrated circuit apparatus
JP2004146674A (en) 2002-10-25 2004-05-20 Kawasaki Microelectronics Kk Semiconductor integrated circuit
WO2004068577A1 (en) 2003-01-27 2004-08-12 Matsushita Electric Industrial Co., Ltd. Semiconductor device
WO2006057106A1 (en) 2004-11-29 2006-06-01 Kabushiki Kaisha Toyota Jidoshokki Method for supplying power to circuit block in semiconductor device for radio, and semiconductor device for radio
JP2009117625A (en) 2007-11-07 2009-05-28 Sony Corp Semiconductor integrated circuit
JP2014120194A (en) 2012-12-19 2014-06-30 Ps4 Luxco S A R L Semiconductor device

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984542A (en) * 1982-11-08 1984-05-16 Nec Corp High-frequency semiconductor integrated circuit
JP2580065B2 (en) * 1990-07-17 1997-02-12 株式会社日立製作所 Power supply wiring method for large-scale integrated circuits
JPH0575038A (en) * 1991-09-11 1993-03-26 Seiko Epson Corp Semiconductor mos integrated circuit
JPH06310656A (en) * 1993-04-27 1994-11-04 Hitachi Ltd Semiconductor integrated circuit
JPH08330523A (en) * 1995-06-02 1996-12-13 Hitachi Ltd Wire layout method
JPH11345936A (en) * 1998-05-29 1999-12-14 Nec Eng Ltd Semiconductor integrated circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002373940A (en) 2001-06-15 2002-12-26 Denso Corp Semiconductor integrated circuit apparatus
JP2004146674A (en) 2002-10-25 2004-05-20 Kawasaki Microelectronics Kk Semiconductor integrated circuit
WO2004068577A1 (en) 2003-01-27 2004-08-12 Matsushita Electric Industrial Co., Ltd. Semiconductor device
WO2006057106A1 (en) 2004-11-29 2006-06-01 Kabushiki Kaisha Toyota Jidoshokki Method for supplying power to circuit block in semiconductor device for radio, and semiconductor device for radio
JP2009117625A (en) 2007-11-07 2009-05-28 Sony Corp Semiconductor integrated circuit
JP2014120194A (en) 2012-12-19 2014-06-30 Ps4 Luxco S A R L Semiconductor device

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