JPH08330523A - Wire layout method - Google Patents

Abstract

PURPOSE: To suppress the peak value of noise in such a lattice wiring as power supply wiring by selectively switching the pitch of the lattice wiring which is virtually arranged in a lattice according to the noise occurrence situation. CONSTITUTION: The pitch, namely an electrical length L1 , of a lattice wiring corresponding to modules MOD 1 and MOD2 corresponds to the noise occurrence situation of the modules. That is, after obtaining a noise compression rate αwhere the peak value of noise to be propagated reaches a specific value or less, the pitch is calculated as an electrical length L0 where the noise compression rate α is obtained and the pitch of the lattice wiring corresponding to the module MOD3, namely an electrical length L2 , can also be calculated in a similar manner. Therefore, the electrical lengths become optimized values to fully reduce the peak value of noise at each lattice point of the power supply wiring although the peak value of the noise generated from each module is relatively large and hence fully stabilizing the operation of a large-scale integrated circuit device LSI.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring layout method,
For example, the present invention relates to a large-scale integrated circuit device having a grid wiring such as a power supply wiring and a technique which is particularly effective for the layout design thereof.

[0002]

2. Description of the Related Art There is a large scale integrated circuit device such as a high speed logic integrated circuit including a plurality of modules. These large-scale integrated circuit devices are provided with power supply wiring for supplying a power supply voltage and a ground potential of a circuit serving as an operation power supply to each part thereof, that is, each module.

[0003]

In the conventional large-scale integrated circuit device, the power supply wiring is a so-called grid wiring in which, for example, two orthogonal metal wiring layers are arranged in a grid, and the pitch thereof is different from each other. The voltage drop of the power supply wiring due to the current supply to the module, that is, the level fluctuation of the power supply voltage of the circuit or the ground potential is determined to be within a predetermined value.

On the other hand, the large scale and high speed operation of large scale integrated circuit devices is remarkable, and the influence of noise on the stable operation is also increasing. However, in the conventional large-scale integrated circuit device, as described above, the setting of the pitch of the power supply wiring as the grid wiring mainly focuses on the level fluctuation of the power supply voltage or the ground potential of the circuit, in other words, in the grid wiring. Since it is performed without being aware of the propagation form of noise, there are cases where the optimum solution is not always obtained when viewed from the propagation form of noise. As a result, the amount of noise in the large-scale integrated circuit device increases, and the stabilization of its operation is restricted.

An object of the present invention is to provide a wiring arrangement method capable of suppressing the peak value of noise in grid wiring such as power supply wiring. Another object of the present invention is to suppress noise in a large scale integrated circuit device or the like and stabilize its operation.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a large-scale integrated circuit device or the like having a plurality of modules and having grid wiring such as power supply wiring, the pitch of the grid wiring is set according to the noise occurrence state of each module, that is, the peak value of the propagated noise. After the noise compression rate that is less than or equal to the predetermined value is obtained, the noise compression rate is selectively set based on the calculation result of the electrical length that obtains this noise compression rate, and optimized for each module.

[0008]

According to the research conducted by the inventors of the present application, the noise compression rate in grid wiring such as power supply wiring is a function of at least twice its electrical length and the rise time of noise, and the peak value of noise in grid wiring is also It is a function of the noise compression rate, that is, the electrical length of the lattice wiring. Therefore, by setting the pitch of the grid wiring by the above method, it is possible to suppress the peak value of noise in the grid wiring such as the power supply wiring, thereby stabilizing the operation of the large-scale integrated circuit device or the like. .

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a general board layout diagram of power supply wiring of a large scale integrated circuit device. In addition, in FIG.
A conceptual diagram for explaining a reflection coefficient and a transmission coefficient at a connection point of a general transmission line is shown, and FIG. 3 is a conceptual diagram for explaining an idea of impedance at a grid point A of the power supply wiring of FIG. It is shown. Further, FIGS. 4 and 5 are conceptual diagrams for explaining the level calculation method at the time t = 2Lo and at the time t = 4Lo of the noise at the grid point A of the power supply wiring of FIG. 1, respectively. 6 and 7 are conceptual diagrams of one embodiment for explaining the propagation state of noise at the lattice point A of the power supply wiring of FIG. 1 when Tr = Lo and Tr = 4Lo, respectively. In addition, FIG. 8 shows a characteristic diagram of an embodiment for explaining the relationship between the crest value of noise and the electrical length in the power supply wiring of FIG. 1, and FIG. 9 shows the noise compression ratio and Tr / 2Lo. A characteristic diagram of one embodiment for explaining the relationship of is shown. Based on these drawings, a noise propagation characteristic in a grid wiring, a method of setting a pitch of the grid wiring, and its characteristics, which are the principles of the present invention, will be described.

In FIG. 1, the power supply wiring of this large-scale integrated circuit device is a grid wiring in which two metal wiring layers are arranged orthogonally, and the metal wiring in the X-axis and Y-axis directions constituting this grid wiring is formed. The layers are arranged at a predetermined pitch so that the unit electrical length Lo per grid has a predetermined value. Here, the unit electrical length Lo is L and C, which are the inductance and capacitance per unit length of the grid wiring, and the wiring pitch is x.
, Lo = (L · C) ^1/2 · x ……………………………………………… (1), whose unit is ps [picoseconds] It becomes such a time unit. In the drawings and the description of this specification,
Instead of the physical wiring pitch x, the unit electrical length Lo that is an electrical wiring pitch is used as the pitch of the grid wiring.

Next, let us focus on the grid point A of the power supply wiring shown in FIG. First, as illustrated in FIG. 2, the levels Vr and Vt of the reflected wave and the transmitted wave at the connection point A of the two transmission lines whose characteristic impedances are Z ₁ and Z ₂ , respectively, are well known as follows. When the level of the incident wave at the connection point A is Vo and the reflection coefficient and the transmission coefficient are Kr and Kt, respectively, Vr = Kr × Vo Vt = Kt × Vo is obtained, and the reflection coefficient Kr and the transmission coefficient Kt are Kr = (Z ₂ −Z ₁ ) / (Z ₁ + Z ₂ ) ……………………………… (2) Kt = 2Z ₂ / (Z ₁ + Z ₂ ) ……………… ……………………………… (3) is required.

On the other hand, the original form of the grid point A in FIG. 1 is shown in FIG.
As shown in (a), the characteristic impedance Zo of the metal wiring layer, which is the power supply wiring, is represented by four transmission paths. The characteristic impedance Zo is represented by four transmission lines. When combined, the three wirings to the right and above and below the grid point A are replaced with one transmission line having a characteristic impedance Zo / 3 of one third, as shown in FIG. 3 (b). be able to. Therefore, the grid point A
The reflection coefficient Kr at is from the above equation (2): Kr = (Zo / 3−Zo) / (Zo + Zo / 3) = − 1
Therefore, the transmission coefficient Kt is Kt = (2 × Zo / 3) / (Zo + Zo / 3) = 1/2 from the above equation (3).

Here, the noise generated at the grid point A is 4 adjacent to each other at time t = Lo as shown in FIG.
Reaching the number of grid points and multiplying the reflection coefficient by Kr, that is, -1 /
Two times each is reflected and returns to the grid point A. Therefore, at time t = 2Lo, the level Vn of noise that reaches the grid point A and remains after transmission is Vn = (-1/2 when the noise generation level at time t = 0, that is, the grid point A is 1. ) × (1/2) × 4 = −1, which is an inverted phase signal having the same absolute value as the generated noise.

Noise reaching four adjacent grid points at time t = Lo is multiplied by its transmission coefficient Kt, that is, 1 /
After double transmission through each grid point, as illustrated in FIGS. 5A and 5B, at time t = 2Lo, the grid point is further outside or adjacent to four grid points adjacent to each other. To reach. Then, the reflection coefficient Kr times, that is, -1 /
After twice the reflection, at time t = 3Lo, it returns to the adjacent grid point, and its transmission coefficient Kt times, that is, 1/2 times, passes through each adjacent grid point and returns to the grid point A. Further, noise reaching the grid points above and below the adjacent grid point at time t = 2Lo is transmitted through each grid point by a transmission coefficient Kt times, that is, 1/2 times, as illustrated in FIG. 5C. And reaches the grid points above and below the grid point A, and its transmission coefficient K
t times, that is, 1/2 times, returns to the grid point A. Therefore, at time t = 4Lo, the level Vn of the noise that reaches the grid point A and remains after transmission is Vn = (1/2) ³ × (−1/2) × 4 in the case of FIG. = -1 / 4. In the case of FIG. 5B, Vn = (1/2) ³ × (−1/2) × 2 × 4 = −1 / 2, and in the case of FIG. 5C, Vn = (1/2) ⁴ x 2 x 4 = 1/2.

On the other hand, the (-1/2) times noise reflected at each adjacent lattice point at time t = Lo is, as illustrated in FIG. 5D, the reflection coefficient Kr times, that is, -1/2. After double reflection at the grid point A and returning to each adjacent grid point, the reflection coefficient Kr times, that is, −1/2 times, is further reflected at each adjacent grid point and returns to the grid point A. Further, as illustrated in FIG. 5E, after the transmission coefficient Kt times, that is, 1/2 times, passes through the grid point A and reaches the adjacent grid point on the opposite side, the reflection coefficient Kr times further. That is, -1/2 times is reflected by these adjacent grid points and returns to the grid point A. In addition, FIG.
As illustrated in (f), after the transmission coefficient Kt times, that is, 1/2 times, passes through the grid point A and reaches the adjacent grid points above and below it, the reflection coefficient Kr times, that is, −1/2 times.
Double the reflection at these adjacent grid points back to grid point A. As a result, at time t = 4Lo, the level Vn of the noise reaching the grid point A and remaining after transmission is as follows: Vn = (1/2) × (−1/2) ³ × 4 = -1 / 4. In the case of FIG. 5E, Vn = (1/2) ² × (−1/2) ² × 4 = 1/4, and in the case of FIG. 5F, Vn = (1 / 2) ² x (-1/2) ² x 2 x 4 = 1/2.

From these facts, the total level Vn _T of the noise reaching the grid point A and remaining after passing through at the lattice point A at time t = 4Lo is the sum of the noise levels Vn in the case of FIGS. 5 (a) to 5 (f). Then, Vn _T = (-1/4) + (-1/2) + (1/2) +
(-1/4) + (1/4) + (1/2) = 1/4, which is a signal of the same phase having an absolute value of 1/4 of the generated noise.

By the way, the state of noise propagation in the lattice wiring is closely related to the rise time Tr of the generated noise. That is, for example, as shown in FIG. 6, when the rise time Tr of the noise input to the lattice point A0 is the same as the unit electrical length Lo of the lattice wiring, that is, Tr = Lo, the noise level (voltage ) Has a maximum value of 1 at time t = Lo, and reaches a peak value of −1 again due to the reflected wave in FIG. 4 at time t = 3Lo. Further, at the time t = 5Lo, the reflected wave and the transmitted wave in FIG. 5 are received, and the peak value becomes 1/4, and further at the time t = 7Lo.
Reaches a peak value of -1/4. The noise input to the grid point A0 reaches the adjacent grid point A1 at time t = 2Lo to make a peak value of 1/2 in the noise level, and further to the grid point A2 outside thereof at time t = 2Lo. It reaches and makes a peak value of 1/4 at the noise level.

Below, the noise level at each grid point is
As shown in the computer simulation result of FIG. 6, it changes in time series under the influence of the reflected wave and the transmitted wave, but in the case of this embodiment, the rise time Tr of the generated noise is the unit electrical length Lo of the grid wiring. The noise level at each grid point is the same as
It is not affected by and is only affected by reflected and transmitted waves. In this embodiment, Tr / 2Lo, which will be described later, is 1
/ 2, that is, 0.5.

On the other hand, as illustrated in FIG. 7, the grid point A
When the rise time Tr of the noise input to 0 is 4 times the unit electrical length Lo of the grid wiring, that is, Tr = 4Lo, the noise level at the grid point A0 is the time t = 4L.
It should be a maximum value of 1 at o, but since the negative reflected wave of FIG. 4 appears at the lattice point A0 from the time t = 2Lo, its peak value is limited to 1/2 or 0.5. Also,
The noise level of the grid point A1 that should reach the peak value of 1/2 at the time t = 6Lo is also limited due to the decrease in the noise level of the grid point A0, and reaches the peak value of 1/4 at the time t = 8Lo. The noise level at the supposed grid point A2 barely reaches its peak value. In this embodiment,
Tr / 2Lo described later is 4/2, that is, 2.

As described above, when twice the unit electric length Lo of the grid wiring, that is, 2Lo, is smaller than the rise time Tr of the noise input to the grid point A0, the noise level at each grid point including the grid point A0. Is limited, and its peak value is at least a function of twice the unit electrical length Lo of the grid wiring and the noise rise time Tr, that is, Tr / 2Lo. That is, as shown in FIG. 8, for example, when the unit electrical length Lo of the lattice wiring is 500 ps or more and Tr / 2Lo is 1 or less with respect to the noise rise time Tr, that is, 1000 ps, the lattice point is A
The noise level at 0 rises to the peak value of the generated noise without being affected by the reflected wave or the like. However, for example, the unit electrical length Lo is 375 ps and Tr / 2 is set.
When Lo is about 1.3, the peak value of noise at the grid point A0 is limited to 3/4, that is, 0.75,
For example, the unit electric length Lo is 250 ps and Tr / 2Lo is set.
Is set to 2, it is limited to 1/2, that is, 0.50. Hereinafter, it becomes apparent that the limiting rate of the noise peak value, that is, the noise compression rate α changes according to the characteristic diagram of FIG. 9 obtained by computer simulation and becomes a function of Tr / 2Lo.

Now, let's calculate the pitch x of the grid wiring by giving a specific numerical value. For example, the standard rise time tr and fall time tf of the circuit are 500 ps,
Impedance L and capacitance C per unit length of power wiring
Is 1 nH [nanohenry] / mm [millimeter] and 1 pF [picofarad] / mm, and the characteristic impedance Zo, that is, (L / C) ^1/2 is 32 Ω [ohm], in the case of (L ・C) ^1/2 = (10 ⁻⁹ · 10 ⁻¹² ) ^1/2 ≈32 [ps / mm], and the unit electrical length Lo of the grid wiring is Lo = (L · C) from the above equation (1). ^1/2 · x = 32 × [ps].

On the other hand, assuming that a noise current In of 100 mA [milliampere] flows into a certain lattice point,
At this lattice point, Vn = In × Zo / 4 = 0.1 × 32/4 = 0.8 That is, a noise voltage of 0.8 V [volt] is generated. Therefore, assuming that the amplitude of the internal signal is, for example, 2 V, the allowable noise level is 5% of the signal amplitude, that is, 100 mV.
When [millivolt] is set, the required noise compression rate α
Becomes α = 0.1 / 0.8 = 0.125, and Tr / 2Lo at which this noise compression rate α can be obtained
From FIG. 9, Tr / 2Lo≈11 …………………………………………………… (4).

As described above, the unit electrical length Lo is Lo = 32x [ps], and therefore the above equation (4) is Tr / 2Lo = 500 × 10 ^-12 / 2 × 32x × 10 ^-12 ≈7 .8 / x = 11. As a result, the required pitch x of the grid wiring is x = 7.8 / 20 = 0.71 [mm], that is, 710 μm [micrometer], and by setting the grid wiring at this pitch, the noise peak at each grid point The value can be suppressed to 100 mV or less, and the operation of the large-scale integrated circuit device can be stabilized.

FIG. 10 shows a board layout diagram of an embodiment of power supply wiring of a large scale integrated circuit device LSI to which the present invention is applied. The large-scale integrated circuit device LSI of this embodiment is a so-called high-speed logic integrated circuit, which is not particularly limited, and forms a predetermined computer system together with other constituent elements.

In FIG. 10, the large-scale integrated circuit device LSI of this embodiment is not particularly limited, but is a module M.
A plurality of modules including OD1 to MOD3 are provided, and the power supply wirings thereof are basically arranged in a grid pattern with a predetermined wiring pitch corresponding to the unit electrical length Lo. In this example, modules MOD1 and MOD2 are expected to generate relatively large noise. The module MOD3 is expected to generate the next largest noise, and the other modules are expected to generate relatively less noise. Therefore, in this example,
Module MOD expected to generate the largest noise
1 and MOD2, the pitch of the grid wiring as the power supply wiring is made smaller to correspond to a quarter of the normal portion, that is, the electrical length L ₁ , and the module MOD3 is expected to generate the next largest noise. ½ of that, that is, the electrical length L ₂ is reduced.

Here, the modules MOD1 and MOD2
The pitch of the grid wiring, that is, the electrical length L ₁ corresponding to the above, depends on the noise generation status of these modules, that is, the noise compression ratio at which the peak value of the noise propagated first from the characteristic diagram of FIG. After obtaining α, this noise compression rate α is calculated as the electrical length Lo, and the pitch of the grid wiring corresponding to the module MOD3, that is, the electrical length L ₂ is also calculated by the same method. Therefore,
These electrical lengths are optimized to sufficiently reduce the peak value of noise at each grid point of the power supply wiring, even though the peak value of noise generated from each module is relatively large. As a result, the operation of the large-scale integrated circuit device LSI is sufficiently stabilized.

The functions and effects obtained from the above embodiments are as follows. That is, (1) In a large-scale integrated circuit device or the like having a plurality of modules and having grid wiring such as power supply wiring, the pitch of the grid wiring is set according to the noise occurrence state of each module, that is, the noise propagated first. After obtaining the noise compression rate at which the peak value of is less than the specified value, set it selectively based on the calculation result of the electrical length to obtain this noise compression rate, and optimize it for each module. It is possible to obtain an effect that the peak value of the noise at each grid point can be sufficiently suppressed according to the peak value of the noise generated from the corresponding module. (2) According to the above item (1), it is possible to obtain an effect that a wiring arrangement method capable of suppressing the peak value of noise in the grid wiring such as the power supply wiring can be realized. (3) According to the above items (1) and (2), it is possible to suppress the noise of the large-scale integrated circuit device having the lattice wiring and stabilize the operation.

The invention made by the present inventor has been specifically described above based on the embodiments, but the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 10, the shape of the semiconductor substrate of the large-scale integrated circuit device LSI is not restricted by this embodiment, and the shape of each module is arbitrary. Further, the pitch of the power supply wiring as the grid wiring may take different values in the X-axis direction and the Y-axis direction, and the combination with the module can be set arbitrarily. The large-scale integrated circuit device LSI can have a predetermined number of capacitors for absorbing noise at lattice points. Furthermore, the impedance L, the capacitance C, the characteristic impedance Zo, and other specific numerical examples used in the calculation process do not affect the gist of the present invention.

In the above description, the case where the invention made by the present inventor is mainly applied to the large-scale integrated circuit device such as a high-speed logic integrated circuit and the layout design of its power supply wiring, which is the field of use in the background of the invention, will be described. However, the present invention is not limited to this, and can be applied to, for example, power supply wirings of various memory integrated circuits, clock supply wirings of high-speed logic integrated circuits, printed circuit boards, and the like. The present invention
It can be widely applied as an electronic device having at least a grid wiring and a wiring arrangement method thereof.

[0030]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a large-scale integrated circuit device or the like having a plurality of modules and having grid wiring such as power supply wiring, the pitch of the grid wiring is set according to the noise occurrence state of each module, that is, the peak value of the noise propagated first. After obtaining the noise compression rate that is less than or equal to a predetermined value, set it selectively based on the calculation result of the electrical length that can obtain this noise compression rate, and optimize it for each module. The peak value of noise in the wiring can be suppressed, and thus the operation of the large-scale integrated circuit device or the like can be stabilized.

[Brief description of drawings]

FIG. 1 is a general board layout diagram of power supply wiring of a large-scale integrated circuit device.

FIG. 2 is a conceptual diagram for explaining a reflection coefficient and a transmission coefficient at a connection point of a general transmission line.

FIG. 3 is a conceptual diagram for explaining the concept of impedance at a grid point A of the power supply wiring in FIG.

FIG. 4 is a conceptual diagram for explaining a level calculation method when noise time t = 2Lo at grid point A of the power supply wiring of FIG. 1;

5 is a conceptual diagram for explaining a method of calculating a level at a time t = 4Lo of noise at a grid point A of the power supply wiring of FIG.

6 is a graph showing the noise T at the grid point A of the power supply wiring shown in FIG.
It is a conceptual diagram which shows one Example for demonstrating the propagation condition at the time of r = Lo.

7 is a graph of noise T at grid point A of the power supply wiring shown in FIG.
It is a conceptual diagram which shows one Example for demonstrating the propagation condition at the time of r = 4Lo.

8 is a characteristic diagram showing an example for explaining the relationship between the peak value of noise and the electrical length in the power supply wiring of FIG.

9 is a noise compression ratio and Tr in the power supply wiring of FIG.
It is a characteristic view showing an example for explaining the relationship of / 2Lo.

FIG. 10 is a substrate layout diagram showing an embodiment of power supply wiring of a large scale integrated circuit device to which the present invention is applied.

[Explanation of symbols]

LSI ... Large-scale integrated circuit device, A ... Lattice point, Lo ...
… Unit electricity length. Z _{1 to} Z ₂ ... Characteristic impedance, V
o ... incident wave, Vr ... reflected wave, Vt ... transmitted wave, Kr
...... Reflection coefficient, Kt ...... Transmission coefficient. Zo ... Characteristic impedance. Vn: noise level, Vn _T: total noise level. A0 to A2 ... Lattice points, Tr ... Noise rise time. α: Noise compression rate. MOD1 to MOD
3 ...... module, L ₁ ~L ₂ ...... electrical length.

Claims (3)

[Claims] 1. A wiring layout method, wherein the pitch of grid wirings arranged in a substantially grid pattern is selectively switched according to a noise occurrence situation. 2. The noise generation status includes a peak value and rise time of generated noise, and a noise compression rate in the grid wiring is at least twice the electrical length and the rise time. The pitch of the grid wiring is a function, and after the noise compression rate at which the peak value of the propagated noise is less than or equal to a predetermined value is obtained, the electrical length calculation result that obtains this noise compression rate is calculated. The wiring placement method according to claim 1, wherein the wiring placement method is set based on the original setting. 3. The grid wiring is a power wiring of a large-scale integrated circuit device including a plurality of modules, and the pitch thereof can take different values for each module. Alternatively, the wiring arrangement method according to claim 2.