JP7012166B2 - 半導体デバイス及びその製造方法 - Google Patents
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Description
本発明の実施例は、半導体技術分野に関し、特に半導体デバイス及びその製造方法に関する。
a.高温焼きなまし
b.イオン注入
c.重ドープ
101 基板
102 半導体層
121 チャンネル層
122 バリア層
123 核生成層
124 バッファ層
103 ソース電極
104 ゲート電極
141 ゲートリセス
105 ドレイン電極
106 ドレイン接合終端
161 成長半導体層
162 オーミック電極
1061 第1のドレイン接合終端
1062 第2のドレイン接合終端
1063 第3のドレイン接合終端
107 誘電体層
20 二次元電子ガス
Claims (11)
- 基板と、
前記基板の一側に配置される半導体層と、
前記半導体層の前記基板と反対側に配置されるソース電極、ゲート電極及びドレイン電極と、
前記半導体層の前記基板と反対側に配置され且つ前記ゲート電極と前記ドレイン電極との間に離間配置される少なくとも2つのドレイン接合終端と、を含み、
前記半導体層はチャンネル層とバリア層とを含み、前記チャンネル層と前記バリア層との間の界面において二次元電子ガスが形成され、
前記少なくとも2つのドレイン接合終端はそれぞれ前記ドレイン電極と電気的に接続され、
前記少なくとも2つのドレイン接合終端は、前記ゲート電極から前記ドレイン電極に向かう延伸方向に沿って配置され、
前記少なくとも2つのドレイン接合終端のうち前記ドレイン電極に近接するドレイン接合終端の前記延伸方向における長さは、前記少なくとも2つのドレイン接合終端のうち前記ゲート電極に近接するドレイン接合終端の前記延伸方向における長さより長い
ことを特徴とする半導体デバイス。 - 前記少なくとも2つのドレイン接合終端は、前記ゲート電極から前記ドレイン電極に向かう延伸方向に沿って配置され、
前記少なくとも2つのドレイン接合終端のうち前記ドレイン電極に近接するドレイン接合終端の厚さは、前記少なくとも2つのドレイン接合終端のうち前記ドレイン電極から離れる側にあるドレイン接合終端の厚さより厚い
ことを特徴とする請求項1に記載の半導体デバイス。 - 前記少なくとも2つのドレイン接合終端の厚さは、前記ゲート電極から前記ドレイン電極に向かう延伸方向において漸次厚くなる
ことを特徴とする請求項2に記載の半導体デバイス。 - 前記少なくとも2つのドレイン接合終端のうち前記ゲート電極に近接するドレイン接合終端と前記ゲート電極との間の距離は、前記少なくとも2つのドレイン接合終端のうち前記ドレイン電極に近接するドレイン接合終端と前記ドレイン電極との間の距離以上である
ことを特徴とする請求項1乃至3のいずれか一項に記載の半導体デバイス。 - 前記少なくとも2つのドレイン接合終端のうち前記ゲート電極に近接する2つの隣接するドレイン接合終端の間の距離は、前記少なくとも2つのドレイン接合終端のうち前記ドレイン電極に近接する2つの隣接するドレイン接合終端の間の距離以上である
ことを特徴とする請求項1乃至4のいずれか一項に記載の半導体デバイス。 - 前記少なくとも2つのドレイン接合終端のうち、隣接する2つのドレイン接合終端の間の距離は、前記ゲート電極から前記ドレイン電極に向かう延伸方向において漸次短くなる
ことを特徴とする請求項5に記載の半導体デバイス。 - 前記少なくとも2つのドレイン接合終端は、第1のドレイン接合終端、第2のドレイン接合終端及び第3のドレイン接合終端を含み、
前記第1のドレイン接合終端は前記ゲート電極に近接して配置され、前記第3のドレイン接合終端は前記ドレイン電極に近接して配置され、前記第2のドレイン接合終端は前記第1のドレイン接合終端と前記第3のドレイン接合終端との間に配置され、
前記第1のドレイン接合終端と前記第2のドレイン接合終端との間の距離は、前記第2のドレイン接合終端と前記第3のドレイン接合終端との間の距離より長い
ことを特徴とする請求項1乃至6のいずれか一項に記載の半導体デバイス。 - 前記少なくとも2つのドレイン接合終端のうちの各ドレイン接合終端は、
前記半導体層の前記基板と反対側に成長される第1の成長半導体層と、
前記第1の成長半導体層の前記半導体層と反対側に配置されるオーミック電極と、を含み、
前記ドレイン接合終端は前記オーミック電極によって前記ドレイン電極と短絡するように接続され、前記少なくとも2つのドレイン接合終端はそれぞれ前記ドレイン電極と同一の電位を維持する
ことを特徴とする請求項1乃至7のいずれか一項に記載の半導体デバイス。 - 前記ゲート電極と前記バリア層との間には第2の成長半導体層が成長され、前記第2の成長半導体層の少なくとも一部が前記バリア層の表面まで、又は前記バリア層の内部まで、又は前記チャンネル層の内部まで延びる
ことを特徴とする請求項1乃至8のいずれか一項に記載の半導体デバイス。 - 前記バリア層の上側に位置する誘電体層を更に含み、
前記誘電体層にはゲートリセスが設けられ、
前記ゲートリセスは前記誘電体層から前記バリア層の表面又は前記バリア層の内部まで延び、又は、
前記ゲートリセスは前記誘電体層から前記チャンネル層の内部まで延びて、前記ゲート電極と前記バリア層との間の前記第2の成長半導体層が前記ゲートリセスの中に位置する
ことを特徴とする請求項9に記載の半導体デバイス。 - 基板の一側にチャンネル層とバリア層とを含む半導体層を配置し、前記チャンネル層と前記バリア層との間の界面に二次元電子ガスを形成するステップと、
前記半導体層の前記基板と反対側に少なくとも2つのドレイン接合終端を離間配置するステップと、
前記半導体層の前記基板と反対側にソース電極、ゲート電極及びドレイン電極を配置するステップと、を含み、
前記少なくとも2つのドレイン接合終端は前記ゲート電極と前記ドレイン電極との間に位置し、それぞれ前記ドレイン電極と電気的に接続され、
前記少なくとも2つのドレイン接合終端は、前記ゲート電極から前記ドレイン電極に向かう延伸方向に沿って配置され、
前記少なくとも2つのドレイン接合終端のうち前記ドレイン電極に近接するドレイン接合終端の前記延伸方向における長さは、前記少なくとも2つのドレイン接合終端のうち前記ゲート電極に近接するドレイン接合終端の前記延伸方向における長さより長い
ことを特徴とする半導体デバイスの製造方法。
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WO2013021628A1 (ja) | 2011-08-08 | 2013-02-14 | パナソニック株式会社 | 半導体装置 |
WO2014174810A1 (ja) | 2013-04-25 | 2014-10-30 | パナソニックIpマネジメント株式会社 | 半導体装置 |
JP2018022870A (ja) | 2016-07-22 | 2018-02-08 | 株式会社東芝 | 半導体装置、電源回路、及び、コンピュータ |
US20180138306A1 (en) | 2016-11-17 | 2018-05-17 | Semiconductor Components Industries, Llc | High-electron-mobility transistor (hemt) semiconductor devices with reduced dynamic resistance |
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