JP7011544B2 - Power converter - Google Patents

Description

The present invention relates to a power conversion device.

In recent years, power conversion devices have realized higher-speed switching operation by technological innovation of the power semiconductor module, which is a main component thereof, and reduced the loss generated from this power semiconductor. As a result, the cooler can be particularly miniaturized, and as a result, the power conversion device can be miniaturized. Further, by reducing the loss of the power semiconductor, the efficiency of the power conversion device can be improved.

For example, a wide bandgap device such as SiC or GaN has an electron saturation rate about twice or more that of Si, so that SW loss can be reduced by high-speed SW (Switching) operation, and high-frequency inverter SW operation can be performed.

On the other hand, in the SiC- MOSFET, the negative gate withstand voltage is lower and the threshold voltage is lower than that of the Si-IGBT. That is, in the SiC-PWM, the allowable vibration range of the gate voltage for avoiding erroneous arc (turn-on) and exceeding the rating is narrow. The jump / fall voltage of this gate voltage has a trade-off relationship with the high-speed SW operation.

Patent Document 1 discloses a structure in which gate source terminals are individually provided in order to suppress gate vibration caused by a common source inductance.

JP-A-2015-126342A

However, the technique described in Patent Document 1 is a 4-terminal package product of gate, source, drain, and gate source, and it is difficult to replace the general-purpose 3-terminal device of gate, source, and drain.

An object of the present invention is to provide a power conversion device capable of suppressing gate voltage vibration accompanying high-speed driving of a power device.

In order to achieve the above object, the power conversion device of the present invention has a bridge circuit including a first power device and a second power device connected in series with the first power device, and the capacity of the gate of the second power device. When the voltage between the gate drive circuit for charging and discharging and the gate and source of the second power device is smaller than a predetermined value, a clamp that conducts the gate of the second power device and the source of the second power device. The clamp circuit comprises a circuit, the clamp circuit comprises a switching element, a first resistor connected in series with the switching element, and a first diode connected in parallel to the first resistor .

According to the present invention, it is possible to suppress gate voltage vibration associated with high-speed driving of a power device. Issues, configurations and effects other than those described above will be clarified by the following description of the embodiments.

It is a schematic block diagram of the power conversion apparatus to which an embodiment of this invention is applied. It is a schematic internal block diagram of the converter, the inverter and the chopper shown in FIG. It is an equivalent circuit diagram which shows the structure of a converter. It is an equivalent circuit diagram which shows the structure of an inverter. It is an equivalent circuit diagram which shows the structure of a chopper. It is a figure which shows the appearance of a power device. It is a figure which shows the appearance of a cooling fin. It is a block diagram of the single-phase bridge circuit of 1st Embodiment of this invention. It is a figure which shows the operation when the upper arm turns on in the single-phase bridge circuit of 1st Embodiment of this invention. It is a figure which shows the operation when the upper arm turns off in the single-phase bridge circuit of 1st Embodiment of this invention. It is a figure which shows the single-phase bridge circuit of the 2nd Embodiment of this invention. It is a figure which shows the single-phase bridge circuit of the 3rd Embodiment of this invention. It is a figure which shows the single-phase bridge circuit of the 4th Embodiment of this invention. It is a figure which shows the single-phase bridge circuit of the 5th Embodiment of this invention. It is a figure which shows an example of the circuit structure of the power conversion apparatus to which this invention is applied. It is a figure which shows the layout (top view) which mounted the circuit of the power conversion apparatus of FIG. 13 on a board. It is a figure which shows an example of the wiring layout (L1 layer) in the circuit configuration shown in FIG. It is a figure which shows an example of the wiring layout (L2 layer) in the circuit configuration shown in FIG. It is a figure which shows an example of the wiring layout (L3 layer) in the circuit configuration shown in FIG. It is a figure which shows an example of the wiring layout (L4 layer) in the circuit configuration shown in FIG. 15A is a cross-sectional view taken along the line BB'of FIG. 15A.

Hereinafter, embodiments for carrying out the present invention will be described with reference to the accompanying drawings. In the following description, an uninterruptible power conversion device will be described as an example of a power conversion device having a plurality of operating states. Although the object of this embodiment partially overlaps with the above-mentioned object, for example, a highly efficient and compact power conversion device that suppresses gate vibration associated with high-speed driving of a power semiconductor device and reduces power semiconductor device loss is realized. It is to be.

(Rough configuration)
FIG. 1 is a schematic configuration diagram of a power conversion device 100 to which an embodiment of the present invention is applied.

In FIG. 1, the power conversion device 100 includes a converter 102, an inverter 103, a chopper 104, and an upper control circuit 105 that controls them.

The converter 102 is a three-phase converter that converts the three-phase AC power supplied from the commercial power supply (AC power supply) 106 into DC power and supplies it to the inverter 103.

The inverter 103 is a three-phase inverter that converts the DC power supplied from the converter 102 into three-phase AC power again and supplies it to the load 108.

The chopper 104 boosts or steps down the DC power supplied from the storage battery (DC power supply) 107 to a predetermined voltage, converts it into a predetermined DC power, and supplies the DC power to the inverter 103.

The upper control circuit 105 controls the converter 102, the inverter 103, and the chopper 104. The upper control circuit 105 is, for example, a microcomputer, and is composed of a processor, a memory, an input / output circuit, and the like.

If the commercial power supply 106 fails for some reason, the chopper 104 supplies the power stored in the storage battery 107 to the inverter 103 as DC power. The inverter 103 converts the DC power supplied from the chopper 104 into AC power and supplies it to the load 108. As a result, the power conversion device 100 can supply power to the load 108 without interruption.

FIG. 2 is a schematic internal configuration diagram of the converter 102, the inverter 103, and the chopper 104. As shown in FIG. 2, the converter 102, the inverter 103, and the chopper 104 include a plurality of rectifying elements and switching elements.

FIG. 3 is an equivalent circuit diagram in the internal configuration of the converter 102.

In FIG. 3, the converter 102 includes three half-bridge circuits 201, 202, 203 (power conversion unit), and these half-bridge circuits 201, 202, 203 are converter control units (drive units of the power conversion unit). Controlled by 204. The converter 102 converts the three-phase AC power from the three-phase AC commercial power supply 106 supplied from the R, S, and T terminals into DC power between the positive terminal P and the negative terminal N.

The half-bridge circuit 201 includes an upper arm switching element 21 and a rectifying element 23, and a lower arm switching element 22 and a rectifying element 24. In the example of FIG. 3, an IGBT (Insulated Gate Bipolar Transistor) is used for the switching elements 21 and 22, and a diode is used for the rectifying elements 23 and 24, but the switching elements 23 and 24 are not limited thereto.

The rectifying element 23 is connected in the direction from the emitter of the switching element 21 to the collector. The emitter of the switching element 21 is connected to the collector of the switching element 22 and the AC terminal R. The capacitors 25 and 26 are connected in parallel between the collector of the switching element 21 and the emitter of the switching element 22. In the circuit diagram of FIG. 3, in order to make the drawing easier to see, the parallel connection of the capacitor 25 and the capacitor 26 is omitted, and a single capacitor symbol is used. The gate of the switching element 21 is connected to the converter control unit 204.

The rectifying element 24 is connected in the direction from the emitter of the switching element 22 to the collector. The gate of the switching element 22 is connected to the converter control unit 204.

The half-bridge circuit 202 is configured in the same manner as the half-bridge circuit 201 (power conversion unit) except that the connection node between the emitter of the switching element 21 and the collector of the switching element 22 is connected to the AC terminal S. ..

The half-bridge circuit 203 is configured in the same manner as the half-bridge circuit 201 (power conversion unit) except that the connection node between the emitter of the switching element 21 and the collector of the switching element 22 is connected to the AC terminal T. ..

Hereinafter, the operation of the converter 102 will be described with reference to FIG. 3 as appropriate.

The three-phase AC power supplied from the commercial power supply 106 is supplied to the half-bridge circuits 201, 202, 203 of each phase of the converter 102 via the AC terminals R, S, and T. The switching timing of the switching element 21 and the rectifying element 23 of the upper arm of the half bridge circuits 201, 202, 203 and the switching element 22 and the rectifying element 24 of the lower arm are controlled by the converter control unit 204 to rectify the AC power. do.

FIG. 4 is an equivalent circuit diagram showing the configuration of the inverter 103.

In FIG. 4, the inverter 103 includes three half-bridge circuits 301, 302, 303 (power conversion unit), and is further controlled by an inverter control unit (drive unit of the power conversion unit) 304. The inverter 103 converts the DC power between the P terminal and the N terminal into three-phase AC power.

The half-bridge circuit 301 is configured in the same manner as the half-bridge circuit 201 (see FIG. 3) except that the connection node between the emitter of the switching element 21 and the collector of the switching element 22 is connected to the AC terminal U. ..

The half-bridge circuit 302 is configured in the same manner as the half-bridge circuit 201 (see FIG. 3) except that the connection node between the emitter of the switching element 21 and the collector of the switching element 22 is connected to the AC terminal V. ..

The half-bridge circuit 303 is configured in the same manner as the half-bridge circuit 201 (see FIG. 3) except that the connection node between the emitter of the switching element 21 and the collector of the switching element 22 is connected to the AC terminal W. ..

Hereinafter, the operation of the inverter 103 will be described with reference to FIG. 4 as appropriate.

The DC power converted by the converter 102 is supplied between the terminal P and the terminal N. The switching timing of the switching element 21 and the rectifying element 23 of the upper arm of the half bridge circuits 301, 302, 303 and the switching element 22 and the rectifying element 24 of the lower arm are controlled by the inverter control unit 304, and this DC power is supplied. It is converted to AC power and output to AC terminals U, V, and W.

FIG. 5 is an equivalent circuit diagram showing the configuration of the chopper 104.

In FIG. 5, the chopper 104 includes a half-bridge circuit 401 (power conversion unit) and a reactor 406, and is controlled by a chopper control unit (drive unit of the power conversion unit) 405. The chopper 104 mutually converts a low-voltage DC voltage generated by the storage battery 107 and a high-voltage DC voltage between the terminal P and the terminal N.

The half-bridge circuit 401 is configured in the same manner as the half-bridge circuit 201 (see FIG. 3) except that the connection node between the emitter of the switching element 21 and the collector of the switching element 22 is connected to the terminal C.

The reactor 406 connects the positive electrode of the storage battery 107 to the terminal C.

Hereinafter, the operation of the chopper 104 will be described with reference to FIG.

While the switching element 22 of the lower arm of the half-bridge circuit 401 is on, energy is stored in the reactor 406 connected between the storage battery 107 and the terminal C. Next, when the switching element 22 is turned off, the rectifying element 23 of the upper arm is turned on by the counter electromotive voltage generated by the reactor 406. As a result, a voltage obtained by adding the DC voltage of the storage battery 107 and the counter electromotive voltage of the reactor 406 is generated at the output end of the chopper 104. As a result, the chopper 104 boosts the DC voltage of the storage battery 107. The chopper control unit 405 can arbitrarily set the boost ratio by controlling the switching timing of the half-bridge circuit 401.

From the above, the converter 102, the inverter 103, and the chopper 104 mounted on the power conversion device 100 to which the embodiment of the present invention is applied are all the switching element 21 and the rectifying element 23 of the upper arm and the switching element of the lower arm. The basic configuration is a two-level half-bridge circuit 20 in which 22 and a rectifying element 24 are connected in series.

In the above example, the power device 30 is composed of an IGBT (switching elements 21 and 22) and a diode (rectifying elements 23 and 24), but is not limited to this, and is not limited to the SiC- MOSFET (Metal-Oxide-Semiconductor Field-). Other power devices such as Effect Transistor) may be used.

6 (6A, 6B) show the power device 30 (switching elements and rectifying elements (21 and 23, 22 and 24) in the half-bridge circuits 201 to 203, 301 to 303, 401) according to the embodiment of the present invention. It is a figure which shows the appearance with the cooling fin 40 connected to a power device 30.

The power device 30 of FIG. 6A is, for example, a SiC-PWM, and has a form in which a switching element and a diode are included in one package.

FIG. 6A shows the appearance of the power device 30, and FIG. 6B shows the appearance of the power device 30 in a state where the cooling fins 40 are connected to the power device 30.

In a standard package (for example, TO-247) consisting of three electrode terminals of drain, source, and gate as shown in FIG. 6A, since the source terminal is composed of one, an increase in common source inductance is a problem. It becomes.

(First Embodiment)
Next, the SW operation of the power device in the single-phase bridge circuit will be shown.

FIG. 7A shows a single-phase bridge circuit according to the first embodiment of the present invention.

The single-phase bridge circuit of FIG. 7A includes two power semiconductor devices and a separate gate drive circuit. In other words, the single-phase bridge circuit (bridge circuit) includes an upper arm device 30H (first power device) and a lower arm device 30L (second power device) connected in series with the upper arm device 30H.

The individual gate drive circuits 50H and 50L include a clamp SW (SWc) connecting the gate and the source when off, a clamp SW control circuit, and a clamp resistance circuit (Rc) in series with the clamp SW. The clamp SW means a switch (switching element) for clamping. Further, the GDS of FIG. 7A shows a gate drive signal (gate signal).

The gate drive circuit 50L charges and discharges the capacity of the gate of the lower arm device 30L (second power device). The clamp switch SWc (switching element) and the clamp resistance circuit Rc (first resistance) constitute a clamp circuit. The clamp circuit conducts the gate of the lower arm device 30L and the source of the lower arm device 30L when the voltage VgsL between the gate and the source of the lower arm device 30L (second power device) is smaller than the predetermined value Vthc. The clamp switch SWc (switching element) is a bidirectional switching element capable of passing a current in both directions in the on state. As a result, the gate voltage vibration can be suppressed in both directions.

Next, in the single-phase bridge circuit of FIG. 7A, the operation when the upper arm is turned on is shown in FIG. 7B.

The upper arm turns on Ph. In the period of 1, the gate signal VgsH of the upper arm is in the Hi state, while the gate signal VgsL of the lower arm is in the Low state. Further, the clamp SW control signal SWc of the lower arm is in the Hi state, and the gate-source of the lower arm is in the conduction state via the clamp SW and the clamp resistance circuit.

With the turn-on operation of the upper arm, the drain-source current IsH of the upper arm increases, and the drain-source current IsL (diode current) of the lower arm changes in the decreasing direction. At this time, the voltage across the common source inductance LCM of the lower arm (VssL = LCM × dIsL / dt) jumps up according to the change in the diode current.

As the voltage VssL across the common source inductance rises, the gate current IgL of the lower arm flows in the direction of discharging Cgs. When this gate current is bypassed at the low impedance line of the clamp SW to which the clamp resistance circuit is not connected, the clamp line voltage VcL does not fluctuate, and as a result, the gate-source voltage VgsL (VcL-VssL) of the lower arm becomes. It vibrates to the negative side due to the voltage VssL across the common source inductance. If the negative peak voltage of the gate-source voltage exceeds the gate negative rating, the gate oxide film deteriorates and the life is shortened.

On the other hand, when the clamp line has a series resistance Rc (clamp resistance circuit), the clamp line voltage VcL jumps to the positive side in the same phase with respect to VssL due to the influence of the series resistance Rc. Since the gate vibration VgsL of the anti-arm is defined by VcL-VssL, the negative peak caused by the common source can be reduced (cancelled) by increasing the jump voltage VcL caused by the clamp line series resistance Rc, and between the gate sources. By suppressing the negative vibration of the voltage, the load on the gate oxide film can be reduced, which has the effect of extending the service life.

Next, in the single-phase bridge circuit of FIG. 7A, Ph. The operation for two periods is shown in FIG. 7B.

With the SW on operation of the upper arm, the drain-source voltage VdsL of the lower arm rises. At this time, assuming that the VdsL rising speed is dV / dt, a mirror current (IgL = Cdg × dV / dt) flows into the gate of the lower arm via the mirror capacitance Cdg. When this mirror current flows to the source via the clamp SW, a jump voltage ΔVgsL (IgL × Rc) is generated at the gate-source voltage in the immediate vicinity of the device. When the jump voltage ΔVgsL becomes equal to or higher than the gate threshold voltage, the upper and lower arms are turned on at the same time, and the element is destroyed due to the short circuit current.

In the present embodiment in which the clamp line series resistance is connected to the clamp SW, the gate vibration caused by the mirror current increases, while the gate vibration caused by the common source inductance can be reduced.

Next, in the single-phase bridge circuit of FIG. 8, the operation when the upper arm is turned off is shown. FIG. 8 is the first embodiment of the present invention as in FIG. 7 (7A, 7B), and each of the individual gate drive circuits includes a clamp SW (SWc) connecting the gate and the source when the circuit is off, and a clamp. It includes a SW control circuit and a clamp resistance circuit (Rc) in series with the clamp SW.

The upper arm turns off Ph. In the period of 1, the gate signal VgsH of the upper arm is in the Low state, and the gate signal VgsL of the lower arm is in the Low state. Further, the clamp SW control signal SWc of the lower arm is in the Hi state, and the gate-source of the lower arm is in the conduction state via the clamp SW and the clamp resistance circuit.

With the turn-off operation of the upper arm, the drain-source voltage VdsH of the upper arm increases, and the drain-source voltage VdsL of the lower arm changes in the decreasing direction. At this time, assuming that the VdsL rising speed is dV / dt, a mirror current (IgL = Cdg × dV / dt) flows into the gate of the lower arm via the mirror capacitance Cdg. When this mirror current flows to the source via the clamp SW, a jump voltage ΔVgsL (IgL × Rc) is generated at the gate-source voltage in the immediate vicinity of the device. When this bounce voltage ΔVgsL exceeds the gate negative rating, the gate oxide film deteriorates and the life is shortened.

Next, in the single-phase bridge circuit of FIG. 8, Ph. The operation for two periods is shown.

With the turn-off operation of the upper arm, the drain-source current IdsH of the upper arm decreases, and the drain-source current IsL (diode current) of the lower arm changes in the increasing direction. At this time, the voltage across the common source inductance of the lower arm (VssL = LCM × dIsL / dt) jumps down according to the change in the diode current.

As the voltage VssL across the common source inductance decreases, the gate current IgL of the lower arm flows in the direction of charging Cgs. When this gate current is bypassed at the low impedance line of the clamp SW to which the clamp resistance circuit is not connected, the clamp line voltage Vc does not fluctuate, and as a result, the gate-source voltage VgsL (VcL-VssL) of the lower arm becomes. It vibrates to the positive side due to the voltage VssL across the common source inductance. When the jump voltage VgsL becomes equal to or higher than the gate threshold voltage, the upper and lower arms are turned on at the same time, and the element is destroyed due to the short circuit current.

On the other hand, when the clamp line has a series resistance Rc (clamp resistance circuit), the clamp line voltage VcL is affected by the series resistance Rc and jumps to the negative side in the same phase with respect to VssL. Since the gate vibration VgsL of the anti-arm is defined by VcL-VssL, the positive peak caused by the common source can be reduced (cancelled) by increasing the jump voltage VcL caused by the clamp line series resistance Rc, and the error is turned on. Has a preventive effect.

Even in the turn-off operation, in the present embodiment in which the clamp line series resistance is connected to the clamp SW, the gate vibration caused by the mirror current increases, while the gate vibration caused by the common source inductance can be reduced.

As described above, according to the first embodiment of the present invention, it is possible to reduce the gate voltage vibration of the non-drive arm due to the common source inductance in the turn-on and turn-off operations. That is, according to the present embodiment, it is possible to suppress the gate voltage vibration associated with the high-speed drive of the power device.

(Second embodiment)
FIG. 9 shows a single-phase bridge circuit according to a second embodiment of the present invention.

The single-phase bridge circuit of FIG. 9 includes two power semiconductor devices and a separate gate drive circuit.

The individual gate drive circuit includes a clamp SW (SWc) that connects the gate and the source when off, a clamp SW control circuit, a clamp resistance circuit (Rc) in series with the clamp SW, and the clamp resistance circuit in parallel. Includes diode Dc. In other words, the clamp circuit further comprises a diode Dc (first diode) connected in parallel to the clamp resistance circuit Rc (first resistor). In the example of FIG. 9, the cathode of the diode Dc (first diode) is connected to the gate of the lower arm device 30L (second power device).

In the configuration of FIG. 9, when the upper arm is turned on, the clamp switch SWc is in a conductive state. At this time, in the turn-on period, the mirror current due to the VdsL fluctuation (Ph2 period in FIG. 7B) and the gate current due to the voltage fluctuation VssL across the common source inductance due to the IsL fluctuation (Ph1 period in FIG. 7B) use the clamp resistance Rc. Via the clamp switch SWc, it is bypassed to the source. Therefore, the gate vibration on the negative side at the time of turn-on is reduced.

On the other hand, when the upper arm is turned off, the clamp switch SWc is in a conductive state. At this time, in the turn-off period, the mirror current due to the VdsL fluctuation (Ph1 period in FIG. 8) and the gate current due to the voltage fluctuation VssL across the common source inductance due to the IsL fluctuation (Ph2 period in FIG. 8) use the clamp diode Dc. Via the clamp switch SWc, it is bypassed to the source. Therefore, the gate vibration on the negative side is reduced even at the time of turn-off.

With the above configuration, the gate vibration on the negative side can be reduced for both turn-on and turn-off. Therefore, it is particularly effective when the negative gate withstand voltage of the power semiconductor device is small, and by suppressing the gate vibration on the negative side of the non-drive arm, the load on the gate oxide film can be reduced, and the length of the power semiconductor device can be reduced. It has the effect of extending the life.

(Third embodiment)
FIG. 10 shows a single-phase bridge circuit according to a third embodiment of the present invention.

The single-phase bridge circuit of FIG. 10 includes two power semiconductor devices and a separate gate drive circuit.

The individual gate drive circuit includes a clamp SW (SWc) that connects the gate and the source when off, a clamp SW control circuit, a clamp resistance circuit (Rc) in series with the clamp SW, and the clamp resistance circuit in parallel. Includes diode Dc.

In the example of FIG. 10, the anode of the diode Dc (first diode) is connected to the gate of the lower arm device 30L (second power device).

In the configuration of FIG. 10, when the upper arm is turned on, the clamp switch SWc is in a conductive state. At this time, in the turn-on period, the mirror current due to the VdsL fluctuation (Ph2 period in FIG. 7B) and the gate current due to the voltage fluctuation VssL across the common source inductance due to the IsL fluctuation (Ph1 period in FIG. 7B) use the clamp diode Dc. Via the clamp switch SWc, it is bypassed to the source. Therefore, the gate vibration on the positive side at the time of turn-on is reduced.

On the other hand, when the upper arm is turned off, the clamp switch SWc is in a conductive state. At this time, in the turn-off period, the mirror current due to the VdsL fluctuation (Ph1 period in FIG. 8) and the gate current due to the voltage fluctuation VssL across the common source inductance due to the IsL fluctuation (Ph2 period in FIG. 8) use the clamp resistance Rc. Via the clamp switch SWc, it is bypassed to the source. Therefore, the gate vibration on the positive side is reduced even at the time of turn-off.

With the above configuration, the gate vibration on the positive side can be reduced for both turn-on and turn-off. Therefore, it is particularly effective when the threshold voltage of the power semiconductor device is low, and it is due to the short-circuit current caused by the simultaneous on of the upper and lower arms by suppressing the gate vibration on the positive side in the non-drive arm. It is possible to prevent element destruction.

(Fourth Embodiment)
FIG. 11 shows a single-phase bridge circuit according to a fourth embodiment of the present invention.

The single-phase bridge circuit of FIG. 11 includes two power semiconductor devices and a separate gate drive circuit. The individual gate drive circuits include a clamp SW (SWc) that connects the gate and the source when off, a clamp SW control circuit, a clamp resistance circuit (Rc1, Rc2) in series with the clamp SW, and the clamp resistance circuit. Includes series clamp diodes (Dc1, Dc2).

The clamp circuit consists of a clamp diode Dc1 (first diode) connected in series to the clamp resistance circuit Rc1 (first resistor) and a clamp resistance circuit Rc2 (second resistor) connected in series to the clamp switch SWc (switching element). A resistor) and a clamp diode Dc2 (second diode) connected in series to the clamp resistance circuit Rc2 are further provided. In the example of FIG. 11, the anode of the clamp diode Dc1 is connected to the gate of the lower arm device 30L, and the cathode of the clamp diode Dc2 is connected to the gate of the lower arm device 30L.

In the configuration of FIG. 11, when the upper arm is turned on, the mirror current due to VdsL fluctuation (Ph2 period in FIG. 7B) and the gate current due to the voltage fluctuation VssL across the common source inductance due to IsL fluctuation (Ph1 period in FIG. 7B). Is bypassed to the source by the clamp switch SWc via the clamp diode Dc1 and the clamp resistor Rc1.

On the other hand, when the upper arm is turned off, the mirror current due to VdsL fluctuation (Ph1 period in FIG. 8) and the gate current due to the voltage fluctuation VssL across the common source inductance due to IsL fluctuation (Ph2 period in FIG. 8) are clamp resistance Rc2. Then, it is bypassed to the source by the clamp switch SWc via the clamp diode Dc2.

With the above configuration, the clamp line voltage VcL can be adjusted individually for turn-on and turn-off. Gate vibration due to common source inductance can be individually reduced according to the switching speed at turn-off and turn-on.

(Fifth Embodiment)
FIG. 12 shows a single-phase bridge circuit according to a fifth embodiment of the present invention.

The single-phase bridge circuit of FIG. 12 includes two power semiconductor devices and a separate gate drive circuit. The individual gate drive circuits include a clamp SW (SWc) that connects the gate and the source at the time of off, a gate capacitance charge current adjustment resistor Rgon at the time of turn-on, a gate capacitance discharge current adjustment resistor Rgoff at the time of turn-off, and a gate drive. Includes circuit BUF.

According to this embodiment, the wiring inductance Lp2 from the power semiconductor device to the clamp circuit is mounted so as to be smaller than the wiring inductance Lp1 from the power semiconductor device to the gate drive circuit.

As shown in FIG. 12, the inductance Lp2 of the clamp circuit wiring indicating the wiring connecting the gate of the lower arm device 30L (second power device) and the clamp circuit is that of the lower arm device 30L (second power device). It is smaller than the inductance Lp1 of the drive circuit wiring indicating the wiring connecting the gate and the gate drive circuit.

By making the clamp circuit wiring inductance Lp2 smaller than the drive circuit wiring inductance Lp1, the gate current flowing through the drive circuit resistance Rgon / Rgoff can be reduced in the non-drive arm, and the gate vibration of the non-drive arm can be reduced.

(Sixth Embodiment)
FIG. 13 is a diagram showing an example of a circuit configuration of a power converter (power converter) to which the present invention is applied.

Comparing FIG. 13 with the circuit configuration of the first embodiment shown in FIG. 2, in the example of FIG. 13, the DC link capacitor of FIG. 2 is composed of two capacitors 601 and a capacitor 602 connected in series with each other, and is a capacitor. The connection points between 601 and 602 are connected to the R, S, and T terminals via the capacitor 2100 (first AC filter capacitor) connected to the AC power supply side, and the output side of the inverter 103 (load 108). It is connected to the U, V, and W terminals via the capacitor 2000 (second AC filter capacitor) connected to the side).

The connection points between the capacitors 601 and 602 are connected to the capacitors 2000 and 2100, and have an intermediate potential of 4000. Further, the reactor 406A is connected to the connection midpoint (connection point) between the upper arm switching element 104-1B and the lower arm switching element 104-2B of the chopper 104, and the upper arm switching element 104-1A and the lower arm switching element 104- Reactor 406B is connected to the connection midpoint with 2A.

FIG. 14 is a diagram showing a layout (top view) in which the circuit of the power conversion device of FIG. 13 is mounted on a substrate.

The DC link capacitor 600 is arranged on the upstream side (upwind side) of the cooling air of the converter 102 and the inverter 103, and the DCAC reactor 800 is arranged on the downstream side (downwind side) of the chopper 104.

Due to this configuration, the DC link capacitor 600 is arranged on the upstream side of the cooling air of the converter 102 and the inverter 103, so that the influence of heat generation (effect of tilting heat) due to the operation of the converter 102 and the inverter 103 on the DC link capacitor 600 can be seen. Can be removed. Furthermore, since the converter and the chopper do not generate maximum heat at the same time, it is possible to reduce the heat generated between the converter and the chopper.

Further, since the DCAC reactor 800 is arranged on the downstream side of the cooling air of the converter 102, the inverter 103 and the chopper 104, the influence of heat generation (the influence of the tilting heat) on the converter 102, the inverter 103 and the chopper 104 by the DCAC reactor 800 is removed. be able to.

Gate drive circuits 102U1D, 102U2D, 102V1D, 102V2D, 102W1D and 102W2D (converter control unit (power conversion unit drive unit) 204) for driving the power devices 30 of the converters 102U, 102V and 102W are placed in the vicinity of the respective power devices 30. Deploy.

The converter 102 has two pairs of the power device 30 and the cooling fins 40 for each of the U phase, the V phase, and the W phase, but the U phase and the V phase are arranged at positions adjacent to each other. In the pair of the power device 30 and the cooling fin 40, the respective power devices 30 are arranged to face each other, and the gate drive circuits 102U2D and 102V1D are arranged to face each other. Further, in the pair of the power device 30 and the cooling fins 40 in which the V phase and the W phase are arranged adjacent to each other, the respective power devices 30 are arranged so as to face each other, and the gate drive circuits 102V2D and 102W1D are arranged. Are arranged facing each other.

Further, the gate drive circuits 103U1D, 103U2D, 103V1D, 103V2D, 103W1D and 103W2D (inverter control unit (power conversion unit drive unit) 304) for driving the power devices 30 of the inverters 103U, 103V and 103W are used in the respective power devices 30. Place it in the vicinity. The inverter 103 has two pairs of the power device 30 and the cooling fins 40 for each of the U phase, the V phase, and the W phase, but the U phase and the V phase are arranged at positions adjacent to each other. In the pair of the power device 30 and the cooling fin 40, the respective power devices 30 are arranged to face each other, and the gate drive circuits 103U2D and 103V1D are arranged to face each other. Further, in the pair of the power device 30 and the cooling fins 40 in which the V phase and the W phase are arranged adjacent to each other, the respective power devices 30 are arranged so as to face each other, and the gate drive circuits 103V2D and 103W1D are arranged. Are arranged facing each other.

The W phase of the converter 102 and the U phase of the inverter 103 are arranged adjacent to each other, and in the pair of the power device 30 and the cooling fins 40 arranged at positions adjacent to each other, the respective power devices 30 are arranged with each other. The gate drive circuits 102W2D and 103U1D are arranged to face each other and face each other.

Further, the gate drive circuits 104-1D1, 104-1D2, 104-2D1 and 104-2D2 (chopper control unit (power conversion unit drive unit) 405) for driving the power devices 30 of the choppers 104-1 and 104-2 are provided. It is arranged in the vicinity of each power device 30.

The chopper 104 has a set of a power device 30 and a cooling fin 40, and each of the choppers 104-1 and 104-2 has two sets. In the pair of the power device 30 and the cooling fins 40 in which the choppers 104-1 and 104-2 are arranged adjacent to each other, the power devices 30 are arranged so as to face each other, and the gate drive circuit 104- 1D2 and 104-2D1 are arranged so as to face each other.

According to this configuration, since the power device 30 and its gate drive circuit (102U1D to 102W1D, 103U1D to 103W2D, 104-1D1 to 104-2D2) are arranged close to each other, the wiring inductance of the gate drive circuit is reduced and unnecessary. Resonance can be suppressed and the power device 30 can be driven at high speed.

(7th Embodiment)
FIG. 15 is a diagram showing an example of a wiring layout in the circuit configuration shown in FIG.

The wiring example shown in FIG. 15 is an L1 layer (AC wiring of the converter 102 and the inverter 103), an L2 layer (P pole wiring), an L3 layer (N pole wiring), and an L4 layer (AC wiring of the chopper 104, intermediate). It has a multi-layered structure (intermediate electrode wiring with a potential of 4000). In other words, the power conversion device 100 includes a multilayer substrate including at least a first layer, a second layer, and a third layer in order from the surface.

As shown in FIG. 15A, wiring 1021, 1022, 1023 of the converter 102 is formed in the L1 layer. Further, AC wiring 1031, 1032, 1033 of the inverter 103 is formed.

That is, the AC wirings (1031, 1032, 1033) indicating the wirings connected to the AC side terminals (U, V, W) of the power conversion device 100 are arranged in the L1 layer (first layer). This makes it possible to improve the cooling efficiency of the AC wiring.

Further, as shown in FIG. 15B, the P pole wiring 3000P is formed in the L2 layer. That is, the P pole wiring 3000P indicating the wiring connected to the DC positive terminal (P) of the power conversion device 100 is arranged on one of the L2 layer (second layer) and the L3 layer (third layer).

Further, as shown in FIG. 15C, N-pole wiring 2000N is formed in the L3 layer. That is, the N-pole wiring 2000N indicating the wiring connected to the DC negative terminal (N) of the power conversion device 100 is arranged on the other side of the L2 layer (second layer) and the L3 layer (third layer).

Further, as shown in FIG. 15D, in the L4 layer, chopper AC wirings 1041 and 1042 are formed, and intermediate potential wiring 4000L is formed.

FIG. 16 is a cross-sectional view (schematic diagram) along the line BB'of FIG. 15A.

In FIG. 16, the gate drive wiring 5000GL4 and the AC intermediate potential wiring 5000ML4 are formed in the L4 layer, and the gate drive wiring 5000GL3 and the N pole wiring 5000ML3 are formed in the L3 layer.

Further, the L2 layer is formed with the gate drive wiring 5000GL2 and the P pole wiring 5000ML2, and the L1 layer is formed with the gate drive wiring 5000GL1 and the AC wiring 5000ML1.

An insulating layer 5000I is arranged between the layers to insulate each other. Further, a via 6200 is formed through the L1 layer to the L4 layer, and a lead 6100 is arranged in the via 6200. Above the L1 layer, a lower arm device 30L and an upper arm device 30H connected to the lead 6100 are connected. Further, a gate drive circuit and a gate clamp circuit (clamp circuit) are arranged above the gate drive wiring 5000GL1 of the L1 layer.

With the above configuration, the gate drive wiring 5000G and the main circuit wiring 5000M can be separated in the layer direction to reduce noise. Further, by forming the main circuit wiring 5000M into a multi-layer wiring structure (laminated wiring structure), it is possible to reduce the inductance and suppress the jumping of the main circuit voltage due to the switching operation.

Further, in the wiring configuration of FIG. 16, the source lead of the power device and the source wiring of the gate drive circuit are connected by the L1 layer. In other words, the gate source wiring indicating the wiring connecting the gate drive circuit 50L and the source of the lower arm device 30L (second power device) is arranged in the L1 layer (first layer). With this configuration, the common source inductance LCM can be reduced, and the gate vibration caused by the common source inductance can be reduced in the non-drive arm.

Further, as shown in the wiring configuration of FIG. 16, the source wiring of the gate drive circuit is wired with Lp1, the gate wiring of the gate drive circuit is wired with Lp2, and both have a laminated structure to reduce the wiring inductance of the gate drive circuit. It can be reduced and the gate vibration in the non-drive arm can be reduced.

The present invention is not limited to the above-described embodiment, and includes various modifications. For example, the above-described embodiments have been described in detail in order to explain the present invention in an easy-to-understand manner, and are not necessarily limited to those having all the described configurations. Further, it is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. Further, it is possible to add / delete / replace a part of the configuration of each embodiment with another configuration.

20 ... Half bridge circuits 21, 22 ... Switching elements 23, 24 ... Rectifier elements 25, 26 ... Condenser 30 ... Power device 30H ... Upper arm device 30L ... Lower arm device 40 ... Cooling fins 50H, 50L ... Gate drive circuit 100 ... Power converter 102 ... Converter 102U ... Converter 102U1D ... Gate drive circuit 102U2D ... Gate drive circuit 102V ... Converter 102V1D ... Gate drive circuit 102V2D ... Gate drive circuit 102W ... Converter 102W1D ...
102W1D ... Gate drive circuit 102W2D ... Gate drive circuit 103 ... Inverter 103U ... Inverter 103U1D ... Gate drive circuit 103U2D ... Gate drive circuit 103V ... Inverter 103V1D ... Gate drive circuit 103V2D ... Gate drive circuit 103W ... Inverter 103W1D ... Gate drive circuit 104 ... Chopper 104-1 ... Chopper 104-1A ... Upper arm switching element 104-1B ... Upper arm switching element 104-1D1 ... Gate drive circuit 104-1D2 ... Gate drive circuit 104-2 ... Chopper 104-2A ... Lower arm switching element 104-2B ... Lower arm switching element 104-2D1 ... Gate drive circuit 104-2D2 ... Gate drive circuit 105 ... Upper control circuit 106 ... Commercial power supply (AC power supply)
107 ... Storage battery (DC power supply)
108 ... Load 201 ... Half bridge circuit 202 ... Half bridge circuit 203 ... Half bridge circuit 204 ... Converter control unit (power conversion unit drive unit)
301 ... Half-bridge circuit 302 ... Half-bridge circuit 303 ... Half-bridge circuit 304 ... Inverter control unit (power conversion unit drive unit)
401 ... Half bridge circuit 405 ... Chopper control unit (power conversion unit drive unit)
406 ... Reactor 406A ... Reactor 406B ... Reactor 600 ... Link capacitor 601 ... Capacitor 602 ... Condenser 800 ... Reactor 2000 ... Capacitor 2100 ... Condenser 5000I ... Insulation layer 6100 ... Lead 6200 ... Via

Claims (9)

A bridge circuit including a first power device and a second power device connected in series with the first power device.
A gate drive circuit that charges and discharges the capacity of the gate of the second power device, and
When the voltage between the gate and the source of the second power device is smaller than a predetermined value, a clamp circuit for conducting the gate of the second power device and the source of the second power device is provided.
The clamp circuit is
A power conversion device comprising a switching element, a first resistor connected in series to the switching element, and a first diode connected in parallel to the first resistor . The power conversion device according to claim 1 .
The cathode of the first diode is
A power conversion device characterized by being connected to the gate of the second power device. The power conversion device according to claim 1 .
The anode of the first diode is
A power conversion device characterized by being connected to the gate of the second power device. A bridge circuit including a first power device and a second power device connected in series to the first power device, a gate drive circuit for charging and discharging the capacity of the gate of the second power device, and a gate of the second power device. When the voltage between the sources is smaller than a predetermined value, the clamp circuit comprises a clamp circuit that conducts the gate of the second power device and the source of the second power device, and the clamp circuit is in series with the switching element. A power conversion device composed of a connected first resistor .
The clamp circuit is
A first diode connected in series with the first resistance,
A second resistor connected in series to the switching element,
Further comprising a second diode connected in series with the second resistor.
The anode of the first diode is
Connected to the gate of the second power device,
The cathode of the second diode is
A power conversion device characterized by being connected to the gate of the second power device. The power conversion device according to claim 1.
The inductance Lp2 of the clamp circuit wiring , which is the wiring connecting the gate of the second power device and the clamp circuit, is the drive circuit wiring which is the wiring connecting the gate of the second power device and the gate drive circuit. A power conversion device characterized by having an inductance smaller than that of Lp1. The power conversion device according to claim 5 .
The side on which the power device is mounted is the surface,
Further, a multilayer substrate containing at least a first layer and a second layer in order from the surface is provided.
A power conversion device characterized in that the gate source wiring , which is wiring connecting the gate drive circuit and the source of the second power device, is arranged in the first layer. The power conversion device according to claim 6 .
The multilayer board is a multilayer board including at least a first layer, a second layer, and a third layer.
A power conversion device characterized in that the AC wiring , which is the wiring connected to the AC side terminal of the power conversion device, is arranged in the first layer. The power conversion device according to claim 7 .
The P pole wiring , which is the wiring connected to the DC positive terminal of the power conversion device, is
Arranged in one of the second layer and the third layer,
The N-pole wiring , which is the wiring connected to the negative DC terminal of the power conversion device, is
Arranged on the other side of the second layer and the third layer
A power conversion device characterized by that. The power conversion device according to claim 1.
The switching element is
A power conversion device characterized by being a bidirectional switching element that can flow current in both directions when it is on.

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