JP7011013B2 - 並列ビットインターリーバ - Google Patents
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- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
- H03M13/116—Quasi-cyclic LDPC [QC-LDPC] codes, i.e. the parity-check matrix being composed of permutation or circulant sub-matrices
- H03M13/1165—QC-LDPC codes as defined for the digital video broadcasting [DVB] specifications, e.g. DVB-Satellite [DVB-S2]
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- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
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- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
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- H03M13/25—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM]
- H03M13/255—Error detection or forward error correction by signal space coding, i.e. adding redundancy in the signal constellation, e.g. Trellis Coded Modulation [TCM] with Low Density Parity Check [LDPC] codes
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- H03M13/27—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques
- H03M13/2703—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes using interleaving techniques the interleaver involving at least two directions
- H03M13/271—Row-column interleaver with permutations, e.g. block interleaving with inter-row, inter-column, intra-row or intra-column permutations
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- H—ELECTRICITY
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
- H03M13/2957—Turbo codes and decoding
- H03M13/296—Particular turbo code structure
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/35—Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
- H03M13/356—Unequal error protection [UEP]
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- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6522—Intended application, e.g. transmission or communication standard
- H03M13/6552—DVB-T2
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0041—Arrangements at the transmitter end
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- H—ELECTRICITY
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0045—Arrangements at the receiver end
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0057—Block codes
- H04L1/0058—Block-coded modulation
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0061—Error detection codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
- H04L1/0056—Systems characterized by the type of code used
- H04L1/0071—Use of interleaving
Description
図1は、一般的なビットインターリーブ符号化変調(bit-interleaved coding and modulation:BICM)エンコーダを含むトランスミッタの構成を示すブロック図である。図1に示すトランスミッタ100は、入力プロセシングユニット110、BICMエンコーダ(低密度パリティチェック(low-density parity check:LDPC)エンコーダ120、ビットインターリーバ130、コンステレーションマッパ140を含む)、およびモジュレータ150を備える。
1つのLDPC符号語の巡回ブロック数:N=12
1つのコンステレーションのビット数:M=4、即ち16QAM
上記パラメータでは、1つのLDPC符号語がマッピングされるコンステレーション数はQ×N/M=24である。通常、パラメータQおよびNの選択は、システムがサポートする全てのコンステレーションについて、Q×NがMの倍数となるように行われなければならない。
16QAMの場合、4050セル
64QAMの場合、2700セル
256QAMの場合、2025セル
上記の表1によると、QPSKより大きなコンステレーションについては、並列ストリームの数はカラム‐ロウインターリーバの列数に等しい。16K LDPC符号について、16QAMコンステレーション、64QAMコンステレーション、256QAMコンステレーションに対応するビット‐セルデマルチプレクサを、それぞれ、図11、図12、図13に示す。なお、ビットの表記はDVB-T2規格で用いられているものである。
発明者は、鋭意研究を行った結果、以下の2つの条件が満たされるとき、非常に効率的なインターリーバが提供できるという知見を得た。
各コンステレーション語のM個のビットが、LDPC符号語のM個の異なる巡回ブロックにマッピングされる。これは、LDPC符号語のM個の異なる巡回ブロックから1ビットずつコンステレーション語にマッピングする、ことと等価である。この概要を図18(a)に示す。
M個の巡回ブロックにマッピングされるすべてのコンステレーション語が、当該M個の巡回ブロックのみにマッピングされる。これは、QビットからなるM個の異なる巡回ブロックのM×Q個のビットの全ては、Q個のコンステレーション語にのみマッピングされる、ことと等価である。この概要を図18(b)に示す。
以下、上記の条件1、条件2を満たすビットインターリーバ(並列ビットインターリーバ)の詳細について説明する。なお、以下において、実質的に同じ処理内容、および、同じ処理内容を行う構成ユニットには同じ符号を付す。
ステージB:巡回ブロック内パーミュテーション
ステージC:カラム‐ロウパーミュテーション
ここで、巡回ブロック(間)パーミュテーションは符号語を構成するN個の巡回ブロックの並び順を換えるパーミュテーションであり、巡回ブロック内パーミュテーションは巡回ブロックを構成するQ個のビットの並び順を換えるパーミュテーションであり、カラム‐ロウパーミュテーションは、セクションを構成するM×Q個のビットの並び順を換えるパーミュテーションである。
p(b=0)はビットbが0である確率を示し、p(b=1)はビットbが1である確率を示す。ただし、p(b=0)+p(b=1)=1が成り立つ。
本発明は上記の実施の形態で説明した内容に限定されず、本発明の目的とそれに関連又は付随する目的を達成するためのいかなる形態においても実施可能であり、例えば、以下であってもよい。
本発明に係るビットインターリーブ方法、ビットインターリーバ、ビットデインターリーブ方法、ビットデインターリーバ、およびデコーダとその効果について説明する。
2010 ビットパーミュテーションユニット
2021~2023 セクションパーミュテーションユニット
2101、2201 ビットパーミュテーションユニット
2111~2122 巡回ブロック内パーミュテーションユニット
2131~2133 カラム‐ロウパーミュテーションユニット
2310 巡回ブロックパーミュテーションユニット
2500 トランスミッタ
2510 LDPCエンコーダ
2520 ビットインターリーバ
2530 コンステレーションマッパ
2700、2800 レシーバ
2710 コンステレーションデマッパ
2720 ビットデインターリーバ
2730 LDPCデコーダ
2740 減算ユニット
2750 ビットインターリーバ
Claims (2)
- リピートアキュミュレート疑似巡回低密度パリティチェック符号化方式を含む疑似巡回低密度パリティチェック符号化方式で生成された符号語を送信する送信方法であって、
それぞれがQ個のビットからなるN個の巡回ブロックで構成されるN×Qビットの前記符号語に対して、前記巡回ブロックの並び替えを規定した巡回ブロックパーミュテーション規則に従って前記巡回ブロック単位の並び替えを行う巡回ブロックパーミュテーション処理を施す巡回ブロックパーミュテーションステップと、
前記巡回ブロックパーミュテーション処理が施された前記符号語に対して、各前記巡回ブロックのQ個のビットをM行の行列のうちの一つの行の行方向に書き込み、列方向に読み出すことと等価なカラム-ロウパーミュテーション処理を施すビットパーミュテーションステップと、
前記カラム-ロウパーミュテーション処理が施された符号語を、それぞれがM個のビットよりなる複数のコンステレーション語に分割する分割ステップと、
前記分割ステップで分割された前記符号語を、前記コンステレーション語にマッピングするマッピングステップと、
前記符号語がマッピングされた前記コンステレーション語に対してOFDM(Orthogonal Frequency Division Multiplexing)変調を行って送信信号を生成する信号生成ステップと、
を有し、
前記Nは前記Mの倍数であり、
前記マッピングの方式は、QPSKを含む
ことを特徴とする送信方法。 - リピートアキュミュレート疑似巡回低密度パリティチェック符号化方式を含む疑似巡回低密度パリティチェック符号化方式で生成された符号語であって、それぞれがQ個のビットからなるN個の巡回ブロックで構成される符号語のビットの並び替え処理を行い、M個のビットずつ分割し、コンステレーション語にマッピングして生成されるN×Q/M個のコンステレーション語を変調して送信された信号を処理する信号処理方法であって、
前記ビットの並び替え処理は、
前記巡回ブロックの並び替えを規定した巡回ブロックパーミュテーション規則に従う前記符号語の前記巡回ブロック単位の並び替えを行う巡回ブロックパーミュテーション処理と、
各前記巡回ブロックのQ個のビットをM行の行列のうちの一つの行の行方向に書き込み、列方向に読み出すことと等価なカラム-ロウパーミュテーション規則に従う前記巡回ブロックパーミュテーション処理が施された前記符号語のビットの並び替えを行うビットパーミュテーション処理と、
を含み、
前記Nは前記Mの倍数であり、
前記信号処理方法は、
送信された信号に対してOFDM(Orthogonal Frequency Division Multiplexing)に基づく復調を行うことで前記符号語がマッピングされた前記N×Q/M個のコンステレーション語を生成する生成ステップと、
前記N×Q/M個のコンステレーション語を復調することで復調信号を生成する復調ステップと、
前記巡回ブロックパーミュテーション規則及び前記カラム-ロウパーミュテーション規則に基づいて前記復調信号をデコードして、前記疑似巡回低密度パリティチェック符号化方式による符号化前のデータを生成するデコードステップと、
を有し、
前記復調ステップにおいて、QPSKに対応する復調を行う
ことを特徴とする信号処理方法。
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EP2525498A1 (en) | 2011-05-18 | 2012-11-21 | Panasonic Corporation | Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes |
EP2525497A1 (en) | 2011-05-18 | 2012-11-21 | Panasonic Corporation | Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes |
EP2525496A1 (en) | 2011-05-18 | 2012-11-21 | Panasonic Corporation | Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes |
EP2525495A1 (en) | 2011-05-18 | 2012-11-21 | Panasonic Corporation | Bit-interleaved coding and modulation (BICM) with quasi-cyclic LDPC codes |
EP2552043A1 (en) * | 2011-07-25 | 2013-01-30 | Panasonic Corporation | Spatial multiplexing for bit-interleaved coding and modulation with quasi-cyclic LDPC codes |
US9654316B2 (en) * | 2012-07-27 | 2017-05-16 | Sun Patent Trust | Transmission method, transmitter, reception method, and receiver |
US9735809B2 (en) * | 2013-09-26 | 2017-08-15 | Samsung Electronics Co., Ltd. | Transmitting apparatus and signal processing method thereof |
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