JP6954237B2 - 半導体装置 - Google Patents
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- 238000001514 detection method Methods 0.000 claims description 61
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- 229910052785 arsenic Inorganic materials 0.000 description 3
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 3
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Description
本発明は、上記課題に鑑みてなされたものであり、その目的は、ノイズによる誤動作を低減できる半導体装置を提供することにある。
図1から図3に示すように、半導体装置1は、温度検出素子20及びスイッチング素子40を備えている。図1において、温度検出素子20の左側はアノード側A、右側はカソード側Kとする。半導体装置1にはVf測定装置42が接続されている。実施形態では、温度検出素子20は複数のpn接合ダイオードからなる感温ダイオードにより構成されている。Vfは温度検出素子20を構成するダイオード201から204の順電圧である。
容量値Ca+容量値Cacap>容量値Cdi ・・・(1)
第1実施形態において、温度検出素子20のアノード側Aにおいて、容量電極22aにより構成されたアノード容量22と、アノードパッド24aにより構成されたアノードパッド容量24との容量値の和(容量値Ca+容量値Cacap)が、温度検出素子20と半導体基板10との間に構成されるダイオード下容量30の容量値(容量値Cdi)よりも大きくなるように構成されている。すなわち、温度検出素子20直下に比較して、アノード側A直下のインピーダンスが小さく構成されている。これにより、温度検出素子20に入力されるノイズを低減することができる。
容量値Ck+容量値Ckcap>容量値Cdi ・・・(2)
この場合でも同様の効果を奏する。
次に、第2実施形態にかかる半導体装置1について説明する。図6、及び図7に示すように、第2実施形態においては、アノード側Aのアノード容量55が、アクティブ領域60に形成されている。より詳細には、アノード容量55を構成する容量電極55aが、アクティブ領域60における酸化膜60a上に形成されている。
次に、第3実施形態にかかる半導体装置1について説明する。図8に示すように、第3実施形態においては、アノード側Aのアノードパッド容量62において、アノードパッド62aと素子分離絶縁膜12との間に形成される絶縁物として、高誘電体物質64を設けた。このため、アノードパッド62aと半導体基板10との間に誘電率が高い高誘電体物質64が狭在するため、アノードパッド容量62の容量値を大きくすることができる。
次に、第4実施形態にかかる半導体装置1について説明する。図9に示すように、第3実施形態においては、アノード側Aのアノードパッド容量66において、アノードパッド66aと素子分離絶縁膜12との間に形成される酸化膜の膜厚を小さくした。具体的には、アノードパッド66aを素子分離絶縁膜12上に配置するようにした。このため、アノードパッド66aと半導体基板10との間の距離が小さくなるため、アノードパッド容量66の容量値を大きくすることができる。すなわち、温度検出素子20直下に比較して、アノード側A直下のインピーダンスが小さく構成されている。
次に、第5実施形態にかかる半導体装置1について説明する。温度検出素子20のアノード側Aの容量電極22a下方、アノードパッド24a下方、及びカソード側Kの容量電極26a下方、及びカソードパッド28a下方の半導体基板10において、第1実施形態では低濃度不純物領域10aが設けられていたところ、第5実施形態においては図10に示すように、高濃度不純物領域70、72が形成されている点において異なる。
Claims (6)
- 半導体基板(10)と、
前記半導体基板に設けられた絶縁膜(12、14、60a、64、68)と、
前記絶縁膜上に設けられた温度検出素子(20)と、前記温度検出素子のアノード側(A)、又はカソード側(K)に設けられた容量素子(22,24、26、28、55)と、を備え、
アノード側、又はカソード側の前記容量素子の容量値の和は、前記温度検出素子の容量値(Cdi)よりも大きい半導体装置。 - 前記温度検出素子のアノード側、又は、カソード側の一方側には、温度検出素子を構成する半導体と同層の半導体(22a、26a)と前記半導体基板との間で構成される第1容量素子(22,26)と、前記第1容量素子に接続される電極パッド(24a、28a)と前記半導体基板との間で構成される第2容量素子(24、28)と、が接続され、
前記温度検出素子のアノード側、又は、カソード側の一方側の前記第2容量素子の電極パッドは、他方側の第2容量素子の電極パッドよりも面積が大きい請求項1に記載の半導体装置。 - 前記温度検出素子のアノード側、又は、カソード側の一方側には、温度検出素子を構成する半導体と同層の半導体(22a、26a)と前記半導体基板との間で構成される第1容量素子(22,26)と、前記第1容量素子に接続される電極パッド(24a、28a)と前記半導体基板との間で構成される第2容量素子(24、28)と、が接続され、
前記アノード側、もしくは、カソード側の少なくとも一方の前記第1容量素子の容量値と前記第2容量素子の容量値を加えた容量値は、前記温度検出素子と前記半導体基板との間に構成される容量値よりも大きい請求項1又は2記載の半導体装置。 - 少なくとも、前記アノード側には、前記温度検出素子を構成する半導体と同層の半導体で構成される第1容量素子と、前記容量素子に接続される電極パッドにより構成される第2容量素子とを備える請求項1に記載の半導体装置。
- 半導体基板(10)と、
前記半導体基板に設けられた絶縁膜(12、14、60a、64、68)と、
前記絶縁膜上に設けられた温度検出素子(20)と、を備え、
前記温度検出素子のアノード側(A)の下方の前記半導体基板の抵抗値、又はカソード側(K)の下方の前記半導体基板の抵抗値は、前記温度検出素子の下方の前記半導体基板の抵抗値より小さい半導体装置。 - 半導体基板(10)と、
前記半導体基板に設けられた絶縁膜(12、14、60a、64、68)と、
前記絶縁膜上に設けられた温度検出素子(20)と、を備え、
前記温度検出素子のアノード側(A)の下方のインピーダンス、又はカソード側(K)の下方のインピーダンスは、前記温度検出素子の下方のインピーダンスより小さい半導体装置。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2018127563A JP6954237B2 (ja) | 2018-07-04 | 2018-07-04 | 半導体装置 |
PCT/JP2019/018394 WO2020008721A1 (ja) | 2018-07-04 | 2019-05-08 | 半導体装置 |
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