JP6934322B2 - Electronic components - Google Patents

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JP6934322B2
JP6934322B2 JP2017104118A JP2017104118A JP6934322B2 JP 6934322 B2 JP6934322 B2 JP 6934322B2 JP 2017104118 A JP2017104118 A JP 2017104118A JP 2017104118 A JP2017104118 A JP 2017104118A JP 6934322 B2 JP6934322 B2 JP 6934322B2
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substrate
insulating film
functional element
functional elements
functional
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JP2018201083A (en
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秀太郎 中澤
秀太郎 中澤
松田 隆志
隆志 松田
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Taiyo Yuden Co Ltd
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Taiyo Yuden Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1517Multilayer substrate
    • H01L2924/15172Fan-out arrangement of the internal vias
    • H01L2924/15174Fan-out arrangement of the internal vias in different layers of the multilayer substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

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  • Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
  • Piezo-Electric Or Mechanical Vibrators, Or Delay Or Filter Circuits (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Description

本発明は、電子部品に関し、例えば基板上に機能素子を有する基板が実装された電子部品に関する。 The present invention relates to an electronic component, for example, an electronic component in which a substrate having a functional element is mounted on the substrate.

圧電薄膜共振器(FBAR:Film Bulk Acoustic Resonator)または弾性表面波(SAW:Surface Acoustic Wave)共振器等の弾性波素子は、携帯電話に代表される45MHzから4GHzの周波数帯の無線信号を処理する各種回路におけるバンドパスフィルタ等に用いられる。このような弾性波素子等の機能素子の実装方法として、基板上に下面に機能素子を有するチップをフリップチップ実装することが知られている(例えば特許文献1および2)。 A surface acoustic wave element such as a piezoelectric thin film resonator (FBAR) or a surface acoustic wave (SAW) resonator processes a radio signal in the frequency band of 45 MHz to 4 GHz represented by a mobile phone. It is used as a band path filter in various circuits. As a method for mounting a functional element such as an elastic wave element, it is known that a chip having a functional element on the lower surface is flip-chip mounted on a substrate (for example, Patent Documents 1 and 2).

特開2010−245739号公報JP-A-2010-245739 特開2006−203149号公報Japanese Unexamined Patent Publication No. 2006-203149

例えば弾性波素子等を有する電子部品は、携帯電話やスマートフォン等の多機能化に伴い、小型化が求められている。一方、電波を送信するためのパワーアンプのハイパワー化に伴い、高耐電力化が求められている。電子部品の小型化かつ高耐電力化のため、機能素子からの放熱性を高めることが考えられる。しかしながら、機能素子が空隙を介し基板の上面に対向していると、機能素子の下面から放熱することができない。 For example, electronic components having elastic wave elements and the like are required to be miniaturized as mobile phones, smartphones and the like become multifunctional. On the other hand, with the increase in power of power amplifiers for transmitting radio waves, high power withstand is required. In order to reduce the size of electronic components and increase the power resistance, it is conceivable to improve heat dissipation from functional elements. However, if the functional element faces the upper surface of the substrate through the gap, heat cannot be dissipated from the lower surface of the functional element.

本発明は、上記課題に鑑みなされたものであり、機能素子からの放熱性を向上させることを目的とする。 The present invention has been made in view of the above problems, and an object of the present invention is to improve heat dissipation from a functional element.

本発明は、第1面を有する第1基板と、1または複数の第1機能素子が設けられた第2面を有し、前記1または複数の第1機能素子が前記第1面と空隙を挟み対向するように、前記第1基板上に実装された第2基板と、前記第1面と前記第2面との間に設けられ、前記第1基板と前記第2基板とを接続する接続端子と、前記第1面および前記第2面のいずれか一方に設けられ、平面視において前記1または複数の第1機能素子のうち少なくとも1つの第1機能素子を囲み、前記少なくとも1つの第1機能素子との距離が前記接続端子と前記少なくとも1つの第1機能素子との距離より小さく、少なくとも一部が前記空隙を挟み前記第1面および前記第2面の他方と対向する第3面を有する絶縁膜と、を具備し、前記第1面と前記第2面との間において、前記第1面および前記第2面の両方に接触し前記第1機能素子を前記空隙に封止する封止部は設けられていない電子部品である。
The present invention has a first substrate having a first surface and a second surface provided with one or more first functional elements, and the one or more first functional elements have a gap with the first surface. A connection provided between a second substrate mounted on the first substrate and the first surface and the second surface so as to sandwich and face each other, and to connect the first substrate and the second substrate. A terminal and one of the first surface and the second surface are provided to surround at least one first functional element of the one or a plurality of first functional elements in a plan view, and the at least one first functional element is surrounded. The distance to the functional element is smaller than the distance between the connection terminal and the at least one first functional element, and at least a part of the third surface facing the first surface and the other of the second surface sandwiches the gap. A seal having an insulating film and having contact with both the first surface and the second surface between the first surface and the second surface to seal the first functional element in the gap. The stop is an electronic component that is not provided.

上記構成において、前記1または複数の第1機能素子は複数の第1機能素子であり、平面視において前記絶縁膜は前記複数の第1機能素子を各々囲む構成とすることができる。 In the above configuration, the one or a plurality of first functional elements are a plurality of first functional elements, and the insulating film may be configured to surround the plurality of first functional elements in a plan view.

本発明は、第1面を有する第1基板と、1または複数の第1機能素子が設けられた第2面を有し、前記1または複数の第1機能素子が前記第1面と空隙を挟み対向するように、前記第1基板上に実装された第2基板と、前記第1面と前記第2面との間に設けられ、前記第1基板と前記第2基板とを接続する接続端子と、前記第1面および前記第2面のいずれか一方に設けられ、平面視において前記1または複数の第1機能素子のうち少なくとも1つの第1機能素子を囲み、前記少なくとも1つの第1機能素子との距離が前記接続端子と前記少なくとも1つの第1機能素子との距離より小さく、少なくとも一部が前記空隙を挟み前記第1面および前記第2面の他方と対向する第3面を有する絶縁膜と、を具備し、前記1または複数の第1機能素子は複数の第1機能素子であり、平面視において、前記絶縁膜は、前記複数の第1機能素子のうち一部の第1機能素子を各々囲み、他の第1機能素子を囲まない電子部品である
The present invention has a first substrate having a first surface and a second surface provided with one or more first functional elements, and the one or more first functional elements have a gap with the first surface. A connection provided between a second substrate mounted on the first substrate and the first surface and the second surface so as to sandwich and face each other, and to connect the first substrate and the second substrate. A terminal and one of the first surface and the second surface are provided to surround at least one first functional element of the one or a plurality of first functional elements in a plan view, and the at least one first functional element is surrounded. The distance to the functional element is smaller than the distance between the connection terminal and the at least one first functional element, and at least a part of the third surface facing the first surface and the other of the second surface sandwiches the gap. The one or a plurality of first functional elements are a plurality of first functional elements, and the insulating film is a part of the first functional element among the plurality of first functional elements in a plan view. It is an electronic component that surrounds one functional element and does not surround the other first functional element.

上記構成において、前記絶縁膜の厚さは、前記第1面と前記第2面との距離の1/2以上である構成とすることができる。 In the above configuration, the thickness of the insulating film may be ½ or more of the distance between the first surface and the second surface.

上記構成において、前記第3面は前記第1面および前記第2面の他方と接触しない構成とすることができる。 In the above configuration, the third surface may be configured so as not to come into contact with the other of the first surface and the second surface.

上記構成において、前記1または複数の第1機能素子は各々弾性波素子である構成とすることができる。 In the above configuration, each of the one or more first functional elements may be an elastic wave element.

本発明は、第1面を有する第1基板と、複数の弾性波素子が設けられた第2面を有し、前記複数の弾性波素子が前記第1面と空隙を挟み対向するように、前記第1基板上に実装された第2基板と、前記第1面と前記第2面との間に設けられ、前記第1基板と前記第2基板とを接続する接続端子と、前記第1面および前記第2面のいずれか一方に設けられ、平面視において前記複数の弾性波素子のうち少なくとも1つの弾性波素子を囲み、前記少なくとも1つの弾性波素子との距離が前記接続端子と前記少なくとも1つの弾性波素子との距離より小さく、少なくとも一部が前記空隙を挟み前記第1面および前記第2面の他方と対向する第3面を有する絶縁膜と、入力端子と出力端子との間に直列に接続され前記複数の弾性波素子のうち一部である1または複数の直列共振器と、前記入力端子と前記出力端子との間に並列に接続され前記複数の弾性波素子の別の一部である1または複数の並列共振器と、を具備し、平面視において前記絶縁膜は前記1または複数の直列共振器の少なくとも1つを囲み、前記1または複数の直列共振器および前記1または複数の並列共振器のうち他の共振器の少なくとも一部を囲まない電子部品である
The present invention has a first substrate having a first surface and a second surface provided with a plurality of elastic wave elements so that the plurality of elastic wave elements face the first surface with a gap in between. A second board mounted on the first board, a connection terminal provided between the first surface and the second surface and connecting the first board and the second board, and the first surface. It is provided on either one of the surface and the second surface, surrounds at least one elastic wave element among the plurality of elastic wave elements in a plan view, and the distance between the connection terminal and the at least one elastic wave element is the distance between the connection terminal and the said second surface. An insulating film smaller than a distance from at least one elastic wave element and having a third surface facing the first surface and the other of the second surface with at least a part sandwiching the gap, and an input terminal and an output terminal. and one or more series resonators that are part of the serially connected plurality of acoustic wave element between another of said plurality of acoustic wave devices are connected in parallel between the input terminal and the output terminal The insulating film surrounds at least one of the one or more series resonators, and the one or more series resonators and said It is an electronic component that does not surround at least a part of another resonator among one or a plurality of parallel resonators.

上記構成において、平面視において前記絶縁膜は前記1または複数の直列共振器のうち両側に直列共振器が接続された直列共振器を囲み、前記1または複数の直列共振器および前記1または複数の並列共振器のうち他の共振器の少なくとも一部を囲まない構成とすることができる。 In the above configuration, in plan view, the insulating film surrounds a series resonator in which series resonators are connected to both sides of the one or more series resonators, and the one or more series resonators and the one or more series resonators. It is possible to configure the parallel resonator so as not to surround at least a part of the other resonators.

本発明は、第1面を有する第1基板と、1または複数の第1機能素子が設けられた第2面を有し、前記1または複数の第1機能素子が前記第1面と空隙を挟み対向するように、前記第1基板上に実装された第2基板と、前記第1面と前記第2面との間に設けられ、前記第1基板と前記第2基板とを接続する接続端子と、前記第1面および前記第2面のいずれか一方に設けられ、平面視において前記1または複数の第1機能素子のうち少なくとも1つの第1機能素子を囲み、前記少なくとも1つの第1機能素子との距離が前記接続端子と前記少なくとも1つの第1機能素子との距離より小さく、少なくとも一部が前記空隙を挟み前記第1面および前記第2面の他方と対向する第3面を有する絶縁膜と、1または複数の第2機能素子が設けられた第4面を有し、前記1または複数の第2機能素子が前記第1面と空隙を挟み対向するように、前記第1基板上に実装された第3基板を具備し、前記絶縁膜は前記第1面と前記第4面との間に設けられていない電子部品である
The present invention has a first substrate having a first surface and a second surface provided with one or more first functional elements, and the one or more first functional elements have a gap with the first surface. A connection provided between a second substrate mounted on the first substrate and the first surface and the second surface so as to sandwich and face each other, and to connect the first substrate and the second substrate. A terminal and one of the first surface and the second surface are provided to surround at least one first functional element of the one or a plurality of first functional elements in a plan view, and the at least one first functional element is surrounded. The distance to the functional element is smaller than the distance between the connection terminal and the at least one first functional element, and at least a part of the third surface facing the first surface and the other of the second surface sandwiches the gap. The first surface has an insulating film and a fourth surface provided with one or more second functional elements, and the one or more second functional elements face the first surface with a gap in between. A third substrate mounted on the substrate is provided, and the insulating film is an electronic component not provided between the first surface and the fourth surface.

上記構成において、前記弾性波素子を含むフィルタを具備する構成とすることができる。 In the above configuration, a filter including the elastic wave element can be provided.

上記構成において、前記フィルタを含むマルチプレクサを具備する構成とすることができる。 In the above configuration, the configuration may include a multiplexer including the filter.

本発明によれば、機能素子からの放熱性を向上させることができる。 According to the present invention, the heat dissipation from the functional element can be improved.

図1(a)は、実施例1に係る電子部品の断面図、図1(b)は、図1(a)の領域Aの拡大図、図1(c)は、実施例1の変形例1に係る電子部品の断面図、図1(d)は、図1(c)の領域Aの拡大図である。1 (a) is a cross-sectional view of an electronic component according to the first embodiment, FIG. 1 (b) is an enlarged view of a region A of FIG. 1 (a), and FIG. 1 (c) is a modified example of the first embodiment. FIG. 1 (d), which is a cross-sectional view of the electronic component according to FIG. 1, is an enlarged view of a region A of FIG. 1 (c). 図2(a)は、実施例1における機能素子を示す平面図、図2(b)は、実施例1の変形例1における機能素子を示す断面図である。FIG. 2A is a plan view showing the functional element in the first embodiment, and FIG. 2B is a cross-sectional view showing the functional element in the first modification of the first embodiment. 図3(a)および図3(b)は、それぞれ実施例1の変形例2および3に係る電子部品の断面図である。3 (a) and 3 (b) are cross-sectional views of electronic components according to modifications 2 and 3, respectively, of the first embodiment. 図4(a)は、実施例1の変形例4に係る電子部品の断面図、図4(b)は、図4(a)の領域Aの拡大図、図4(c)は、実施例1の変形例5に係る電子部品の断面図、図4(d)は、図4(c)の領域Aの拡大図である。4 (a) is a cross-sectional view of an electronic component according to a modified example 4 of the first embodiment, FIG. 4 (b) is an enlarged view of a region A of FIG. 4 (a), and FIG. 4 (c) is an embodiment. FIG. 4 (d), which is a cross-sectional view of the electronic component according to the modified example 5 of No. 1, is an enlarged view of the region A of FIG. 4 (c). 図5(a)および図5(b)は、それぞれ実施例1の変形例6および7に係る電子部品の断面図である。5 (a) and 5 (b) are cross-sectional views of electronic components according to modifications 6 and 7, respectively, of the first embodiment. 図6(a)および図6(b)は、それぞれ実施例1の変形例8および9に係る電子部品の断面図である。6 (a) and 6 (b) are cross-sectional views of the electronic components according to the modified examples 8 and 9, respectively, of the first embodiment. 図7(a)から図7(c)は、それぞれ実施例2、実施例2の変形例1および比較例1に係るデュプレクサの断面図である。7 (a) to 7 (c) are cross-sectional views of a duplexer according to a second embodiment, a modified example 1 of the second embodiment, and a comparative example 1, respectively. 図8(a)は、実施例2およびその変形例1並びに比較例1に係るデュプレクサの回路図、図8(b)は、送信フィルタの回路図である。FIG. 8A is a circuit diagram of a duplexer according to Example 2, a modification 1 thereof, and Comparative Example 1, and FIG. 8B is a circuit diagram of a transmission filter. 図9は、実施例2およびその変形例1並びに比較例1におけるデバイスチップの平面図である。FIG. 9 is a plan view of the device chip in the second embodiment, the first modification thereof, and the first comparative example. 図10(a)は、実施例2およびその変形例1における基板の平面図、図10(b)は、比較例1における基板の平面図である。10 (a) is a plan view of the substrate in Example 2 and its modified example 1, and FIG. 10 (b) is a plan view of the substrate in Comparative Example 1. 図11(a)は、実施例2およびその変形例1並びに比較例1および2における印加電力に対する最高温度を示す図、図11(b)は、印加電力に対する温度降下量を示す図である。FIG. 11 (a) is a diagram showing the maximum temperature with respect to the applied power in Example 2, its modified examples 1, and Comparative Examples 1 and 2, and FIG. 11 (b) is a diagram showing the amount of temperature drop with respect to the applied power. 図12は、実施例2の変形例1における膜厚T1に対する温度降下量の割合を示す図である。FIG. 12 is a diagram showing the ratio of the amount of temperature drop to the film thickness T1 in the modified example 1 of the second embodiment. 図13は、実施例2の変形例2における基板の平面図である。FIG. 13 is a plan view of the substrate in the second modification of the second embodiment. 図14は、実施例2の変形例3における基板の平面図である。FIG. 14 is a plan view of the substrate according to the third modification of the second embodiment. 図15は、実施例2の変形例4における基板の平面図である。FIG. 15 is a plan view of the substrate in the modified example 4 of the second embodiment. 図16は、実施例2の変形例5における基板の平面図である。FIG. 16 is a plan view of the substrate in the modified example 5 of the second embodiment.

以下図面を参照し実施例について説明する。 Examples will be described below with reference to the drawings.

[実施例1および実施例1の変形例1]
図1(a)は、実施例1に係る電子部品の断面図、図1(b)は、図1(a)の領域Aの拡大図、図1(c)は、実施例1の変形例1に係る電子部品の断面図、図1(d)は、図1(c)の領域Aの拡大図である。
[Example 1 and variant 1 of Example 1]
1 (a) is a cross-sectional view of an electronic component according to the first embodiment, FIG. 1 (b) is an enlarged view of a region A of FIG. 1 (a), and FIG. 1 (c) is a modified example of the first embodiment. FIG. 1 (d), which is a cross-sectional view of the electronic component according to FIG. 1, is an enlarged view of a region A of FIG. 1 (c).

図1(a)および図1(c)に示すように、基板20の上面に、基板10が実装されている。基板20は、絶縁基板であり、例えばHTCC(High Temperature Co-fired Ceramic)またはLTCC(Low Temperature Co-fired Ceramic)等のセラミックス基板または樹脂基板である。基板20は積層された複数の絶縁層20aおよび20bを有する。絶縁層20aおよび20bの上面にそれぞれ金属層28および26cが形成されている。絶縁層20bの下面に金属層24が形成されている。絶縁層20aおよび20bを貫通するビア配線26aおよび26bが形成されている。ビア配線26aは、金属層28と26cとを電気的に接続し、ビア配線26bは、金属層26cと24とを電気的に接続する。 As shown in FIGS. 1A and 1C, the substrate 10 is mounted on the upper surface of the substrate 20. The substrate 20 is an insulating substrate, for example, a ceramic substrate such as HTCC (High Temperature Co-fired Ceramic) or LTCC (Low Temperature Co-fired Ceramic) or a resin substrate. The substrate 20 has a plurality of laminated insulating layers 20a and 20b. Metal layers 28 and 26c are formed on the upper surfaces of the insulating layers 20a and 20b, respectively. A metal layer 24 is formed on the lower surface of the insulating layer 20b. Via wirings 26a and 26b penetrating the insulating layers 20a and 20b are formed. The via wiring 26a electrically connects the metal layers 28 and 26c, and the via wiring 26b electrically connects the metal layers 26c and 24.

基板20の上面に設けられた金属層28は例えばバンプ16が接合するパッドおよび配線である。金属層24は、例えば外部と電気的に接続するための外部端子であり、例えばフットパッドである。ビア配線26a、26bおよび金属層26cは、金属層24と28とを接続する内部配線26を形成する。金属層24、28および内部配線26は、銅層、金層またはアルミニウム層等の金属層である。基板20の上面に絶縁膜22が設けられている。絶縁膜22は例えば樹脂等の有機絶縁体または酸化シリコン等の無機絶縁体である。絶縁膜22が樹脂膜の場合、絶縁膜22は例えば基板20上に印刷法により形成され、加熱処理することにより乾燥される。 The metal layer 28 provided on the upper surface of the substrate 20 is, for example, a pad and wiring to which the bumps 16 are joined. The metal layer 24 is, for example, an external terminal for electrically connecting to the outside, for example, a foot pad. The via wires 26a and 26b and the metal layer 26c form an internal wiring 26 that connects the metal layers 24 and 28. The metal layers 24, 28 and the internal wiring 26 are metal layers such as a copper layer, a gold layer, or an aluminum layer. An insulating film 22 is provided on the upper surface of the substrate 20. The insulating film 22 is, for example, an organic insulator such as resin or an inorganic insulator such as silicon oxide. When the insulating film 22 is a resin film, the insulating film 22 is formed on the substrate 20 by a printing method, for example, and is dried by heat treatment.

デバイスチップ11は、基板10、機能素子12および金属層18を有する。機能素子12および金属層18は基板10の下面に設けられている。機能素子12は図1(a)および図1(b)では弾性表面波素子であり、図1(c)および図1(d)では圧電薄膜共振器である。金属層18は、バンプ16が接合するパッドおよび配線である。 The device chip 11 has a substrate 10, a functional element 12, and a metal layer 18. The functional element 12 and the metal layer 18 are provided on the lower surface of the substrate 10. The functional element 12 is a surface acoustic wave element in FIGS. 1 (a) and 1 (b), and a piezoelectric thin film resonator in FIGS. 1 (c) and 1 (d). The metal layer 18 is a pad and wiring to which the bump 16 is joined.

デバイスチップ11はバンプ16を介し基板20上にフリップチップ(フェースダウン)実装されている。機能素子12は空隙14を挟み基板20の上面に対向している。機能素子12が空隙14に露出されているため、機能素子12の振動等が抑制されない。バンプ16は、例えば銅バンプ、金バンプまたは半田バンプである。絶縁膜22は、平面視において機能素子12を囲むように設けられ、機能素子12とは重ならない。絶縁膜22と基板10の下面との間には空隙14が設けられている。 The device chip 11 is flip-chip (face-down) mounted on the substrate 20 via the bump 16. The functional element 12 faces the upper surface of the substrate 20 with the gap 14 interposed therebetween. Since the functional element 12 is exposed in the gap 14, vibration of the functional element 12 and the like are not suppressed. The bump 16 is, for example, a copper bump, a gold bump or a solder bump. The insulating film 22 is provided so as to surround the functional element 12 in a plan view, and does not overlap with the functional element 12. A gap 14 is provided between the insulating film 22 and the lower surface of the substrate 10.

図1(b)および図1(d)に示すように、基板20の上面と基板10の下面の距離をL1、絶縁膜22の上面と基板10の下面との距離をL2、絶縁膜22の膜厚をT1、機能素子12と絶縁膜22との距離をL3とする。距離L3は距離L1より小さい。また、例えば、L1>T1≧L1/2であり、T1≧L2である。これにより、機能素子12において発生した熱を絶縁膜22を介し放出することができる。 As shown in FIGS. 1B and 1D, the distance between the upper surface of the substrate 20 and the lower surface of the substrate 10 is L1, the distance between the upper surface of the insulating film 22 and the lower surface of the substrate 10 is L2, and the insulating film 22. The film thickness is T1, and the distance between the functional element 12 and the insulating film 22 is L3. The distance L3 is smaller than the distance L1. Further, for example, L1> T1 ≧ L1 / 2 and T1 ≧ L2. As a result, the heat generated in the functional element 12 can be released through the insulating film 22.

図2(a)は、実施例1における機能素子を示す平面図、図2(b)は、実施例1の変形例1における機能素子を示す断面図である。図2(a)に示すように、基板10上にIDT(Interdigital Transducer)40と反射器42が形成されている。IDT40は、互いに対向する1対の櫛型電極40aを有する。櫛型電極40aは、複数の電極指40bと複数の電極指40bを接続するバスバー40cとを有する。反射器42は、IDT40の両側に設けられている。IDT40が基板10に弾性表面波を励振する。基板10は、例えばタンタル酸リチウム基板またはニオブ酸リチウム基板等の圧電基板である。IDT40および反射器42は例えばアルミニウム膜または銅膜により形成される。基板10は、サファイア基板、アルミナ基板、スピネル基板またはシリコン基板等の支持基板の下面に接合されていてもよい。IDT40および反射器42を覆う保護膜または温度補償膜が設けられていてもよい。この場合、保護膜または温度補償膜を含め機能素子12として機能する。 FIG. 2A is a plan view showing the functional element in the first embodiment, and FIG. 2B is a cross-sectional view showing the functional element in the first modification of the first embodiment. As shown in FIG. 2A, an IDT (Interdigital Transducer) 40 and a reflector 42 are formed on the substrate 10. The IDT 40 has a pair of comb-shaped electrodes 40a facing each other. The comb-shaped electrode 40a has a plurality of electrode fingers 40b and a bus bar 40c for connecting the plurality of electrode fingers 40b. Reflectors 42 are provided on both sides of the IDT 40. IDT40 excites surface acoustic waves on the substrate 10. The substrate 10 is a piezoelectric substrate such as a lithium tantalate substrate or a lithium niobate substrate. The IDT 40 and the reflector 42 are formed of, for example, an aluminum film or a copper film. The substrate 10 may be bonded to the lower surface of a support substrate such as a sapphire substrate, an alumina substrate, a spinel substrate, or a silicon substrate. A protective film or a temperature compensation film may be provided to cover the IDT 40 and the reflector 42. In this case, it functions as a functional element 12 including a protective film or a temperature compensation film.

図2(b)に示すように、基板10上に圧電膜46が設けられている。圧電膜46を挟むように下部電極44および上部電極48が設けられている。下部電極44と基板10との間に空隙45が形成されている。下部電極44および上部電極48は圧電膜46内に、厚み縦振動モードの弾性波を励振する。下部電極44および上部電極48は例えばルテニウム膜等の金属膜である。圧電膜46は例えば窒化アルミニウム膜である。基板10は例えばシリコン基板もしくは砒化ガリウム等の半導体基板、またはサファイア基板、アルミナ基板、スピネル基板またはガラス基板等の絶縁基板である。図2(a)および図2(b)のように、機能素子12は弾性波を励振する電極を含む。このため、弾性波を規制しないように、機能素子12は空隙14に覆われている。 As shown in FIG. 2B, the piezoelectric film 46 is provided on the substrate 10. The lower electrode 44 and the upper electrode 48 are provided so as to sandwich the piezoelectric film 46. A gap 45 is formed between the lower electrode 44 and the substrate 10. The lower electrode 44 and the upper electrode 48 excite elastic waves in the thickness longitudinal vibration mode in the piezoelectric film 46. The lower electrode 44 and the upper electrode 48 are metal films such as a ruthenium film. The piezoelectric film 46 is, for example, an aluminum nitride film. The substrate 10 is, for example, a silicon substrate, a semiconductor substrate such as gallium arsenide, or an insulating substrate such as a sapphire substrate, an alumina substrate, a spinel substrate, or a glass substrate. As shown in FIGS. 2A and 2B, the functional element 12 includes an electrode that excites an elastic wave. Therefore, the functional element 12 is covered with a gap 14 so as not to regulate elastic waves.

[実施例1の変形例2および3]
図3(a)および図3(b)は、それぞれ実施例1の変形例2および3に係る電子部品の断面図である。図3(a)および図3(b)に示すように、平面視において基板10を囲むように封止部30が設けられている。封止部30は基板20の上面に接合されている。封止部30および基板10上にリッド32が設けられている。封止部30は半田等の金属または樹脂等の絶縁体である。リッド32は金属板または絶縁板である。封止部30により、機能素子12が空隙14に気密封止される。その他の構成は実施例1およびその変形例1と同じであり説明を省略する。
[Modifications 2 and 3 of Example 1]
3 (a) and 3 (b) are cross-sectional views of electronic components according to modifications 2 and 3, respectively, of the first embodiment. As shown in FIGS. 3A and 3B, a sealing portion 30 is provided so as to surround the substrate 10 in a plan view. The sealing portion 30 is joined to the upper surface of the substrate 20. A lid 32 is provided on the sealing portion 30 and the substrate 10. The sealing portion 30 is an insulator such as a metal such as solder or a resin. The lid 32 is a metal plate or an insulating plate. The sealing portion 30 airtightly seals the functional element 12 in the gap 14. Other configurations are the same as those of the first embodiment and the first modification thereof, and the description thereof will be omitted.

[実施例1の変形例4および5]
図4(a)は、実施例1の変形例4に係る電子部品の断面図、図4(b)は、図4(a)の領域Aの拡大図、図4(c)は、実施例1の変形例5に係る電子部品の断面図、図4(d)は、図4(c)の領域Aの拡大図である。
[Modified Examples 4 and 5 of Example 1]
4 (a) is a cross-sectional view of an electronic component according to a modified example 4 of the first embodiment, FIG. 4 (b) is an enlarged view of a region A of FIG. 4 (a), and FIG. 4 (c) is an embodiment. FIG. 4 (d), which is a cross-sectional view of the electronic component according to the modified example 5 of No. 1, is an enlarged view of the region A of FIG. 4 (c).

図4(a)および図4(c)に示すように、絶縁膜22は基板10の下面に設けられ、絶縁膜22の下面と基板20の上面との間に空隙14が設けられている。 As shown in FIGS. 4A and 4C, the insulating film 22 is provided on the lower surface of the substrate 10, and a gap 14 is provided between the lower surface of the insulating film 22 and the upper surface of the substrate 20.

図4(b)および図4(d)に示すように、基板20の上面と機能素子12の下面の距離をL1、絶縁膜22の下面と基板20の上面との距離をL2、絶縁膜22の膜厚をT1、機能素子12と絶縁膜22との距離をL3とする。距離L3は距離L1より十分小さい。また、例えば、L1>T1≧L1/2であり、T1≧L2である。これにより、機能素子12において発生した熱を絶縁膜22を介し放出することができる。その他の構成は、実施例1およびその変形例1と同じであり説明を省略する。 As shown in FIGS. 4 (b) and 4 (d), the distance between the upper surface of the substrate 20 and the lower surface of the functional element 12 is L1, the distance between the lower surface of the insulating film 22 and the upper surface of the substrate 20 is L2, and the insulating film 22. The film thickness is T1, and the distance between the functional element 12 and the insulating film 22 is L3. The distance L3 is sufficiently smaller than the distance L1. Further, for example, L1> T1 ≧ L1 / 2 and T1 ≧ L2. As a result, the heat generated in the functional element 12 can be released through the insulating film 22. Other configurations are the same as those of the first embodiment and the first modification thereof, and the description thereof will be omitted.

[実施例1の変形例6および7]
図5(a)および図5(b)は、それぞれ実施例1の変形例6および7に係る電子部品の断面図である。図5(a)および図5(b)に示すように、実施例1の変形例2および3と同様に、平面視において基板10を囲むように封止部30が設けられている。その他の構成は実施例1の変形例2および3と同じであり説明を省略する。
[Modified Examples 6 and 7 of Example 1]
5 (a) and 5 (b) are cross-sectional views of electronic components according to modifications 6 and 7, respectively, of the first embodiment. As shown in FIGS. 5A and 5B, a sealing portion 30 is provided so as to surround the substrate 10 in a plan view, as in the modifications 2 and 3 of the first embodiment. Other configurations are the same as the modifications 2 and 3 of the first embodiment, and the description thereof will be omitted.

[実施例1の変形例8および9]
図6(a)および図6(b)は、それぞれ実施例1の変形例8および9に係る電子部品の断面図である。図6(a)に示すように、絶縁膜22の上面の一部は領域50において基板10の下面に設けられた金属層18の下面に接触している。その他の構成は実施例1と同じであり説明を省略する。
[Modified Examples 8 and 9 of Example 1]
6 (a) and 6 (b) are cross-sectional views of the electronic components according to the modified examples 8 and 9, respectively, of the first embodiment. As shown in FIG. 6A, a part of the upper surface of the insulating film 22 is in contact with the lower surface of the metal layer 18 provided on the lower surface of the substrate 10 in the region 50. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.

図6(b)に示すように、絶縁膜22の下面の一部は領域50において基板20の上面に接触している。その他の構成は実施例1の変形例4と同じであり説明を省略する。実施例1の変形例8および9のように、絶縁膜22の上面の一部が基板10の下面に接触していてもよいし、絶縁膜22の下面の一部が基板20の上面に接触していてもよい。 As shown in FIG. 6B, a part of the lower surface of the insulating film 22 is in contact with the upper surface of the substrate 20 in the region 50. Other configurations are the same as those of the modified example 4 of the first embodiment, and the description thereof will be omitted. As in the modified examples 8 and 9 of the first embodiment, a part of the upper surface of the insulating film 22 may be in contact with the lower surface of the substrate 10, or a part of the lower surface of the insulating film 22 is in contact with the upper surface of the substrate 20. You may be doing it.

[実施例2、実施例2の変形例1および比較例1]
実施例2およびその変形例は、デュプレクサの例である。図7(a)から図7(c)は、それぞれ実施例2、実施例2の変形例1および比較例1に係るデュプレクサの断面図である。図7(a)に示すように、実施例2では、基板20上にデバイスチップ11aおよび11bがフリップチップ実装されている。デバイスチップ11aおよび11bにおいて、それぞれ基板10aおよび10bの下面に機能素子12aおよび12bが設けられている。基板20の上面にはデバイスチップ11aおよび11bを囲むように環状金属層29が設けられている。
[Example 2, Modified Example 1 of Example 2 and Comparative Example 1]
Example 2 and its modifications are examples of duplexers. 7 (a) to 7 (c) are cross-sectional views of a duplexer according to a second embodiment, a modified example 1 of the second embodiment, and a comparative example 1, respectively. As shown in FIG. 7A, in the second embodiment, the device chips 11a and 11b are flip-chip mounted on the substrate 20. In the device chips 11a and 11b, functional elements 12a and 12b are provided on the lower surfaces of the substrates 10a and 10b, respectively. An annular metal layer 29 is provided on the upper surface of the substrate 20 so as to surround the device chips 11a and 11b.

デバイスチップ11aおよび11bを囲むように封止部30が設けられている。封止部30は半田であり、環状金属層29に接合されている。封止部30、デバイスチップ11aおよび11bの上面にリッド32が設けられている。絶縁膜22は、基板20の上面に設けられ、平面視において機能素子12aおよびバンプ16を囲む。デバイスチップ11bに対応する領域に絶縁膜22は設けられていない。その他の構成は実施例1と同じであり説明を省略する。 A sealing portion 30 is provided so as to surround the device chips 11a and 11b. The sealing portion 30 is solder and is bonded to the annular metal layer 29. A lid 32 is provided on the upper surfaces of the sealing portion 30, the device chips 11a and 11b. The insulating film 22 is provided on the upper surface of the substrate 20 and surrounds the functional element 12a and the bump 16 in a plan view. The insulating film 22 is not provided in the region corresponding to the device chip 11b. Other configurations are the same as those in the first embodiment, and the description thereof will be omitted.

図7(b)に示すように、実施例2の変形例1では、絶縁膜22には、基板10aの下面に設けられている。その他の構成は実施例2と同じであり説明を省略する。 As shown in FIG. 7B, in the first modification of the second embodiment, the insulating film 22 is provided on the lower surface of the substrate 10a. Other configurations are the same as those in the second embodiment, and the description thereof will be omitted.

図7(c)に示すように、比較例1では、絶縁膜22は基板20の上面に設けられている。絶縁膜22は、平面視において機能素子12aに重なる。その他の構成は実施例2と同じであり説明を省略する。 As shown in FIG. 7C, in Comparative Example 1, the insulating film 22 is provided on the upper surface of the substrate 20. The insulating film 22 overlaps the functional element 12a in a plan view. Other configurations are the same as those in the second embodiment, and the description thereof will be omitted.

図8(a)は、実施例2およびその変形例1並びに比較例1に係るデュプレクサの回路図、図8(b)は、送信フィルタの回路図である。図8(a)に示すように、共通端子Antと送信端子Txとの間に送信フィルタ60が設けられている。共通端子Antと受信端子Rxとの間に受信フィルタ62が設けられている。送信フィルタ60は、送信端子Txから入力した高周波信号のうち送信信号を共通端子Antに通過させ他の周波数の信号を抑圧する。受信フィルタ62は、共通端子Antから入力した高周波信号のうち受信信号を受信端子Rxに通過させ他の周波数の信号を抑圧する。送信フィルタ60は、デバイスチップ11aに形成されており、機能素子12aを含む。受信フィルタ62は、デバイスチップ11bに形成されており、機能素子12bを含む。 FIG. 8A is a circuit diagram of a duplexer according to Example 2, a modification 1 thereof, and Comparative Example 1, and FIG. 8B is a circuit diagram of a transmission filter. As shown in FIG. 8A, a transmission filter 60 is provided between the common terminal Ant and the transmission terminal Tx. A reception filter 62 is provided between the common terminal Ant and the reception terminal Rx. The transmission filter 60 passes the transmission signal among the high frequency signals input from the transmission terminal Tx through the common terminal Ant and suppresses signals of other frequencies. The reception filter 62 passes the received signal among the high frequency signals input from the common terminal Ant through the receiving terminal Rx and suppresses signals of other frequencies. The transmission filter 60 is formed on the device chip 11a and includes a functional element 12a. The reception filter 62 is formed on the device chip 11b and includes a functional element 12b.

図8(b)に示すように、送信フィルタ60は直列共振器S1からS4および並列共振器P1からP3を有する。直列共振器S1からS4は、送信端子Txと共通端子Antの間に直列に接続されている。並列共振器P1からP3は送信端子Txと共通端子Antの間に並列に接続されている。 As shown in FIG. 8B, the transmission filter 60 has series resonators S1 to S4 and parallel resonators P1 to P3. The series resonators S1 to S4 are connected in series between the transmission terminal Tx and the common terminal Ant. The parallel resonators P1 to P3 are connected in parallel between the transmission terminal Tx and the common terminal Ant.

図9は、実施例2およびその変形例1並びに比較例1におけるデバイスチップの平面図である。デバイスチップ11aの下面を上から透視した平面図である。図9に示すように、基板10aの下面に、複数の機能素子12aおよび金属層18が設けられている。機能素子12aは図2(a)に示した弾性表面波共振器である。複数の機能素子12aは直列共振器S1からS4および並列共振器P1からP3を含む。金属層18は配線およびパッドである。配線は複数の機能素子12a間を接続する。パッドは機能素子12aに接続されている。パッドにはバンプ16が設けられている。バンプ16は、共通端子Ant、送信端子Txおよびグランド端子Gndに対応する。 FIG. 9 is a plan view of the device chip in the second embodiment, the first modification thereof, and the first comparative example. FIG. 5 is a plan view of the lower surface of the device chip 11a as seen through from above. As shown in FIG. 9, a plurality of functional elements 12a and a metal layer 18 are provided on the lower surface of the substrate 10a. The functional element 12a is a surface acoustic wave resonator shown in FIG. 2 (a). The plurality of functional elements 12a include series resonators S1 to S4 and parallel resonators P1 to P3. The metal layer 18 is a wiring and a pad. Wiring connects a plurality of functional elements 12a. The pad is connected to the functional element 12a. The pad is provided with a bump 16. The bump 16 corresponds to the common terminal Ant, the transmission terminal Tx, and the ground terminal Gnd.

図10(a)は、実施例2およびその変形例1における基板の平面図である。絶縁膜22を太破線、デバイスチップ11aおよび11bを破線、およびデバイスチップ11a内の共振器を細破線で図示する。図10(a)に示すように、実施例2およびその変形例1では、基板20の上面には金属層28および環状金属層29が設けられている。環状金属層29は、基板20の上面の周縁に設けられている。金属層28は配線およびパッドである。配線はパッド間を接続する。パッドにはバンプ16が設けられている。バンプ16は、共通端子Ant、送信端子Tx、受信端子Rxおよびグランド端子Gndに対応する。 FIG. 10A is a plan view of the substrate in the second embodiment and the first modification thereof. The insulating film 22 is shown by a thick dashed line, the device chips 11a and 11b are shown by a broken line, and the resonator in the device chip 11a is shown by a broken line. As shown in FIG. 10A, in the second embodiment and the first modification thereof, a metal layer 28 and an annular metal layer 29 are provided on the upper surface of the substrate 20. The annular metal layer 29 is provided on the peripheral edge of the upper surface of the substrate 20. The metal layer 28 is a wiring and a pad. Wiring connects the pads. The pad is provided with a bump 16. The bump 16 corresponds to the common terminal Ant, the transmission terminal Tx, the reception terminal Rx, and the ground terminal Gnd.

絶縁膜22は、平面視においてデバイスチップ11aと重なり、デバイスチップ11bとは重なっていない。絶縁膜22は、直列共振器S1からS4および並列共振器P1からP3と重ならず、これらの共振器を囲む。 The insulating film 22 overlaps with the device chip 11a in a plan view and does not overlap with the device chip 11b. The insulating film 22 does not overlap with the series resonators S1 to S4 and the parallel resonators P1 to P3, and surrounds these resonators.

図10(b)は、比較例1における基板の平面図である。図10(b)に示すように、比較例1では、絶縁膜22は、平面視においてバンプ16以外のデバイスチップ11aと重なり、直列共振器S1からS4および並列共振器P1からP3とも重なっている。 FIG. 10B is a plan view of the substrate in Comparative Example 1. As shown in FIG. 10B, in Comparative Example 1, the insulating film 22 overlaps with the device chip 11a other than the bump 16 in a plan view, and also overlaps with the series resonators S1 to S4 and the parallel resonators P1 to P3. ..

基板10a内の温度をシミュレーションした。シミュレーション条件は以下である。基板10aおよび10bを厚さ150μmの42°回転YカットX伝搬タンタル酸リチウム基板とした。基板20を厚さが166μmのLTCC基板とした。封止部30はAgSn半田とした。基板20上面と基板10aの下面の距離L1を20μmとした。機能素子12aである弾性表面波共振器の電極指の厚さは1μm未満である。リッド32は、膜厚が60μmのコバール板とした。絶縁膜22は、熱伝導率が約0.25W/m・Kの樹脂膜とした。絶縁膜22の膜厚T1は、実施例1およびその変形例では19μm、比較例1では15μmとした。平面視における機能素子12aと絶縁膜22との距離L3を5μmとした。 The temperature inside the substrate 10a was simulated. The simulation conditions are as follows. The substrates 10a and 10b were made into a 42 ° rotating Y-cut X-propagated lithium tantalate substrate having a thickness of 150 μm. The substrate 20 was an LTCC substrate having a thickness of 166 μm. The sealing portion 30 was made of AgSn solder. The distance L1 between the upper surface of the substrate 20 and the lower surface of the substrate 10a was set to 20 μm. The thickness of the electrode finger of the surface acoustic wave resonator, which is the functional element 12a, is less than 1 μm. The lid 32 was a coval plate having a film thickness of 60 μm. The insulating film 22 is a resin film having a thermal conductivity of about 0.25 W / m · K. The film thickness T1 of the insulating film 22 was 19 μm in Example 1 and its modifications, and 15 μm in Comparative Example 1. The distance L3 between the functional element 12a and the insulating film 22 in a plan view was set to 5 μm.

送信フィルタ60および受信フィルタ62は、E−UTRA(Evolved Universal Terrestrial Radio Access) Operating Bandのバンド8(送信帯域:880−915MHz、受信帯域:925−960MHz)の送信フィルタおよび受信フィルタとした。送信端子Txにバンド8の送信信号を入力した。印加電力を28dBm、30dBmおよび32dBmとした。共通端子Antおよび受信端子Rxは50Ωに終端した。基板10a内の下面の最高温度をシミュレーションした。 The transmission filter 60 and the reception filter 62 are transmission filters and reception filters of band 8 (transmission band: 880-915 MHz, reception band: 925-960 MHz) of the E-UTRA (Evolved Universal Terrestrial Radio Access) Operating Band. A band 8 transmission signal was input to the transmission terminal Tx. The applied power was 28 dBm, 30 dBm and 32 dBm. The common terminal Ant and the receiving terminal Rx were terminated to 50Ω. The maximum temperature of the lower surface in the substrate 10a was simulated.

比較例2として、絶縁膜22を設けていない場合もシミュレーションした。 As Comparative Example 2, a simulation was also performed when the insulating film 22 was not provided.

図11(a)は、実施例2およびその変形例1並びに比較例1および2における印加電力に対する最高温度を示す図、図11(b)は、印加電力に対する温度降下量を示す図である。温度降下量は、比較例2(絶縁膜22なし)の温度から実施例2およびその変形例1並びに比較例1の温度を引いた温度である。 FIG. 11 (a) is a diagram showing the maximum temperature with respect to the applied power in Example 2, its modified examples 1, and Comparative Examples 1 and 2, and FIG. 11 (b) is a diagram showing the amount of temperature drop with respect to the applied power. The amount of temperature drop is the temperature obtained by subtracting the temperatures of Example 2, the modified examples 1 thereof, and Comparative Example 1 from the temperature of Comparative Example 2 (without the insulating film 22).

図11(a)および図11(b)に示すように、実施例2、実施例2の変形例1および比較例2では、比較例2に比べ同程度に温度が下がる。なお、基板10aの下面のうち最高温度となる箇所は図9の直列共振器S2に対応する箇所である。 As shown in FIGS. 11 (a) and 11 (b), in the second embodiment, the modified examples 1 and the comparative example 2 of the second embodiment, the temperature is lowered to the same extent as that of the comparative example 2. The portion of the lower surface of the substrate 10a that has the highest temperature is the portion corresponding to the series resonator S2 in FIG.

実施例2の変形例1において、絶縁膜22の膜厚T1を変え、温度をシミュレーションした。図12は、実施例2の変形例1における膜厚T1に対する温度降下量の割合を示す図である。絶縁膜22の膜厚T1を20μmとして、絶縁膜22の下面の全面が基板20の上面に接触している比較例3を基準とした。絶縁膜22のない比較例2に対する比較例3の温度降下量を1とし、温度降下量を規格化したものが温度降下量の割合である。印加電力は28dBmとした。 In the modified example 1 of the second embodiment, the temperature was simulated by changing the film thickness T1 of the insulating film 22. FIG. 12 is a diagram showing the ratio of the amount of temperature drop to the film thickness T1 in the modified example 1 of the second embodiment. The film thickness T1 of the insulating film 22 was set to 20 μm, and Comparative Example 3 in which the entire lower surface of the insulating film 22 was in contact with the upper surface of the substrate 20 was used as a reference. The temperature drop amount of Comparative Example 3 with respect to Comparative Example 2 without the insulating film 22 is set to 1, and the temperature drop amount is standardized as the ratio of the temperature drop amount. The applied power was 28 dBm.

図12に示すように、膜厚T1が大きくなると温度降下量の割合が大きくなる。膜厚T1が10μmを超えると、温度降下量の割合は急激に増加し、膜厚T1が15μm以上では温度降下量の割合は0.4以上であり、膜厚T1が18μm以上では温度降下量の割合は0.6以上である。 As shown in FIG. 12, as the film thickness T1 increases, the ratio of the amount of temperature drop increases. When the film thickness T1 exceeds 10 μm, the rate of temperature drop increases sharply, when the film thickness T1 is 15 μm or more, the rate of temperature drop is 0.4 or more, and when the film thickness T1 is 18 μm or more, the temperature drop rate. The ratio of is 0.6 or more.

実施例1、2およびその変形例並びに比較例2によれば、基板10もしくは10a(第2基板)の下面(第2面)に1または複数の機能素子12もしくは12a(第1機能素子)が設けられている。機能素子12または12aが基板20(第1基板)の上面(第1面)と空隙14を挟み対向するように、基板10または10aが基板20上に実装されている。バンプ16(接続端子)は、基板20の上面と基板10または10aとの間に設けられ、基板20と基板10または10aとを接続する。 According to Examples 1 and 2, modifications thereof, and Comparative Example 2, one or more functional elements 12 or 12a (first functional element) are placed on the lower surface (second surface) of the substrate 10 or 10a (second substrate). It is provided. The substrate 10 or 10a is mounted on the substrate 20 so that the functional element 12 or 12a faces the upper surface (first surface) of the substrate 20 (first substrate) with the gap 14 interposed therebetween. The bump 16 (connection terminal) is provided between the upper surface of the substrate 20 and the substrate 10 or 10a, and connects the substrate 20 and the substrate 10 or 10a.

このような電子部品では、比較例2のように、空隙14により機能素子12aにおいて発生した熱の放出が妨げられる。そこで、比較例1のように、機能素子12aに対向するように絶縁膜22を設ける。これにより、機能素子12aにおいて発生した熱は、絶縁膜22に輻射および対流により伝わり、絶縁膜22を介し基板20に伝導する。よって、図11(a)および図11(b)のように、比較例2に比べ基板10aの温度の上昇を抑制できる。 In such an electronic component, as in Comparative Example 2, the gap 14 prevents the heat generated in the functional element 12a from being released. Therefore, as in Comparative Example 1, the insulating film 22 is provided so as to face the functional element 12a. As a result, the heat generated in the functional element 12a is transmitted to the insulating film 22 by radiation and convection, and is conducted to the substrate 20 via the insulating film 22. Therefore, as shown in FIGS. 11A and 11B, the temperature rise of the substrate 10a can be suppressed as compared with Comparative Example 2.

比較例1において、放熱性を高めるためには、絶縁膜22を厚くすることが好ましい。しかしながら、バンプ16の高さは製造ばらつきが大きい。絶縁膜22の上面が機能素子12aに接触すると、空隙14を設ける意味がなくなってしまう。このため、バンプ16が低くなったときを想定し、製造マージンを確保しようとすると、絶縁膜22を厚くできない。また、機能素子12aに絶縁膜22が対向すると、機能素子12aの特性(例えば高周波特性)が劣化する。 In Comparative Example 1, it is preferable to make the insulating film 22 thicker in order to improve heat dissipation. However, the height of the bump 16 has a large manufacturing variation. When the upper surface of the insulating film 22 comes into contact with the functional element 12a, there is no point in providing the gap 14. Therefore, assuming that the bump 16 becomes low, the insulating film 22 cannot be thickened in order to secure a manufacturing margin. Further, when the insulating film 22 faces the functional element 12a, the characteristics (for example, high frequency characteristics) of the functional element 12a deteriorate.

実施例1、2およびその変形例では、絶縁膜22は、基板20の上面および基板10または10aの下面のいずれか一方に設けられており、平面視において1または複数の機能素子12または12aを囲む。これにより、バンプ16が低くなっても絶縁膜22が機能素子12または12aに接触することを抑制できる。また、絶縁膜22による特性の劣化を抑制できる。絶縁膜22と機能素子12または12aとの最小の距離L3をバンプ16と機能素子12または12aとの最小の距離より近くする。これにより、機能素子12または12aにおいて発生した熱が効率よく絶縁膜22に伝わる。よって、機能素子12または12aからの放熱性を向上させることができる。 In Examples 1 and 2 and modifications thereof, the insulating film 22 is provided on either the upper surface of the substrate 20 or the lower surface of the substrate 10 or 10a, and one or a plurality of functional elements 12 or 12a are provided in a plan view. surround. As a result, it is possible to prevent the insulating film 22 from coming into contact with the functional element 12 or 12a even if the bump 16 is lowered. In addition, deterioration of the characteristics due to the insulating film 22 can be suppressed. The minimum distance L3 between the insulating film 22 and the functional element 12 or 12a is made closer than the minimum distance between the bump 16 and the functional element 12 or 12a. As a result, the heat generated in the functional element 12 or 12a is efficiently transferred to the insulating film 22. Therefore, the heat dissipation from the functional element 12 or 12a can be improved.

絶縁膜22が基板20の上面に設けられている場合、絶縁膜22の上面の全てが基板10または10aの下面に接触すると、絶縁膜22の膜厚T1により、バンプ16の高さが制限される。絶縁膜22が基板10または10aの下面に設けられている場合、絶縁膜22の下面の全てが基板20の上面に接触すると、絶縁膜22の膜厚T1により、バンプ16の高さが制限される。これにより、バンプ16と基板10aおよび/または基板20との接合強度が小さくなる可能性がある。また、基板10aの下面または基板20の上面上の高周波信号が伝搬する配線に絶縁膜22が接触する可能性がある。これにより、特性が劣化する可能性がある。 When the insulating film 22 is provided on the upper surface of the substrate 20, when the entire upper surface of the insulating film 22 comes into contact with the lower surface of the substrate 10 or 10a, the height of the bump 16 is limited by the film thickness T1 of the insulating film 22. NS. When the insulating film 22 is provided on the lower surface of the substrate 10 or 10a, when the entire lower surface of the insulating film 22 comes into contact with the upper surface of the substrate 20, the height of the bump 16 is limited by the film thickness T1 of the insulating film 22. NS. As a result, the bonding strength between the bump 16 and the substrate 10a and / or the substrate 20 may be reduced. Further, the insulating film 22 may come into contact with the wiring on which the high frequency signal propagates on the lower surface of the substrate 10a or the upper surface of the substrate 20. This can lead to deterioration of the characteristics.

そこで、絶縁膜22が基板20の上面に設けられている場合、絶縁膜22の上面(第3面)の少なくとも一部が空隙14を挟み基板10または10aの下面と対向する。絶縁膜22が基板10または10aの下面に設けられている場合、絶縁膜22の下面(第3面)の少なくとも一部が空隙14を挟み基板20の上面と対向する。これにより、バンプ16の接合強度を大きくできる、および/または特性劣化を抑制できる。絶縁膜22の代わりに金属膜を用いると、機能素子12aの近くに金属膜が設けられる。このため機能素子12aの特性が劣化する。 Therefore, when the insulating film 22 is provided on the upper surface of the substrate 20, at least a part of the upper surface (third surface) of the insulating film 22 faces the lower surface of the substrate 10 or 10a with the gap 14 interposed therebetween. When the insulating film 22 is provided on the lower surface of the substrate 10 or 10a, at least a part of the lower surface (third surface) of the insulating film 22 faces the upper surface of the substrate 20 with the gap 14 interposed therebetween. Thereby, the bonding strength of the bump 16 can be increased and / or the deterioration of the characteristics can be suppressed. When a metal film is used instead of the insulating film 22, the metal film is provided near the functional element 12a. Therefore, the characteristics of the functional element 12a deteriorate.

機能素子12または12aから効率的に放熱するため、絶縁膜22の膜厚T1は、距離L1の1/2以上であることが好ましい。T1はL1の75%以上が好ましく、90%以上がより好ましい。また、機能素子12または12aの下面と絶縁膜22の上面との距離L2は、T1以下が好ましく、T1/2以下がより好ましく、T1/4以下がさらに好ましい。 In order to efficiently dissipate heat from the functional element 12 or 12a, the film thickness T1 of the insulating film 22 is preferably ½ or more of the distance L1. T1 is preferably 75% or more, more preferably 90% or more of L1. The distance L2 between the lower surface of the functional element 12 or 12a and the upper surface of the insulating film 22 is preferably T1 or less, more preferably T1 / 2 or less, and even more preferably T1 / 4 or less.

機能素子12または12aから効率的に放熱するため、距離L3は、バンプ16と機能素子12aとの距離の1/2以下が好ましく、1/4以下がより好ましい。または、距離L3は、距離L1の1/2以下が好ましく、1/4以下がより好ましい。 In order to efficiently dissipate heat from the functional element 12 or 12a, the distance L3 is preferably 1/2 or less, more preferably 1/4 or less of the distance between the bump 16 and the functional element 12a. Alternatively, the distance L3 is preferably 1/2 or less, more preferably 1/4 or less of the distance L1.

絶縁膜22の熱伝導率は、空気の熱伝導率である0.025W/m・Kより大きければよいが、より放熱効果を高めるため、空気の熱伝導率の5倍以上が好ましく、10倍以上がより好ましい。熱伝導率の大きな絶縁膜22として、エポキシ樹脂、ポリイミド樹脂、シリコーン、ソルダーレジスト、窒化ホウ素、窒化アルミニウム、酸化亜鉛または酸化シリコン等を用いることができる。放熱性向上のため絶縁膜22は基板20の上面に直接接触していることが好ましい。 The thermal conductivity of the insulating film 22 may be larger than the thermal conductivity of air, 0.025 W / m · K, but in order to further enhance the heat dissipation effect, it is preferably 5 times or more, preferably 10 times or more the thermal conductivity of air. The above is more preferable. As the insulating film 22 having a large thermal conductivity, epoxy resin, polyimide resin, silicone, solder resist, boron nitride, aluminum nitride, zinc oxide, silicon oxide or the like can be used. The insulating film 22 is preferably in direct contact with the upper surface of the substrate 20 in order to improve heat dissipation.

絶縁膜22は、平面視において機能素子12または12aを完全に囲んでもよいが、一部を囲んでもよい。例えば、機能素子12または12aの平面形状が4角形の場合、絶縁膜22は、機能素子12aまたは12aの4辺のうち3辺を囲んでもよい。 The insulating film 22 may completely surround the functional element 12 or 12a in a plan view, or may partially surround the functional element 12 or 12a. For example, when the planar shape of the functional element 12 or 12a is a quadrangle, the insulating film 22 may surround three of the four sides of the functional element 12a or 12a.

実施例2およびその変形例1のように、絶縁膜22は、平面視において複数の機能素子12aを各々囲むことが好ましい。これにより、放熱性を高めることができる。 As in the second embodiment and the first modification thereof, it is preferable that the insulating film 22 surrounds each of the plurality of functional elements 12a in a plan view. As a result, heat dissipation can be improved.

実施例1の変形例8のように、絶縁膜22の上面の一部が基板10の下面(金属層18の下面)に接触してもよい。実施例1の変形例9のように、絶縁膜22の下面の一部が基板20の上面に接触してもよい。しかし、バンプ16の接合強度等の観点から、絶縁膜22が基板20の上面に設けられている場合、絶縁膜22の上面は基板10または10aの下面に接触しないことが好ましい。絶縁膜22が基板10または10aの下面に設けられている場合、絶縁膜22の下面は基板20の上面に接触しないことが好ましい。 As in the modified example 8 of the first embodiment, a part of the upper surface of the insulating film 22 may come into contact with the lower surface of the substrate 10 (the lower surface of the metal layer 18). As in the modified example 9 of the first embodiment, a part of the lower surface of the insulating film 22 may come into contact with the upper surface of the substrate 20. However, from the viewpoint of the bonding strength of the bump 16, when the insulating film 22 is provided on the upper surface of the substrate 20, it is preferable that the upper surface of the insulating film 22 does not come into contact with the lower surface of the substrate 10 or 10a. When the insulating film 22 is provided on the lower surface of the substrate 10 or 10a, it is preferable that the lower surface of the insulating film 22 does not come into contact with the upper surface of the substrate 20.

[実施例2の変形例2]
図13は、実施例2の変形例2における基板の平面図である。図13に示すように、絶縁膜22は、基板20の上面の共通端子Antおよび送信端子Txに接続された金属層28には重なっていない。絶縁膜22が基板20の上面に設けられた高周波信号が伝搬する金属層28と重なると、高周波特性が劣化する。そこで、実施例2の変形例2のように、絶縁膜22は金属層28と重ならない。これにより、特性の劣化を抑制できる。その他の構成は実施例2およびその変形例1と同じであり、説明を省略する。
[Modification 2 of Example 2]
FIG. 13 is a plan view of the substrate in the second modification of the second embodiment. As shown in FIG. 13, the insulating film 22 does not overlap the metal layer 28 connected to the common terminal Ant and the transmission terminal Tx on the upper surface of the substrate 20. When the insulating film 22 overlaps with the metal layer 28 on which the high frequency signal propagates provided on the upper surface of the substrate 20, the high frequency characteristics deteriorate. Therefore, the insulating film 22 does not overlap with the metal layer 28 as in the modified example 2 of the second embodiment. As a result, deterioration of the characteristics can be suppressed. Other configurations are the same as those of the second embodiment and the first modification thereof, and the description thereof will be omitted.

[実施例2の変形例3]
図14は、実施例2の変形例3における基板の平面図である。図14に示すように、絶縁膜22は、金属層28の全てと重なっていない。絶縁膜22が金属層28と重なる領域では、絶縁膜22の上面が機能素子12aおよび/または金属層18と接触する可能性がある。これにより、機能素子12aの特性が劣化する可能性がある。そこで、実施例2の変形例2のように、絶縁膜22は全ての金属層28と重ならない。これにより、特性の劣化を抑制できる。その他の構成は実施例2およびその変形例1と同じであり説明を省略する。
[Modification 3 of Example 2]
FIG. 14 is a plan view of the substrate according to the third modification of the second embodiment. As shown in FIG. 14, the insulating film 22 does not overlap with all of the metal layers 28. In the region where the insulating film 22 overlaps the metal layer 28, the upper surface of the insulating film 22 may come into contact with the functional element 12a and / or the metal layer 18. As a result, the characteristics of the functional element 12a may deteriorate. Therefore, the insulating film 22 does not overlap with all the metal layers 28 as in the modified example 2 of the second embodiment. As a result, deterioration of the characteristics can be suppressed. Other configurations are the same as those of the second embodiment and the first modification thereof, and the description thereof will be omitted.

実施例2の変形例2および3では、絶縁膜22が金属層28と重ならない例を説明したが、絶縁膜22は基板10aの下面に設けられた高周波信号が伝搬する金属層18と重ならなくてもよい。また、絶縁膜22は基板10aの下面に設けられた全ての金属層18と重ならなくてもよい。 In the modifications 2 and 3 of the second embodiment, the example in which the insulating film 22 does not overlap with the metal layer 28 has been described, but if the insulating film 22 overlaps with the metal layer 18 on the lower surface of the substrate 10a on which the high frequency signal propagates. It does not have to be. Further, the insulating film 22 does not have to overlap with all the metal layers 18 provided on the lower surface of the substrate 10a.

[実施例2の変形例4]
図15は、実施例2の変形例4における基板の平面図である。最高温度となる共振器は直列共振器S2である。そこで、図15に示すように、絶縁膜22を、平面視において直列共振器S2に隣接する直列共振器S1からS3および並列共振器P1およびP2を囲むように設け、直列共振器S2に隣接しない直列共振器S4および並列共振器P3を囲むようには設けない。これにより、直列共振器S2から効率的に放熱し、かつ絶縁膜22が共振器に近接することによる特性の劣化を抑制できる。その他の構成は実施例2およびその変形例1と同じであり説明を省略する。
[Modification 4 of Example 2]
FIG. 15 is a plan view of the substrate in the modified example 4 of the second embodiment. The resonator having the highest temperature is the series resonator S2. Therefore, as shown in FIG. 15, the insulating film 22 is provided so as to surround the series resonators S1 to S3 and the parallel resonators P1 and P2 adjacent to the series resonator S2 in a plan view, and is not adjacent to the series resonator S2. It is not provided so as to surround the series resonator S4 and the parallel resonator P3. As a result, heat can be efficiently dissipated from the series resonator S2, and deterioration of characteristics due to the insulating film 22 approaching the resonator can be suppressed. Other configurations are the same as those of the second embodiment and the first modification thereof, and the description thereof will be omitted.

[実施例2の変形例5]
図16は、実施例2の変形例5における基板の平面図である。図16に示すように、絶縁膜22を、平面視において直列共振器S2を囲み直列共振器S1、S3、S4および並列共振器P1からP3を囲まないように設ける。これにより、直列共振器S2から効率的に放熱し、かつ絶縁膜22が共振器に近接することによる特性の劣化を抑制できる。その他の構成は実施例2およびその変形例1と同じであり説明を省略する。
[Modification 5 of Example 2]
FIG. 16 is a plan view of the substrate in the modified example 5 of the second embodiment. As shown in FIG. 16, the insulating film 22 is provided so as to surround the series resonator S2 in a plan view and not to surround the series resonators S1, S3, S4 and the parallel resonators P1 to P3. As a result, heat can be efficiently dissipated from the series resonator S2, and deterioration of characteristics due to the insulating film 22 approaching the resonator can be suppressed. Other configurations are the same as those of the second embodiment and the first modification thereof, and the description thereof will be omitted.

実施例2の変形例4および5のように、絶縁膜22を平面視において複数の機能素子12aの一部を各々囲み複数の機能素子12aの他を囲まないように設ける。これにより、放熱性を高めかつ特性の劣化を抑制できる。 As in the modifications 4 and 5 of the second embodiment, the insulating film 22 is provided so as to surround a part of each of the plurality of functional elements 12a in a plan view and not to surround the other of the plurality of functional elements 12a. As a result, heat dissipation can be improved and deterioration of characteristics can be suppressed.

ラダー型フィルタでは、直列共振器が並列共振器より発熱しやすい。そこで、絶縁膜22を平面視において1または複数の直列共振器S1からS4の少なくとも1つを各々囲み、1または複数の直列共振器S1からS4および1または複数の並列共振器P1からP3のうち他の共振器の少なくとも一部を囲まないようにする。これにより、放熱性を高めかつ特性の劣化を抑制できる。 In the ladder type filter, the series resonator generates more heat than the parallel resonator. Therefore, the insulating film 22 surrounds at least one of one or more series resonators S1 to S4 in a plan view, and one or more series resonators S1 to S4 and one or more parallel resonators P1 to P3. Do not enclose at least part of the other resonator. As a result, heat dissipation can be improved and deterioration of characteristics can be suppressed.

また、直列共振器S1からS4のうち両側に直列共振器が接続された共振器は発熱しやすい。そこで、絶縁膜22を1または複数の直列共振器S1からS4のうち両側に直列共振器S1およびS3が接続された直列共振器S2を囲み、1または複数の直列共振器S1からSS4および1または複数の並列共振器P1からP3のうち他の共振器の少なくとも一部と囲まないようにする。これにより、放熱性を高めかつ特性の劣化を抑制できる。 Further, the resonator in which the series resonators are connected to both sides of the series resonators S1 to S4 tends to generate heat. Therefore, the insulating film 22 surrounds the series resonator S2 in which the series resonators S1 and S3 are connected to both sides of the one or more series resonators S1 to S4, and one or more series resonators S1 to SS4 and 1 or Do not surround the plurality of parallel resonators P1 to P3 with at least a part of other resonators. As a result, heat dissipation can be improved and deterioration of characteristics can be suppressed.

実施例2およびその変形例において、発熱するデバイスチップ11aは送信フィルタ60が設けられているチップである。そこで、絶縁膜22を、基板20の上面と、受信フィルタ62が設けられた基板10b(第3基板)の下面(第4面)との間に設けない。これにより、特性の劣化を抑制しかつ放熱性を高めることができる。 In the second embodiment and its modifications, the device chip 11a that generates heat is a chip provided with the transmission filter 60. Therefore, the insulating film 22 is not provided between the upper surface of the substrate 20 and the lower surface (fourth surface) of the substrate 10b (third substrate) provided with the receiving filter 62. As a result, deterioration of characteristics can be suppressed and heat dissipation can be improved.

実施例2およびその変形例として、機能素子12aおよび12bが弾性表面波共振器の例を説明したが、機能素子12aおよび12bは圧電薄膜共振器でもよい。ラダー型フィルタの直列共振器および並列共振器の数は任意に設定できる。フィルタとしてラダー型フィルタを例に説明したが、フィルタは多重モードフィルタでもよい。マルチプレクサとしてデュプレクサの例を説明したが、トリプレクサまたはクワッドプレクサでもよい。 Although the functional elements 12a and 12b have described examples of surface acoustic wave resonators as Examples 2 and its modifications, the functional elements 12a and 12b may be piezoelectric thin film resonators. The number of series resonators and parallel resonators of the ladder type filter can be set arbitrarily. A ladder type filter has been described as an example of the filter, but the filter may be a multiple mode filter. Although the example of a duplexer has been described as a multiplexer, a triplexer or a quadplexer may be used.

実施例1、2およびその変形例において、機能素子12または12aは、アンプおよび/またはスイッチのような能動素子でもよい。また、機能素子12または12aは、インダクタおよび/またはキャパシタ等の受動素子でもよい。さらに、機能素子12または12bはMEMS(Micro Electro Mechanical Systems)素子でもよい。 In Examples 1 and 2 and modifications thereof, the functional element 12 or 12a may be an active element such as an amplifier and / or a switch. Further, the functional element 12 or 12a may be a passive element such as an inductor and / or a capacitor. Further, the functional element 12 or 12b may be a MEMS (Micro Electro Mechanical Systems) element.

以上、本発明の実施例について詳述したが、本発明はかかる特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。 Although the examples of the present invention have been described in detail above, the present invention is not limited to such specific examples, and various modifications and modifications are made within the scope of the gist of the present invention described in the claims. It can be changed.

10、10a、10b、20 基板
11,11a、11b デバイスチップ
12、12a、12b 機能素子
14 空隙
16 バンプ
18、28 金属層
22 絶縁膜
60 送信フィルタ
62 受信フィルタ
10, 10a, 10b, 20 Substrate 11, 11a, 11b Device chip 12, 12a, 12b Functional element 14 Void 16 Bump 18, 28 Metal layer 22 Insulating film 60 Transmission filter 62 Reception filter

Claims (11)

第1面を有する第1基板と、
1または複数の第1機能素子が設けられた第2面を有し、前記1または複数の第1機能素子が前記第1面と空隙を挟み対向するように、前記第1基板上に実装された第2基板と、
前記第1面と前記第2面との間に設けられ、前記第1基板と前記第2基板とを接続する接続端子と、
前記第1面および前記第2面のいずれか一方に設けられ、平面視において前記1または複数の第1機能素子のうち少なくとも1つの第1機能素子を囲み、前記少なくとも1つの第1機能素子との距離が前記接続端子と前記少なくとも1つの第1機能素子との距離より小さく、少なくとも一部が前記空隙を挟み前記第1面および前記第2面の他方と対向する第3面を有する絶縁膜と、
を具備し、
前記第1面と前記第2面との間において、前記第1面および前記第2面の両方に接触し前記第1機能素子を前記空隙に封止する封止部は設けられていない電子部品。
A first substrate having a first surface and
It has a second surface provided with one or more first functional elements, and the one or more first functional elements are mounted on the first substrate so as to face the first surface with a gap in between. 2nd board and
A connection terminal provided between the first surface and the second surface and connecting the first substrate and the second substrate,
It is provided on either one of the first surface and the second surface, surrounds at least one first functional element of the one or a plurality of first functional elements in a plan view, and is formed with the at least one first functional element. Is smaller than the distance between the connection terminal and the at least one first functional element, and at least a part of the insulating film has a third surface facing the first surface and the other of the second surface with the gap in between. When,
Equipped with
An electronic component that is not provided with a sealing portion between the first surface and the second surface that contacts both the first surface and the second surface and seals the first functional element in the gap. ..
前記1または複数の第1機能素子は複数の第1機能素子であり、
平面視において前記絶縁膜は前記複数の第1機能素子を各々囲む請求項1記載の電子部品。
The one or more first functional elements are a plurality of first functional elements, and the first functional element is a plurality of first functional elements.
The electronic component according to claim 1, wherein the insulating film surrounds each of the plurality of first functional elements in a plan view.
第1面を有する第1基板と、
1または複数の第1機能素子が設けられた第2面を有し、前記1または複数の第1機能素子が前記第1面と空隙を挟み対向するように、前記第1基板上に実装された第2基板と、
前記第1面と前記第2面との間に設けられ、前記第1基板と前記第2基板とを接続する接続端子と、
前記第1面および前記第2面のいずれか一方に設けられ、平面視において前記1または複数の第1機能素子のうち少なくとも1つの第1機能素子を囲み、前記少なくとも1つの第1機能素子との距離が前記接続端子と前記少なくとも1つの第1機能素子との距離より小さく、少なくとも一部が前記空隙を挟み前記第1面および前記第2面の他方と対向する第3面を有する絶縁膜と、
を具備し、
前記1または複数の第1機能素子は複数の第1機能素子であり、
平面視において、前記絶縁膜は、前記複数の第1機能素子のうち一部の第1機能素子を各々囲み、他の第1機能素子を囲まない電子部品
A first substrate having a first surface and
It has a second surface provided with one or more first functional elements, and the one or more first functional elements are mounted on the first substrate so as to face the first surface with a gap in between. 2nd board and
A connection terminal provided between the first surface and the second surface and connecting the first substrate and the second substrate,
It is provided on either one of the first surface and the second surface, surrounds at least one first functional element of the one or a plurality of first functional elements in a plan view, and is formed with the at least one first functional element. Is smaller than the distance between the connection terminal and the at least one first functional element, and at least a part of the insulating film has a third surface facing the first surface and the other of the second surface with the gap in between. When,
Equipped with
The one or more first functional elements are a plurality of first functional elements, and the first functional element is a plurality of first functional elements.
In a plan view, the insulating film is an electronic component that surrounds a part of the first functional elements of the plurality of first functional elements and does not surround the other first functional elements.
第1面を有する第1基板と、
複数の弾性波素子が設けられた第2面を有し、前記複数の弾性波素子が前記第1面と空隙を挟み対向するように、前記第1基板上に実装された第2基板と、
前記第1面と前記第2面との間に設けられ、前記第1基板と前記第2基板とを接続する接続端子と、
前記第1面および前記第2面のいずれか一方に設けられ、平面視において前記複数の弾性波素子のうち少なくとも1つの弾性波素子を囲み、前記少なくとも1つの弾性波素子との距離が前記接続端子と前記少なくとも1つの弾性波素子との距離より小さく、少なくとも一部が前記空隙を挟み前記第1面および前記第2面の他方と対向する第3面を有する絶縁膜と、
入力端子と出力端子との間に直列に接続され前記複数の弾性波素子のうち一部である1または複数の直列共振器と、
前記入力端子と前記出力端子との間に並列に接続され前記複数の弾性波素子の別の一部である1または複数の並列共振器と、
を具備し、
平面視において前記絶縁膜は前記1または複数の直列共振器の少なくとも1つを囲み、前記1または複数の直列共振器および前記1または複数の並列共振器のうち他の共振器の少なくとも一部を囲まない電子部品
A first substrate having a first surface and
A second substrate mounted on the first substrate so as to have a second surface provided with a plurality of elastic wave elements so that the plurality of elastic wave elements face the first surface with a gap in between.
A connection terminal provided between the first surface and the second surface and connecting the first substrate and the second substrate,
It is provided on either one of the first surface and the second surface, surrounds at least one elastic wave element among the plurality of elastic wave elements in a plan view, and the distance from the at least one elastic wave element is the connection. An insulating film having a third surface that is smaller than the distance between the terminal and the at least one elastic wave element and has at least a part sandwiching the gap and facing the other of the first surface and the second surface.
One or more series resonators connected in series between the input terminal and the output terminal and are a part of the plurality of elastic wave elements.
One or more parallel resonators connected in parallel between the input terminal and the output terminal and which are another part of the plurality of elastic wave elements.
Equipped with
In plan view, the insulating film surrounds at least one of the one or more series resonators, and at least a part of the one or more series resonators and the other resonator among the one or more parallel resonators. Electronic components that do not surround.
平面視において前記絶縁膜は前記1または複数の直列共振器のうち両側に直列共振器が接続された直列共振器を囲み、前記1または複数の直列共振器および前記1または複数の並列共振器のうち他の共振器の少なくとも一部を囲まない請求項記載の電子部品。 In plan view, the insulating film surrounds a series resonator in which series resonators are connected to both sides of the one or more series resonators, and the one or more series resonators and the one or more parallel resonators. The electronic component according to claim 4 , wherein at least a part of the other resonator is not enclosed. 第1面を有する第1基板と、
1または複数の第1機能素子が設けられた第2面を有し、前記1または複数の第1機能素子が前記第1面と空隙を挟み対向するように、前記第1基板上に実装された第2基板と、
前記第1面と前記第2面との間に設けられ、前記第1基板と前記第2基板とを接続する接続端子と、
前記第1面および前記第2面のいずれか一方に設けられ、平面視において前記1または複数の第1機能素子のうち少なくとも1つの第1機能素子を囲み、前記少なくとも1つの第1機能素子との距離が前記接続端子と前記少なくとも1つの第1機能素子との距離より小さく、少なくとも一部が前記空隙を挟み前記第1面および前記第2面の他方と対向する第3面を有する絶縁膜と、
1または複数の第2機能素子が設けられた第4面を有し、前記1または複数の第2機能素子が前記第1面と空隙を挟み対向するように、前記第1基板上に実装された第3基板を具備し、
前記絶縁膜は前記第1面と前記第4面との間に設けられていない電子部品
A first substrate having a first surface and
It has a second surface provided with one or more first functional elements, and the one or more first functional elements are mounted on the first substrate so as to face the first surface with a gap in between. 2nd board and
A connection terminal provided between the first surface and the second surface and connecting the first substrate and the second substrate,
It is provided on either one of the first surface and the second surface, surrounds at least one first functional element of the one or a plurality of first functional elements in a plan view, and is formed with the at least one first functional element. Is smaller than the distance between the connection terminal and the at least one first functional element, and at least a part of the insulating film has a third surface facing the first surface and the other of the second surface with the gap in between. When,
It has a fourth surface provided with one or more second functional elements, and the one or more second functional elements are mounted on the first substrate so as to face the first surface with a gap in between. Also equipped with a third substrate
The insulating film is an electronic component that is not provided between the first surface and the fourth surface.
前記1または複数の第1機能素子は各々弾性波素子である請求項1から3および6のいずれか一項記載の電子部品。 The electronic component according to any one of claims 1 to 3 and 6 , wherein the one or a plurality of first functional elements are elastic wave elements, respectively. 前記絶縁膜の厚さは、前記第1面と前記第2面との距離の1/2以上である請求項1からのいずれか一項記載の電子部品。 The electronic component according to any one of claims 1 to 7 , wherein the thickness of the insulating film is ½ or more of the distance between the first surface and the second surface. 前記第3面は前記第1面および前記第2面の他方と接触しない請求項1からのいずれか一項記載の電子部品。 The electronic component according to any one of claims 1 to 8 , wherein the third surface does not come into contact with the other of the first surface and the second surface. 前記弾性波素子を含むフィルタを具備する請求項記載の電子部品。 The electronic component according to claim 7 , further comprising a filter including the elastic wave element. 前記フィルタを含むマルチプレクサを具備する請求項10記載の電子部品。
The electronic component according to claim 10, further comprising a multiplexer including the filter.
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