JP6931311B2 - 異方性導電膜またはペーストを用いて高さの異なる複数のチップを可撓性基板上に同時に接着する方法 - Google Patents

異方性導電膜またはペーストを用いて高さの異なる複数のチップを可撓性基板上に同時に接着する方法 Download PDF

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JP6931311B2
JP6931311B2 JP2017193915A JP2017193915A JP6931311B2 JP 6931311 B2 JP6931311 B2 JP 6931311B2 JP 2017193915 A JP2017193915 A JP 2017193915A JP 2017193915 A JP2017193915 A JP 2017193915A JP 6931311 B2 JP6931311 B2 JP 6931311B2
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semiconductor chips
flexible substrate
pin
semiconductor chip
aca
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JP2018074148A (ja
JP2018074148A5 (enExample
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ブレント・エス・クルソー
ピン・メイ
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パロ アルト リサーチ センター インコーポレイテッド
パロ アルト リサーチ センター インコーポレイテッド
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    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector

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JP2020119983A (ja) * 2019-01-23 2020-08-06 トヨタ自動車株式会社 半導体素子接合装置、及び半導体素子接合方法
KR102789194B1 (ko) * 2020-05-12 2025-03-28 삼성전자주식회사 반도체 칩 실장용 테이프 및 상기 테이프를 이용한 반도체 패키지 제조 방법
TWI786447B (zh) * 2020-10-15 2022-12-11 均華精密工業股份有限公司 生產設備及預接合裝置
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