JP6877846B2 - Pachinko machine - Google Patents

Description

The present invention relates to a gaming machine such as a pachinko machine.

Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when a game ball wins a prize at the starting port, and a big hit game is performed when the result of the lottery is a big hit. Further, for example, a liquid crystal display for displaying the effect image is provided, and the effect image determined by lottery is displayed on the liquid crystal display.

In this type of gaming machine, lottery is performed in various situations, and the lottery is performed by generating and acquiring random numbers. For example, in Patent Document 1, the number of digits of a newly acquired random number value is determined, a one-digit numerical value is calculated from the reference random number value by the determined number of digits, and the calculated value is arranged in each digit. How to get a good number is described. (See, for example, Patent Document 1).

JP-A-2017-023629

In the random number acquisition process for acquiring random numbers, it is required that the acquired random numbers are less likely to have regularity. However, if the processing is complicated, the control load becomes large, which is not preferable. Therefore, it is preferable to perform a random number acquisition process in which regularity is unlikely to occur while suppressing an increase in the control load.

The present invention has been made in view of such a point, and an object of the present invention is to provide a gaming machine capable of performing processing in which regularity is unlikely to occur while suppressing an increase in a control load.

The gaming machine according to the present invention
A gaming machine that draws lots using a predetermined random number.
A real-time clock (for example, RTC) that can output time information,
A random number generating means for generating a random number used in a predetermined lottery (for example, a host control circuit 210 that executes the processes of FIGS. 70 and 71) and
With
The random number generating means
An initialization means (for example, a host control circuit 210 that executes a random number initialization process) that acquires time information from the real-time clock and generates an initial value of a random number using the acquired time information.
A steady-state update means ( for example, a host control circuit 210 that executes the process of FIG. 70 ) that periodically updates the random number at a predetermined cycle (for example, 33.3 msec) regardless of whether or not the generated random number is used for the lottery. )When,
An unsteady update means (for example, a host control circuit 210 that executes the process of FIG. 71) that updates a random number when the generated random number is used in the lottery even if the period is not the predetermined period.
It is characterized by having.

According to the above-mentioned gaming machine, since the initial value of the random number is generated using the time information acquired from the real-time clock, the acquired random number can be randomized, and the acquired random number is biased. Can be suppressed. In particular, since the initial value of the random number is involved in the time when the power is turned on in units of minutes and seconds, it is possible to make the initial value different each time.

According to the present invention, it is possible to provide a gaming machine capable of performing processing in which regularity is unlikely to occur while suppressing an increase in a control load.

It is a figure which shows the functional flow of the pachinko gaming machine which concerns on one Embodiment of this invention. It is external perspective view of the pachinko gaming machine which concerns on one Embodiment of this invention. It is an exploded perspective view of the pachinko gaming machine which concerns on one Embodiment of this invention. It is a front view which shows the structure of the game board of the pachinko game machine which concerns on one Embodiment of this invention. It is a block diagram which shows the circuit structure of the pachinko gaming machine which concerns on one Embodiment of this invention. It is a block diagram which shows the internal structure of the sub-control circuit of the pachinko gaming machine which concerns on one Embodiment of this invention. It is a block diagram which shows the internal structure of the voice / LED control circuit of the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure for demonstrating an example of the output signal of the voice / LED control circuit in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a control block diagram for demonstrating an example of volume control by a host control circuit in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a schematic connection configuration diagram between the built-in relay board and the speaker of the pachinko gaming machine which concerns on one Embodiment of this invention. It is a block diagram which shows the internal structure of the display control circuit of the pachinko gaming machine which concerns on one Embodiment of this invention. It is a schematic connection configuration diagram between the sub-board and the CGROM board (NOR type) of the pachinko gaming machine which concerns on one Embodiment of this invention. It is a schematic connection configuration diagram between the sub-board and the CGROM board (NAND type) of the pachinko gaming machine which concerns on one Embodiment of this invention. It is a truth table for explaining the operation of the AND circuit provided in the sub-board of the pachinko gaming machine which concerns on one Embodiment of this invention. It is a truth table for explaining the operation of the bidirectional balance transceiver provided in the sub-board of the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the big hit random number determination table (at the time of the 1st start opening winning) in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the big hit random number determination table (at the time of the 2nd start opening winning) in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the symbol determination table (at the time of the 1st start opening winning) in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the symbol determination table (at the time of the 2nd start opening winning) in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the jackpot type determination table (the 1) in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the jackpot type determination table (the 2) in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the jackpot type determination table (the 3) in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the jackpot type determination table (the 4) in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the effect information determination table at the time of winning in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the variation effect pattern determination table in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows an example of the variation effect table in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure for demonstrating the outline of the drawing process in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the main control main processing executed by the main CPU in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the special symbol control processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the special symbol memory check processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the special symbol display time management processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the jackpot end interval processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the system timer interrupt processing executed by the main CPU in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the switch input detection processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the start opening prize detection processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the sub-control main process executed by the host control circuit (sub-control circuit) in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the timer interrupt processing executed by the host control circuit (sub-control circuit) in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a figure which shows an example for demonstrating the sub-device input discrimination information created in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the sub-device input processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the sub-device input ON edge information (with a repeat function) processing in the pachinko gaming machine which concerns on one Embodiment of this invention. An example of the sub-device input ON edge information (with repeat function) processing in the pachinko gaming machine according to the embodiment of the present invention is shown, and is a flowchart continuing from FIG. 40. It is a figure for conceptually explaining the backlight control process in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the backlight control processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the timer interrupt processing which accompanies the modification of the backlight control processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows the modification of the backlight control processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the timer interrupt processing which shows the backlight control processing in the pachinko gaming machine which concerns on one Embodiment of this invention. In the pachinko gaming machine according to the embodiment of the present invention, the sub-control main process (overall flow) executed by the host control circuit for explaining the first embodiment of the process of adjusting the brightness of the backlight and various LEDs. .. In the pachinko gaming machine according to the embodiment of the present invention, it is a sub-control main process (overall flow) executed by a host control circuit for explaining a second embodiment of the process of adjusting the brightness of the backlight and various LEDs. .. In the pachinko gaming machine according to the embodiment of the present invention, it is a sub-control main process (overall flow) executed by a host control circuit for explaining a third embodiment of the process of adjusting the brightness of the backlight and various LEDs. .. It is a flowchart which shows an example of RTC acquisition processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the animation control main processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of composition reproduction control processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the sound amplifier check process in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the amplifier check process for use in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the amplifier check process for deep bass in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the sound amplifier check processing which performs the normal amplifier / deep bass amplifier (collective) check processing in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the more preferable form of the sound amplifier check process in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of a more preferable form of the amplifier check process for a normal use amplifier and a deep bass in a pachinko gaming machine which concerns on one Embodiment of this invention. An example of a more preferable form of a normal amplifier / deep bass amplifier check process in a pachinko gaming machine according to an embodiment of the present invention is shown, and is a flowchart continuing from FIG. 58. It is a flowchart which shows an example of the sound request control processing when there are a plurality of sound requests for the same channel in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows 1st Embodiment of the sound request control processing at the time of volume adjustment in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows the 2nd Embodiment of the sound request control processing at the time of volume adjustment in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows the 3rd Embodiment of the sound request control processing at the time of volume adjustment in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows 4th Embodiment of the sound request control processing at the time of volume adjustment in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows 5th Embodiment of the sound request control processing at the time of volume adjustment in the pachinko gaming machine which concerns on one Embodiment of this invention. It is an attenuation table which shows an example of the luminance attenuation value of each color (red, green, blue) corresponding to the light emission intensity of strong, medium, and weak LEDs in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a block diagram which shows an example of the connection state of an LED port, an LED and a solenoid in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the data load processing which is executed as one of various initialization processing by a host control circuit in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the random number initialization process which is executed as one of various initialization processes by a host control circuit in the pachinko gaming machine which concerns on one Embodiment of this invention. It is a flowchart which shows an example of the random number periodical update process in the pachinko gaming machine which concerns on one Embodiment of this invention. In the pachinko gaming machine according to the embodiment of the present invention, (a) a flowchart showing an example of random number 1 acquisition processing, (b) a flowchart showing an example of random number 2 acquisition processing, and (c) an example of random number 3 acquisition processing are shown. The flowchart, (d) is the flowchart which shows an example of the random number 4 acquisition process. It is a flowchart which shows an example of the random number acquisition processing which is executed when a random number is used in the pachinko gaming machine which concerns on one Embodiment of this invention. This is a sub-control main process (overall flow) executed by a host control circuit for explaining a modified example of the sub-random number process in the pachinko gaming machine according to the embodiment of the present invention. It is a flowchart which shows an example of the reception interrupt processing executed by the host control circuit in the pachinko gaming machine which concerns on one Embodiment of this invention.

Hereinafter, the configuration and various operations of the pachinko gaming machine (gaming machine) according to the embodiment of the present invention will be described with reference to the drawings.

<Function flow>
First, the functions of the pachinko gaming machine according to the present embodiment will be described with reference to FIG. FIG. 1 is a diagram showing a functional flow of a pachinko gaming machine according to the present embodiment.

As shown in FIG. 1, the pachinko game is a game in which a game ball is launched by a user's operation, and when the game ball wins various prizes, the payout control process of the game ball is performed. Further, the pachinko game includes a special symbol game using a special symbol and a normal symbol game using a normal symbol. When it becomes a "big hit" in a special symbol game or when it becomes a "hit" in a normal symbol game, the possibility that the game ball wins is relatively increased, and the payout control process of the game ball is easily performed. Become.

In addition, various prizes include a special symbol start prize, which is one condition for variable display of a special symbol in a special symbol game, and one condition for variable display of a normal symbol in a normal symbol game. A certain ordinary symbol start prize is also included.

The "variable display" referred to in the present specification is a concept that is displayed in a variable manner. For example, a "variable display" that is actually displayed in a variable manner and a "stop display" that is actually stopped and displayed. , Etc. are possible. Further, in the "variable display", for example, a "derivative display" in which a special symbol (identification information) is displayed as a result of a special symbol game can be performed. That is, in the present specification, the operation from the start of the "variable display" to the "derivative display" is referred to as one "variable display". Further, in the present specification, the "identification information" refers to "designs" used in pachinko games such as special symbols, ordinary symbols, decorative symbols, and identification symbols, and identification symbols and decorations used in pachislot or slot games. It means that a symbol used when displaying or suggesting the result of the game may be included in the player playing the game, such as a symbol, and the various symbols in the embodiments and various modifications described below are also included. Can include.

The outline of the processing flow of the special symbol game and the ordinary symbol game will be described below.

(1) Special symbol game When a special symbol start prize is awarded in the special symbol game, random numbers (big hit determination random value and symbol determination random value) are extracted from the jackpot determination counter and the symbol determination counter, respectively. , Each extracted random number value is stored (see the flow of the special symbol start winning process in the special symbol game shown in FIG. 1).

Further, as shown in FIG. 1, in the special symbol control process during the special symbol game, it is first determined whether or not the condition for starting the variable display of the special symbol is satisfied. In this determination process, it is referred to whether or not the random number value is memorized by the special symbol start winning, and one condition is that the random value is memorized, and the condition for starting the variable display of the special symbol is satisfied. judge.

Next, when the variable display of the special symbol is started, the jackpot determination random value extracted from the jackpot determination counter is referred to, and the jackpot determination as to whether or not to make a "big hit" is performed. After that, the stop symbol determination process is performed. In this process, the symbol determination random value extracted from the symbol determination counter and the result of the jackpot determination described above are referred to, and a special symbol to be stopped and displayed is determined.

Next, the fluctuation pattern determination process is performed. In this process, a random number value is extracted from the fluctuation pattern determination counter, and the random value, the result of the jackpot determination described above, and the special symbol to be stopped and displayed described above are referred to, and the fluctuation pattern of the special symbol is determined.

Next, the effect pattern determination process is performed. In this process, a random number value is extracted from the effect pattern determination counter, and the random number value, the result of the jackpot determination described above, the special symbol to be stopped and displayed described above, and the fluctuation pattern of the special symbol described above are referred to. Determine the effect pattern to be executed along with the variable display of the special symbol.

Next, as a result of the determined jackpot determination, the special symbol to be stopped and displayed, the variation pattern of the special symbol, and the effect pattern accompanying the variable display of the special symbol are referred to, and the variable display control process for controlling the variable display of the special symbol is performed. , And the effect control process for performing a predetermined effect is executed.

Then, when the variable display control process and the effect display control process are completed, it is determined whether or not the "big hit" is achieved. In this determination process, if it is determined that the "big hit" has been achieved, the big hit game control process for performing the big hit game is executed. In the jackpot game, the possibility of various winnings described above increases. On the other hand, if it is determined that the "big hit" has not been achieved, the big hit game control process is not executed.

When it is determined that the "big hit" has not been achieved, or when the big hit game control process is completed, the game state transition control process for shifting the game state is performed. In this game state transition control process, the game state at the normal time, which is different from the jackpot game state, is managed. As the normal gaming state, for example, in the above-mentioned jackpot determination, a gaming state in which the probability of being determined as a "big hit" increases (hereinafter, referred to as a "probability variable gaming state") and a special symbol start winning prize can be easily obtained. A game state (hereinafter referred to as a "short-time game state") and the like can be mentioned. After that, the determination process of whether or not to start the variable display of the special symbol is performed again, and then various processes of the above-mentioned special symbol control process are repeated.

In the pachinko gaming machine of the present embodiment, when the game ball starts winning a prize during the variable display of the special symbol, various data (random value for jackpot determination, random value for determining symbol, etc.) acquired at the time of the starting prize are obtained. ) Is put on hold. That is, if the game ball wins a start prize during the variable display of the special symbol, the variable display (variable display) of the special symbol corresponding to the start prize is suspended, and after the currently executed variable display of the special symbol ends. The variable display of the reserved special symbol is started. In the following, the variable display of the special symbol on hold is also referred to as a "holding ball".

Further, in the pachinko gaming machine of the present embodiment, as will be described later, two types of special symbol start prizes (first start opening prize and second start opening prize) are provided, and a maximum of four for each special symbol start prize. You can get the reserved ball. That is, in the present embodiment, a maximum of eight reserved balls can be acquired.

Further, although not shown in FIG. 1, the pachinko gaming machine of the present embodiment determines whether or not the reserved ball has been won (whether or not the "big hit" has been won) based on the above-mentioned information on the reserved ball, and further, the determination result is used. It also has a function of performing a predetermined effect based on that, that is, a look-ahead effect function.

(2) Normal symbol game When there is a normal symbol start prize in the normal symbol game, a random number value is extracted from the hit judgment counter and the random value value is stored (normal in the normal symbol game shown in FIG. 1). See the flow of the symbol start winning process).

Further, as shown in FIG. 1, in the normal symbol control process during the normal symbol game, it is first determined whether or not the condition for starting the variable display of the normal symbol is satisfied. In this determination process, it is referred to whether or not the random number value is stored by the normal symbol start winning, and one condition is that the random value is stored, and the condition for starting the variable display of the normal symbol is satisfied. judge.

Next, when the variable display of the normal symbol is started, the random value extracted from the hit determination counter is referred to, and the hit determination as to whether or not to make a "hit" is performed. After that, the fluctuation pattern determination process is performed. In this process, the result of the hit determination is referred to, and the fluctuation pattern of the normal symbol is determined.

Next, the determined hit determination result and the variation pattern of the normal symbol are referred to, and the variable display control process for controlling the variable display of the normal symbol and the effect control process for performing a predetermined effect are executed.

When the variable display control process and the effect display control process are completed, it is determined whether or not the result is a "hit". In this determination process, if it is determined to be a "hit", a hit game control process for performing a hit game is executed. In the winning game control process, the possibility of various winnings described above, in particular, the possibility of winning a special symbol start of the game ball in the special symbol game increases. On the other hand, if it is determined that the result is not "hit", the hit game control process is not executed. After that, the determination process of whether or not to start the variable display of the ordinary symbol is performed again, and then various processes of the above-mentioned ordinary symbol control process are repeated.

As described above, in the pachinko game, the payout control of the game ball is determined by the conditions such as whether or not the special symbol game is a "big hit", the transition status of the game state, and whether or not the normal symbol game is a "hit". The ease with which processing is performed changes.

In this embodiment, as various random number value extraction methods, a soft random number method that generates random number values by executing a program is used. However, the present invention is not limited to this, and for example, when the pachinko game machine includes a random number generator in which random numbers are updated at a predetermined cycle, a random number value is obtained from a counter (so-called ring counter) in the random number generator. The hard random number method for extracting the above-mentioned random number values may be adopted as the above-mentioned extraction method for various random number values. When the hard random number method is used, it is possible to prevent the same random number value from being extracted in the predetermined cycle by determining the initial value of the random number value at a timing different from the predetermined cycle.

<Structure of pachinko game machine>
Next, the structure of the pachinko gaming machine according to the present embodiment will be described with reference to FIGS. 2 and 3. Note that FIG. 2 is a perspective view showing the appearance of the pachinko gaming machine. Further, FIG. 3 is an exploded perspective view of the pachinko gaming machine.

As shown in FIGS. 2 and 3, the pachinko gaming machine 1 includes a main body 2, a base door 3 that is openable and closable to the main body 2, and a glass door that is openable and closable to the base door 3. 4 and.

[Main body]
The main body 2 is composed of a frame-shaped member having a rectangular opening 2a (see FIG. 3). The main body 2 is formed of a material such as wood.

[Base door]
The base door 3 is composed of a plate-shaped member having a rectangular outer shape substantially equal to the outer shape of the main body 2. The base door 3 is arranged in front of the main body 2 (front side of the pachinko gaming machine 1), and by rotating the base door 3 around one side end of the main body 2, the main body 2 The opening 2a is opened and closed. As shown in FIG. 3, the base door 3 is provided with a square opening 3a. The opening 3a is formed from a substantially central portion of the base door 3 to an upper region, and is formed in a size that occupies most of the region.

Further, a speaker 11, a game board 12, a display device 13, a dish unit 14, a launching device 15, a payout device 16, and a board unit 17 are attached to the base door 3.

The speaker 11 is arranged at the upper part (near the upper end portion) of the base door 3. The game board 12 is arranged in front of the base door 3 (front side of the pachinko gaming machine 1) and is arranged so as to cover the opening 3a of the base door 3.

The game board 12 is composed of a plate-shaped resin member having light transmission. As the light-transmitting resin, for example, an acrylic resin, a polycarbonate resin, a methacrylic resin, or the like can be used.

Further, on the front surface of the gaming board 12 (the surface on the front side of the pachinko gaming machine 1), a gaming area 12a on which the gaming balls launched from the launching device 15 roll is formed. The game area 12a is an area surrounded by the guide rail 41 (specifically, the outer rail 41a shown in FIG. 4 described later), and the outer peripheral shape thereof is substantially circular. Further, a plurality of game nails (see FIG. 4 described later) are driven into the game area 12a. The configuration of the game board 12 (game area 12a) will be described in detail later with reference to FIG. 4 described later.

The display device 13 is attached to the back side of the game board 12 (the side opposite to the front side of the pachinko game machine 1). The display device 13 has a display area 13a for displaying an image. The size of the display area 13a is set so as to occupy all or a part of the surface of the game board 12. In the display area 13a of the display device 13, various images such as an identification symbol for effect, an effect image, and a decorative image (decorative symbol) are displayed based on the result of a special symbol lottery process described later. The player can visually recognize various images displayed in the display area 13a of the display device 13 via the game board 12.

In this embodiment, a liquid crystal display device is used as the display device 13. However, the present invention is not limited to this, and a display device such as a plasma display, a rear projection display, or a CRT (Cathode Ray Tube) display may be applied as the display device 13.

Further, a spacer 19 is provided on the back side of the game board 12 (the side opposite to the front side of the pachinko game machine 1). The spacer 19 is provided between the back surface of the gaming board 12 (the surface on the back side of the pachinko gaming machine 1) and the front surface of the display device 13 (the surface on the front side of the pachinko gaming machine 1). It forms a space that serves as a flow path for a gaming ball that rolls in the region 12a. The spacer 19 is made of a light-transmitting material. The present invention is not limited to this, and the spacer 19 may be, for example, partially formed of a light-transmitting material or a non-light-transmitting material. ..

The plate unit 14 is arranged below the game board 12. The plate unit 14 has an upper plate 21 and a lower plate 22 arranged below the upper plate 21. As shown in FIG. 2, the upper plate 21 and the lower plate 22 are formed with a payout outlet 21a and a payout outlet 22a for lending the game ball and paying out the game ball (prize ball), respectively. When the predetermined payout conditions are satisfied, the game balls are discharged from the payout port 21a and the payout port 22a, and are stored in the upper plate 21 and the lower plate 22, respectively. Further, the game ball stored in the upper plate 21 is launched into the game area 12a by the launching device 15.

Further, the plate unit 14 is provided with an effect button 23. The effect button 23 is mounted on the upper plate 21. Further, a dial operation unit (jog dial) 24 is rotatably attached to the peripheral edge of the effect button 23 with respect to the effect button 23. The pachinko gaming machine 1 of the present embodiment has a predetermined effect function performed by using the effect button 23 and / or the dial operation unit 24, and when performing a predetermined effect, the display area 13a of the display device 13 is displayed. An image prompting the operation of the effect button 23 and / or the dial operation unit 24 is displayed.

The launcher 15 is arranged in the lower right region (near the lower right corner) on the front surface of the base door 3. The launching device 15 includes a launching handle 25 that can be operated by the player, and a panel body 26 that engages with the lower right portion of the dish unit 14. The firing handle 25 is arranged on the front surface side of the panel body 26 and is rotatably supported by the panel body 26.

Although not shown in FIGS. 2 and 3, a solenoid actuator (driving device) for controlling the firing operation of the game ball is provided on the back side of the panel body 26. Further, although not shown in FIGS. 2 and 3, a touch sensor is provided on the peripheral edge of the launch handle 25, and a launch volume is provided inside the launch handle 25. The firing volume changes the resistance value according to the amount of rotation of the firing handle 25, and changes the electric power supplied to the solenoid actuator.

In the pachinko gaming machine 1 of the present embodiment, when the player's hand comes into contact with the touch sensor of the firing handle 25, the touch sensor outputs a detection signal. As a result, it is detected that the player holds the launch handle 25, and the game ball can be launched by the solenoid actuator. Then, when the player grasps the launch handle 25 and rotates it clockwise (clockwise when viewed from the player side), the resistance value of the launch volume changes according to the rotation angle of the launch handle 25. , The power corresponding to the resistance value is supplied to the solenoid actuator. As a result, the game balls stored in the upper plate 21 are sequentially launched, and the launched game balls are guided by the guide rail 41 (see FIG. 4 described later) and discharged to the game area 12a of the game board 12.

Further, although not shown in FIGS. 2 and 3, a launch stop button is provided on the side portion of the launch handle 25. The launch stop button is a button provided to stop the launch of the game ball by the solenoid actuator. When the player presses the launch stop button, the launch of the game ball is stopped even in the state where the launch handle 25 is gripped and rotated.

The payout device 16 and the substrate unit 17 are arranged on the back side of the base door 3. A game ball is supplied to the payout device 16 from a storage unit (not shown). The payout device 16 pays out a predetermined number of game balls from the game balls supplied from the storage unit to the upper plate 21 or the lower plate 22 based on the establishment of the payout condition. The board unit 17 has various control boards. The main control circuit 70 and the sub control circuit 200, which will be described later, are provided on the various control boards (see FIG. 5 described later).

[Glass door]
The glass door 4 is composed of a plate-shaped member having a substantially square surface. Further, the glass door 4 is arranged on the front side of the game board 12 and has a size of covering the game board 12. A speaker cover 29 is provided on the front surface of the glass door 4 in an upper region facing the speaker 11.

Further, in the central portion of the glass door 4, an opening 4a having a size that exposes at least the game area 12a is formed in the area of the game board 12 facing the game area 12a. A protective glass 28 having light transmission is attached to the opening 4a of the glass door 4, whereby the opening 4a is closed. Therefore, when the glass door 4 is closed with respect to the base door 3, the protective glass 28 is arranged so as to face at least the game area 12a of the game board 12.

[Game board]
Next, the configuration of the game board 12 will be described with reference to FIG. FIG. 4 is a front view showing the configuration of the game board 12.

On the front surface of the game board 12, as shown in FIG. 4, a guide rail 41, a ball passage detector 43, a first starting port 44, a second starting port 45 (starting area), and an ordinary electric accessory 46 And are provided. Further, on the front surface of the game board 12, there are a plurality of general winning openings 51 and 52, a first large winning opening 53 (variable winning device), a second large winning opening 54 (variable winning device), and an out opening 55. The game nail 56 is provided. Further, on the front surface of the game board 12, above the display area 13a of the display device 13 arranged substantially in the center thereof, a special symbol display device 61, a normal symbol display device 62, a normal symbol hold display device 63, and a normal symbol hold display device 63. A first special symbol hold display device 64 and a second special symbol hold display device 65 are provided.

Although not shown in FIG. 4, a 7-segment counter for directing is also provided on the front surface of the game board 12. The 7-segment counter for production is composed of a display counter capable of displaying two-digit numbers and two alphabetic characters. Further, in the present embodiment, a notification LED (Light Emitting Diode) that lights up when the result of the stop display of the special symbol is "big hit", a round number display LED that displays the number of rounds during the big hit game, and the like are provided. May be good.

[Various components of the game area]
The guide rail 41 is composed of an outer rail 41a extending in an arc shape for partitioning the game area 12a, and an inner rail 41b extending in an arc shape arranged inside (inner peripheral side) of the outer rail 41a. Will be done. The game area 12a is formed inside the outer rail 41a. The outer rail 41a and the inner rail 41b are arranged so as to face each other near the left end portion of the game area 12a when viewed from the player side, whereby the launching device is placed between the outer rail 41a and the inner rail 41b. A guide path 41c that guides the game ball launched by 15 to the upper part of the game area 12a is formed.

Further, at the tip of the inner rail 41b located on the upper left side of the game area 12a, a ball discharge port 41d is formed by the tip of the inner rail 41b and a part of the outer rail 41a facing the tip of the inner rail 41b. Then, a ball return prevention piece 42 is provided at the tip of the inner rail 41b so as to close the ball discharge port 41d. The ball return prevention piece 42 prevents the game ball released from the ball discharge port 41d into the game area 12a from passing through the ball discharge port 41d again and entering the guide path 41c.

The game ball released from the ball discharge port 41d flows down from the upper part to the lower part of the game area 12a. At this time, the game ball collides with various members provided in the game area 12a such as the plurality of game nails 56, the first start port 44, and the second start port 45, and changes the traveling direction of the game area 12a. It flows down from the top to the bottom.

A display area 13a of the display device 13 is provided at substantially the center of the game area 12a. An obstacle 13b is provided at the upper end of the display area 13a. By providing the obstacle 13b, the game ball does not pass over the area overlapping the display area 13a in the game area 12a.

The ball passage detector 43 is arranged near the right end portion of the display area 13a when viewed from the player side. The ball passing detector 43 is provided with a passing ball sensor 43a (see FIG. 5 described later) for detecting a game ball passing through the ball passing detector 43. Further, when the game ball passes through the ball passage detector 43, a lottery for whether or not it is a "hit" is performed, and the variation display of the normal symbol is started based on the result of the lottery.

The first starting port 44 is arranged below the display area 13a, and the second starting port 45 is arranged below the first starting port 44. The first starting port 44 and the second starting port 45 are made of members capable of accepting game balls. Hereinafter, the entry or passage of the game ball into or passing through the first starting port 44 or the second starting port 45 is referred to as "winning". Then, when the game balls win the first start port 44 or the second start port 45, the first predetermined number (three in the present embodiment) of the game balls are paid out. In addition, when the game ball enters the first starting port 44, a lottery is performed to determine whether it is a "big hit" or a "small hit", and the special symbol changes based on the result of the lottery. The display starts. Further, when the game ball enters the second starting port 45, a lottery for whether or not it is a "big hit" is performed, and the variable display of the special symbol is started based on the result of the lottery.

The first starting port 44 is provided with a first starting port winning ball sensor 44a (see FIG. 5 described later) for detecting a game ball that has won a prize in the first starting port 44. Further, the second starting port 45 is provided with a second starting port winning ball sensor 45a (see FIG. 5 described later) for detecting a game ball that has won a prize in the second starting port 45. The game balls that have won the first start port 44 and the second start port 45 are conveyed to the game ball collection section (not shown) through the collection port (not shown) provided on the game board 12. ..

The ordinary electric accessory 46 is provided at the second starting port 45. The ordinary electric accessory 46 includes a pair of blade members rotatably attached to both sides of the second starting port 45 and an ordinary electric accessory solenoid 46a (see FIG. 5 described later) for driving the pair of blade members. Have. The ordinary electric accessory 46 is driven by the ordinary electric accessory solenoid 46a, and is in an open state in which a pair of blade members are expanded to facilitate winning a game ball in the second starting port 45, and the pair of blade members are closed. One of the closed states that makes it impossible to win the game ball is generated in the second starting port 45. In the present embodiment, when the ordinary electric accessory 46 is in the closed state, the opening form of the pair of blade members is not a form that makes it impossible to win a prize, but a form that makes it difficult to win a game ball. May be good.

The general winning opening 51 is arranged near the lower left portion of the game area 12a when viewed from the player side. Further, the general winning opening 52 is arranged below the ball passage detector 43, and is arranged near the lower right portion of the game area 12a when viewed from the player side. The general winning opening 51 and the general winning opening 52 are made of members capable of accepting a game ball. In the following, the entry or passage of a game ball into or passing through the general winning opening 51 or the general winning opening 52 is also referred to as "winning". When a game ball wins in the general winning opening 51 or the general winning opening 52, a second predetermined number (10 in this embodiment) of game balls is paid out.

The general winning opening 51 is provided with a general winning ball sensor 51a (see FIG. 5 described later) for detecting a game ball that has won a prize in the general winning opening 51. Further, the general winning opening 52 is provided with a general winning ball sensor 52a (see FIG. 5 described later) for detecting a game ball that has won a prize in the general winning opening 52.

The first special winning opening 53 and the second special winning opening 54 are arranged below the ball passage detector 43 and between the first starting opening 44 and the general winning opening 52. The first large winning opening 53 and the second large winning opening 54 are arranged in the vertical direction along the flow path of the game ball, and the first large winning opening 53 is arranged above the second large winning opening 54. To. Both the first prize opening 53 and the second prize opening 54 are so-called attacker type opening / closing devices, and the opening / closing shutters 53a and 54a and the solenoid actuator for driving the shutter (the first in FIG. 5 to be described later). It has a large winning opening solenoid 53b and a second winning opening solenoid 54b).

Each of the first prize opening 53 and the second prize opening 54 accepts a game ball when the corresponding shutter is open (open state), and when the shutter is closed (closed state), the game is played. Do not accept the ball. In the following, the entry or passage of a game ball into or passing through the first prize opening 53 or the second prize opening 54 is also referred to as "winning". When a game ball wins in the first large winning opening 53, a third predetermined number of balls (10 in this embodiment) are paid out. On the other hand, when a game ball wins in the second large winning opening 54, a fourth predetermined number of balls (15 in the present embodiment) are paid out.

Further, the first large winning opening 53 is provided with a count sensor 53c (see FIG. 5 described later) for counting the game balls that have won the first large winning opening 53. Further, the second large winning opening 54 is provided with a count sensor 54c (see FIG. 5 described later) for counting the game balls that have won the second large winning opening 54.

The out port 55 is provided at the bottom of the game area 12a. The out opening 55 is a game in which none of the first starting opening 44, the second starting opening 45, the general winning opening 51, the general winning opening 52, the first major winning opening 53, and the second major winning opening 54 has won a prize. Accept the ball.

When the arrangement of the various constituent members in the game area 12a of the present embodiment is as shown in FIG. 4, when the game ball is driven into the area on the right side of the game area 12a by the player (when the game ball is hit right). The game ball is guided to the second starting port 45 by the game nail 56 or the like. In this case, there is almost no possibility of winning the first starting port 44. In the present embodiment, as will be described later, it is easier for the player to win the "big hit" lottery, which is advantageous for the player, than the case where the second starting port 45 is won. Therefore, in the "short-time game state" described later, in which the winning of the second starting opening 45 becomes relatively easy, there is a possibility of winning the winning of the first starting opening 44 by hitting the right side (disadvantageous for the player). The possibility of being in a gaming state) can be reduced.

[Special symbol display device]
As shown in FIG. 4, the special symbol display device 61 is arranged substantially in the center of the upper part of the display area 13a of the display device 13.

The special symbol display device 61 is a display device that variably displays (variable display and stop display) the special symbol in the special symbol game. In the present embodiment, as shown in FIG. 4, the special symbol display device 61 is configured by a device that displays a special symbol as a symbol composed of numbers, symbols, or the like. The present invention is not limited to this, and the special symbol display device 61 may be configured by, for example, a plurality of LEDs. In this case, a display pattern composed of turning on / off of a plurality of LEDs is represented as a special symbol.

The special symbol display device 61 displays the special symbol (identification information) in a variable manner when the game ball wins a prize in the first start port 44 or the second start port 45 (special symbol start prize). Then, the special symbol display device 61 displays the special symbol in a variable manner for a predetermined time, and then displays the stop of the special symbol. In the following, when the game ball wins the first starting port 44, the special symbol that is variablely displayed on the special symbol display device 61 is referred to as the first special symbol. Further, a special symbol that is variablely displayed on the special symbol display device 61 when the game ball wins the second starting port 45 is referred to as a second special symbol.

In the special symbol display device 61, when the first special symbol or the second special symbol stopped and displayed is in a specific mode (a mode of "big hit"), the gaming state is advantageous to the player from the normal gaming state. It shifts to the jackpot game state which is the state. That is, in the special symbol display device 61, it is "big hit" that the first special symbol or the second special symbol is stopped and displayed in a mode of shifting to the big hit game state.

In the big hit game state, the first big winning opening 53 or the second big winning opening 54 is opened. Specifically, in the present embodiment, when the game ball wins the first starting port 44 and the first special symbol is stopped and displayed in a specific mode on the special symbol display device 61, the first big winning opening 53 is in the open state. On the other hand, when the game ball wins the second starting opening 45 and the second special symbol is stopped and displayed in the special symbol display device 61 in a specific mode, the second large winning opening 54 is opened.

The open state of each large winning opening is maintained until a predetermined number of game balls are won or a certain period (for example, 30 sec) elapses. Then, when the elapsed period of the open state of each large winning opening satisfies any of these conditions, the large winning opening that was in the open state is closed.

In the following, a game in which the first large winning opening 53 or the second large winning opening 54 is in a state in which it is easy to accept a game ball (open state) is referred to as a round game. During the round game, the big prize opening will be closed. In addition, the round game is counted as the number of rounds such as one round and two rounds. For example, the first round game is referred to as a first round, and the second round game is referred to as a second round.

In the special symbol display device 61, when the stop-displayed special symbol is in a mode other than a specific mode (a mode of "loss"), the gaming state does not shift unless the fall lottery is won. That is, the special symbol game is a game in which the special symbol is displayed in a variable manner by the special symbol display device 61, and then the special symbol is stopped and displayed, and the game state is shifted or maintained depending on the result.

Further, in the pachinko gaming machine 1 of the present embodiment, when the game ball wins a prize in the first starting port 44 during the variable display of the first special symbol or the second special symbol, the variable first special symbol corresponding to the winning is changed. The display (holding ball) is put on hold. Then, when the first special symbol or the second special symbol currently being displayed in a variable manner is stopped and displayed, the pending display of the fluctuation of the first special symbol is started. In the present embodiment, the number of variable displays of the first special symbol to be held (so-called "holding number (number of holding balls)") is defined as a maximum of 4 times (pieces).

Further, in the present embodiment, when the game ball wins the second starting port 45 during the variable display of the first special symbol or the second special symbol, the variable display (holding ball) of the second special symbol corresponding to the winning is made. Is put on hold. Then, when the first special symbol or the second special symbol currently being displayed in a variable manner is stopped and displayed, the pending display of the fluctuation of the second special symbol is started. In the present embodiment, the number of variable displays (number of hold) of the second special symbol to be held is defined as a maximum of 4 times (pieces). Therefore, in the present embodiment, the maximum number of pending special symbols for variable display is eight in total.

Further, in the present embodiment, when the reserved ball of the first special symbol and the reserved ball of the second special symbol are mixed, the variable display of one special symbol is preferentially executed over the variable display of the other special symbol. .. The present invention is not limited to this, and when the reserved balls of the first special symbol and the reserved balls of the second special symbol are mixed, the variable display of the special symbols may be executed in the reserved order.

[Ordinary symbol display device]
As shown in FIG. 4, the ordinary symbol display device 62 is arranged substantially in the center of the upper part of the display area 13a of the display device 13. Then, in the present embodiment, the ordinary symbol display device 62 is arranged on the right side of the special symbol display device 61 when viewed from the player side.

The normal symbol display device 62 is a display device that variably displays (variable display and stop display) the normal symbol in the normal symbol game. In the present embodiment, as shown in FIG. 4, the ordinary symbol display device 62 is composed of two LEDs (ordinary symbol display LEDs) arranged in the vertical direction. Then, in the ordinary symbol display device 62, a display pattern composed of turning on / off of each ordinary symbol display LED is represented as a normal symbol.

The normal symbol display device 62 alternately turns on and off the two normal symbol display LEDs when the game ball passes through the ball passage detector 43, and displays the fluctuation of the normal symbol. Then, the normal symbol display device 62 performs a variable display of the normal symbol for a predetermined time, and then performs a stop display of the normal symbol.

In the ordinary symbol display device 62, when the stopped-displayed ordinary symbol is in a predetermined mode (“hit” mode), the ordinary electric accessory 46 is changed from the closed state to the open state for a predetermined period. On the other hand, when the normal symbol displayed as stopped is in a mode other than the predetermined mode (a mode of "loss"), the normal electric accessory 46 maintains the closed state. That is, the ordinary symbol game is a game in which the ordinary symbol is displayed in a variable manner by the ordinary symbol display device 62, then the ordinary symbol is stopped and displayed, and the ordinary electric accessory 46 operates according to the result.

If the game ball passes through the ball passage detector 43 during the variable display of the normal symbol, the variable display of the normal symbol is suspended. Then, when the normal symbol currently being displayed in a variable manner is stopped and displayed, the variable display of the reserved normal symbol is started. In the present embodiment, the number of variable displays of ordinary symbols to be held (that is, "the number of holdings") is defined as a maximum of 4 times (pieces).

[Ordinary symbol hold display device]
As shown in FIG. 4, the normal symbol hold display device 63 is arranged substantially in the center of the upper part of the display area 13a of the display device 13. Then, in the present embodiment, the ordinary symbol holding display device 63 is arranged below the special symbol display device 61 and the ordinary symbol display device 62.

The normal symbol hold display device 63 is a device that displays the number of holds for variable display of normal symbols. In the present embodiment, as shown in FIG. 4, the ordinary symbol hold display device 63 is composed of four LEDs (ordinary symbol hold display LEDs) arranged in the left-right direction. Then, the normal symbol hold display device 63 displays the number of holds for the variable display of the normal symbol by turning on / off each of the normal symbol hold display LEDs.

Specifically, when the number of hold of the variable display of the normal symbol is 1, the normal symbol hold display LED located on the leftmost side when viewed from the player side (the first normal symbol hold display LED from the left). Turns on and the other normal symbol hold display LEDs turn off. When the number of hold of the variable display of the normal symbol is 2, the first and second normal symbol hold display LEDs from the left are turned on, and the other normal symbol hold display LEDs are turned off. When the number of hold of the variable display of the normal symbol is 3, the 1st to 3rd normal symbol hold display LEDs from the left are turned on, and the other normal symbol hold display LEDs are turned off. Then, when the number of hold of the variable display of the normal symbol is 4, all the normal symbol hold display LEDs are turned on.

[1st special symbol hold display device]
As shown in FIG. 4, the first special symbol holding display device 64 is arranged on the upper side of the display area 13a of the display device 13 and on the left side of the special symbol display device 61 when viewed from the player side.

The first special symbol hold display device 64 is a device that displays information regarding the variable display of the first special symbol (holding ball of the first special symbol) that is being held. In the present embodiment, as shown in FIG. 4, the first special symbol hold display device 64 includes a first special symbol hold quantity display unit 64a and a first special symbol hold information display unit 64b. The first special symbol reservation information display unit 64b is arranged on the left side of the special symbol display device 61, and the first special symbol reservation quantity display unit 64a is arranged on the left side of the first special symbol reservation information display unit 64b. ..

The first special symbol reservation number display unit 64a has four LEDs (first special symbol reservation display LED) arranged in the left-right direction. The display mode of the first special symbol hold quantity display unit 64a is the same as the display mode of the normal symbol hold display device 63. That is, when the variable display of the first special symbol is held, the first special symbol hold display LED from the first special symbol hold display LED located on the leftmost side to the number of holds is displayed from the player side. Lights up.

In addition, the first special symbol hold information display unit 64b displays information about the hold ball of the first special symbol. For example, the first special symbol holding information display unit 64b displays information (identification information) regarding the holding ball of the first special symbol to be variablely displayed next as a symbol composed of numbers, symbols, and the like. The configuration of the first special symbol holding display device 64 is not limited to the example shown in FIG. 4, and can be arbitrarily configured as long as it can display at least the number of holdings of the variable display of the first special symbol. ..

[Second special symbol hold display device]
As shown in FIG. 4, the second special symbol holding display device 65 is arranged on the upper side of the display area 13a of the display device 13 and on the right side of the normal symbol display device 62 when viewed from the player side.

The second special symbol hold display device 65 is a device that displays information regarding the variable display of the second special symbol (holding ball of the second special symbol) that is being held. In the present embodiment, as shown in FIG. 4, the second special symbol hold display device 65 includes a second special symbol hold quantity display unit 65a and a second special symbol hold information display unit 65b. The second special symbol reservation information display unit 65b is arranged on the right side of the normal symbol display device 62, and the second special symbol reservation quantity display unit 65a is arranged on the right side of the second special symbol reservation information display unit 65b. ..

The second special symbol reservation number display unit 65a has four LEDs (second special symbol reservation display LED) arranged in the left-right direction. The display mode of the second special symbol hold quantity display unit 65a is the same as the display mode of the normal symbol hold display device 63. That is, when the variable display of the second special symbol is held, the second special symbol hold display LED from the second special symbol hold display LED located on the leftmost side to the number of holds is displayed on the leftmost side when viewed from the player side. Lights up.

In addition, the second special symbol hold information display unit 65b displays information about the hold ball of the second special symbol. For example, the second special symbol holding information display unit 65b displays information (identification information) regarding the holding ball of the second special symbol to be variablely displayed next by a symbol including numbers and symbols. The configuration of the second special symbol holding display device 65 is not limited to the example shown in FIG. 4, and can be arbitrarily configured as long as it can display at least the number of holdings of the variable display of the second special symbol. ..

[Display device]
The display device 13 is composed of a liquid crystal display device as described above, and performs various image display effects in the display area 13a.

Specifically, in the present embodiment, the effect image related to the special symbol displayed on the special symbol display device 61 is displayed in the display area 13a. At this time, for example, when the special symbol is being displayed in a variable manner on the special symbol display device 61, a plurality of identification symbols (decoration) composed of numbers 1 to 8 and various characters are used, except for specific cases. The symbol) is variablely displayed in the display area 13a. Then, when the special symbol is stopped and displayed in the special symbol display device 61, a plurality of decorative symbols (such as a jackpot symbol described later) corresponding to the special symbol are also stopped and displayed in the display area 13a.

Then, when the special symbol stopped and displayed on the special symbol display device 61 has a specific mode (the result of the stop display is a "big hit"), the player is made to understand that it is a "big hit". The effect image is displayed in the display area 13a. As an effect for making the player understand that it is a "big hit", for example, first, a plurality of decorative symbols stopped and displayed are arranged in a specific mode (for example, the same decorative symbols are arranged in a predetermined direction). ), And then an effect such as displaying an image notifying the "big hit" can be mentioned.

Further, in the present embodiment, in the display area 13a of the display device 13, an effect image related to the display contents of the first special symbol hold display device 64 and the second special symbol hold display device 65 is displayed. For example, in the display area 13a, hold information (for example, the same number of hold symbols as the hold number) for notifying the hold number of the variable display of the special symbol is displayed. Further, for example, in the pachinko gaming machine 1 of the present embodiment, the pre-reading effect is performed based on the information of the reserved ball of the special symbol, and the advance notice at this time is also displayed in the display area 13a.

In the present embodiment, when the normal symbol stopped and displayed on the normal symbol display device 62 is in a predetermined mode, an effect image for causing the player to grasp the information is displayed in the display area 13a of the display device 13. Further functions may be provided.

<Circuit configuration of pachinko machine>
Next, with reference to FIG. 5, the configurations of various circuits included in the pachinko gaming machine 1 of the present embodiment will be described. Note that FIG. 5 is a block diagram showing a circuit configuration of the pachinko gaming machine 1.

As shown in FIG. 5, the pachinko gaming machine 1 mainly controls a game operation, a main control circuit 70, a payout / launch control circuit 123, and a sub-control circuit that controls an effect operation according to the progress of the game. Has 200 and.

[Main control circuit]
The main control circuit 70 includes a one-chip microcomputer 77, a clock generation circuit 74, and an initial reset circuit 75. As described above, in the present embodiment, the special symbol lottery process is performed at the time of winning the first start port 44 or the second start port 45, and this process is controlled by the main control circuit 70. That is, the main control circuit 70 also serves as a means (lottery means) for performing a lottery process as to whether or not to shift the gaming state to a state advantageous to the player.

The one-chip microcomputer 77 is composed of a main CPU (Central Processing Unit) 71, a main ROM (Read Only Memory) 72, a main RAM (Random Access Memory) 73, and a serial communication unit 76. The main CPU 71, the main ROM 72, the main RAM 73, and the serial communication unit 76 may be provided separately.

Further, in the present embodiment, the configuration in which the main ROM 72 is built in the substrate of the main control circuit 70 will be described, but the present invention is not limited thereto. For example, a ROM board on which the main ROM 72 is mounted may be connected to the board of the main control circuit 70. Further, in the present embodiment, the various circuits in the main control circuit 70 may be integrally formed or may be formed as separate bodies. Further, the main ROM 72 does not have to be configured to be installed in the gaming machine, and may have a configuration capable of communicating with the gaming machine.

A clock generation circuit 74 and an initial reset circuit 75 are connected to the one-chip microcomputer 77. Various programs for controlling the operation of the pachinko gaming machine 1 by the main CPU 71 (see FIGS. 28 to 35 described later), various data tables (see FIGS. 16 to 26 described later), and the like are stored in the main ROM 72. ing.

The main CPU 71 executes various processes according to the program stored in the main ROM 72. The main RAM 73 acts as a temporary storage area when the main CPU 71 executes various processes, and the values of various flags and variables required for the main CPU 71 for the various processes are stored. In the present embodiment, the main RAM 73 is used as the temporary storage area of the main CPU 71, but the present invention is not limited to this, and any recording medium can be used as the temporary storage medium as long as it is a readable and writable storage medium. ..

The clock generation circuit 74 generates clock pulses at a predetermined cycle (for example, 2 msec) in order to execute the system timer interrupt process described later. The initial reset circuit 75 generates a reset signal when the power is turned on. Then, the serial communication unit 76 supplies a command to the sub-control circuit 200.

Further, as shown in FIG. 5, various devices that operate in response to the output signal sent from the main control circuit 70 are connected to the main control circuit 70.

Specifically, a special symbol display device 61, a normal symbol display device 62, a normal symbol hold display device 63, a first special symbol hold display device 64, and a second special symbol hold display device 65 are connected to the main control circuit 70. Will be done. Each of these devices performs a predetermined operation based on the output signal sent from the main control circuit 70. For example, when a predetermined output signal is transmitted from the main control circuit 70 to the special symbol display device 61, the special symbol display device 61 controls the operation of the variable display of the special symbol in the special symbol game based on the output signal. Do.

Further, the main control circuit 70 is connected to the ordinary electric accessory solenoid 46a, the first special winning opening solenoid 53b, and the second special winning opening solenoid 54b. Then, the main control circuit 70 drives and controls the ordinary electric accessory solenoid 46a to bring the pair of blade members of the ordinary electric accessory 46 into an open state or a closed state. Further, the main control circuit 70 drives and controls the first special winning opening solenoid 53b and the second special winning opening solenoid 54b, respectively, to open or close the first special winning opening 53 and the second special winning opening 54. To do.

Further, as shown in FIG. 5, the main control circuit 70 is connected to various sensors and receives output signals of the various sensors. Specifically, the main control circuit 70 includes a count sensor 53c, 54c, a general winning ball sensor 51a, 52a, a passing ball sensor 43a, a first starting port winning ball sensor 44a, a second starting port winning ball sensor 45a, and a backup. A clear switch 121 or the like is connected.

The count sensor 53c counts the game balls that have won in the first large winning opening 53, and outputs a predetermined output signal indicating the result to the main control circuit 70. The count sensor 54c counts the game balls that have won in the second large winning opening 54, and outputs a predetermined output signal indicating the result to the main control circuit 70. When the game ball wins in the general winning opening 51, the general winning ball sensor 51a outputs a predetermined detection signal to the main control circuit 70, and the general winning ball sensor 52a wins the game ball in the general winning opening 52. In this case, a predetermined detection signal is output to the main control circuit 70.

Further, the passing ball sensor 43a outputs a predetermined detection signal to the main control circuit 70 when the game ball passes through the ball passing detector 43. The first starting port winning ball sensor 44a outputs a predetermined detection signal to the main control circuit 70 when the game ball wins the first starting port 44. The second starting port winning ball sensor 45a outputs a predetermined detection signal to the main control circuit 70 when the game ball wins the second starting port 45. Further, the backup clear switch 121 sends a predetermined detection signal to the main control circuit 70 and the payout / launch control circuit 123 when the backup data is cleared according to the operation of the manager of the game store or the like at the time of power failure or the like. Output.

Further, a payout / launch control circuit 123 is connected to the main control circuit 70. The contents of the payout / launch control circuit 123 and various peripheral devices connected thereto will be described in detail later.

[Payout / launch control circuit and its peripherals]
The payout / launch control circuit 123 is connected to the prize ball case unit 170, the payout status notification display device 178, the lower plate full tank switch 179, the launcher 15, the external terminal plate 140, and the card unit 150. Further, the external terminal plate 140 is connected to the data display 141, and the card unit 150 is connected to the rental operation unit 151.

The payout / launch control circuit 123 inputs and outputs signals and the like to and from these peripheral devices based on various commands and the like transmitted from the main control circuit 70, and controls the operation of each peripheral device. For example, the payout / launch control circuit 123 receives a prize ball control command transmitted from the main control circuit 70 and a ball rental control signal to be described later transmitted from the card unit 150, and is predetermined to the prize ball case unit 170. Send a signal. As a result, the prize ball case unit 170 pays out the game ball.

The prize ball case unit 170 is a device for paying out game balls, and is a first 15-ball mortgage switch 172a, a second 15-ball mortgage switch 172b, a first counting switch 181a, a second counting switch 181b, and a payout. It has a motor 174. These components included in the prize ball case unit 170 are connected to the payout / launch control circuit 123, respectively.

Further, although not shown here, two ball supply passages are provided inside the prize ball case unit 170. Then, the first 15-ball collateral switch 172a detects the game ball supplied to one of the ball supply passages, and outputs a predetermined output signal indicating the detection result to the payout / launch control circuit 123. Further, the second 15-ball collateral switch 172b detects the game ball supplied to the other ball supply passage, and outputs a predetermined output signal indicating the detection result to the payout / launch control circuit 123.

Further, although not shown here, two payout passages are provided inside the prize ball case unit 170. Then, the first counting switch 181a detects the game ball paid out in one of the payout passages, and outputs a predetermined output signal indicating the detection result to the payout / launch control circuit 123. Further, the second counting switch 181b detects the game ball paid out in the other payout passage, and outputs a predetermined output signal indicating the detection result to the payout / launch control circuit 123.

The payout motor 174 is composed of a stepping motor and is driven in response to a control signal input from the payout / launch control circuit 123. The payout motor 174 rotationally drives a sprocket (rotating member) (not shown) provided in the prize ball case unit 170. Then, by the rotational operation of the sprocket, the game balls accumulated in each ball supply path move one by one to the corresponding payout passage.

The payout status notification display device 178 is a device for notifying the type of the abnormality when an abnormality occurs in the payout of the game ball, and is composed of a 7-segment display. The payout status notification display device 178 is attached at a position so that only the manager of the game store (game hall) can see it, and is attached to, for example, a predetermined position on the back surface of the pachinko gaming machine 1.

The lower plate full tank switch 179 detects when the game balls stored in the lower plate 22 are full, and outputs the detection result to the payout / launch control circuit 123.

When a signal indicating that the lower plate is full is input from the lower plate full tank switch 179, the payout / launch control circuit 123 notifies the payout status notification display device 178 that the lower plate is full. In addition to notifying by using, a signal indicating that the lower plate is full is output to the main control circuit 70. After that, when an effect control command is transmitted from the main control circuit 70 to the sub control circuit 200, the sub control circuit 200 uses, for example, a speaker 11, a lamp group 18, a display device 13, and the like to fill the lower plate 22. Notify that there is.

The launching device 15 has a launching handle 25 that can be rotated by the player when launching the gaming ball stored in the upper plate 21 into the gaming area 12a. The payout / launch control circuit 123 is attached to a solenoid actuator (not shown) of the launch device 15 according to the rotation angle when the launch handle 25 is gripped by the player and is rotated in the clockwise direction. Supply power. As a result, the launching device 15 launches the game ball. As the driving means of the launching device 15, a motor may be used instead of the solenoid actuator.

The external terminal plate 140 is used for transmitting data to a hall computer that manages all pachinko gaming machines in the game store. The data display 141 is installed, for example, on the upper part of the pachinko gaming machine 1 as ancillary equipment of a game store, and has a function of calling a hall clerk and a function of displaying the number of hits.

When operated by the player, the rental operation unit 151 outputs a signal requesting the card unit 150 to rent the game ball. The card unit 150 determines the number of game balls (number of balls to be rented) to be paid out via the prize ball case unit 170 based on a signal output from the rental operation unit 151 requesting the rental of game balls. Then, when the card unit 150 receives the signal requesting the rental of the game ball from the rental operation unit 151, the card unit 150 transmits the rental ball control signal including the information on the determined number of rental balls to the payout / launch control circuit 123.

[Sub-control circuit]
The sub control circuit 200 is connected to the serial communication unit 76 of the main control circuit 70. Then, the sub control circuit 200 (host control circuit 210 described later) controls the entire sub control circuit 200 according to various commands (information regarding the progress of the game) transmitted from the main control circuit 70. Then, the sub-control circuit 200 controls the voice reproduction operation by the speaker 11, controls the image display operation by the display device 13, and the lamp by the lamp group 18 including the LED, based on various commands transmitted from the main control circuit 70. It controls the lighting / extinguishing operation, controls the effect operation by the accessory 20 (decorative member), and the like. That is, the sub control circuit 200 controls various effect devices based on the command from the main control circuit 70, and executes various effects according to the progress of the game. In the present embodiment, the sub-control circuit 200 cannot supply a signal to the main control circuit 70, but the present invention is not limited to this, and the sub-control circuit 200 can transmit a signal to the main control circuit 70. It may have various configurations.

Next, the internal configuration of the sub-control circuit 200 will be described in more detail with reference to FIG. Note that FIG. 6 is a block diagram showing the circuit configuration inside the sub-control circuit 200 and the connection relationship between the sub-control circuit 200 and various peripheral devices thereof.

As shown in FIG. 6, the sub-control circuit 200 includes a relay board 201, a sub-board 202 (first board), a control ROM board 203, and a CGROM (Character Generator ROM) board 204 (second board). .. Then, the sub-board 202 is connected to the relay board 201, the control ROM board 203, and the CG ROM board 204. In the sub-control circuit 200, the sub-board 202 and various ROM boards (control ROM board 203 and CG ROM board 204) are connected via a board-to-board connector (not shown).

The relay board 201 is a relay board for receiving a command transmitted from the main control circuit 70 and transmitting the received command to the sub board 202.

The sub-board 202 is provided with a host control circuit 210, an audio / LED control circuit 220, a display control circuit 230, an SDRAM (Synchronous Dynamic RAM) 250, and a built-in relay board 260. Of these, at least the host control circuit 210, the audio / LED control circuit 220, and the display control circuit 230 are configured as one board.

The host control circuit 210 is a circuit that controls the operation of the entire sub control circuit 200 based on various commands transmitted from the main control circuit 70, and is a CPU processor, a sub work RAM 210a, a SRAM 210b, an RTC (real time clock), and the like. It is configured to include a watchdog timer. The host control circuit 210 is connected to the voice / LED control circuit 220, the display control circuit 230, and the built-in relay board 260 in the sub-board 202. Further, the host control circuit 210 is connected to the control ROM board 203.

Further, the host control circuit 210 has a subwork RAM 210a and a SRAM (Static RAM) 210b. The subwork RAM 210a is a storage device that acts as a temporary storage area for work when the host control circuit 210 executes various processes, and various flags and variables required when the host control circuit 210 executes various processes. Memorize the value of. The SRAM 210b is a storage device that backs up predetermined data in the subwork RAM 210a. In the present embodiment, the RAM is used as the temporary storage area of the host control circuit 210, but the present invention is not limited to this, and any recording medium may be used as the temporary storage medium as long as it is a readable and writable storage medium. ..

The voice / LED control circuit 220 is connected to the speaker 11 and the lamp group 18 via the built-in relay board 260, and is based on the control signals (sound request and lamp request described later) input from the host control circuit 210. This is a circuit that controls the sound reproduction operation by the lamp group 18 and the light emission operation by the lamp group 18. Therefore, functionally, the voice / LED control circuit 220 has a voice controller 220a and a lamp controller 220b. The voice controller 220a and the lamp controller 220b are substantially included in the sound lamp control module 226 described later. The internal configuration of the voice / LED control circuit 220 will be described in detail later with reference to the drawings.

In the present embodiment, when the control signal and data (for example, LED data described later) output from the voice / LED control circuit 220 are transmitted to the lamp group 18 via the built-in relay board 260, the voice / LED Communication between the control circuit 220 and the lamp group 18 is performed by a communication method (a kind of serial communication method) of SPI (Serial Periperal Interface). Further, in the present embodiment, the lamp group 18 includes one or more LEDs and one or more LED drivers for controlling each LED.

The display control circuit 230 is connected to the display device 13 and displays an image (decorative pattern image, background image, effect image, etc.) related to the effect based on the control signal (drawing request) input from the host control circuit 210. It is a circuit for controlling various processing operations when displaying with. The display control circuit 230 has a display controller (first display controller 238 and second display controller 239 described later) and a built-in VRAM (Video RAM) 237.

Further, the display control circuit 230 is connected to the SDRAM 250 in the sub-board 202. Further, the display control circuit 230 is connected to the CGROM board 204. Further, the display controller in the display control circuit 230 is directly connected to the display device 13 without going through the relay board. The internal configuration of the display control circuit 230 will be described in detail later with reference to the drawings.

The SDRAM 250 is composed of a DDR2 (Double-Date Rate2) SDRAM. Further, the SDRAM 250 is provided with various buffers for temporarily storing various image data in the drawing process of images (moving images and still images) displayed by the display device 13. Specifically, for example, the SDRAM 250 is provided with a texture buffer, a movie buffer, a blend buffer, two frame buffers (first frame buffer and second frame buffer), a motion buffer, and the like.

The built-in relay board 260 receives various signals and various data output from the host control circuit 210 and the audio / LED control circuit 220, and transmits the received various signals and various data to the speaker 11, the lamp group 18, and the accessory 20. It is a relay board for transmission.

Further, the built-in relay board 260 has an I2C (Inter-Integrated Circuit) controller 261 and a digital audio power amplifier 262 (amplification means). In the present embodiment, an example in which the I2C controller 261 and the digital audio power amplifier 262 are mounted on the same relay board is shown, but the present invention is not limited to this, and the relay board on which the I2C controller 261 is mounted is used for digital audio. It may be provided separately from the relay board on which the power amplifier 262 is mounted.

The I2C controller 261 is connected to the host control circuit 210 and the motor controller 270 of the accessory 20. That is, the host control circuit 210 is connected to the accessory 20 via the I2C controller 261 and the motor controller 270. Then, the control signal and data (for example, excitation data described later) output from the host control circuit 210 are input to the accessory 20 via the I2C controller 261 and the motor controller 270.

In the present embodiment, the communication between the I2C controller 261 and the motor controller 270 is performed by the I2C communication method (a type of serial communication method). Further, in the present embodiment, the accessory 20 includes one or more motors, and the motor controller 270 includes one or more motor drivers for driving each motor. Although FIG. 6 shows an example in which only one accessory 20 is provided, the present invention is not limited to this, and a plurality of accessories 20 may be provided.

Further, in the configuration of the present embodiment, the host control circuit 210 may directly drive the motor of the accessory 20 without using the motor controller 270, or a control circuit for motor control may be separately provided. Good. Further, in the present embodiment, a plurality of motor drivers (motors) are controlled by one control circuit, but the present invention is not limited to this. In the present embodiment, one or more (one or more) control circuits may be used to control one or more (one or more) motors (motor drivers), or one or more (one or more) control circuits may be used to control one or more motors (motor drivers). It may be configured to control one motor (motor driver), or it may be configured to control one motor (motor driver) by one control circuit.

Further, the digital audio power amplifier 262 is connected to the voice / LED control circuit 220 and the speaker 11. That is, the voice / LED control circuit 220 is connected to the speaker 11 via the digital audio power amplifier 262. Therefore, the audio signal or the like output from the audio / LED control circuit 220 is input to the speaker 11 via the digital audio power amplifier 262.

A sub-main ROM 205 is provided on the control ROM board 203. In the sub-main ROM 205, various programs for controlling the effect operation of the pachinko gaming machine 1 by the host control circuit 210 and various data tables (see, for example, FIG. 26, which will be described later) are stored. Then, the host control circuit 210 executes various processes according to the program stored in the sub-main ROM 205.

In the present embodiment, the sub-main ROM 205 is applied as a storage means for storing programs, various tables, and the like used in the host control circuit 210, but the present invention is not limited thereto. As such a storage means, a storage medium of another aspect may be used as long as it is a storage medium that can be read by a computer provided with a control means. For example, a hard disk device, a CD-ROM, a DVD-ROM, a ROM cartridge, or the like. Storage medium may be applied. Moreover, each of the programs may be recorded in a separate storage medium. Further, the program may be recorded in a recording medium in advance, or may be downloaded from the outside or the like after the power is turned on and recorded in the sub-main ROM 205.

The CGROM board 204 is provided with the CGROM 206. The CGROM 206 is composed of a NOR type or NAND type flash memory. Further, the CGROM 206 stores, for example, image data displayed on the display device 13, audio data reproduced by the speaker 11 (sometimes referred to as sound data in this specification), and the like. At this time, various data are compressed (encoded) and stored in the CGROM 206, but the present invention is not limited to this, and various data may be stored in the CGROM 206 without being compressed.

In the present embodiment, the configuration in which various ROM boards (control ROM board 203 and CGROM board 204) and the sub board 202 are connected by a board-to-board connector in the sub control circuit 200 has been described. The invention is not limited to this. For example, various ROMs may be directly inserted into a port such as a socket provided on the sub-board 202, and the sub-board 202 may be configured by a single board having a ROM function or having the ROM itself. That is, the sub-board 202 and various ROMs may be integrally configured. Further, when the sub-board 202 is composed of a single board having a ROM function or the ROM itself, the sub-control circuit 200 uses a sub board according to the type of memory used as the CG ROM. A switching means for physically or electrically switching the circuit on the board, or a switching means for switching the information of the circuit on the sub-board to be used depending on the type of memory may be provided.

Further, in the present embodiment, the magnitude relationship of the data communication speed between each of the various storage means (sub-main ROM 205, CGROM 206, built-in VRAM 237, SDRAM 250) and the corresponding control circuit is determined by the built-in VRAM 237> SDRAM 250> sub-main. ROM205≈CGROM206. That is, in the present embodiment, the communication speed between the built-in VRAM 237 and the various circuits in the display control circuit 230 is the fastest, and then the communication speed between the SDRAM 250 and the display control circuit 230 is the fastest. Then, the communication speed between the sub-main ROM 205 and the host control circuit 210 and the communication speed between the CGROM 206 and the display control circuit 230 become the slowest. However, the present invention is not limited to this, and the magnitude relationship of the communication speed between each of the various storage means and the corresponding control circuit can be arbitrarily set. For example, the magnitude relationship of the communication speed between each of the various storage means and the corresponding control circuit may be different from that of the present embodiment, and the communication speed between each storage means and the corresponding control circuit may be different. May all be the same.

Here, possible configurations of the various storage means described above will be described. In the present embodiment, the storage means of the information related to the image data (compressed (encoded) image data) is the information related to the transparency data (alpha table described later) that can be used when the transparency is set for the image data. A configuration example that is the same as the storage means (CGROM206) has been described. That is, a configuration example in which the "first information storage means" is physically the same as the "second information storage means" has been described. However, the present invention is not limited to this. For example, the "first information storage means" may be composed of a storage means (storage medium) physically different from the "second information storage means".

Further, the "information storage means" referred to in the present specification means not only a storage means such as CGROM206, but also a table stored in the storage means, a data storage area in the storage means, and the like. Good. Therefore, for example, the "first information storage means" and the "second information storage means" may be different data storage areas or different tables in the same storage means. Further, the mode may be stored in different register addresses. That is, the "information storage means" referred to in the present specification is different not only when the storage means (storage medium) are physically different, but also when they are physically the same storage means (for example, ROM, RAM, etc.). However, it also includes the case where the data areas (storage areas distinguished by addresses, registers, tables, structures, etc.) are different in the storage means.

The above-mentioned meaning of the "information storage means" in the present specification is also applicable to the above-mentioned "third information storage means" (SDRAM250) and "fourth information storage means" (built-in VRAM 237). Therefore, for example, the "first information storage means" to the "fourth information storage means" may be composed of physically different storage means (storage media), or the "first information storage means" to. The "fourth information storage means" may be composed of different data areas (storage areas distinguished by addresses, registers, tables, structures, etc.) in one storage means.

Further, in the present embodiment, the "first information storage means" and the "second information storage means" are configured in one storage means (CGROM206) with different data areas, and the "third information storage means" is defined as a "third information storage means". , The storage means (CGROM206) including the "first information storage means" and the "second information storage means" and the storage means (SDRAM250) physically different from each other, and the "fourth information storage means" is the "fourth information storage means". An example will be described in which a storage means (CGROM206) including the "1 information storage means" and the "second information storage means" and a storage means (built-in VRAM237) physically different from the "third information storage means" (SDRAM250) are used. However, the present invention is not limited to this. Whether the "information storage means" is composed of a data area or a storage means, and how the combination of the "information storage means" defined as the data area and the "information storage means" defined as the storage means is used. It can be appropriately set according to, for example, the configuration (number, type, etc.) of the storage means provided in the gaming machine. For example, in the present embodiment, the "first information storage means" to the "third information storage means" are configured by different data areas in one storage means, and the "fourth information storage means" is the "fourth information storage means". It may be composed of a storage means physically different from the storage means including the "1 information storage means" to the "third information storage means".

[Voice / LED control circuit]
Next, the internal configuration of the voice / LED control circuit 220 will be described with reference to FIG. 7. FIG. 7 is a block diagram showing the internal circuit configuration of the voice / LED control circuit 220 and the connection relationship between the voice / LED control circuit 220 and its various peripheral devices and peripheral circuit units. In FIG. 7, for the sake of simplification of the description, the illustration of the relay board and the like provided between the voice / LED control circuit 220 and various peripheral devices and circuit units is omitted.

As shown in FIG. 7, the audio / LED control circuit 220 includes an LSI (Large-Scale Integration) interface 221, a memory interface 222, a digital audio interface 223, a peripheral interface 224, a command register 225, and a sound lamp. It includes a control module 226, a main generator 227, and a multi-effector 228. The connection relationship of each part in the voice / LED control circuit 220 is as follows.

In the audio / LED control circuit 220, the sound lamp control module 226 is connected to the memory interface 222, the peripheral interface 224, the command register 225, the main generator 227, and the multi-effector 228. Further, the command register 225 is connected to the LSI interface 221 in addition to the sound lamp control module 226. In addition to the sound lamp control module 226, the main generator 227 is connected to the memory interface 222 and the multi-effect unit 228. Further, the multi-effector 228 is connected to the memory interface 222 and the digital audio interface 223 in addition to the sound lamp control module 226 and the main generator 227.

Next, the configuration of each part in the voice / LED control circuit 220 will be described.

The LSI interface 221 is an interface circuit used when input / output of control signals (for example, sound request, lamp request, etc.) is performed between the host control circuit 210 and the command register 225. That is, the command register 225 is connected to the host control circuit 210 via the LSI interface 221.

The memory interface 222 is an interface circuit used when performing input / output operations such as voice data between the sub-main ROM 205 and each of the sound lamp control module 226, the main generator 227, and the multi-effector 228.

The digital audio interface 223 is an interface circuit used when an audio signal or the like is output from the multi-effect unit 228 to the speaker 11. Further, the digital audio interface 223 outputs an audio input signal to the multi-effect unit 228.

The peripheral interface 224 is an interface circuit used when input / output of a lamp signal or the like (LED data or the like described later) is performed between the lamp group 18 and the sound lamp control module 226. Further, the peripheral interface 224 is provided with three physical systems as physical systems (SPI channels) for outputting data to the LED driver included in the lamp group 18. In this embodiment, as described later, two physical systems (physical system 0 (SPI channel 0) and physical system 1 (SPI channel 1)) are used.

The command register 225 is composed of a large number of registers (for example, a large number of voice control registers) accessed from the host control circuit 210. The command register 225 sets the function control of the sound lamp control module 226, the main generator 227, and the multi-effect unit 228. The command register 225 also sets the operating conditions of each interface (LSI interface 221 and memory interface 222, digital audio interface 223, and peripheral interface 224).

An IC (Integrated Circuit) is mounted on each register constituting the command register 225, and each register is configured by a memory chip whose operation is stabilized by memory access control. When registers having such a configuration are used, the load on the signal bus to which each register is connected is reduced. Therefore, by increasing the number of memory chips (registers), the capacity per memory module (register) can be easily increased. The capacity of the command register 225) can be increased.

The sound lamp control module 226 comprehensively controls the voice reproduction operation and the like, and controls the operation of each component (each block) in the voice / LED control circuit 220 according to the setting contents of the command register 225. .. As shown in FIG. 7, the sound lamp control module 226 includes a simple access controller 226a, a sequencer 226b, a lamp control unit 226c, and a peripheral control unit 226d.

The simple access controller 226a is a circuit unit that collectively processes commands. The sequencer 226b has various sequencers (automatic reproduction function units) for controlling automatic reproduction operations such as lamp lighting and voice. Then, each sequencer controls various operations according to a timer and step conditions (for example, conditions set for each step process during sequence reproduction such as LED animation and voice described later).

The lamp control unit 226c calculates the set luminance value in all the channels (8 channels) in which the LED data described later can be set, and transmits the calculation result to the outside (LED driver). Further, the peripheral control unit 226d performs physical transmission control when transmitting the calculation result data output from the lamp control unit 226c to the LED driver.

The main generator 227 is a circuit unit that generates an audio signal. Specifically, the main generator 227 acquires predetermined audio data stored in the CGROM 206 based on the control signal input from the sound lamp control module 226, and uses the acquired audio data as a predetermined audio signal. Convert to. The main generator 227 is a channel mix unit 227c that mixes a decoder 227a that is divided into playback channels CH1 to CH32 to reproduce compressed data, a channel volume 227b (V1 to V4) that adjusts the volume, and a playback sound of the decoder 227a. And a remix unit 227d that executes the final mixing operation.

The multi-effect unit 228 includes a mixer that synthesizes an audio signal input from the main generator 227 and an audio input signal input from the digital audio interface 223, and various effectors for giving various sound effects to the audio. Then, the multi-effector 228 outputs the audio signal synthesized by the mixer, the output signal from the effector, and the like to the speaker 11 via the digital audio interface 223.

FIG. 8 is a drawing for explaining the output signal of the voice / LED control circuit. The CGROM 206 stores a maximum of 8192 types of sequence code groups and a maximum of 8192 types of SAC data groups. Sequence code and SAC data, respectively, have been identified in the 13 bit long sequence code number or SAC number, a relationship of 8192 ^{= 2 13.}

In the case of this embodiment, the sequencer 226b is provided with 16 series (SQ0 to SQ15) operating in parallel, and the simple accelerator controller 226a is provided with 4 series (SAC0 to SAC3) operating in parallel. There is. Corresponding to this configuration, the command register 225 is provided with a voice control register RGj2 for controlling sequencers (SQ0 to SQ15) and a voice control register RGj1 for controlling SAC (SAC0 to SAC3).

Then, when the host control circuit 210 composed of the CPU processor writes the SAC number and its attached information to the predetermined voice control register RGj1 for SAC control based on the transmission operation of the voice command, the corresponding simple The access controller 226a starts to function, and the simple access controller 226a writes a group of setting data specified by the SAC number to a group of voice control registers instructed by the SAC data. In the present embodiment, the complicated setting operation can be completed by transmitting one SAC number and its attached information.

On the other hand, the host control circuit 210 configured by the CPU processor transmits the sequence code number and its attached information to the predetermined voice control register RGj2 for controlling the sequencer 226b (SQ0 to SQ7) based on the transmission operation of the voice command. Upon writing, the corresponding sequencer SQi starts functioning and writes a group of setting data specified by the sequence code to a group of voice control registers instructed by the sequence code.

Here, in the predetermined voice control register RGj2 for controlling the sequencers (SQ0 to SQ7), a plurality of (up to 8) sequence code numbers and loop information for the production of each sequence code number are stored in the predetermined voice control register RGj2 for any sequencer SQi. Can be entered. Therefore, for example, when n + 1 sequence code numbers (X0, X1, ..., Xn) are specified for the sequencer SQi, the sequence code number X0 setting operation → the sequence code number X1 setting operation. → ... The setting operation of the sequence code number Xn is executed in order, and the sound effect corresponding to the setting operation is executed.

Further, since loop information such as the number of repetitions can be specified for each sequence code number, the sound effect specified by the sequence code number is repeated a predetermined number of times, and then the sound effect specified by the next sequence code number is used. Can be migrated.

As described above, the data to be set in the sequencer SQi is diverse, and it is necessary to appropriately set these sequence code numbers and accompanying data in the voice control register RGj2 for sequencer control. Therefore, in this embodiment, the entire sequence code number and accompanying data are divided in 1-byte units, and the divided 1-byte data and the register address of the sequencer control register RGj2 in which the 1-byte data should be set are divided. A group of SAC data as a set is secured in the CGROM 206 (hereinafter, this is referred to as SAC data for starting a sequencer).

Then, the host control circuit 210 activates the simple access controller 226a by designating a predetermined SAC number in the voice control register RGj1 for SAC control. Here, of course, the SAC number specifies the SAC data for starting the sequencer. Then, based on the operation of the SAC (Simple Access Controller), necessary data is expanded in the sequencer control register RGj2. Therefore, it is easy to set the activation data of the sequencers SQ0 to SQ15.

By the way, as described above with respect to FIG. 8, since a plurality of operation units (sequence steps) separated by a step end code (FFFEH) are described in a group of sequence codes specified by one sequence code number. After all, after executing all the plurality of sequence steps specified by one sequence code number, the plurality of sequence steps specified by the next sequence code number are executed.

Since the standby time can be set for each sequencer, the first sequence step (writing operation of a group of setting data) is started after the standby time indicated by the host control circuit 210 configured by the CPU processor. , When the step end code (FFFEH) is executed, the next group of setting data is written to the group of voice control registers after the waiting time. As the waiting time, a single time information can be set for each sequencer (SQ0 to SQ7). For example, in the preceding sequence step, the waiting time applied to the subsequent sequence steps following the sequence step is set. By doing so, the waiting time for each sequence step can be set arbitrarily.

Further, to continue the explanation of the internal configuration of the audio / LED control circuit 220, as shown in FIG. 7, the output signals of the 6 channels of the channel mix unit 227c (mixed L0, mixed R0, mixed L1, mixed R1, mixed SUB0, The mixed SUB1) is supplied to the total volume 229 (TV0 to TV3) after being digitally filtered based on the operation parameters specified in the predetermined audio control register of the command register 225 in the multi-effector 228, and the total volume value. Amplified based on TV.

The total volume value TV is defined by an operation parameter written in the corresponding voice control register, and as described above, this operation parameter is, in principle, a setting switch (hardware) operated by a staff member in this embodiment. It is specified based on the wear switch). However, if the player operates the volume switch (screen operation) during the game operation (however, while waiting for the sound effect), the total volume TV is defined (changed) based on the set value. When the player operates the volume switch, the channel volume 227b (V1 to V4) is defined (changed) instead of or in addition to the total volume TV being defined based on the set value. You can do it.

[Speaker volume control]
Next, the volume control of each speaker 11 executed by the host control circuit 210 will be described with reference to FIG. FIG. 9 is a control block diagram for explaining an example of volume control by the host control circuit.

The sounds such as game sounds output from each speaker 11 (L0 / R0 / L1 / R1, SUB0, SUB1) are the audio signals of the total volume TVs 0 to 3 output to all channels and the individual audio signals of all channels. By multiplying the audio signal for each playback channel output to the channel, the volume is controlled by the volume transition operation in which the volume value of the audio signal is gradually changed.

The "audio signal" has volume information (for example, information such as wattage), and can be simply called "volume". For example, in this specification, "audio signal for each reproduction channel" may be referred to as "volume for each reproduction channel".

The audio signals of the total volume TVs 0 to 3 are output by the total value of the audio signal by the volume control 281 by the hardware switch and the audio signal output by the user volume control 282 by the volume setting screen, and the debug volume control 283 at the time of debugging. It is specified by multiplying the audio signal. The host control circuit 210 that executes the volume control 281 by the hardware switch, the user volume control 282 by the volume setting screen, and the debug volume control 283 at the time of debugging corresponds to the "first volume control means" of the present invention.

Further, the volume for each playback channel is obtained by multiplying the audio signal of the primary volume and the audio signal of the secondary volume. The audio signal of the primary volume is the audio signal output by the primary control 284 of the first reproduction channel affected by the volume adjustment and the audio signal output by the primary control 285 of the second reproduction channel not affected by the volume adjustment. It is defined by the total value. In the first playback channel primary control 284, control is performed to change the volume of a normal game sound (that is, the audio signal (the same applies hereinafter)) based on, for example, an operation of changing the volume by a player or the like. It is said. The second playback channel primary control 285 is a control that outputs a specific game sound (for example, an error sound or an alarm sound at the time of illegal activity) at a constant volume regardless of whether or not an operation for changing the volume is performed. Is done. This constant volume may always be the maximum volume. In this way, the second playback channel primary control 285, which is not affected by the volume adjustment, is controlled so that a specific game sound is output at a constant volume, so that it can be specified only in a specific playback channel, not as a whole. It is possible to execute control to keep the volume of the game sound constant. Further, the audio signal of the secondary volume is a volume incorporated in the audio data specified by the SAC number, and is output by the volume control 286, 287, 288. The host control circuit 210 that executes the first reproduction channel primary control 284, the second reproduction channel primary control 285, and the volume control 286, 287, 288 incorporated in the audio data is the "second volume" of the present invention. Corresponds to "control means".

In this way, the sounds output from each speaker 11 (L0 / R0 / L1 / R1, SUB0, SUB1) are the volume of the total volume TVs 0 to 3, the volume of the primary volume which is the volume for each playback channel, and the secondary. Since it is defined by multiplying the volume of the volume, it is possible to give diversity to the volume of the game sound. In particular, since the volume of the total volume TVs 0 to 3 is also defined by the volume output by the debug volume control 283 during debugging, the game sound data used in the game can be used as it is during debugging, and during debugging. It is possible to improve the work efficiency of.

In addition, regarding the volume of normal game sounds, the volume can be changed based on the operation of changing the volume by the player or the like, but specific sounds such as error sounds and alarm sounds at the time of illegal acts are specified. As for the game sound, a constant volume is output by the second reproduction channel primary control 285 regardless of whether or not the operation of changing the volume is performed. Therefore, it is not possible to hide the occurrence of an error or an illegal act, and it is possible to enhance security.

In the pachinko gaming machine 1 of the present embodiment, the volume control 281 by the hardware switch has, for example, three stages of large, medium, and small. Further, the user volume control 282 by the volume setting screen has seven stages, and is set to [small] = [1], [medium] = "4], and [large] = "7] in conjunction with the hardware switch.

As described above, in the pachinko gaming machine 1 of the present embodiment, for example, the volume of a specific sound such as an error sound can be maintained only by the control by the second reproduction channel primary control 285. It is possible to easily perform volume control such as changing the volume according to the volume adjustment for other normal sounds while maintaining the volume. The processing by the host control circuit 210 when the volume adjustment is performed will be described later with reference to FIGS. 61 to 65.

[Connection configuration between digital audio power amplifier and speakers]
Next, with reference to FIG. 10, a connection configuration between the digital audio power amplifier 262 and its peripheral circuits provided in the built-in relay board 260 and the speaker 11 will be described. FIG. 10 is a connection configuration diagram between the built-in relay board 260 and the speaker 11. Note that FIG. 10 shows a state in which the speaker 11 is not connected to the built-in relay board 260 in order to clarify the configuration of the connection portion.

In the pachinko gaming machine 1 of the present embodiment, as shown in FIG. 10, the speaker box 11a provided with the speaker 11 is connected to the built-in relay board 260 via the harness 300.

The built-in relay board 260 includes a digital audio power amplifier 262, an LC circuit 263, a connection terminal group 264 including four connection terminals (first connection terminal to fourth connection terminal), two resistors 265 and 266, and a capacitor. It has 267 and a NOT circuit (logic circuit) 268.

The digital audio power amplifier 262 amplifies the input audio signal (audio data), outputs the amplified audio signal to the speaker 11, and drives the speaker 11. The LC circuit 263 is composed of a resonance circuit including a coil and a capacitor. Further, the NOT circuit 268 is a logic circuit that inverts the level of the input signal and outputs it.

The clock input terminal (MCK) and data input terminal (SDATA) of the digital audio power amplifier 262 are connected to the audio / LED control circuit 220. The clock signal (master clock signal) output from the audio / LED control circuit 220 is input to the clock input terminal (MCK) of the digital audio power amplifier 262, and the audio / LED is input to the data input terminal (SDATA). The audio signal (audio data) output from the control circuit 220 is input.

Further, the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262 are the first connection terminal and the first connection terminal in the connection terminal group 264 of the built-in relay board 260, respectively, via the LC circuit 263. It is connected to the second connection terminal. In the present embodiment, an example in which two output terminals of the digital audio power amplifier 262 are provided will be shown, but the present invention is not limited to this, and may be appropriately changed according to, for example, the function and specifications of the speaker 11. Can be done.

Further, the digital audio power amplifier 262 has a mute terminal (MUTE: audio output control terminal). The digital audio power amplifier 262 receives audio signals from the first output terminal (OUTM1) and the second output terminal (OUTM2) when the level (amplitude value) of the voltage signal applied to the mute terminal is the LOW level. It has a function of stopping the output or making these output terminals grounded via a high resistance (hereinafter referred to as a mute function). That is, when the level of the voltage signal applied to the mute terminal is the LOW level, the digital audio power amplifier 262 is the first of the built-in relay board 260 from the first output terminal (OUTM1) and the second output terminal (OUTM2). It has a function of generating a state in which the output of the audio signal to the connection terminal and the second connection terminal is stopped.

On the other hand, when the level (amplitude value) of the voltage signal applied to the mute terminal (MUTE) is the HIGH level, the digital audio power amplifier 262 has a first output terminal (OUTM1) and a second output terminal (OUTM2). Outputs an audio signal from.

The third connection terminal in the connection terminal group 264 of the built-in relay board 260 is connected to the input terminal of the NOT circuit 268 via a resistor 266. Further, the output terminal of the NOT circuit 268 is connected to the mute terminal (MUTE) of the digital audio power amplifier 262. The signal wiring between the third connection terminal of the built-in relay board 260 and the resistor 266 is connected to the power supply voltage (+ 5V) terminal provided in the built-in relay board 260 via the resistor 265. Further, the signal wiring between the input terminal of the NOT circuit 268 and the resistor 266 is connected (grounded) to the grounded (GND) terminal provided in the built-in relay board 260 via the capacitor 267. Further, the fourth connection terminal of the built-in relay board 260 is connected to the ground (GND) terminal.

As shown in FIG. 10, the speaker 11 is attached to a speaker box 11a composed of a wooden frame. Further, the speaker box 11a is provided with a connection terminal group 11b including four connection terminals (first connection terminal to fourth connection terminal). Then, the first connection terminal and the second connection terminal of the speaker box 11a are connected to the speaker 11 via signal wiring. Further, the third connection terminal (specific connection terminal) of the speaker box 11a is electrically connected to the fourth connection terminal by the signal wiring W1.

As shown in FIG. 10, the harness 300 is configured by bundling four signal wirings. Then, one of the four connection terminals (first connection terminal to fourth connection terminal) of the four signal wirings is connected to the first connection terminal to the fourth connection terminal of the built-in relay board 260, respectively. On the other hand, the other four connection terminals (fifth connection terminal to eighth connection terminal) of the four signal wirings are connected to the first connection terminal to the fourth connection terminal of the speaker box 11a, respectively. That is, the first connection terminal of the built-in relay board 260 and the first connection terminal of the speaker box 11a are connected by signal wiring between the first connection terminal and the fifth connection terminal in the harness 300, and the built-in relay board 260 is connected. The second connection terminal of the speaker box 11a and the second connection terminal of the speaker box 11a are connected by signal wiring between the second connection terminal and the sixth connection terminal in the harness 300. Further, the third connection terminal of the built-in relay board 260 and the third connection terminal of the speaker box 11a are connected by signal wiring between the third connection terminal and the seventh connection terminal in the harness 300, and the built-in relay board 260 is connected. The fourth connection terminal of the speaker box 11a and the fourth connection terminal of the speaker box 11a are connected by signal wiring between the fourth connection terminal and the eighth connection terminal in the harness 300. As a result, the speaker 11 is connected to the built-in relay board 260 via the harness 300.

The number of signal wirings included in the harness 300 is not limited to four, and is appropriately changed according to, for example, the specifications of the digital audio power amplifier 262 and the speaker 11, the connection configuration between the two, and the like. The harness 300 has at least a signal wiring for connecting the output terminal of the digital audio power amplifier 262 and the speaker 11, and a signal wiring for grounding the mute terminal of the digital audio power amplifier 262 via the speaker box 11a. Should be included.

When the built-in relay board 260 and the speaker 11 are connected via the harness 300 as described above, the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262 are connected via the harness 300. Is connected to the speaker 11. Further, the mute terminal (MUTE) of the digital audio power amplifier 262 is grounded via the NOT circuit 268, the harness 300, and the signal wiring W1 between the third connection terminal and the fourth connection terminal of the speaker box 11a.

As a result, when the speaker 11 is connected to the built-in relay board 260 (digital audio power amplifier 262) via the harness 300, the LOW level voltage signal is input to the NOT circuit 268, so that the digital audio power amplifier 262 The level (amplitude value) of the voltage signal input to the mute terminal (MUTE) of is the HIGH level. In this case, an audio signal is output to the speaker 11 from the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262.

On the other hand, when the speaker 11 is not connected to the built-in relay board 260 (digital audio power amplifier 262), the third connection terminal of the built-in relay board 260 is opened. In this case, since the power supply voltage (+ 5V) is input to the NOT circuit 268, the level (amplitude value) of the voltage signal input to the mute terminal (MUTE) of the digital audio power amplifier 262 becomes the LOW level, and the digital audio power amplifier. The above-mentioned mute function of 262 is activated.

That is, when the speaker 11 is disconnected from the built-in relay board 260 (digital audio power amplifier 262), the built-in relay board 260 is connected from the first output terminal (OUTM1) and the second output terminal (OUTM2) of the digital audio power amplifier 262. A state is generated in which the output of the audio signal to the first connection terminal and the second connection terminal of the above is stopped. As a result, the occurrence of a resonance phenomenon between the digital audio power amplifier 262 (output terminal) and the first and second connection terminals of the built-in relay board 260 is suppressed, and problems such as failure of the digital audio power amplifier 262 occur. Can be prevented.

As described above, in the present embodiment, the mute function of the digital audio power amplifier 262 can be operated regardless of the software control by the host control circuit 210 and the voice / LED control circuit 220. Therefore, for example, in a situation where the speaker 11 is detached from the built-in relay board 260, even if it is recognized that the host control circuit 210 and the audio / LED control circuit 220 are performing the output stop control of the audio signal, the program In the case where the audio signal is erroneously output due to a bug or the like, or in the pachinko game machine 1 having a structure in which the game board cannot be replaced unless the speaker 11 is removed from the harness 300, after the replacement of the game board is completed. Even if a situation occurs such as when the door is closed without connecting the speaker 11 and the harness 300 by mistake and the audio output is started, the mute function of the digital audio power amplifier 262 described above operates in terms of hardware. In this case, the digital audio power amplifier 262 can be reliably protected, and the safety of the pachinko gaming machine 1 can be improved.

Further, in the present embodiment, as described above, the third connection terminal of the built-in relay board 260 is connected to the harness 300 and the signal wiring W1 between the third connection terminal and the fourth connection terminal of the speaker box 11a. It is connected to a ground (GND) terminal provided in the built-in relay board 260. In such a configuration, when the signal level of the third connection terminal of the built-in relay board 260 is LOW, is this factor due to the grounding of the fourth connection terminal of the built-in relay board 260? Since it can be determined by measuring the signal level of the fourth connection terminal of the built-in relay board 260, it is possible to more accurately manage the digital output operation from the digital audio power amplifier 262.

[Display control circuit]
Next, the internal configuration of the display control circuit 230 will be described with reference to FIG. FIG. 11 is a block diagram showing a circuit configuration inside the display control circuit 230 and a connection relationship between the display control circuit 230 and its various peripheral devices and peripheral circuit units.

As shown in FIG. 11, the display control circuit 230 includes a memory controller 231, a command memory 232, a command parser 233, a moving image decoder 234, a still image decoder 235, an SDRAM controller 236, a built-in VRAM 237, and a first display control circuit 230. It includes a display controller 238, a second display controller 239, a 3D (Dimension) geometry engine 240, and a rendering engine 241. The connection relationship of each part in the display control circuit 230 and the connection relationship between the display control circuit 230 and its various peripheral devices and peripheral circuits are as follows.

In the display control circuit 230, the memory controller 231 is connected to the command parser 233, the moving image decoder 234, and the still image decoder 235. The command parser 233 is connected to the command memory 232, the moving image decoder 234, the still image decoder 235, and the 3D geometry engine 240 in addition to the memory controller 231. The moving image decoder 234 is connected to the SDRAM controller 236 in addition to the memory controller 231 and the command parser 233. The still image decoder 235 is connected to the built-in VRAM 237 in addition to the memory controller 231 and the command parser 233.

Further, in the display control circuit 230, the SDRAM controller 236 is connected to the built-in VRAM 237, the first display controller 238, and the second display controller 239 in addition to the moving image decoder 234. The built-in VRAM 237 is connected to the first display controller 238, the second display controller 239, and the rendering engine 241 in addition to the still image decoder 235 and the SDRAM controller 236. Further, the 3D geometry engine 240 is connected to the rendering engine 241 in addition to the command parser 233.

The SDRAM 250 is connected to the memory controller 231 and the SDRAM controller 236 in the display control circuit 230. Further, the CGROM board 204 is connected to the memory controller 231 in the display control circuit 230. Further, the host control circuit 210 is connected to the memory controller 231 and the command memory 232 in the display control circuit 230. Further, the display device 13 is connected to the first display controller 238 and the second display controller 239 in the display control circuit 230.

Next, the configuration of each part in the display control circuit 230 will be described.

The memory controller 231 mainly controls communication between various external memories (CGROM board 204 and SDRAM 250) and the display control circuit 230. For example, the memory controller 231 performs processing such as transmission / reception of an address designation signal of an external memory to be controlled, memory readiness, busy management, and the like, and data stored at a designated address for various memories (effect data). , Command data, etc.).

The command memory 232 is a built-in memory for storing a command list. In addition to the command memory 232, the command list can also be stored in the SDRAM 250 and the CGROM board 204 (CGROM206).

The command parser 233 acquires a command list from the designated memory (command memory 232, SDRAM 250 or CGROM 206). Specifically, in the present embodiment, the type of memory (command memory 232, SDRAM 250 or CGROM 206) in which the command list is arranged in the system control register (not shown) in the display control circuit 230 by the host control circuit 210, and The starting address is set. Then, the command parser 233 accesses the start address in the memory specified in the system control register (not shown) to acquire the command list.

Further, the command parser 233 analyzes the acquired command list to generate a specific control code, and outputs the control code to the moving image decoder 234, the still image decoder 235, and the 3D geometry engine 240. In the present embodiment, each image processing module in the display control circuit 230 operates based on the control code output by the command parser 233.

The video decoder 234 decodes (decodes) the video compressed data acquired from the CGROM board 204 or the SDRAM 250. Then, the moving image decoder 234 outputs the decoded moving image data to the SDRAM 250 (external RAM). The moving image data (decoding result) output from the moving image decoder 234 is stored in the movie buffer provided in the SDRAM 250.

The still image decoder 235 decodes the still image compressed data acquired from the CGROM board 204 or the SDRAM 250. Then, the still image decoder 235 outputs the decoded still image data to the built-in VRAM 237. The still image data (decoding result) output from the still image decoder 235 is temporarily stored in a sprite buffer described later provided in the built-in VRAM 237.

The SDRAM controller 236 is a controller that controls operations such as storage processing of decoded moving image data and still image data in RAM, and image data transfer processing between the built-in VRAM 237 and the CGROM board 204 or SDRAM 250.

The built-in VRAM 237 operates as a work RAM when executing various processes such as a decoding process and a rendering process in the drawing process by the display control circuit 230. Further, in the image data transfer process between the built-in VRAM 237 and the CGROM board 204 or the SDRAM 250, which is performed in each processing process in the drawing process described later, various image data are temporarily stored in the built-in VRAM 237.

Each of the first display controller 238 and the second display controller 239 acquires a rendering result (drawing result) generated by the rendering engine 241 and outputs the rendering result to the display device 13. As a result, a predetermined image is displayed on the display screen of the display device 13. When two display controllers are provided as in the pachinko gaming machine 1 of the present embodiment, two screens are provided on the display device 13 by one display control circuit 230 (1 chip) to display each screen. It can be controlled independently.

The 3D geometry engine 240 performs a process of converting 3D information into 2D information (projection conversion process) based on a control code input from the command parser 233, and an affine transformation such as enlargement, reduction, rotation, and movement of a figure. Performs (figure conversion) processing. Then, the 3D geometry engine 240 outputs the result of the conversion process to the rendering engine 241.

The rendering engine 241 refers to a texture source (SDRAM250 in this embodiment) in which stretched still image data and moving image data are stored, and performs rendering (drawing) processing on the image data. Then, the rendering engine 241 writes the rendering result to the rendering target (in this embodiment, the built-in VRAM 237 or the SDRAM 250).

The term "rendering" as used herein means editing data decoded according to specified information such as enlargement / reduction and rotation of a moving image (in this embodiment, information output from the 3D geometry engine 240). It is to be. Further, the "rendering engine" referred to here also includes, for example, a "rasterizer" and a "pixel shader". Therefore, in the rendering engine 241, similarly to the pixel shader, the ARGB value (A: alpha value indicating transparency (opacity), R: luminance value of red component, G: green component) for image data in pixel units. The calculation process of the luminance value of B: the luminance value of the blue component) is also performed.

[Connection configuration between display control circuit and CGROM]
The pachinko gaming machine 1 of the present embodiment has a configuration that can deal with different types of CGROMs (NOR type or NAND type) connected to the display control circuit 230. Here, the connection configuration between the display control circuit 230 provided in the sub-board 202 and its peripheral circuits and the CGROM mounted on the CGROM board will be described with reference to FIGS. 12 and 13.

FIG. 12 is a connection configuration diagram between the sub-board 202 and the CGROM board 204a when the CGROM is a NOR-type CGROM206a (NOR-type flash memory). Further, FIG. 13 is a connection configuration diagram between the sub-board 202 and the CGROM board 204b when the CGROM is a NAND type CGROM206b (NAND type flash memory). Note that FIGS. 12 and 13 show a state in which the CGROM board is detached from the sub-board 202 in order to clarify the configuration of the connection portion, but in reality, both boards are connected via a board-to-board connector. Be connected.

(1) Configuration of Sub-Board First, the internal configuration of the sub-board 202 will be described. As is clear from the comparison between FIGS. 12 and 13, the configuration of the sub-board 202 when the NOR type CGROM 206a is mounted on the CGROM board 204a is the same as that when the NAND type CGROM 206b is mounted on the CGROM board 204b. The same is true.

As shown in FIGS. 12 and 13, a display control circuit 230 is provided on the sub-board 202, and a bidirectional balance transceiver 301 and an AND circuit 302 (AND gate) are provided as peripheral circuits thereof. Further, the sub-board 202 is provided with various signal wirings (buses) and a terminal group 303 including a plurality of connection terminals directly or indirectly connected to the display control circuit 230 via various buses.

The bidirectional balanced transceiver 301 has one four input / output terminals (terminals A0 to A3 in FIG. 12) and the other four connected to the one four input / output terminals (terminals A0 to A3), respectively. It has two input / output terminals (terminals B0 to B3 in FIG. 12). Further, the bidirectional balanced transceiver 301 has two control terminals (terminals in FIG. 12) for switching and controlling the signal communication direction between the input / output terminals A0 to the input / output terminals A3 and the input / output terminals B0 to the input / output terminals B3. It has OE and terminal DIR).

The bidirectional balanced transceiver 301 is between the input / output terminals A0 to the input / output terminals A3 and the input / output terminals B0 to the input / output terminals B3 according to the combination of the signal levels of the voltage signals applied to the control terminal OE and the control terminal DIR, respectively. Switch the communication direction of the signal in. As a result, even if the communication direction (communication operation) is inconsistent for some reason, the safety of the communication operation between the display control circuit 230 and the CGROM can be ensured. The communication direction switching control operation of the bidirectional balance transceiver 301 will be described in detail later. Further, the bidirectional balanced transceiver 301 used in the present embodiment can also be used for a system having two power supplies of 3.3V and 5V.

The display control circuit 230 is provided with four input / output terminals (terminals GMA31 / GRB3 to terminals GMA28 / GRB0 in FIG. 12). The input / output combined terminals GMA31 / GRB3 to the input / output combined terminals GMA28 / GRB0 act as output terminals of the address bus when the CGROM is a NOR type CGROM206a, and are ready when the CGROM is a NAND type CGROM206b. / Acts as an input terminal for busy signals. Further, the display control circuit 230 is provided with 26 output terminals (terminals GMA27 to GMA2 in FIG. 12) that act as output terminals for data (address designation data, etc.) related to the address of the data storage area in the CGROM. Be done.

Further, the display control circuit 230 is provided with two CG memory chip enable output terminals (terminal GCE_0 and terminal GCE_1 in FIG. 12). In the present embodiment, the display control circuit 230 has two memory spaces corresponding to two CG memory chip enable output terminals (GCE_0, GCE_1: specific output terminals), and each memory space has a memory. Information such as type, bus width, and access timing is set. However, in the present embodiment, the display control circuit 230 has a configuration that cannot be supported (used) when the ROM in the synchronous mode and the ROM in the asynchronous mode are mixed.

Further, the display control circuit 230 is provided with a plurality of data bus input terminals for acquiring image data (compressed video / still image data) from the CGROM via the data bus.

The electrical connection of the components provided on the sub-board 202 is as follows.

The input / output terminals GMA31 / GRB3 to the input / output terminals GMA28 / GRB0 of the display control circuit 230 are connected to the input / output terminals B0 to the input / output terminals B3 of the bidirectional balance transceiver 301, respectively, as shown in FIGS. 12 and 13. Will be done. Then, the input / output terminals A to the input / output terminals A3 of the bidirectional balance transceiver 301 are connected to the first connection terminal to the fourth connection terminal of the terminal group 303, respectively. That is, the input / output combined terminals GMA31 / GRB3 to the input / output combined terminals GMA28 / GRB0 of the display control circuit 230 are connected to the first connection terminal to the fourth connection terminal of the terminal group 303 via the bidirectional balance transceiver 301, respectively. To.

Further, the output terminals GMA27 to output terminals GMA2 of the display control circuit 230 are connected to the ninth connection terminal to the 34th connection terminal of the terminal group 303, respectively, and the CG memory chip enable output terminal GCE_0 and the CG memory chip enable output terminal GCE_1 are , It is connected to the 35th connection terminal and the 36th connection terminal of the terminal group 303, respectively. Further, the plurality of data bus input terminals of the display control circuit 230 are respectively connected to the corresponding connection terminals after the 37th connection terminal of the terminal group 303.

The control terminal DIR of the bidirectional balance transceiver 301 is connected to the fifth connection terminal of the terminal group 303, and the control terminal OE is connected to the output terminal of the AND circuit 302. One input terminal of the AND circuit 302 is connected to the CG memory chip enable output terminal GCE_1, and the other input terminal of the AND circuit 302 is connected to the CG memory chip enable output terminal GCE_1. Further, the 6th connection terminal and the 7th connection terminal of the terminal group 303 of the sub-board 202 are connected to the power supply voltage (+ 3.3V) terminal provided on the sub-board 202, and the 8th connection terminal is connected to the sub-board 202. It is connected to the provided ground (GND) terminal.

(2) Configuration of CGROM Substrate (NOR Type) Next, the internal configuration of the CGROM substrate 204a on which the NOR type CGROM206a is mounted will be described with reference to FIG.

When the NOR type CGROM206a is mounted on the CGROM board 204a, the CGROM board 204a includes various signal wirings (buses) and a plurality of connection terminals connected to the CGROM206a via various buses together with the NOR type CGROM206a. A group 311 is provided.

The first to fourth connection terminals and the connection terminals after the ninth connection terminal in the terminal group 311 provided on the CGROM board 204a are connected to the CGROM 206a.

In the example shown in FIG. 12, since the CGROM206a is a NOR type flash memory (random access type flash memory), the first connection terminal to the fourth connection terminal and the ninth connection terminal to the 34th connection terminal in the terminal group 311 are used. The connection terminal is connected to an input terminal (not shown) of the address bus of the CGROM206a. Further, the 35th connection terminal and the 36th connection terminal in the terminal group 311 are connected to the CG memory chip enable input terminal (not shown) of the CGROM 206a, and the display control circuit 230 is connected to the connection terminals after the 37th connection terminal of the CGROM206a. It is connected to the data output terminal of the CGROM 206a used when acquiring image data (compressed data of moving image / still image) from.

Further, the fifth connection terminal (predetermined connection terminal) in the terminal group 311 provided on the CGROM board 204a is connected to the eighth connection terminal via the signal wiring W2, and the eighth connection terminal is connected to the CGROM board 204a. It is connected to the provided ground (GND) terminal. That is, when the CGROM206a is a NOR type flash memory, the fifth connection terminal is grounded via the signal wiring W2. Further, the sixth connection terminal and the seventh connection terminal in the terminal group 311 are connected to the power supply voltage (+ 3.3V) terminal provided on the CGROM board 204a.

The number of connection terminals included in the terminal group 311 is the same as the number of connection terminals of the terminal group 303 for connecting the CGROM board provided on the sub-board 202. Then, when the CGROM board 204a is connected (mounted) to the sub-board 202, both boards are connected so that the connection terminals of the CGROM board 204a are connected to the connection terminals of the sub-board 202 having the same terminal number. That is, as shown in FIG. 12, the first connection terminal, the second connection terminal, ..., the 37th connection terminal, ... Of the CGROM board 204a are the first connection terminal, the second connection terminal, ..., The third of the sub-board 202. It is connected to 37 connection terminals, ...

(3) Configuration of CGROM Substrate (NAND Type) Next, the internal configuration of the CGROM substrate 204b on which the NAND type CGROM206b is mounted will be described with reference to FIG. In the configuration of the CGROM substrate 204b shown in FIG. 13, the same configuration as the CGROM substrate 204a on which the NOR type CGROM206a shown in FIG. 12 is mounted is indicated by the same reference numerals.

When the NAND type CGROM206b is mounted on the CGROM board 204b, the CGROM board 204b is provided with the NAND type CGROM206b and a transistor circuit 312 as a peripheral circuit thereof. Further, the CGROM board 204b is provided with various signal wirings (buses) and a terminal group 311 including a plurality of connection terminals directly or indirectly connected to the CGROM 206b via various buses.

The first connection terminal to the fourth connection terminal in the terminal group 311 of the CGROM board 204b are connected to the drain terminal of the transistor circuit 312. The gate terminal of the transistor circuit 312 is connected to the CGROM 206b, and the source terminal is connected to the ground (GND) terminal provided on the CGROM board 204b. That is, the first connection terminal to the fourth connection terminal are connected to the CGROM 206b via the transistor circuit 312.

In the example shown in FIG. 13, since the CGROM206b is a NAND type flash memory (sequential access type flash memory), the gate terminal of the transistor circuit 312, that is, the first connection terminal to the fourth connection in the terminal group 311 The terminal is connected to a ready / busy output terminal (not shown) provided on the CGROM 206b.

Further, the fifth connection terminal (predetermined connection terminal) in the terminal group 311 of the CGROM board 204b is connected to the sixth connection terminal and the seventh connection terminal via the signal wiring W3, and the sixth connection terminal and the seventh connection are connected. The terminals are connected to the power supply voltage (+ 3.3V) terminals provided on the CGROM board 204b. That is, when the CGROM206b is a NAND flash memory, the fifth connection terminal is connected to the power supply voltage (+ 3.3V) terminal via the signal wiring W3.

Further, the eighth connection terminal in the terminal group 311 of the CGROM board 204b is connected to the ground (GND) terminal provided on the CGROM board 204b.

Further, the connection terminals after the ninth connection terminal in the terminal group 311 of the CGROM board 204b are connected to the CGROM 206b. At this time, the 9th connection terminal to the 34th connection terminal are connected to an input terminal (not shown) for data relating to the address provided in the CGROM 206b, and the 35th connection terminal and the 36th connection terminal are CGs provided in the CGROM206b. Connected to the memory chip enable input terminal. Further, the connection terminals after the 37th connection terminal are connected to the data output terminal (not shown) of the CGROM 206b used when the display control circuit 230 acquires image data (compressed data of moving image / still image) from the CGROM 206b. To.

Even when the NAND type CGROM206b is mounted on the CGROM board 204b, the number of connection terminals included in the terminal group 311 of the CGROM board 204b is the number of the terminal group 303 for connecting the CGROM board provided on the sub board 202. It is the same as the number of connection terminals. Then, when the CGROM board 204b is connected (mounted) to the sub-board 202, both boards are connected so that the connection terminals of the CGROM board 204b are connected to the connection terminals of the sub-board 202 having the same terminal number. That is, as shown in FIG. 13, the first connection terminal, the second connection terminal, ..., the 37th connection terminal, ... Of the CGROM board 204b are the first connection terminal, the second connection terminal, ..., The third of the sub-board 202. It is connected to 37 connection terminals, ...

[Communication operation between display control circuit and CGROM]
Next, the operation when the display control circuit 230 acquires the image data (compressed data of the moving image / still image) from the CGROM will be described with reference to FIGS. 12 to 15. FIG. 14 is a truth table showing the correspondence between the input signal and the output signal in the AND circuit 302 provided on the sub-board 202, and FIG. 15 is a bidirectional balanced transceiver 301 provided on the sub-board 202. Is a truth table showing the correspondence between the signal level applied to the control terminal OE and the control terminal DIR and the communication direction.

(1) Operation of AND Circuit and Bidirectional Balance Transceiver As shown in FIG. 14, the AND circuit 302 is bidirectional balanced transceiver 301 only when a HIGH level signal (voltage signal) is input to both input terminals. A HIGH level signal is output to the control terminal OE of the above, and a LOW level signal is output to the control terminal OE under other input conditions.

As shown in FIG. 15, the bidirectional balanced transceiver 301 is a bidirectional balanced transceiver when a LOW level signal (voltage signal) is input to the control terminal OE and a LOW level signal is input to the control terminal DIR. The input / output terminals A0 to input / output terminals A3 of 301 act as output terminals, and the input / output terminals B0 to input / output terminals B3 act as input terminals. In this case, the communication direction between the display control circuit 230 and the CGROM is the direction from the display control circuit 230 to the CGROM.

Further, when the LOW level signal is input to the control terminal OE and the HIGH level signal is input to the control terminal DIR, the bidirectional balanced transceiver 301 has input / output terminals A0 to input / output of the bidirectional balanced transceiver 301. The terminal A3 acts as an input terminal, and the input / output terminals B0 to the input / output terminal B3 act as output terminals. In this case, the communication direction between the display control circuit 230 and the CGROM is the direction from the CGROM to the display control circuit 230.

When the combination of the signal level input to the control terminal OE of the bidirectional balance transceiver 301 and the signal level input to the control terminal DIR is a combination other than the above (HIGH to the control terminal OE of the bidirectional balance transceiver 301). When a level signal is input), the input / output terminals A0 to input / output terminals A3 and the input / output terminals B0 to the input / output terminals B3 of the bidirectional balance transceiver 301 are in the HIGH impedance state (“Z” in FIG. 15). ), That is, the state is equivalent to the open state, and communication is not performed between the display control circuit 230 and the CGROM.

(2) Communication operation between the display control circuit and the CGROM (NOR type) Here, first, consider the case where the CGROM board 204a on which the NOR type CGROM206a is mounted is connected (mounted) to the sub-board 202.

In this case, in the present embodiment, since the LOW level signal is output from at least one of the two CG memory chip enable output terminals GCE_0 and GCE_1 of the display control circuit 230, the control terminal OE of the bidirectional balance transceiver 301 is LOW. The level signal is input. The signal levels of the CG memory chip enable output terminals GCE_0 and GCE_1 are set in the hardware initialization process (see FIG. 38 described later).

In the present embodiment, the amplitude values of the output signals from the CG memory chip enable output terminals GCE_0 and GCE_1 (specific terminals), which are preset by the sub-control circuit 200, are different depending on the type of CGROM, so that the display control circuit The amplitude value of the signal output from the CG memory chip enable output terminals GCE_0 and GCE_1 provided in 230 changes according to the type of storage means. However, the mode in which "the amplitude value of the output signal changes according to the type of CGROM" is not limited to this mode. As described in the modified example 7 described later, the display control circuit 230 detects the type of the connected storage means, and based on the detection result, from the CG memory chip enable output terminals GCE_0 and GCE_1 (specific terminals). The amplitude value of the output signal may be set.

Further, as shown in FIG. 12, the fifth connection terminal of the sub-board 202 to which the control terminal DIR of the bidirectional balance transceiver 301 is connected is grounded via the fifth connection terminal of the CGROM board 204a and the signal wiring W2. Therefore, a LOW level signal is input to the control terminal DIR.

Therefore, when the CGROM board 204a on which the NOR type CGROM 206a is mounted is connected to the sub board 202, the input / output terminals A to the input / output terminals A3 of the bidirectional balance transceiver 301 are used as output terminals as shown in FIG. It acts, and the input / output terminals B0 to the input / output terminals B3 act as input terminals. That is, the communication direction between the display control circuit 230 and the CGROM 206a in the bidirectional balance transceiver 301 is the direction from the display control circuit 230 toward the CGROM 206a.

In this case, the signal wiring connected via the first connection terminal to the fourth connection terminal of the sub-board 202 and the first connection terminal to the fourth connection terminal of the CGROM board 204a can be used as an address bus, and display control can be performed. The circuit 230 can normally execute the memory addressing operation on the NOR type CGROM206a. As a result, the display control circuit 230 can directly specify the address via the address bus and perform the data read operation.

(3) Communication operation between the display control circuit and the CGROM (NAND type) Next, consider the case where the CGROM board 204b on which the NAND type CGROM 206b is mounted is connected (mounted) to the sub board 202.

Also in this case, in the present embodiment, since the LOW level signal is output from at least one of the two CG memory chip enable output terminals CGE_0 and CGE_1 of the display control circuit 230, the control terminal OE of the bidirectional balance transceiver 301 is used. Is input with a LOW level signal. That is, in the present embodiment, a LOW level signal is input to the control terminal OE of the bidirectional balance transceiver 301 regardless of whether the type of CGROM is NOR type or NAND type. Further, as shown in FIG. 13, the fifth connection terminal of the sub-board 202 to which the control terminal DIR of the bidirectional balance transceiver 301 is connected is connected to the power supply voltage (as shown in FIG. 13) via the fifth connection terminal of the CGROM board 204b and the signal wiring W3. Since it is connected to the + 3.3V) terminal, a HIGH level signal is input to the control terminal DIR.

Therefore, when the CGROM board 204b equipped with the NAND type CGROM206b is connected to the sub board 202, the input / output terminals A to the input / output terminals A3 of the bidirectional balance transceiver 301 are used as input terminals as shown in FIG. It acts, and the input / output terminals B0 to the input / output terminals B3 act as output terminals. That is, the communication direction between the display control circuit 230 and the CGROM 206b in the bidirectional balance transceiver 301 is the direction from the CGROM 206b toward the display control circuit 230.

In this case, the signal wiring connected via the first connection terminal to the fourth connection terminal of the sub-board 202 and the first connection terminal to the fourth connection terminal of the CGROM board 204b shall be used as the communication wiring of the ready / busy signal. Can be done. That is, in this case, the process of transmitting the ready / busy signal referred to by the display control circuit 230 from the NAND type CGROM 206b to the display control circuit 230 when reading the data by the sequential access method can be executed. As a result, the display control circuit 230 can normally execute the memory state (ready / busy state) acquisition operation on the NAND type CGROM206b.

As described above, in the present embodiment, even if the type of CGROM is changed, the communication operation between the display control circuit 230 and the CGROM can be normally executed without changing the configuration of the sub-board 202. Therefore, in the present embodiment, for example, the optimum CGROM can be selected in consideration of data capacity, communication speed, price, and the like. Further, for example, when manufacturing a new pachinko gaming machine 1, the sub-board 202 used in the pachinko gaming machine manufactured in the past is diverted from the conditions such as data capacity and communication speed, and only the type of CGROM is changed. Even in such a case, it can be easily dealt with. That is, in the pachinko gaming machine 1 of the present embodiment, the CGROM can be selected according to the embodiment, and the expandability of the pachinko gaming machine 1 can be ensured.

Further, in the present embodiment, by using the bidirectional balanced transceiver 301, the first connection terminal to the fourth connection terminal in the terminal group 303 of the sub-board 202 and the first connection in the terminal group 311 of the CGROM board 204 are used. The terminals to the fourth connection terminal can be used as data input / output terminals. In this case, it is not necessary to separately provide the data input terminal and the output terminal corresponding to the first connection terminal to the fourth connection terminal of the sub board 202 and the CGROM board 204, and the space of the sub board 202 and the CGROM board 204 can be saved. Can be achieved.

As described above, in the present embodiment, the bidirectional balanced transceiver 301 can switch the "communication mode" between the display control circuit 230 and the CGROM according to the type of the CGROM. However, the "communication mode" between the display control circuit 230 and the CGROM as used herein means the overall mode of transmitting and receiving various information between the display control circuit 230 and the CGROM.

For example, the "communication mode" between the display control circuit 230 and the CGROM referred to in the present specification includes data (image data (compressed data of moving image / still image)) required for displaying information related to the effect operation on the display device 13. )) Not only the transmission / reception mode between the display control circuit 230 and the CGROM, but also the transmission / reception mode and display when communicating the information specifying the address of the data stored in the CGROM between the display control circuit 230 and the CGROM. It means that the control circuit 230 also includes a transmission / reception mode when receiving a ready / busy signal from the CGROM. The present invention is not limited to this, and the "communication form" referred to in the present specification may mean only the communication form of the portion where the transmission / reception mode of information changes according to the type of CGROM.

<Type of game state>
Next, the types of gaming states controlled and managed by the main CPU 71 will be described.

In the present embodiment, the types of gaming states controlled and managed by the main CPU 71 are "big hit gaming state" (special gaming state) and "small hit gaming state" (specific gaming state) in which the expectations of prize balls are different from each other. There is. The "big hit game state" is a game state in which a round game occurs in which the shutter opening period (that is, the period of one round) of the first big prize opening 53 or the second big winning opening 54 is long (for example, 30 sec). It is a game state in which a player can expect a big prize ball. That is, in the "big hit game state", the repeated mode of the open state and the closed state of the shutter of the big winning opening becomes advantageous for the player.

On the other hand, the "small hit game state" is a game state in which a round game occurs in which the period of one round is shorter (for example, 1.8 sec) than in the "big hit game state", and a large prize ball cannot be expected for the player. It is in a game state. That is, in the "small hit game state", the repeated mode of the open state and the closed state of the shutter of the big winning opening becomes a disadvantageous state by the player.

Further, in the present embodiment, as the types of game states controlled and managed by the main CPU 71, "probability variation game state" (high probability game state) and "normal game state" (low) in which the winning probabilities of "big hits" are different from each other. There is a stochastic game state).

The "probability variation game state" is a game state in which the winning probability of "big hit" (1/131 in this embodiment) is high. On the other hand, the "normal game state" is a game state in which the winning probability of the "big hit" (1/392 in the present embodiment) is lower than that in the "probability variation game state".

Further, in the present embodiment, as the type of the gaming state controlled and managed by the main CPU 71, the "time saving gaming state" (high) in which the winning probability of the normal symbol (the probability that the normal symbol becomes the "hit" mode) is different from each other. There are a winning game state) and a "non-time saving game state" (low winning game state).

The "time saving game state" referred to in the present specification is a game state in which the probability of winning a normal symbol is high. That is, the "time saving game state" is a game state in which the ordinary electric accessory 46 (blade member) provided in the second start port 45 is likely to be in an open state (a game state in which a second start port winning is likely to occur). , It is an advantageous gaming state for the player. The "time saving game state" ends when the "big hit" is determined, or when the variable display of the special symbol for the predetermined number of time saving times described later is executed. Further, in the time-saving game state, the variation time, which is the time for displaying the variation of the special symbol executed during the state, is easily selected as the variation time shorter than the variation time selected during the normal game state. It may be controlled. By such control, the variable time may be shortened in the time-saving gaming state as compared with the normal gaming state, and the number of games per unit time may be increased to give the player an advantageous gaming state.

On the other hand, the "non-time saving (no time saving) gaming state" is a gaming state in which the winning probability of a normal symbol is lower than that of the "time saving gaming state". Therefore, the "non-time saving game state" is a game state in which the normal electric accessory 46 (blade member) is unlikely to be opened (a game state in which the second start opening winning is unlikely to occur), which is disadvantageous to the player. It is in a state.

Then, in the present embodiment, a gaming state of various combinations of the above-mentioned gaming states other than the "big hit gaming state" and the "small hit gaming state" is provided. Specifically, in the present embodiment, the game state in which the "probability-changing game state" and the "time-saving game state" occur at the same time (hereinafter referred to as the "high-probability time-saving" state) and the "probability-changing game state" A gaming state in which a "non-time saving game state" occurs at the same time (hereinafter, referred to as a "high accuracy no time saving" state) is provided. In addition, since it is difficult for the player to determine whether or not the game state is the "probability variable game state" in the state of "high probability no time reduction", here, such a game state is referred to as the "latent game state". Also called. Further, in the present embodiment, a game state in which a "normal game state" and a "non-time saving game state" occur at the same time (hereinafter referred to as a "low probability no time reduction" state), and a "normal game state" and a "time reduction". A game state in which a "game state" occurs at the same time (hereinafter referred to as a "low probability time reduction" state) is also provided.

<Structure of data table stored in main ROM>
Next, the configurations of various data tables stored in the main ROM 72 of the main control circuit 70 will be described with reference to FIGS. 16 to 25.

[Big hit random number judgment table (at the time of winning the first start opening)]
First, with reference to FIG. 16, the jackpot random number determination table (at the time of winning the first starting opening) will be described. The big hit random number judgment table (at the time of winning the first starting port) is "big hit" and "small hit" based on the random number value for big hit judgment acquired when the game ball enters (wins) the first starting port 44. And, it is a table referred to when one of "loss" is decided by lottery.

The jackpot determination random number value is a random number value for determining the lottery result performed when the start opening prize is won, and more specifically, a lottery of special symbols (first special symbol and second special symbol). It is a random value indicating the result. Further, in the present embodiment, the jackpot determination random value (random value for lottery of special symbols) is selected from 0 to 65535 (65536 types).

In the present embodiment, when a game ball wins a prize in the first starting port 44, one of "big hit", "small hit" and "loss" is determined by lottery. Therefore, in the jackpot random number determination table (at the time of winning the first start opening), as shown in FIG. 16, for each value of the probability variation flag (“0 (= off)” or “1 (= on)”), “ The range of random number values for big hit judgment that determines the winning of each of "big hit", "small hit" and "loss", and the corresponding judgment value data ("big hit judgment value data", "small hit judgment value data" And any of the "loss judgment value data"). The probability change flag is one of the management flags stored in the main RAM 73, and is a flag for managing whether or not the game state is the “probability change game state”. When the gaming state is the "probability changing gaming state", the confirmation flag is "1".

In the present embodiment, as shown in FIG. 16, when the probability variation flag is "0" and the jackpot determination random value is any of "777" to "943" at the time of winning the first starting port 44. , "Big hit" is won, and "Big hit judgment value data" is decided. That is, the winning probability of the "big hit" in this case (the "selection rate" in FIG. 16) is 167/65536.

Further, when the probability variation flag is "0" and the random value for jackpot determination is any of "1" to "300" at the time of winning the first starting port 44, "small hit" is won and "small hit" is won. "Small hit judgment value data" is determined. That is, the winning probability of "small hit" in this case is 300/65536.

Further, when the probability variation flag is "0" and the random value for jackpot determination is neither "1" to "300" nor "777" to "943" at the time of winning the first starting port 44, "missing". "Is won, and the" loss judgment value data "is determined.

On the other hand, when the probability variation flag is "1" and the random value for jackpot determination is any of "777" to "1277" at the time of winning the first starting port 44, as shown in FIG. 16, "big hit" Is won, and the "big hit judgment value data" is determined. That is, the winning probability of the "big hit" in this case (the "selection rate" in FIG. 16) is 500/65536, which is higher than that when the probability variation flag is "0".

Further, when the probability variation flag is "1" and the random value for jackpot determination is any of "1" to "300" at the time of winning the first starting port 44, "small hit" is won and "small hit" is won. "Small hit judgment value data" is determined. That is, the winning probability of "small hit" in this case is 300/65536, which is the same as that when the probability variation flag is "0".

Further, when the probability variation flag is "1" and the random value for jackpot determination is neither "1" to "300" nor "777" to "1277" at the time of winning the first starting port 44, "missing". "Is won, and the" loss judgment value data "is determined.

As described above, in the present embodiment, when the game ball wins the first starting port 44, the selection rate (big hit probability) depends on whether or not the game state at the time of winning is the “probability variation game state”. fluctuate. Specifically, the jackpot probability when the game ball wins the first starting port 44 when the game state is the "probability change game state" is about three times that when the game state is not the "probability change game state". It gets higher.

[Big hit random number judgment table (at the time of winning the second start opening)]
Next, with reference to FIG. 17, the jackpot random number determination table (at the time of winning the second starting opening) will be described. The jackpot random number determination table (at the time of winning the second starting port) is a lottery for whether or not it is a "big hit" based on the random number value for jackpot determination acquired when the game ball enters (wins) the second starting port 45. It is a table that is referred to when performing.

In the present embodiment, when a game ball wins a prize in the second starting port 45, either "big hit" or "loss" is determined by lottery. If the game ball wins in the second starting port 45, the "small hit" is not won. Therefore, in the jackpot random number determination table (at the time of winning the second starting opening), as shown in FIG. 17, for each value of the probability variation flag (“0 (= off)” or “1 (= on)”), “ Relationship between the range of random number values for jackpot judgment for determining the winning of "big hit" and "loss" and the corresponding judgment value data (either "big hit judgment value data" or "loss judgment value data") Is stipulated.

In the present embodiment, as shown in FIG. 17, when the probability variation flag is "0" and the jackpot determination random value is any of "777" to "943" at the time of winning the second starting port 45. , "Big hit" is won, and "Big hit judgment value data" is decided. That is, the winning probability of the "big hit" in this case (the "selection rate" in FIG. 17) is 167/65536.

In addition, when the probability change flag is "0" and the random value for jackpot determination is neither "777" to "943" at the time of winning the second starting port 45, "loss" is won and "loss determination" is made. Value data "is determined.

On the other hand, when the probability variation flag is "1" and the random value for jackpot determination is any of "777" to "1277" at the time of winning the second starting port 45, as shown in FIG. 17, "big hit" Is won, and the "big hit judgment value data" is determined. That is, the winning probability (big hit probability) of the "big hit" in this case is 500/65536, which is higher than that when the probability variation flag is "0".

If the probability variation flag is "1" and the jackpot determination random number value is neither "777" to "1277" at the time of winning the second starting port 45, it becomes "loss" and "loss determination value data". Is decided.

As described above, in the present embodiment, even when the game ball wins in the second starting port 45, the selection rate (big hit probability) depends on whether or not the game state at the time of winning is the “probability changing game state”. Fluctuates. Specifically, as in the case of winning the first starting opening 44, when the second starting opening 45 is won, the game ball wins in the second starting opening 45 when the gaming state is the "probability changing gaming state". The jackpot probability is about three times higher than that when the gaming state is not the "probability changing gaming state".

[Design judgment table (at the time of winning the first starting opening)]
Next, with reference to FIG. 18, the symbol determination table (at the time of winning the first starting opening) will be described.

In the present embodiment, the winning type (“big hit”, “small hit” or “loss”) of the lottery based on the random value for big hit determination performed when the game ball wins in the first start opening 44 and the first start A special symbol is selected based on the symbol random value (random value for determining the symbol) acquired at the time of winning a prize. The symbol determination table (at the time of winning the first start opening) is a table that is referred to when selecting the special symbol. The symbol random value is a random value for determining a special symbol, and is selected from 0 to 99 (100 types) regardless of the winning type of the lottery based on the big hit determination random value.

In the symbol determination table (at the time of winning the first start opening), as shown in FIG. 18, a symbol specification command for designating a special symbol for each determination value data indicating the winning type of the lottery based on the big hit determination random value. The relationship between ("zA1" to "zA3") and the symbol random value for which the symbol designation command is selected is defined.

If the winning type of the lottery based on the big hit judgment random value is "small hit" (small hit judgment value data), the selected symbol specification command is one type (zA2), and the symbol is always specified. The command (zA2) is determined. Further, even when the winning type of the lottery based on the big hit judgment random value is "loss" (loss judgment value data), the symbol designation command to be selected is one type (zA3), and the symbol designation command (zA3) is always selected. zA3) is determined.

On the other hand, when the winning type of the lottery based on the random value for big hit judgment is "big hit" (big hit judgment value data), as shown in FIG. 18, there are a plurality of types of special symbols to be selected, and "big hit". A plurality of types (“z0” to “z4”) of time symbol designation commands (big hit selection symbol commands in FIG. 18) are also prepared. Then, at the time of "big hit", the big hit selection symbol command to be determined also changes according to the acquired symbol random value. For example, when the symbol random value acquired at the time of "big hit" is any of "40" to "59", the big hit selection symbol command "z2" is selected, and the selection rate is 20/100. Become.

[Design judgment table (at the time of winning the second starting opening)]
Next, with reference to FIG. 19, the symbol determination table (at the time of winning the second starting opening) will be described.

In the present embodiment, the winning type (“big hit” or “loss”) of the lottery based on the random value for big hit determination performed when the game ball wins in the second starting opening 45 and the winning type at the time of winning the second starting opening A special symbol is selected based on the symbol random value (random value for determining the symbol). The symbol determination table (at the time of winning the second starting opening) is a table that is referred to when selecting the special symbol.

In the symbol determination table (at the time of winning the second start opening), as shown in FIG. 19, a symbol specification command for designating a special symbol for each determination value data indicating the winning type of the lottery based on the big hit determination random value. The relationship between ("zA1" and "zA3") and the symbol random value at which the symbol designation command is selected is defined.

Even if the winning type of the lottery based on the big hit judgment random value is "loss" (loss judgment value data), there is only one type (zA3) of the symbol designation command to be selected, and the symbol designation command (zA3) is always selected. zA3) is determined.

On the other hand, when the winning type of the lottery based on the random value for big hit judgment is "big hit" (big hit judgment value data), as shown in FIG. 19, there are a plurality of types of special symbols to be selected, and "big hit". A plurality of types (“z0” and “z4”) of time symbol designation commands (big hit selection symbol commands in FIG. 19) are also prepared. Then, at the time of "big hit", the big hit selection symbol command to be determined also changes according to the acquired symbol random value. For example, when the symbol random value acquired at the time of "big hit" is any of "29" to "99", the big hit selection symbol command "z4" is selected, and the selection rate is 80/100. Become.

[Big hit type determination table]
Next, the jackpot type determination table will be described with reference to FIGS. 20 to 23. In the present embodiment, when the jackpot selection symbol command (any of "z0" to "z4") is determined with reference to the symbol determination table (see FIGS. 18 and 19), the determined jackpot selection is performed. Based on the symbol command, the type of "big hit" (contents of the big hit game) is determined. The jackpot type determination table is a table that is referred to when determining the type of "big hit" (contents of the jackpot game) based on the jackpot selection symbol command.

Further, in the present embodiment, a big hit type determination table is provided for each game state at the time of winning the "big hit". FIG. 20 is a jackpot type determination table (No. 1) that is referred to when a “big hit” is won when the game state is “no low probability time reduction”, and FIG. 21 shows a game state of “low probability time reduction”. This is the jackpot type determination table (No. 2) that is referred to when the "big hit" is won when "yes". Further, FIG. 22 is a jackpot type determination table (No. 3) that is referred to when a “big hit” is won when the gaming state is “no high accuracy time reduction”, and FIG. 23 is a jackpot type determination table (No. 3) in which the gaming state is “high”. It is a jackpot type determination table (No. 4) that is referred to when a "big hit" is won when "there is a certain time reduction".

In each jackpot type determination table, the relationship between the jackpot selection symbol commands (“z0” to “z4”) and various parameters for determining the type of “big hit” is defined. As various parameters for determining the type of "big hit" (contents of the big hit game), the value of the time saving flag, the number of times of time saving, the value of the probability variation flag, and the number of rounds in the big hit game are defined.

For example, when the "big hit" is won in the state of "high accuracy time reduction" and "z1" is determined as the big hit selection symbol command, as shown in FIG. 23, the type of "big hit" ( As various parameters for determining the content of the jackpot game), the time saving flag "1", the time saving number "100", the probability variation flag "0", and the number of rounds "10" are set.

The "number of rounds" specified in each jackpot type determination table is the number of rounds in which the opening time of the jackpot is relatively long in the jackpot game. Further, the "time saving flag" is one of the management flags stored in the main RAM 73, and is a flag for managing whether or not the gaming state is the "time saving gaming state". When the game state is the "time saving game state", the time saving flag is "1 (on)". Further, the "time reduction number of times" is the number of times of variation display of the special symbol given in the "time reduction game state".

[Production information determination table at the time of winning]
Next, with reference to FIG. 24, the effect information determination table at the time of winning will be described.

In the present embodiment, the main control circuit 70 (main CPU71) has a winning type (“big hit”, “small hit” or “missing”) determined at the time of winning (at the time of winning the start opening), and a symbol designation command or a big hit. Based on the time selection symbol command, the sub-control circuit 200 determines the information to be used when determining the effect content. For example, in the sub-control circuit 200, information used for determining the content related to the color change effect of the hold symbol indicating the hold ball of the special symbol, the content related to the look-ahead effect, and the like is determined. The winning effect information determination table is referred to when determining the outline of the effect content executed by the sub control circuit 200 based on the information acquired by the main control circuit 70 at the time of winning (at the time of winning the starting port). It's a table.

In the winning effect information determination table, "winning effect information 1" and "winning effect information 1" showing the combination of various information determined at the time of winning (at the time of winning the starting port) and the outline of the effect contents executed by the sub control circuit 200 The relationship with "Production information 2 at the time of winning" is defined. In the present embodiment, as various information determined at the time of winning (at the time of winning the starting port), the type of the starting port, the type of the judgment value data, the type of the jackpot selection symbol command, and the type of the symbol designation command are winning. It is specified in the time production information determination table.

The winning effect information 1 (“1A” to “1D”) defined in the winning effect information determination table is mainly used in the sub-control circuit 200 to change the color of the holding symbol indicating the holding ball of the special symbol. This is the production information used when deciding the content related to. When the sub-control circuit 200 receives the winning effect information 1 determined based on the winning effect information determination table, the sub-control circuit 200 receives the color change effect of the holding symbol included in the classification of the winning effect information 1. Select one production pattern from multiple types of production patterns related to.

Further, the winning effect information 2 (“2A” to “2D”) defined in the winning effect information determination table is mainly a look-ahead effect (pre-reading continuous) based on the reserved ball of the special symbol in the sub-control circuit 200. This is the production information used when determining the content related to the production). When the sub-control circuit 200 receives the winning effect information 2 determined based on the winning effect information determination table, the sub-control circuit 200 receives a plurality of types of pre-reading effects included in the classification of the winning effect information 2. Select one production pattern from the patterns.

When referring to the winning effect information determination table of the present embodiment, for example, when the "big hit" is won at the time of winning the first start opening, "1A" is set as the winning effect information 1 regardless of the type of the big hit selection symbol command. Is determined, and "2A" is determined as the production information 2 at the time of winning.

[Variable effect pattern determination table]
Next, the variation effect pattern determination table will be described with reference to FIG. 25.

In the present embodiment, the main control circuit 70 (main CPU71) has a winning type (“big hit”, “small hit” or “missing”), a symbol designation command, a big hit selection symbol command, at the start of variable display of the special symbol. The fluctuation effect pattern of the special symbol is determined based on the information such as the fluctuation time. The variation effect pattern determination table is a table that is referred to when determining the variation effect pattern of this special symbol.

The variation effect pattern (information included in the special symbol effect start command described later) determined based on the variation effect pattern determination table is transmitted from the main control circuit 70 to the sub control circuit 200 (host control circuit 210). .. Then, when the sub-control circuit 200 receives the information of the variation effect pattern, the sub-control circuit 200 determines the type of effect based on the received information such as the variation effect pattern and the game state.

As shown in FIG. 25, the variation effect pattern determination table includes a combination of a symbol designation command, a jackpot selection symbol command, and a special symbol variation time determined at the time of winning (starting opening winning), and a variation display of the special symbol. The relationship with the type of effect (variable effect pattern) executed by the sub-control circuit 200 is defined therein.

In the present embodiment, the variation effect pattern is represented by a few two-digit characters, and the “upper” (first digit) parameter and the “lower” (second digit) parameters described in the variation effect pattern column in FIG. 25. It is represented by a combination with parameters. For example, a variation effect when the symbol designation command determined at the time of winning (at the start opening winning) is "zA1", the jackpot selection symbol command is "z0", and the fluctuation time of the special symbol is "15000 msec". The parameter is "C1" (combination of upper "C" and lower "1").

In the present embodiment, the information of the variation effect parameter is included in the special symbol effect start command described later. At this time, the "upper" parameter and the "lower" parameter defined in the variation effect pattern column are stored in different parameter areas. Therefore, in the variation effect pattern determination table, the "upper" parameter and the "lower" parameter of the variation effect pattern are separately defined.

<Structure of data table stored in sub-main ROM>
Next, the configurations of various data tables stored in the sub-main ROM 205 of the sub-control circuit 200 will be described with reference to FIG.

[Variable production table]
First, the variation effect table will be described with reference to FIG.

In the pachinko gaming machine 1 of the present embodiment, as described above, various effects are executed during the variable display of the special symbol by the control of the sub-control circuit 200 (host control circuit 210). The content (effect pattern) of the effect performed at this time is the variation effect of the special symbol included in the special symbol effect start command described later transmitted from the main control circuit 70 to the sub control circuit 200 at the start of the variation display of the special symbol. It is determined based on pattern information and so on. The variable effect table is referred to when determining the effect content (effect pattern) based on information such as the variable effect pattern and the game state.

As shown in FIG. 26, the variable effect table includes a combination of various information (including information on the variable effect pattern) determined at the time of winning (at the time of winning the starting opening) and an effect pattern determined by lottery (“EN00”). "-" EN44 ") and the effect content, and the correspondence relationship between the random value and the selection rate (winning probability) for selecting (determining) each effect pattern is defined. In the present embodiment, as various information determined at the time of winning (at the time of winning the starting opening), the types of variation effect patterns of special symbols (“A0” to “A4”, “B1” to “B3”, and “C1” are used. "-" CF "), the fluctuation time of the special symbol, the winning type ("big hit", "small hit" or "missing"), the symbol designation command and the jackpot selection symbol command are specified in the variation effect table.

In the present embodiment, it is assumed that the variation time of the special symbol defined in the variation effect table is substantially the same as the effect time of the corresponding effect pattern. Further, the random number value defined in the variable effect table is a random number value acquired in the sub lottery process, and is any one of "0" to "999" (1000 types).

When determining the effect pattern with reference to the variation effect table of the present embodiment, for example, when the variation pattern of the special symbol determined at the start of the variation display of the special symbol is "C1" and the effect pattern is selected. When the random number value acquired in is any value from "0" to "499", "EN15" is selected as the effect pattern. In this case, an effect called "normal reach effect A" is performed during the variable display period (15000 msec) of the special symbol. Then, at the end of the "normal reach effect A", the "big hit" mode is displayed in the display area 13a of the display device 13, and the special symbol stops fluctuating.

<Outline of drawing control method>
Next, an outline of the drawing process executed by the display control circuit 230 when the drawing request is output from the host control circuit 210 to the display control circuit 230 will be described with reference to FIG. 27. Note that FIG. 27 is a diagram showing a flow of image data (moving image data and still image data) at the time of drawing processing.

In the present embodiment, the data (compressed data) of the image (moving image and / or still image) displayed on the liquid crystal screen of the display device 13 is stored in the CGROM 206 in the CGROM board 204. Then, when the drawing request is input to the display control circuit 230, the display control circuit 230 first reads the image compressed data from the CGROM 206 and decodes (decompresses) the image compression data. At this time, when the moving image compressed data is read, the moving image compressed data is decoded by the moving image decoder 234 in the display control circuit 230, and when the still image compressed data is read out, the moving image compressed data is read out in the display control circuit 230. The still image compressed data is decoded by the still image decoder 235 of.

Next, the display control circuit 230 writes the decoding result (image expansion data) of the image data to a predetermined buffer designated as the texture source. In the present embodiment, as the texture source, a movie buffer and a texture buffer provided in the SDRAM 250 (external RAM) and a sprite buffer in the built-in VRAM 237 are specified. For example, when displaying one moving image, the decompressed moving image data (decoding result) is written to the movie buffer in the SDRAM 250. Further, for example, when displaying one still image, the expanded still image data is written to the sprite buffer in the built-in VRAM 237.

Next, the display control circuit 230 specifies a rendering target for writing the rendering (drawing) result of the image data. As the rendering target, for example, a frame buffer provided in the SDRAM 250 (external RAM), a frame buffer provided in the built-in VRAM 237, or the like can be specified.

Next, the display control circuit 230 operates the rendering engine 241 to perform rendering processing on the decoding result of the image data written in the texture source, and writes the rendering result to the rendering target. In this process, the rendering process is performed according to designated information (various information input from the 3D geometry engine 240) such as enlargement / reduction and rotation of the moving image.

Next, the display control circuit 230 displays the rendering result (display output data) written to the rendering target on the display screen of the display device 13.

In this embodiment, two frame buffers are prepared as rendering targets. Then, when the rendering engine 241 writes the rendering result to the frame buffer, the frame buffer in which the rendering result is written is switched for each frame. For example, when the rendering result is written to one frame buffer in a predetermined frame, the rendering result is written to the other frame buffer in the next frame, and the rendering result is written to one frame buffer in the next frame. That is, in the present embodiment, the process of writing the rendering result to one frame buffer and the process of writing the rendering result to the other frame buffer are alternately switched and executed for each frame.

Further, in the flow of the rendering result writing process and the display process described above, the rendering result written in one frame buffer in a predetermined frame is displayed on the display screen of the display device 13 in the next frame (on the other hand). The frame buffer function of is switched from the drawing function to the display function). Further, the rendering result written in the other frame buffer in the next frame is displayed on the display screen of the display device 13 in the next frame (the function of the other frame buffer is switched from the drawing function to the display function). That is, in the present embodiment, the rendering result display processing in one frame buffer and the rendering result display processing in the other frame buffer are alternately switched and executed for each frame.

<Overview of audio playback control method>
Next, the outline of the voice reproduction process executed by the voice / LED control circuit 220 when the sound request is output from the host control circuit 210 to the voice / LED control circuit 220 will be described back to FIG.

In the present embodiment, the audio data output to the speaker 11 is stored in the CGROM 206. The audio data stored in the CGROM 206 is phrase compressed data specified by a 13-bit length phrase number NUM (000H to 1FFFH), and is a series of background music songs (BGM) or a set. A maximum of 8192 types (= 213) of production sounds (notice sounds) and the like are stored corresponding to the phrase number NUM. The phrase number NUM is specified by a set value (operating parameter) of a voice command transmitted from the host control circuit 210 to the command register 225 of the voice / LED control circuit 220.

The voice command is used for Individual Write, which transmits a set value of 1 byte length to the voice control register of any one of a large number of voice control registers built in the voice / LED control circuit 220, or a series of N consecutive voice commands. It is used for Block Write, which transmits N set values in a group to the voice control register group of.

In any case, the voice control register to be accessed is specified by a register address having a length of 1 byte, and the storage capacity of each voice control register is 1 byte. Then, in this embodiment, a large number of voice control registers are secured by dividing into seven register banks. That is, since the register bank is divided into seven, the total number of voice control registers is, in principle, a maximum of 7 × 256.

In this embodiment, in all the register banks, the specific register address is a voice control register for register bank setting. Therefore, in order to specify any one of the 7 × 256 voice control registers, the register bank is written in the voice control register for bank setting by the preceding voice command, and then the voice control belonging to that register bank is performed. The register is specified by the register address having a length of 1 byte.

By the way, in the operation of setting the set value in the voice control register, it is not always necessary to directly specify the register address of the voice control register to be set, and the SAC data (Simple Access Code Data) stored in the CGROM 206 or It is also possible to specify a Sequence Code to complete a series of setting operations for a group of voice control registers. In order to realize such an operation, the voice / LED control circuit 220 includes four simple access controllers 226a (simple access controller) and 16 sequencers 226b (Sequencer) shown in FIG. ..

Explaining from the SAC (Simple Access Code) data for operating the simple access controller 226a, the SAC data has the register address (1 byte) of the voice control register and the set value (1 byte) in the voice control register. It means a maximum of 512 sets (= 1024 bytes) of data groups associated with each other and is an aggregate terminated by a SAC end code (FFFFH) (see FIG. 8).

In the case of this embodiment, a maximum of 8192 types (= 213) of such SAC data can be provided, and the host control circuit 210 sets a 13-bit length SAC number to a voice control register for SAC control (see FIG. 8). ), The simple access controller 226a can be made to function. The simple access controller 226a, which has started the function, reads a group of SAC data specified by the SAC number in order from the CGROM 206, and sets the set value indicated by the SAC data in the voice control register indicated by the SAC data.

Therefore, the host control circuit 210 only needs to write (register) the SAC number in the voice control register for SAC control, and performs a series of setting operations without individually specifying the register address of the voice control register. Can be instructed. In the voice control register for SAC control, a standby time (standby information as attached data) that defines the start timing of a series of setting operations can be set, and the SAC number to the voice control register for SAC control can be set. It is also possible to delay the setting start timing to the voice control register by the simple access controller 226a from the writing timing of.

Subsequently, a sequence code (Sequence Code) for operating the sequencer 226b will be described. Similar to the SAC data, the sequence code is also a plurality of sets of data in which the register address (1 byte) of the voice control register and the set value (1 byte) of the voice control register are associated with each other (see FIG. 8). However, unlike the SAC data, the sequence code can specify a plurality of operation steps (plurality of sequence steps) that can be intermittently executed after a predetermined waiting time.

Further, in the voice control register for sequencer control, for each sequencer SQ0 to SQ15, the standby time (standby information) that defines the start timing of the set operation, the presence or absence of the repeat operation, and the number of repetitions (loop information) ) Can be included. Therefore, the sequence code identifies a series of audio effects that are executed over a predetermined time.

As shown in FIG. 8, the plurality of operation steps are separated by a step end code (FFFEH), and the end of the plurality of operation steps is terminated by a sequence end code (FFFFH). In the case of this embodiment, a maximum of 8192 types (= 213) of sequence codes can be provided, and the host control circuit 210 provides a sequence code number having a length of 13 bits and attached data that defines the operation of the sequencer (Sequencer). ) By writing to the voice control register for control, a series of setting operations can be instructed to the sequencer 226b.

In this embodiment, only the necessary sets of such SAC data and sequence codes are stored in advance in the CGROM 206, and a group of SAC data and a group of sequence codes are specified by SAC numbers and sequence code numbers. Therefore, in the case of this embodiment, the voice command for writing defines not only the direct setting operation to the voice control register but also the indirect setting operation via the simple access controller 226a and the sequencer 226b. It is also included when you do.

In order to realize the above operation, the host control circuit 210 and the voice / LED control circuit 220 have a parallel signal line (data bus) capable of transmitting and receiving 1-byte data and a 2-bit length operation management capable of transmitting operation management data. It is connected by a data line (address bus), a 2-bit length control signal line capable of controlling read / write operations, and a chip select signal line for selecting an audio / LED control circuit 220.

The parallel signal line is realized by the data bus of the host control circuit 210, and the operation management data line is realized by the address bus of the host control circuit 210. The voice / LED control circuit 220 is assigned three port numbers PORT in which the upper 6 bits are common and the lower 2 bits are 00, 01, and 10, and the host control circuit 210 is assigned to these ports. When the I / OREAD instruction or the I / OWRITE instruction for the number PORT is executed, the circuit is configured so that the chip select signal CS becomes the active level in each case.

Then, the data output to the lower 2 bits A0 to A1 of the address bus when the I / OREAD instruction or the I / OWRITE instruction is executed becomes the operation management data A0 to A1 for the voice / LED control circuit 220, and the 2 bits A0. Based on ~ A1, it is specified whether the 1-byte data of the data bus at that time is a register address, write data, or read data.

That is, if the address data is [00], the data of the data bus at that timing is evaluated as a register address, while if the address data is [01], the data of the data bus at that timing is write data or read. It becomes data. The read data is when the I / OREAD instruction is executed, and the write data is when the I / OWRITE instruction is executed.

Therefore, the transmission operation of the voice command for writing the predetermined set value to the predetermined voice control register issues the I / OWRITE command while changing the lower 2 bits A0 and A1 of the port number PORT of the voice / LED control circuit 220. It is realized by executing it continuously. Specifically, the lower 2 bits A0 to A1 of the address data are changed from [00] to [01], while the 1-byte data of the data bus is changed from [register address of voice control register] to [voice control register]. By changing to [Data written to], a predetermined voice command transmission operation is realized.

The write data has a multi-byte length and is controlled, as in the case of transmitting the SAC number (13 bits), the sequence code number (13 bits), and the control data (standby information, loop information, etc.) associated therewith. When the register addresses of the register are continuous, the operation management data A0 to A1 of [01] are repeated in the order of [00] → [01] → [01] → [01], and a plurality of bytes of write data are transmitted. ..

The voice command transmitted in this way is subsequently activated inside the voice / LED control circuit 220 unless there is a communication abnormality. However, if a communication abnormality is found, such as data with multiple byte lengths not matching each other, the voice command will not be effective. Then, the error flag of the voice control register is set, and this error flag (status information STS) is an I / OREAD instruction that changes the operation management data A0 to A1 of the address bus from [01] to [10]. Can be received by executing.

As described above, in this embodiment, in the final cycle in which the operation management data A0 to A1 are changed in the order of [00] → [01] → ... [01] → [10], error information (abnormality) having a plurality of bit lengths is used. Time can get FFH). Then, by resending the voice command that could not be properly transmitted in parallel, the voice effect can be appropriately advanced. Therefore, according to the configuration of the present embodiment, it is possible to eliminate the unnaturalness in which the sound production is suddenly interrupted.

On the other hand, in the data reading operation by the I / OREAD operation, the I / OWRITE instruction and the I / OREAD instruction are continuously executed while changing the lower 2 bits A0 and A1 of the port number PORT of the voice / LED control circuit 220. It will be realized by. When the read data has a length of a plurality of bytes, the I / OREAD instructions are continued for the required number of bytes.

Specifically, first, as an I / OWRITE operation, for the port number PORT in which the lower 2 bits A0 to A1 of the address data are [00], [the register address of the voice control register that stores the operation status, etc. ( 1 byte length)] is output. Next, if the I / OREAD instruction is executed for the port number PORT in which the lower 2 bits A0 to A1 of the address data are [01], necessary data such as operation status can be acquired from a predetermined voice control register. Can be done.

The audio reproduced by the audio / LED control circuit 220 having the above configuration is a digital audio in the form of a 5-bit signal (SCLK, LRO, SD0, SD1, SD2) as a digital audio signal of the audio / LED control circuit 220. It is transmitted to the power amplifier 262, amplified in class D by the digital audio power amplifier 262, and supplied to each speaker as an analog audio signal. Specifically, the amplified output (analog audio signal) of the digital audio power amplifier 262 is supplied to the lower speaker for bass, and the amplified output (analog audio signal) of the digital audio power amplifier 262 is supplied to the player. Four normal speakers (for example, see FIG. 9 (L0, R0, L1, R1)) and two deep bass (vibration) speakers (for example, see FIG. 9 (SUB0, SUB0,)) arranged substantially aligned in the vertical and horizontal positions. It is supplied to SUB1).

<Explanation of operation of main control circuit>
Next, with reference to FIGS. 28 to 35, the contents of various processes executed by the main CPU 71 of the main control circuit 70 will be described.

[Main control main processing]
First, with reference to FIG. 28, the main control main process controlled by the main CPU 71 will be described. Note that FIG. 28 is a flowchart showing the procedure of the main control main process in the present embodiment.

When the power is turned on to the pachinko gaming machine 1, the main CPU 71 first performs the initial setting process (S1). In this process, the main CPU 71 performs processes such as access permission to the main RAM 73, backup restoration, and initialization of the work area. Next, the main CPU 71 updates the initial value random number (S2). In this process, the main CPU 71 updates the initial random number counter value.

Next, the main CPU 71 performs a special symbol control process (S3). In this process, the main CPU 71 performs a predetermined control process regarding the progress of the special symbol game and the special symbols (first special symbol and second special symbol) displayed on the special symbol display device 61. The details of the special symbol control process will be described later with reference to FIG. 29 described later.

Next, the main CPU 71 performs a normal symbol control process (S4). In this process, the main CPU 71 performs a predetermined control process regarding the progress of the normal symbol game and the normal symbol displayed on the normal symbol display device 62.

Next, the main CPU 71 performs a control process of the symbol display device (S5). In this process, the main CPU 71 changes the special symbols (first special symbol and second special symbol) and the ordinary symbols based on the execution results of the special symbol control process (S3) and the normal symbol control process (S4). Control the display of the display.

Next, the main CPU 71 performs a game information data generation process (S6). In this process, the main CPU 71 generates game information data to be transmitted to the payout / launch control circuit 123, the sub control circuit 200, the hall computer of the game store, and the like, and stores the game information data in the main RAM 73.

Next, the main CPU 71 performs a storage / game state data generation process (S7). In this process, the main CPU 71 generates the storage / gaming state data to be transmitted to the sub-control circuit 200 based on the value of the probability variation flag and the value of the time saving flag, and stores the storage / gaming state data in the main RAM 73.

Then, after the processing of S7, the main CPU 71 returns the processing to the processing of S2, and repeats the processing after S2 described above.

[Special symbol control processing]
Next, with reference to FIG. 29, the special symbol control process performed in S3 during the main control main process (see FIG. 28) will be described. FIG. 29 is a flowchart showing the procedure of the special symbol control process in the present embodiment. The numerical values (“00” to “08”) in parentheses written in parallel with the code of each processing step shown in FIG. 29 indicate the value of the control state flag, and this control state flag is a predetermined storage in the main RAM 73. Stored in the area. The main CPU 71 advances the special symbol game by executing each processing step corresponding to the numerical value of the control state flag.

First, the main CPU 71 loads the control state flag (S11). In this process, the main CPU 71 reads the value of the control state flag stored in the main RAM 73.

The main CPU 71 determines whether or not to execute various processes of S12 to S20 described later based on the value of the control state flag loaded in S11. This control state flag indicates the state of the game of the special symbol game, and enables any process of S12 to S20 to be executed.

Further, the main CPU 71 executes the processing of each step at a predetermined timing determined according to the waiting time set for each processing of S12 to S20. In the period before reaching this predetermined timing, other subroutine processing is executed without executing the processing of each step. Further, the system timer interrupt process (see FIG. 33 described later), which will be described later, is also executed at a predetermined cycle.

Then, when the process of S11 is completed, the main CPU 71 performs a special symbol memory check process (S12).

In this process, the main CPU 71 checks the number of holds for variable display of the special symbol when the control state flag is a value (“00”) indicating the special symbol memory check process, and when the number of holds is not “0”. (If there is a reserved ball), processing such as hit determination, determination of a special symbol, determination of a variation pattern of a special symbol, etc. is performed. Further, in this process, the main CPU 71 sets the control state flag to a value (“01”) indicating the special symbol variation time management process (S13) described later, and corresponds to the variation pattern determined in this process. Set the fluctuation time of the special symbol in the waiting time timer. That is, by this process, after the variation time of the special symbol corresponding to the variation pattern determined in the process of S12 has elapsed, the special symbol variation time management process described later is set to be executed.

On the other hand, when the number of reserved balls is "0" (when there is no reserved ball), the main CPU 71 performs a demo display process for displaying the demo screen. The details of the special symbol memory check process will be described later with reference to FIG. 30 described later.

Next, the main CPU 71 performs a special symbol fluctuation time management process (S13). In this process, the control state flag of the main CPU 71 is a value (“01”) indicating the special symbol fluctuation time management process, and when the fluctuation time of the special symbol has elapsed, the control status flag displays the special symbol described later. A value (“02”) indicating the time management process (S14) is set, and the waiting time after confirmation is set in the waiting time timer. That is, this process is set so that the special symbol display time management process, which will be described later, is executed after the fixed waiting time set in the process of S13 has elapsed.

Next, the main CPU 71 performs a special symbol display time management process (S14). In this process, the control state flag of the main CPU 71 is a value (“02”) indicating the special symbol display time management process, and when the waiting time after the confirmation set in the process of S13 has elapsed, the result of the hit determination is reached. Is a "big hit" or a "small hit". Then, when the result of the hit determination is "big hit" or "small hit", the main CPU 71 sets the control state flag with a value ("03") indicating the big hit start interval management process (S15) described later. Set the time corresponding to the jackpot start interval in the waiting time timer. That is, by this process, after the time corresponding to the jackpot start interval set in the process of S14 has elapsed, the jackpot start interval management process described later is set to be executed.

On the other hand, when the result of the hit determination is not "big hit" or "small hit", the main CPU 71 sets a value ("08") indicating the special symbol game end processing (S20) described later in the control state flag. That is, in this case, the special symbol game end processing described later is set to be executed. The details of the special symbol display time management process will be described later with reference to FIG. 31 described later.

Next, when the result of the hit determination is determined to be "big hit" or "small hit" in S14, the main CPU 71 performs the big hit start interval management process (S15). In this process, the control state flag of the main CPU 71 is a value (“03”) indicating the jackpot start interval management process, and when the time corresponding to the jackpot start interval set in the process of S14 elapses, the first In order to open the large winning opening 53 or the second large winning opening 54, the variable positioned in the main RAM 73 is updated based on the data read from the main ROM 72.

Further, in this process, the main CPU 71 sets the control state flag to a value (“04”) indicating the process (S16) during opening of the large winning opening, which will be described later, and also sets the opening upper limit time (for example, 30 sec) of the large winning opening. Is set in the large winning opening opening time timer. That is, this process is set so that the process during opening of the large winning opening, which will be described later, is executed.

Next, the main CPU 71 performs a process during opening of the large winning opening (S16). In this process, first, when the control state flag is a value (“04”) indicating the process during opening of the large winning opening, the main CPU 71 is conditioned that the number of winning opening counters is equal to or greater than a predetermined number, and is open. It is determined whether or not one of the conditions that the upper limit time has passed (the large winning opening opening time timer is "0") is satisfied (the predetermined closing condition is satisfied).

In S16, when one of the conditions is satisfied, the main CPU 71 updates the variable positioned in the main RAM 73 in order to close the predetermined big winning opening (first big winning opening or second big winning opening). To do. Then, the main CPU 71 sets the control state flag with a value (“05”) indicating the large winning mouth residual ball monitoring process (S17), which will be described later, and sets the large winning mouth residual ball monitoring time in the waiting time timer. .. That is, by this process, after the time for monitoring the remaining balls in the large winning opening set in S17 has elapsed, the residual ball monitoring process in the large winning opening, which will be described later, is set to be executed.

Further, in S16, the main CPU 71 transmits an inter-round display command to the sub-control circuit 200 immediately before the end of the processing during the opening of the large winning opening.

Next, the main CPU 71 performs a large winning opening residual ball monitoring process (S17). In this process, the control state flag of the main CPU 71 is a value (“05”) indicating the large winning opening residual ball monitoring process, and when the large winning opening residual ball monitoring time elapses, the large winning opening opening count counter It is determined whether or not the condition that the value is equal to or greater than the maximum number of times the large winning opening is opened (the final round) is satisfied.

When it is determined in S17 that the main CPU 71 does not satisfy the above conditions, the main CPU 71 sets a value (“06”) indicating the large winning opening reopening waiting time management process in the control state flag. Further, the main CPU 71 sets the time corresponding to the interval between rounds in the waiting time timer. That is, by this process, after the time corresponding to the interval between rounds has elapsed, the waiting time management process before reopening the large winning opening, which will be described later, is set to be executed.

On the other hand, in S17, when it is determined that the main CPU 71 satisfies the above conditions, the main CPU 71 sets a value (“07”) indicating the jackpot end interval processing in the control state flag, and the time corresponding to the jackpot end interval. (Big hit end interval time) is set in the waiting time timer. That is, by this processing, after the time corresponding to the jackpot end interval set in S17 has elapsed, the jackpot end interval processing described later is set to be executed.

Next, in S17, when the main CPU 71 determines that the value of the large winning opening opening count counter is not equal to or greater than the maximum value of the large winning opening opening count, the main CPU 71 performs the waiting time management process before reopening the large winning opening ( S18). In this process, the control state flag of the main CPU 71 is a value (“06”) indicating the waiting time management process before reopening the large winning opening, and when the time corresponding to the interval between rounds elapses, the large winning opening is opened. The memory is updated so that the value of the count counter is incremented by "1". Further, the main CPU 71 sets a value (“04”) indicating the processing during opening of the large winning opening in the control state flag. Then, the main CPU 71 sets the opening upper limit time (for example, 30 sec) in the large winning opening opening time timer. That is, by this process, the above-mentioned large winning opening opening process (S16) is set to be executed again after the process of S18.

Further, in S18, the main CPU 71 transmits a command indicating that the large winning opening is open to the sub-control circuit 200 immediately before the end of the waiting time management process before reopening the large winning opening.

Further, in S17, when the main CPU 71 determines that the value of the large winning opening opening number counter is equal to or greater than the maximum value of the large winning opening opening number, the big hit end interval processing is performed (S19). In this process, the control state flag of the main CPU 71 is a value indicating the jackpot end interval process (“07”), and when the time corresponding to the jackpot end interval elapses, a value indicating the special symbol game end process (“07”). 08 ") is set in the control status flag. That is, by this process, the special symbol game end process described later is set to be executed after the process of S19. The details of the jackpot end interval processing will be described later with reference to FIG. 32 described later.

Then, the main CPU 71 controls to shift the gaming state to the probabilistic gaming state when the jackpot symbol is the probabilistic symbol, and shifts the gaming state to the normal gaming state when the jackpot symbol is the non-probable variable symbol. Control to make it. When the big hit symbol is a symbol corresponding to the "small hit", the main CPU 71 determines that the game state after the "small hit" game is completed is different from the game state controlled when the "small hit" is won. Is also controlled so as not to shift to an advantageous gaming state.

Next, the main CPU 71 performs a special symbol game end process when the big hit game state or the small hit game state ends, or when the "loss" is won (S20).

In this process, when the control state flag is a value (“08”) indicating the special symbol game end process, the main CPU 71 stores and updates the data indicating the number of held items (starting storage information) so as to decrease by “1”. To do. Further, the main CPU 71 updates the special symbol storage area in order to display the fluctuation of the special symbol next time. Further, the main CPU 71 sets a value (“00”) indicating the special symbol memory check process in the control state flag. That is, by this process, after the process of S20, the above-mentioned special symbol memory check process (S12) is set to be executed.

Then, after the processing of S20, the main CPU 71 ends the special symbol control processing, and shifts the processing to S4 of the main control main processing (see FIG. 28).

As described above, in the pachinko gaming machine 1 of the present embodiment, the special symbol game is advanced by sequentially setting various values in the control state flag. Specifically, when the gaming state is neither the big hit gaming state nor the small hit gaming state and the result of the hit determination is "missing", the main CPU 71 sets the control state flags to "00" and "01". , "02", "08" in that order. As a result, the main CPU 71 performs the above-mentioned special symbol memory check process (S12), special symbol variation time management process (S13), special symbol display time management process (S14), and special symbol game end process (S20) in this order. Execute at a predetermined timing.

Further, when the gaming state is neither the big hit gaming state nor the small hit gaming state and the result of the hit determination is "big hit" or "small hit", the main CPU 71 sets the control state flags to "00" and " Set in the order of "01", "02", "03". As a result, the main CPU 71 performs the above-mentioned special symbol memory check process (S12), special symbol variation time management process (S13), special symbol display time management process (S14), and jackpot start interval management process (S15) in this order. It is executed at a predetermined timing, and the transition control to the big hit game state or the small hit game state is executed.

Further, the main CPU 71 sets the control state flags in the order of "04", "05", and "06" when the transition control to the big hit game state or the small hit game state is executed. As a result, the main CPU 71 performs the above-mentioned processing during opening of the large winning opening (S16), monitoring processing of the remaining balls in the large winning opening (S17), and waiting time management processing before reopening of the large winning opening (S18) in this order at predetermined timings. And execute a big hit game or a small hit game.

If the end condition of the big hit game state is satisfied during the big hit game, the main CPU 71 sets the control state flags in the order of "04", "05", "07", and "08". As a result, the main CPU 71 performs the above-mentioned large winning opening opening processing (S16), large winning opening residual ball monitoring processing (S17), big hit end interval processing (S19), and special symbol game end processing (S20) in this order. It is executed at a predetermined timing, and the jackpot game state is ended.

As described above, in the special symbol control process, the process flow is branched according to the status. Further, the normal symbol control process of S4 during the main control main process shown in FIG. 28 also branches the processing flow according to the status, similarly to the special symbol control process, as will be described later.

The processing program of the present embodiment is programmed so that a pure return processing from a small module to a parent module can be performed by a call instruction when the processing is branched according to the status. As a result, in the present embodiment, the capacity of the program can be reduced as compared with the case where the jump table is arranged to execute the above processing.

[Special symbol memory check processing]
Next, with reference to FIG. 30, the special symbol memory check process performed in S12 during the special symbol control process (see FIG. 29) will be described. Note that FIG. 30 is a flowchart showing the procedure of the special symbol memory check process in the present embodiment.

First, the main CPU 71 loads the control state flag (S31). In this process, the main CPU 71 reads the value of the control state flag stored in the main RAM 73.

Next, the main CPU 71 determines whether or not the control state flag is a value (“00”) indicating the special symbol memory check process (S32). In S32, when the main CPU 71 determines that the control state flag is not "00" (when the determination in S32 is NO), the main CPU 71 ends the special symbol storage check process and performs the process in the special symbol control process (FIG. 29). See).

On the other hand, in S32, when the main CPU 71 determines that the control state flag is "00" (when the determination in S32 is YES), the main CPU 71 wins the second start opening (variable display of the second special symbol). It is determined whether or not the reserved number (second start storage number) is "0" (S33).

In S33, when the main CPU 71 determines that the number of reserved second start opening prizes is not "0" (when the determination in S33 is NO), the main CPU 71 has a second number corresponding to the number of reserved second start opening prizes. The value of the start memory number is subtracted by "1" (S34).

In the present embodiment, the main CPU 71 determines whether or not data is stored in the second special symbol start storage area (0) to the second special symbol start storage area (4) provided in the main RAM 73, and determines whether or not the data is stored in the second special symbol start storage area (0) to the second special symbol start storage area (4). It is determined whether or not there is a start memory of the special symbol game corresponding to the variable display of the second special symbol that is changing or pending. In the second special symbol start storage area (0), the data (information) of the special symbol game corresponding to the variable display of the second special symbol that is changing is stored as the start storage. Then, in the second special symbol start storage area (1) to the second special symbol start storage area (4), a special symbol game corresponding to the variable display (holding ball) of the second special symbol for four times held. Data (information) is stored as a start memory. The data included in the start storage stored in each of the second special symbol start storage areas is, for example, data such as a jackpot determination random value and a jackpot symbol random value acquired at the time of winning the second start port 45. ..

After the process of S34, the main CPU 71 performs a special symbol storage transfer process based on the second start opening winning (S35). In this process, the main CPU 71 transfers (stores) the data of the second special symbol start storage areas (1) to (4) to the second special symbol start storage areas (0) to (3), respectively. Then, after the processing of S35, the main CPU 71 performs the processing of S40 described later.

Here, returning to the process of S33 again, when the main CPU 71 determines in S33 that the number of reserved second start opening prizes is "0" (when the determination in S33 is YES), the main CPU 71 determines. It is determined whether or not the reserved number (first starting memory number) of the first starting opening winning (variable display of the first special symbol) is "0" (S36).

In S36, when the main CPU 71 determines that the number of reserved first start opening prizes is "0" (when the determination in S36 is YES), the main CPU 71 performs a demo display process (S37). Then, after the process of S37, the main CPU 71 ends the special symbol memory check process and returns the process to the special symbol control process (see FIG. 29).

In the demo display process of S37, the main CPU 71 sets the demo display permission value in the main RAM 73. That is, the main CPU 71 has a predetermined time (for example, a state in which the start memory of the special symbol game is "0") when the number of reserved first start opening prizes and second start opening prizes is "0". 30 sec) When it is maintained, a predetermined value is set as the demo display permission value. Further, when the demo display permission value is a predetermined value in the demo display process of S37, the main CPU 71 sets the demo display command data in the main RAM 73. Then, the demo display command data is transmitted from the main CPU 71 of the main control circuit 70 to the host control circuit 210 in the sub control circuit 200. When the sub-control circuit 200 receives the demo display command data, the sub-control circuit 200 displays the demo screen in the display area 13a of the display device 13.

On the other hand, in S36, when the main CPU 71 determines that the number of holdings of the first starting opening prize is not "0" (when the determination of S36 is NO), the main CPU 71 corresponds to the number of holdings of the first starting opening winning. The value of the first start storage number is subtracted by "1" (S38).

In the present embodiment, the main CPU 71 determines whether or not data is stored in the first special symbol start storage area (0) to the first special symbol start storage area (4) provided in the main RAM 73, and determines whether or not the data is stored in the first special symbol start storage area (0) to the first special symbol start storage area (4). It is determined whether or not there is a start memory of the special symbol game corresponding to the variable display of the first special symbol that is changing or pending. In the first special symbol start storage area (0), data (information) of the special symbol game corresponding to the variable display of the fluctuating first special symbol is stored as start storage. Then, in the first special symbol start storage area (1) to the first special symbol start storage area (4), a special symbol game corresponding to the variable display (holding ball) of the first special symbol for four times held. Data (information) is stored as a start memory. The data included in the start memory stored in each first special symbol start storage area is, for example, data such as a jackpot determination random value and a jackpot symbol random value acquired at the time of winning the first start port 44. ..

After the process of S38, the main CPU 71 performs a special symbol storage transfer process based on the first start opening winning (S39). In this process, the main CPU 71 transfers (stores) the data of the first special symbol start storage areas (1) to (4) to the first special symbol start storage areas (0) to (3), respectively. Then, after the processing of S39, the main CPU 71 performs the processing of S40 described later.

Next, after the processing of S35 or S39, the main CPU 71 determines whether or not the value of the time saving state change number counter is “0” (S40).

In S40, when the main CPU 71 determines that the value of the time saving state fluctuation counter is “0” (when the determination in S40 is YES), the main CPU 71 performs the process of S44 described later. On the other hand, in S40, when the main CPU 71 determines that the value of the time saving state fluctuation counter is not "0" (when the determination in S40 is NO), the main CPU 71 subtracts the value of the time saving state fluctuation counter by "1". (S41).

After the processing of S41, the main CPU 71 determines whether or not the value of the time saving state fluctuation number counter is “0” (S42).

In S42, when the main CPU 71 determines that the value of the time saving state fluctuation counter is not "0" (when the determination in S42 is NO), the main CPU 71 performs the process of S44 described later. On the other hand, in S42, when the main CPU 71 determines that the value of the time saving state fluctuation counter is "0" (when the determination in S42 is YES), the main CPU 71 sets the time saving flag to "0" (S43). ).

After the processing of S43, when the determination in S40 is YES or the determination in S42 is NO, the main CPU 71 sets the control state flag to a value (“01”) indicating the special symbol fluctuation time management process (S44). Further, in this process, the main CPU 71 transmits a hold subtraction command and a special symbol effect start command to the sub control circuit 200.

Next, the main CPU 71 performs a jackpot determination process (S45). In this process, the main CPU 71 determines (determines) which of the "big hit", "small hit", and "loss" is won by lottery based on the big hit determination random value acquired at the time of winning the start opening.

Next, the main CPU 71 clears the information (data) of the storage area used for the previous variation display (S46). Next, the main CPU 71 sets the fluctuation time corresponding to the determined fluctuation pattern of the special symbol in the waiting time timer (S47). Then, after the process of S47, the main CPU 71 ends the special symbol memory check process and returns the process to the special symbol control process (see FIG. 29).

[Special symbol display time management process]
Next, with reference to FIG. 31, the special symbol display time management process performed in S14 during the special symbol control process (see FIG. 29) will be described. Note that FIG. 31 is a flowchart showing the procedure of the special symbol display time management process in the present embodiment.

First, the main CPU 71 determines whether or not the control state flag is a value (“02”) indicating the special symbol display time management process (S51). In S51, when the main CPU 71 determines that the control state flag is not a value (“02”) indicating the special symbol display time management process (when the determination in S51 is NO), the main CPU 71 performs the special symbol display time management process. It ends and returns the process to the special symbol control process (see FIG. 29).

On the other hand, in S51, when the main CPU 71 determines that the control state flag is a value (“02”) indicating the special symbol display time management process (when the determination in S51 is YES), the main CPU 71 is the waiting time timer. It is determined whether or not the value (waiting time) is "0" (S52). In this process, the main CPU 71 determines whether or not the waiting time (variation start waiting time) after the fluctuation is confirmed set in the waiting time timer has been exhausted.

In S52, when the main CPU 71 determines that the value of the waiting time timer is not "0" (when the determination in S52 is NO), the main CPU 71 ends the special symbol display time management process and performs the process as a special symbol control process. Return to (see FIG. 29). On the other hand, in S52, when the main CPU 71 determines that the value of the waiting time timer is "0" (when the determination in S52 is YES), the main CPU 71 determines whether or not the special symbol game is a "big hit". Determine (S53). Further, in this process, the main CPU 71 simultaneously transmits a special effect stop command to the sub-control circuit 200.

In S53, when the main CPU 71 determines that the special symbol game is not a "big hit" (when the determination in S53 is NO), the main CPU 71 sets a value ("08") indicating the special symbol game end processing in the control state flag. Set (S54). Then, after the processing of S54, the main CPU 71 ends the special symbol display time management processing, and returns the processing to the special symbol control processing (see FIG. 29).

On the other hand, in S53, when the main CPU 71 determines that the special symbol game is a "big hit" (YES in S53), the main CPU 71 sets the jackpot flag to the ON state (S55). The jackpot flag is a flag indicating whether or not to perform a jackpot game.

Next, the main CPU 71 clears the value of the time saving state change number counter, the value of the time saving flag, and the value of the probability change flag (S56). Next, the main CPU 71 sets the control state flag to a value (“03”) indicating the jackpot start interval management process (S57).

Next, the main CPU 71 sets the jackpot start interval time (for example, 5000 msec) corresponding to the special symbol (first special symbol or second special symbol) in the waiting time timer (S58). Next, the main CPU 71 sets a jackpot start command (special symbol hit start display command) corresponding to the special symbol in the main RAM 73 (S59). Further, in this process, the main CPU 71 simultaneously transmits a special symbol hit start display command to the sub control circuit 200.

Next, the main CPU 71 sets the round number display LED pattern flag to the ON state (S60). The round number display LED pattern flag is a flag indicating whether or not to display the remaining number of rounds in a predetermined pattern. Then, after the processing of S60, the main CPU 71 ends the special symbol display time management processing, and returns the processing to the special symbol control processing (see FIG. 29).

[Big hit end interval processing]
Next, with reference to FIG. 32, the jackpot end interval process performed in S19 during the special symbol control process (see FIG. 29) will be described. Note that FIG. 32 is a flowchart showing the procedure of the jackpot end interval processing in the present embodiment.

First, the main CPU 71 determines whether or not the control state flag is a value (“07”) indicating the jackpot end interval processing (S71).

In S71, when the main CPU 71 determines that the control state flag is not a value indicating the jackpot end interval processing (“07”) (when the determination in S71 is NO), the main CPU 71 ends the jackpot end interval processing and processes it. Is returned to the special symbol control process (see FIG. 29). On the other hand, in S71, when the main CPU 71 determines that the control state flag is a value indicating the jackpot end interval processing (“07”) (when the determination in S71 is YES), the value of the waiting time timer is set in the main CPU 71. It is determined whether or not it is "0" (S72). In this process, the main CPU 71 determines whether or not the jackpot end interval time set in the waiting time timer has been exhausted.

In S72, when the main CPU 71 determines that the value of the waiting time timer is not "0" (when the determination in S72 is NO), the main CPU 71 ends the jackpot end interval process and performs the process as a special symbol control process (FIG. FIG. 29). On the other hand, in S72, when the main CPU 71 determines that the value of the waiting time timer is "0" (when the determination in S72 is YES), the main CPU 71 clears the LED pattern flag indicating the number of times the large winning opening is opened (when the determination is YES in S72). S73).

Next, the main CPU 71 clears the round number distribution flag (sets it to “0”) (S74).

Next, the main CPU 71 sets the control state flag to a value (“08”) indicating the special symbol game end processing (S75). Further, in this process, the main CPU 71 simultaneously transmits a special symbol hit end display command to the sub control circuit 200. Next, the main CPU 71 clears the jackpot flag (S76).

Next, the main CPU 71 refers to the jackpot type determination table (see FIGS. 20 to 23), and sets the value of the probability variation flag based on the game state at the time of winning the jackpot and the type of the symbol command selected at the time of jackpot (S77). .. Next, the main CPU 71 refers to the jackpot type determination table (see FIGS. 20 to 23), and sets the value of the time saving flag based on the game state at the time of winning the jackpot and the type of the symbol command selected at the time of jackpot (S78). ..

Next, the main CPU 71 determines whether or not the value of the time saving flag is "1" (whether or not the time saving flag is on) (S79). In S79, when the main CPU 71 determines that the value of the time saving flag is not "1" (when the determination in S79 is NO), the main CPU 71 ends the jackpot end interval process and performs the process as a special symbol control process (FIG. 29). See).

On the other hand, in S79, when the main CPU 71 determines that the value of the time saving flag is "1" (when the determination in S79 is YES), the main CPU 71 refers to the jackpot type determination table (see FIGS. 20 to 23). Then, based on the game state at the time of winning the big hit and the type of the symbol command selected at the time of the big hit, the value of the corresponding time reduction number is set in the time reduction state fluctuation number counter (S80). Then, after the processing of S80, the main CPU 71 ends the jackpot end interval processing and returns the processing to the special symbol control processing (see FIG. 29).

[System timer interrupt processing]
In the pachinko gaming machine 1 of the present embodiment, the main CPU 71 interrupts the main process at a predetermined cycle and executes the system timer interrupt process even during the execution of the main process. Specifically, the main CPU 71 executes the system timer interrupt process according to the clock pulse generated from the clock generation circuit 74 in a predetermined cycle (for example, 2 msec). Here, the system timer interrupt process executed by the main CPU 71 will be described with reference to FIG. 33. Note that FIG. 33 is a flowchart showing the procedure of the system timer interrupt process in the present embodiment.

First, the main CPU 71 saves the data (information) of each register (S121). Next, the main CPU 71 performs a random number update process (S122). In this process, the main CPU 71 updates various random value values extracted from the jackpot determination counter, the symbol determination counter, the hit determination counter, the fall determination counter, the fluctuation pattern determination counter, the effect pattern determination counter, and the like. .. The jackpot determination counter and the symbol determination counter lack fairness if the update timing of the counter value is indefinite. Therefore, the jackpot determination counter and the symbol determination counter are updated at a fixed timing in a 2 msec cycle in order to ensure fairness.

Next, the main CPU 71 performs a switch input detection process (S123). In this process, the main CPU 71 detects winning or passing through the various starting ports, various winning ports, and the ball passing detector 43. The details of the switch input detection process will be described later with reference to FIG. 34 described later.

Next, the main CPU 71 performs a timer update process (S124). Specifically, the main CPU 71 has various timers such as a waiting time timer for synchronizing the main control circuit 70 and the sub control circuit 200, and a large winning opening opening time timer for measuring the opening time of the large winning opening. Update process.

Next, the main CPU 71 performs a command output process (S125). In this process, the main CPU 71 outputs various commands such as a winning command and a variable command to the host control circuit 210 of the sub control circuit 200.

Next, the main CPU 71 performs game information output processing (S126). In this process, the main CPU 71 outputs various information related to the game processed by the main control circuit 70, the sub control circuit 200, the payout / launch control circuit 123, and the like to the hall computer of the game store.

Next, the main CPU 71 restores the data of each register saved in S121 (S127). Then, after the process of S127, the main CPU 71 ends the system timer interrupt process.

[Switch input detection process]
Next, with reference to FIG. 34, the switch input detection process performed in S123 during the system timer interrupt process (see FIG. 33) will be described. Note that FIG. 34 is a flowchart showing the procedure of the switch input detection process in the present embodiment.

First, the main CPU 71 performs a start opening winning detection process (S131). In this process, the main CPU 71 determines whether or not the game ball has entered (passed) into the first starting port 44 or the second starting port 45. That is, the main CPU 71 detects whether or not the winning of the game ball is detected by the first starting opening winning ball sensor 44a or the second starting opening winning ball sensor 45a. The details of the start opening winning detection process will be described later with reference to FIG. 35 described later.

Next, the main CPU 71 performs a general winning opening passage detection process (S132). In this process, the main CPU 71 determines whether or not a game ball has entered the general winning opening 51 or 52. That is, the main CPU 71 detects whether or not the winning of the game ball is detected by the general winning ball sensor 51a or 52a. Then, when the winning of the game ball to the general winning opening 51 or 52 is detected, the main CPU 71 performs various predetermined processes corresponding to the winning.

Next, the main CPU 71 performs a large winning opening passage detection process (S133). In this process, the main CPU 71 determines whether or not a game ball has entered the first large winning opening 53 or the second large winning opening 54. That is, the main CPU 71 detects whether or not the winning of the game ball is detected by the first special winning opening solenoid 53b or the second special winning opening solenoid 54b. Then, when the winning of the game ball into the first winning opening 53 or the second winning opening 54 is detected, the main CPU 71 performs various predetermined processes corresponding to the winning.

Next, the main CPU 71 performs a gate passage detection process (S134). In this process, the main CPU 71 determines whether or not the game ball has passed through the ball passage detector 43. That is, the main CPU 71 detects whether or not the passing of the game ball is detected by the passing ball sensor 43a. Next, when it is detected that the game ball has passed through the ball passage detector 43, the main CPU 71 performs various predetermined processes corresponding to the passage. Then, after the processing of S134, the main CPU 71 ends the switch input detection processing, and shifts the processing to S124 of the system timer interrupt processing (see FIG. 33).

[Starting opening winning detection process]
Next, with reference to FIG. 35, the start opening winning detection process performed in S131 during the switch input detection process (see FIG. 34) will be described. Note that FIG. 34 is a flowchart showing the procedure of the start opening winning detection process in the present embodiment.

First, the main CPU 71 determines whether or not the winning of the game ball to the first starting port 44 is detected based on the output signal of the first starting port winning ball sensor 44a (S141).

In S141, when the main CPU 71 determines that the winning of the game ball to the first starting port 44 has not been detected (when the determination in S141 is NO), the main CPU 71 performs the process of S149 described later. On the other hand, in S141, when the main CPU 71 determines that the winning of the game ball to the first starting opening 44 has been detected (when the determination in S141 is YES), the main CPU 71 has the payout information corresponding to the first starting opening winning. Is set in the main RAM 73 (S142). In the present embodiment, when the game ball wins the first starting port 44, a predetermined number of game balls are paid out. Therefore, in the process of S142, the payout information of a predetermined number of game balls is set.

After the processing of S142, the main CPU 71 determines whether or not the number of reserved balls (the number of reserved balls) of the first start opening winning (variable display of the first special symbol) is less than "4" (S143).

In S143, when the main CPU 71 determines that the number of reserved first start opening prizes is not less than "4" (when the determination in S143 is NO), the main CPU 71 performs the process of S149 described later. On the other hand, in S143, when the main CPU 71 determines that the number of reserved first start opening prizes is less than "4" (when the determination in S143 is YES), the main CPU 71 determines the number of reserved first start opening prizes. The process of adding "1" is performed (S144).

After the processing of S144, the main CPU 71 acquires various random number values used for the lottery, and stores the acquired various random number values in a predetermined area of the main RAM 73 (S145). Specifically, the main CPU 71 acquires various random values such as a jackpot determination random value, a symbol random value, and a fall determination random value.

Next, the main CPU 71 performs the first special stop symbol determination process (S146). In this process, the main CPU 71 refers to the jackpot random number determination table (first start port) (see FIG. 16) and the symbol determination table (first start port) (see FIG. 18), and the jackpot determination random number acquired in S145. Based on the numerical value and the random number value of the symbol, it is determined whether or not it is a "big hit", and in the case of a "big hit", the jackpot symbol (identification symbol for production) scheduled to be displayed on the display screen of the display device 13 Make a selection (judgment).

Next, the main CPU 71 performs a process of determining whether or not there is a fall (S147). In this process, the main CPU 71 performs a fall lottery based on the fall determination random number value acquired in S145, and determines whether or not a fall has occurred. As a result, the main CPU 71 acquires the fall lottery information (“0”: no fall, or “1”: with fall).

Next, the main CPU 71 sets the hold addition command data at the time of winning the first start opening in the main RAM 73 (S148).

In this process, the main CPU 71 uses a jackpot random number determination table (first start port) (see FIG. 16), a symbol determination table (first start port) (see FIG. 18), and a jackpot type determination table (see FIGS. 20 to 23). ) And the winning production information determination table (see FIG. 24), the game state ("normal", "probability change", "time reduction"), winning type ("big hit", "small hit", "loss" ”), Start memory number (number of reserved first special symbols), symbol designation command, jackpot selection symbol command, winning production information, jackpot judgment result information, fall lottery information, etc. Determine the information (transmission content) to be included in.

At this time, the game state is acquired by referring to the values of the probability variation flag and the time saving flag, and the winning type is acquired by referring to the jackpot random number determination table (first starting port) (see FIG. 16). The symbol designation command and the jackpot selection symbol command are acquired by referring to the symbol determination table (first starting port) (see FIG. 18), and the winning effect information is the winning effect information determination table (see FIG. 24). Obtained by referring to. Further, the result information of the jackpot determination is acquired by the process of S146, and the fall lottery information is acquired by the process of S147.

Further, in the present embodiment, in the process of S148, the hold addition command at the time of winning the first start port is transmitted from the main CPU 71 to the sub control circuit 200 (host control circuit 210). Then, based on the hold addition command at the time of winning the first start opening, the sub-control circuit 200 selects the effect patterns of the hold effect and the look-ahead effect.

After the processing of S148, or when S141 or S143 determines NO, has the main CPU 71 detected the winning of the game ball to the second starting port 45 based on the output signal of the second starting port winning ball sensor 45a? Whether or not it is determined (S149).

In S149, when the main CPU 71 determines that the winning of the game ball to the second starting port 45 has not been detected (when the determination in S149 is NO), the main CPU 71 ends the starting opening winning detection process and processes it. To S132 of the switch input detection process (see FIG. 34). On the other hand, in S149, when the main CPU 71 determines that the winning of the game ball to the second starting opening 45 has been detected (when the determination in S149 is YES), the main CPU 71 has the payout information corresponding to the second starting opening winning. Is set in the main RAM 73 (S150). In the present embodiment, when the game ball wins the second starting port 45, a predetermined number of game balls are paid out. Therefore, in the process of S150, the payout information of a predetermined number of game balls is set.

After the processing of S150, the main CPU 71 determines whether or not the number of reserved balls (the number of reserved balls) of the second start opening winning (variable display of the second special symbol) is less than "4" (S151).

In S151, when the main CPU 71 determines that the number of reserved second start opening prizes is not less than "4" (when the determination in S151 is NO), the main CPU 71 ends the start opening winning detection process and switches the process. Move to S132 of the input detection process (see FIG. 34). On the other hand, in S151, when the main CPU 71 determines that the number of reserved second start opening prizes is less than "4" (when the determination in S151 is YES), the main CPU 71 determines the number of reserved second start opening prizes. The process of adding "1" is performed (S152). After the processing of S152, the main CPU 71 acquires various random number values used for the lottery, and stores the acquired various random number values in a predetermined area of the main RAM 73 (S153). Specifically, the main CPU 71 acquires various random values such as a jackpot determination random value, a symbol random value, and a fall determination random value.

Next, the main CPU 71 performs a second special stop symbol determination process (S154). In this process, the main CPU 71 refers to the jackpot random number determination table (second start port) (see FIG. 17) and the symbol determination table (second start port) (see FIG. 19), and the jackpot determination random number acquired in S153. Based on the numerical value and the symbol random number value, it is determined whether or not it is a "big hit", and in the case of a big hit, the jackpot symbol (identification symbol for production) to be displayed on the display screen of the display device 13 is selected ( Judgment) is performed.

Next, the main CPU 71 performs a process of determining whether or not there is a fall (S155). In this process, the main CPU 71 performs a fall lottery based on the fall determination random number value acquired in S153, and determines whether or not a fall has occurred. As a result, the main CPU 71 acquires the fall lottery information (“0”: no fall, or “1”: with fall).

Next, the main CPU 71 sets the hold addition command data at the time of winning the second start opening in the main RAM 73 (S156).

In this process, the main CPU 71 uses a jackpot random number determination table (second start port) (see FIG. 17), a symbol determination table (second start port) (see FIG. 19), and a jackpot type determination table (see FIGS. 20 to 23). ) And the production information determination table at the time of winning (see FIG. 24), the game state ("normal", "probability change", "time reduction"), winning type ("big hit", "missing"), start memory Information to be included in the hold addition command based on information such as the number (the number of the second special symbol held), the symbol designation command, the jackpot selection symbol command, the winning effect information, the jackpot judgment result information, and the fall lottery information. The content to be sent) is decided.

At this time, the game state is acquired by referring to the values of the probability variation flag and the time saving flag, and the winning type is acquired by referring to the jackpot random number determination table (second starting port) (see FIG. 17). The symbol designation command and the jackpot selection symbol command are acquired by referring to the symbol determination table (second starting port) (see FIG. 19), and the winning effect information is the winning effect information determination table (see FIG. 24). Obtained by referring to. Further, the result information of the jackpot determination is acquired by the process of S154, and the fall lottery information is acquired by the process of S155.

Further, in the present embodiment, in the process of S156, the hold addition command at the time of winning the second start port is transmitted from the main CPU 71 to the sub control circuit 200 (host control circuit 210). The sub-control circuit 200 selects the effect pattern of the hold effect and the look-ahead effect based on the hold addition command at the time of winning the second start opening. Then, after the process of S156, the main CPU 71 ends the start opening winning detection process, and shifts the process to S132 of the switch input detection process (see FIG. 34).

<Explanation of operation of sub-control circuit>
Next, with reference to FIGS. 36 to 74, the contents of various processes executed by the various control circuits in the sub-board 202 of the sub-control circuit 200 (see, for example, FIG. 6) will be described. The sub control circuit 200 receives various commands transmitted from the main control circuit 70 (see, for example, FIG. 6), and performs various processes based on the various commands.

[Sub-control main processing]
First, with reference to FIG. 36, the sub-control main process executed by the host control circuit 210 (see, for example, FIG. 6; the same applies hereinafter) will be described. FIG. 36 is a flowchart showing an example of the sub-control main process in the present embodiment. The sub-control main process is a process started when the power is turned on. In the sub-control main process described with reference to FIG. 36 and the sub-control main process described later (see FIGS. 47, 48, and 49), even if they are the same process, different reference numerals are given for convenience of explanation. ing. For example, when various initialization processes are described as an example, various initialization processes (step S201) in FIG. 36, various initialization processes (step S381) in FIG. 47, and various initialization processes (step S391) in FIG. 48 are described. , The various initialization processes (step S401) of FIG. 48 are substantially the same process but have different reference numerals.

First, the host control circuit 210 performs various initialization processes (step S201). In this process, the host control circuit 210 performs various initial setting processes such as hardware initialization process, device initialization process, various application initialization process, backup data recovery initialization process, and RTC acquisition process. Do. When the game data is erased by clearing the RAM, the random number initialization process is also performed. Further, the host control circuit 210 clears the watchdog timer counter each time each initialization process is completed. At startup, the reset time of the watchdog timer is set, and if the service pulse is not written after that (at the time of timeout), the power interruption process is performed. The timing for clearing the watchdog timer is at the start of each process in the main loop in the sub-control main process, at the start of each initialization process, and at the time of transition to the power interruption process.

Next, the host control circuit 210 enters the main loop and performs an RTC acquisition process based on the RTC time, that is, a process of acquiring the current time (step S202).

The host control circuit 210 performs a random number initialization process in step S203. This random number initialization process will be described later.

The host control circuit 210 acquires the control code of the accessory in step S204 and performs synchronization processing between the accessory and the solenoid (step S205). These processes will be described in the "accessory solenoid control process" described later.

The host control circuit 210 performs the sub-device input process in step S206. In this process, the host control circuit 210 performs an information acquisition process of the operation content based on an input state of the operation means or the like (a process of determining whether or not the player has performed an operation on the operation means such as a button). And so on. This sub-device input process (step S206) includes adjusting the brightness of the LED or the like by the operation of the player or the like.

The host control circuit 210 performs various request control processes in step S207. In this process, the host control circuit 210 performs various request control processes such as sound request control process, LED request control process, and accessory request control process. The sound request, LED request, accessory request, and the like are stored in a buffer and output to each device after the bank flip in step S213, which will be described later. As a result, synchronization with drawing can be achieved. The bank flip is a process of switching the function of one frame buffer from the drawing function to the display function and switching the function of the other frame buffer from the display function to the drawing function.

Next, the host control circuit 210 enters the packet reception loop in the main loop and performs command control processing between main and sub (step S208). In this process, the host control circuit 210 performs a command data reading process (command receiving process) when command data is received from the main CPU 71 and a command data storage process (received data storage process) in the subwork RAM 210a.

The host control circuit 210 performs a game data backup process in step S209. In the pachinko gaming machine 1 of the present embodiment, the first data (magic code, program version and SUM value) and the second data (both are information set in the hall menu) are the game data used for the RAM clear determination. And SUM value) are prepared. Then, in the game data backup process, after the first data is stored in the game data, it is backed up to SRAM 210b (see FIG. 6). In addition, the game data is backed up (mirrored) in another area of the SRAM 210b. After the power is turned on, the game data is restored from the data backed up in the SRAM 210b. At this time, the first data is used to check whether the backed up data is damaged. If the backed up data is corrupted, check if the second data is corrupted. At this time, the data stored in all the SRAM 210b such as the hall menu information is also initialized.

Next, the host control circuit 210 performs an animation request construction process (step S210). In this process, the host control circuit 210 performs command analysis, state setting, and lottery processing, and in response to these, generates an animation request necessary for performing effect control using the display device 13, and this animation request. In response to the effect control (display) in the display device 13 executed based on the above, various requests (sound request, lamp request, and accessory request) for operating the various effect devices are generated.

The host control circuit 210 executes the processes of steps S202 to S05 until it is executed for the number of received commands, and exits the packet reception loop when it is executed for the number of received commands. After that, the host control circuit 210 goes through an animation update process (step S211), a drawing process (step S212), and a bank flip / bank flip end wait (step S213), and each process in the main loop is repeated.

The host control circuit 210 repeatedly executes the processing (main loop processing) of the above-mentioned example of steps S202 to S213 in a predetermined FPS cycle. The FPS cycle is set to, for example, about 16.7 msec (60 FPS), about 33.3 msec (30 FPS), and the like. The predetermined FPS cycle is time adjusted in step S213.

Below, timer interrupt processing, sub-device input processing, backlight control processing, backlight and various LED brightness adjustment, RTC acquisition processing, composition playback control, sound amplifier control processing, sound request control processing (for the same channel) (When there are a plurality of sound requests), sound request control processing (when volume adjustment is performed), LED brightness adjustment processing, accessory solenoid control processing, data load processing, and sub-random number processing will be described in this order. The description order of each of the above processes is different from the process order for convenience of explanation.

[Timer interrupt processing]
In the pachinko gaming machine 1 of the present embodiment, the host control circuit 210 performs interrupt processing at a cycle of 1 msec. The interrupt processing will be described in each process described later, but here, an example of a typical interrupt process will be briefly described with reference to FIG. 37. FIG. 37 is a flowchart showing an example of timer interrupt processing executed by the host control circuit (sub-control circuit). In the timer interrupt process described briefly with reference to FIG. 37 and the timer interrupt process described later (see FIGS. 44 and 46), even if they are the same process, different reference numerals are given for convenience of explanation. For example, when the accessory motor control is described as an example, the accessory motor control of FIG. 37 (step S251), the accessory motor control of FIG. 44 (step S352), and the accessory motor control of FIG. 46 (step S371). Is substantially the same process but has a different reference numeral.

With reference to FIG. 37, in the timer interrupt process, the host control circuit 210 first controls the accessory motor (step S251). Next, the host control circuit 210 performs an input state determination process based on the input information of the subdevice (step S252). Next, the host control circuit 210 performs control processing such as the backlight of the liquid crystal display device used as the display device 13 based on the brightness value (step S253). Next, the host control circuit 210 performs a sound amplifier check process (step S254).

[Sub-device input processing]
In the present embodiment, the host control circuit 210 creates subdevice input discrimination information in the main process every 33.3 msec based on the input state of the subdevice detected by the timer interrupt every 1 msec, and this is created. The sub-device is controlled based on the sub-device input discrimination information.

When the host control circuit 210 detects the input state of the subdevice by a timer interrupt every 1 msec, the subdevice input information and the subdevice are used as the above subdevice input determination information created in the main process based on the detection result. Input ON edge information, sub device input ON edge information (with repeat function), and sub device input OFF edge information are created.

The sub-device input process shown in FIG. 36 will be described below with reference to FIGS. 38 to 41. The sub-device is controlled by the host control circuit 210 based on input (for example, operation) information, such as a push button. Note that FIG. 38 is a diagram showing an example for explaining the sub-device input discrimination information to be created, (a) a diagram showing an input state of the sub-device detected by the timer interrupt, and (b) being created by the main process. A diagram showing the sub-device input information to be input, (c) a diagram showing the sub-device input ON edge information created by the main process, and (c) a sub-device input ON edge information (with a repeat function) created by the main process. The figure which shows, (d) is the figure which shows the sub-device OFF edge information created by the main process. FIG. 39 is a flowchart showing an example of the sub-device input process. FIG. 40 is a flowchart showing an example of sub-device input ON edge information (with repeat function) processing. FIG. 41 shows an example of the sub-device input ON edge information (with repeat function) processing, and is a flowchart continuing from FIG. 40.

As shown in FIG. 38 (b), the sub-device input information created in the main process is created according to the sub-device input state (see FIG. 38 (a)) detected by the timer interrupt. That is, when the subdevice input state detected by the timer interrupt is ON, 1 is set. Further, when the sub-device input state detected by the timer interrupt is OFF, 0 is set.

As shown in FIG. 38 (c), the sub-device input ON edge information is only one frame in the main process when it is detected that the sub-device input state detected by the timer interrupt has changed from OFF to ON. Is set.

The sub-device input ON edge information (with repeat function) is information used for control, for example, when debugging or when the operation button is pressed and held for a long time, and is detected by a timer interrupt as shown in FIG. 38 (d). When it is detected that the input state of the sub-device is changed from OFF to ON, 1 is set for one frame in the main process. Then, if the input state of the sub-device continues to be ON after that, 1 is set in one frame after 10 frames have elapsed in the main process, for example, as a fixed time until the start of key repeat, and after that, in the main process, for example. 1 is set every 4 frames. In this way, the reason why only the first frame is lengthened to 10 frames is to make it possible to determine whether or not the sub-device has been long-pressed, and if the first frame is short, it is determined that it is not long-pressed. Can be done.

As shown in FIG. 38 (e), the sub-device input OFF edge information is only one frame in the main process when it is detected that the sub-device input state detected by the timer interrupt has changed from ON to OFF. Is set.

In the present embodiment, assuming that there are a plurality of sub-devices, the host control circuit 210 manages the sub-device input determination information in bit units. For example, bit0 is the main button, bit1 is the left button, bit2 is the right button, and so on. Sub-device input discrimination information for up to 32 devices can be managed, for example.

Next, the sub-device input process (see, for example, step S206 in FIG. 36) will be described with reference to FIG. 39. In this sub-device input process, the sub-device input discrimination information includes sub-device input information, sub-device input ON edge information, sub-device input ON edge information (with repeat function), and sub-device input OFF edge information, for example, 4. This is the process of creating type information.

First, the host control circuit 210 creates input information of the current subdevice based on the input state of the current subdevice (step S301). Specifically, 1 is set when the sub device is in the ON state, and 0 is set when the sub device is in the OFF state.

Next, the host control circuit 210 updates the input information of the subdevice in accordance with the current subdevice input information, that is, the input information of the subdevice created in step S301 (step S302).

Next, the host control circuit 210 determines whether or not the previous subdevice input information is 0 and the current subdevice input information is 1 (step S303). If the previous sub-device input information is 0 and the current sub-device input information is 1 (YES in step S303), the host control circuit 210 sets the sub-device input ON edge information to 1 (step S304), and steps. Move to S306. On the other hand, if the previous subdevice input information is 0 and the current subdevice input information is not 1 (that is, if the previous subdevice input information is 1 and / and the current subdevice input information is 0), the host The control circuit 210 sets the sub-device input ON edge information to 0 (step S305), and proceeds to step S306.

In step S306, the host control circuit 210 determines whether or not the previous subdevice input information is 1 and the current subdevice input information is 0. If the previous sub-device input information is 1 and the current sub-device input information is 0 (YES in step S306), the host control circuit 210 sets the sub-device input OFF edge information to 1 (step S307), and steps. Move on to S309. On the other hand, if the previous subdevice input information is 1 and the current subdevice input information is not 0 (that is, if the previous subdevice input information is 0 and / and the current subdevice input information is 1), the host The control circuit 210 sets the sub-device input OFF edge information to 0 (step S308), and proceeds to step S309.

In step S309, the host control circuit 210 performs subdevice input ON edge information (with repeat function) processing. Details of this sub-device input ON edge information (with repeat function) processing will be described later.

When the sub-device input ON edge information (with repeat function) processing in step S309 is completed, the host control circuit 210 sets the input information of the current sub-device to the previous sub-device input information (step S310), and inputs the sub-device. End the process.

Next, the sub-device input ON edge information (with repeat function) processing will be described with reference to FIGS. 40 and 41.

As shown in FIG. 40, in the sub-device input ON edge information (with repeat function) processing, the host control circuit 210 first determines whether or not the previous sub-device input information is 0 (step S321). .. If the previous sub-device input information is 0 (YES in step S321), the process proceeds to step S322.

In step S322, the host control circuit 210 determines whether or not the sub-device input information this time is 1. If the current sub-device input information is 1 (YES in step S322), that is, if the previous sub-device input information is 0 and the current sub-device input information is 1, the process proceeds to step S323. On the other hand, if the current sub-device input information is not 1 (NO in step S322), that is, if the previous sub-device input information is 0 and the current sub-device input information is 0, the sub-device input is ON. Ends edge information (with repeat function) processing.

Next, the host control circuit 210 sets the sub-device input ON edge information (with repeat function) to 1 (step S323), sets 10 frames as elapsed frames (step S324), and sets the sub-device input ON edge information (step S324). (With repeat function) Ends the process.

If the previous sub-device input information is 1 in step S321 (NO in step S321), the host control circuit 210 moves to step S325 in FIG. 41.

With reference to FIG. 41, the host control circuit 210 determines in step S325 whether or not the sub-device input information this time is 1. If the current sub-device input information is 1 (YES in step S325), that is, if the previous sub-device input information is 1 and the current sub-device input information is 1, subtract 1 from the elapsed frame. (Step S326), the process proceeds to step S327.

In step S327, the host control circuit 210 determines whether or not the elapsed frame is 0. If the elapsed frame is 0 (YES in step S327), the sub-device input ON edge information (with repeat function) is set to 1 (step S328), and the elapsed frame is set to 4 (step S329), and the sub-device is set. Input ON Edge information (with repeat function) processing ends.

In step S325, if the current subdevice input information is not 1 (NO in step S325), that is, if the previous subdevice input information is 1 and the current subdevice input information is 0, the host control The circuit 210 sets the elapsed frame to 0 (step S330) and proceeds to step S331.

When the sub-device input ON edge information (with repeat function) is set to 0 in step S331, the host control circuit 210 ends the sub-device input ON edge information (with repeat function) processing.

In this way, the host control circuit 210 creates the above-mentioned four types of sub-device input discrimination information in the main process every 33.3 msec based on the input state of the sub-device detected by the timer interrupt every 1 msec. By controlling the sub-devices based on these four types of sub-device input discrimination information, it is possible to easily control the sub-device's repeated hitting effect, long-press effect control, time setting control, and other operation control. It becomes possible.

[Backlight control processing]
Next, the backlight control process (for example, the backlight control process for controlling the backlight of a liquid crystal display or the like) will be described with reference to FIGS. 42 and 43. FIG. 42 is a diagram showing an example for conceptually explaining the backlight control process. FIG. 43 is a flowchart showing an example of the backlight control process.

The backlight control process of the present embodiment uses the function of SPI asynchronous data write (SPI + DMA) to continuously and continuously from the serial output terminal of, for example, the Serial Peripheral Interface (hereinafter referred to as "SPI"). A signal equivalent to pulse width modulation (hereinafter referred to as "PWM") is output so that the duty (brightness) can be changed. This makes it possible to perform backlight control without using a driver for backlight control.

In the present embodiment, for example, the frequency of the SPI clock is 100 kHz, the SPI1 clock is 0.01 msec, the time required for data transmission of 16 bits (1 data of the brightness data is 16 bits) is 0.16 msec, and the host control circuit 210 is scheduled. The interrupt is 1 msec, and the number of brightness data transmitted from the SPI between the scheduled interrupts of the host control circuit 210 is 100 bits. Therefore, the number of luminance data transmitted between the scheduled interrupts of the host control circuit 210 is 6.25 (100/16) (see FIG. 42). Therefore, for example, the number of scheduled interrupts executed until 32 luminance data are replenished in the FIFO (First In First Out) data area where 64 16-bit luminance data can be set (stored) is 5 to 6 times. it is conceivable that. The number of times varies depending on the time of the scheduled interrupt of the host control circuit 210.

For example, if the number of brightness data set (stored) in the FIFO (First In First Out) data area that can set (store) 64 16-bit brightness data is less than 32, the callback function is called, so the FIFO data. The area is not always filled. Therefore, if the process of setting (storing) the luminance data in the FIFO data area does not take time in other processes in the main process executed in the cycle of 33.3 msec, the FIFO data area becomes empty. (The backlight goes black).

Therefore, in the present embodiment, after the power is turned on, first 64 pieces of 1 data 16 bit brightness data are set to fill the FIFA data area, and then 32 pieces of brightness data set in the FIFA data area are set. When the value falls below, the callback function is called, and 32 data are set in the callback function so that the FIFA data area is not emptied.

As shown in FIG. 43, in the backlight control process, the host control circuit 210 first determines whether or not the process is the process at the time of initial setting (step S341). When the host control circuit 210 determines that the process is the process at the time of initial setting (that is, one process in step 201 of FIG. 36) (YES in step S341), 64 luminance data having a luminance of 0 are stored in the data area of the FIFO. It is set (step S342), and the process proceeds to step S343. On the other hand, if it is determined that the process is not the process at the time of initial setting (that is, the process of step S253 in FIG. 37) (NO in step S341), the process of step S342 is skipped and the process proceeds to step S343.

The host control circuit 210 determines in step S343 whether or not the luminance value has been changed. When the host control circuit 210 determines that the luminance value has been changed (YES in step S343), the luminance data set in the FIFO data area is changed (step S344), and the process proceeds to step S345. On the other hand, if it is determined that the luminance value has not been changed (NO in step S343), the process of step S344 is skipped and the process proceeds to step S345.

In step S345, the host control circuit 210 determines whether or not the number of brightness data set in the FIFO data area is less than 32, and the number of brightness data set in the FIFO data area is 32. If the number is less than (YES in step S345), 32 brightness data are set in the FIFO data area, that is, replenished (step S346), and the backlight control process is terminated. On the other hand, if the number of luminance data set in the FIFO data area is more than 32 (NO in step S345), the host control circuit 210 ends the backlight processing.

In this way, by processing the brightness data set in the FIFO data area so that it does not become empty, it is possible to continuously and continuously output a signal equivalent to PWM from the serial data output terminal of the SPI, and back up. Backlight control can be performed without going through a light control driver.

The processing of steps S343 to S346 of the backlight control processing of the present embodiment can be replaced as follows. That is, after setting 64 pieces of data having a brightness of 0 (see step S342), a process of determining whether or not the number of brightness data set in the data area of the FIFO is less than 32 pieces is performed. After that, it is determined whether or not the brightness value has been changed, and when it is determined that the brightness value has been changed, 32 pieces of brightness data according to the setting are set in the FIFA data area, and when it is determined that the brightness value has not been changed, the previous time. 32 pieces of the same luminance data as are set in the FIFA data area. In this way, the luminance data may be set in the FIFO data area and the backlight control process may be terminated.

Further, in the present embodiment, when the number of brightness data set in the FIFA data area is less than 32 (half the number of data that can be set in the FIFA), 32 pieces of brightness data are replenished. The timing of replenishing the data and the number of brightness data to be replenished are not limited to this, and when the brightness data set in the FIFA data area falls below a predetermined number, the predetermined number of brightness data may be replenished. Further, the brightness data to be replenished in the FIFA data area does not have to be the above-mentioned predetermined number. For example, when the brightness data set in the FIFA data area is less than the first number, the number of the second number is increased. The brightness data may be supplemented. However, from the viewpoint of preventing the brightness data set in the FIFA data area from being set too frequently and the brightness data set in the FIFA data area not being emptied, the above-mentioned predetermined number or the first one. The number is preferably about half the number of brightness data that can be set in the FIFA data area, but is not limited to this as described above. The above "about half" is sufficient as long as the frequency of setting the brightness data in the FIFO data area does not become too high and the brightness data set in the FIFO data area is not emptied. There are various judgment methods such as less than half or less than half depending on the consumption speed of the brightness data set in the data area of. For example, since the FIFA data area in the present embodiment can set up to 64 16-bit brightness data, one or more new ones or more when the number of brightness data set in the FIFA data area is 1 to 64. It is possible to set the brightness data, but from the viewpoint of preventing the backlight from becoming dark (the brightness data set in the FIFA data area becomes 0), the FIFO data. When the number of brightness data set in the region is two or more, it is preferable to newly set one or more brightness data. Further, the number of luminance data that can be set in the FIFO data area is not limited to 64, and it is sufficient that at least two or more luminance data can be set. When the number of brightness data set in the FIFA data area is, for example, two or more, and the number of brightness data set in the FIFA data area is less than the first number (for example, two), the second number is obtained. The brightness data (for example, one) may be supplemented.

[Modification example of backlight control processing]
Next, a modification of the backlight control process will be described with reference to FIGS. 44 and 45. FIG. 44 is a flowchart showing an example of timer interrupt processing accompanying a modified example of backlight control processing. FIG. 45 is a flowchart showing a modified example of the backlight control process.

In a modified example of the backlight control processing, when the processing may take a long time in the timer interrupt processing of 1 msec, whether or not a predetermined time or more has passed since the data was set in the data area of the FIFO in the backlight control processing. It is determined whether or not the data is set in the data area of the FIFO when a predetermined time or more has elapsed.

In the timer interrupt process of FIG. 44, the host control circuit 210 first performs the backlight control process (step S351). Hereinafter, for convenience of explanation, the backlight control process in step S351 will be described with reference to FIG. 45 before the processes after step S352 are described.

As shown in FIG. 45, in the backlight control process, the host control circuit 210 first determines whether or not the process is the process at the time of initial setting (step S361). When the host control circuit 210 determines that the process is the process at the time of initial setting (that is, one process in step 201 of FIG. 36) (YES in step S361), 64 luminance data having a luminance of 0 are stored in the data area of the FIFO. It is set (step S362), and then the process proceeds to step S366. On the other hand, if it is determined that the process is not the process at the time of initial setting (that is, the process of step S351) (NO in step S361), the process proceeds to step S363.

In step S363, the host control circuit 210 determines whether or not the number of brightness data set in the FIFA data area is less than 32, and the number of brightness data set in the FIFA data area is 32. If the number is less than (YES in step S363), 32 brightness data are set or replenished in the FIFA data area (step S364), and the process proceeds to step S365. On the other hand, if the number of luminance data set in the FIFO data area is more than 32 (NO in step S363), the process proceeds to step S366. As described above, the above 32 pieces are half of the number of data that can be set in the FIFO.

In step S365, the host control circuit 210 resets the elapsed time (step S365) and starts timing the elapsed time (step S366). When the time counting of the elapsed time is started in step S366, the host control circuit 210 ends the backlight control process.

Returning to FIG. 44, the host control circuit 210 controls the accessory motor after completing the backlight control process in step S351 (step S352).

In this modification, whether or not the elapsed time at which the time counting is started in step S366 has elapsed more than a predetermined time after the host control circuit 210 has performed a process such as the accessory motor control which may take a long time. (Step S353). If a predetermined time or more has passed (YES in step S353), 32 luminance data are set in the FIFO data area (step S354). On the other hand, if the predetermined time or more has not passed (NO in step S353), it is not necessary to replenish the luminance data in the FIFO data area, so the process proceeds to step S357.

As described above, since the time required for 16-bit (1 piece of luminance data is 16 bits) data transmission in SPI is 0.16 msec, it is considered that 5.12 msec is required to transmit 32 luminance data. Be done. Therefore, in this modification, in step S353, it is determined whether or not 5.12 msec or more has elapsed as a predetermined time.

After performing the process of step S354, the host control circuit 210 resets the elapsed time (step S355) and restarts the time counting of the elapsed time (step S356). Then, when the time counting of the elapsed time is started in step S356, the host control circuit 210 performs the input state determination process (step S357) and ends the timer interrupt process.

In this way, when the brightness data is set in the FIFA data area, the time counting is started, and after the processing that may take time, the brightness data is replenished if the above time counting time elapses for a predetermined time or more. By doing so, it is possible to prevent the brightness data in the FIFO data area from becoming empty.

In this modified example, an example in which the processes of steps S353 to S357 are performed after the accessory motor control (step S352) has been described, but this is merely an example. That is, from the viewpoint of preventing the luminance data set in the FIFO data area from becoming empty, if the processing of steps S353 to S357 is performed after the processing that may take time. Often, such processing is not limited to a particular processing.

[Brightness adjustment of backlight and various LEDs]
Next, variations in brightness adjustment of the backlight and various LEDs will be described. The various LEDs correspond to board-side LEDs (for example, LEDs arranged on the game board 12), frame-side LEDs, and the like, and in the present specification, lamp groups 18 and the like including LEDs (for example, see FIG. 5) correspond to these. .. Further, in the present specification, as variations of brightness adjustment of the backlight and various LEDs, three variations of the first embodiment to the third embodiment will be described with reference to FIGS. 46 to 49, respectively. FIG. 46 is a flowchart showing an example of timer interrupt processing showing backlight control processing. FIG. 47 is a sub-control main process (overall flow) executed by the host control circuit 210 for explaining the first embodiment of the process of adjusting the brightness of the backlight and various LEDs. FIG. 48 is a sub-control main process (overall flow) executed by the host control circuit 210 for explaining a second embodiment of the process of adjusting the brightness of the backlight and various LEDs. FIG. 49 is a sub-control main process (overall flow) executed by the host control circuit 210 for explaining a third embodiment of the process of adjusting the brightness of the backlight and various LEDs. However, FIGS. 47 to 49 show only the processes necessary for the explanation, and omit the other processes. In the first to third embodiments described below, as described above, the host control circuit 210 will be placed in the FIFO data area when the luminance data set in the FIFO data area is reduced to about half. Replenish the brightness data.

The timing of replenishing the luminance data in the FIFO data area is not limited to the time when the luminance data set in the FIFO data area is reduced to about half. In the FIFA data area of the present embodiment, for example, up to 64 16-bit luminance data can be set. Therefore, when the luminance data set in the FIFO data area is 1 to 64, one or more new luminance data can be set. Brightness data may be set. However, from the viewpoint of preventing the backlight from becoming dark (the luminance data set in the FIFO data area becomes 0), the luminance data set in the FIFO data area is 2. When there are more than one, it is preferable to newly set one or more luminance data. Further, the number of luminance data that can be set in the FIFO data area is not limited to 64, and it is sufficient that at least two or more luminance data can be set. When the number of brightness data set in the FIFA data area is, for example, two or more, and the number of brightness data set in the FIFA data area is less than the first number (for example, two), the second number is obtained. The brightness data (for example, one) may be supplemented.

(First Example)
For example, when the brightness of the backlight (for example, the backlight of a liquid crystal display or the like) is adjusted by the operation of a player or the like, the brightness of the backlight is changed. At this time, the control of the panel side LED and the frame side LED is performed. May affect. In this embodiment, in such a case, the brightness setting of the backlight and the brightness setting of the panel side LED and the frame side LED are set in common, and the backlight, the panel side LED, and the frame side LED are set according to the setting. It is designed to control. As a result, even if the update timing of the backlight control and the update timing of the control of the panel side LED and the frame side LED are different, it is possible to facilitate the processing.

In the timer interrupt process of FIG. 46, the host control circuit 210 performs the accessory motor control (step S371), the input state determination process (step S372), and the backlight control process (step S373) in this order.

As shown in FIG. 47, the host control circuit 210 performs the initialization process (step S381), then moves to the main loop and performs the LED request control process (step S382). The LED request made in step S382 was created in the animation construction process one frame before (step S386 described later).

When the process of step S382 is performed, the host control circuit 210 performs the above-mentioned subdevice (button) input determination information generation process (step S383) based on the input state of the subdevice, and proceeds to step S384.

In step S384, the host control circuit 210 determines the brightness of the backlight based on the input state of the sub-device (for example, the player or the like operates the brightness setting screen displayed on the liquid crystal display device used as the display device 13). To set. The brightness of the backlight is set in three stages, for example, strong, medium, and weak.

When the process of step S384 is performed, the host control circuit 210 shifts to the packet reception loop, and first, the brightness values of the panel side LED and the frame side LED are set according to the effect mode to be executed and the setting of the brightness value. (Step S385). Similar to the backlight, the brightness of the panel-side LED and the frame-side LED is also set to, for example, three levels of strong, medium, and weak.

Here, by setting the brightness of the panel side LED and the frame side LED and the setting of the brightness of the backlight as a common setting, the brightness of the panel side LED and the frame side LED can be suppressed while suppressing the increase in the control load. Both the setting and the brightness setting of the backlight can be changed by the operation of the player or the like. For example, the host control circuit 210 changes the brightness value of the backlight based on the player or the like operating the brightness setting screen displayed on the liquid crystal display device used as the display device 13 (step S384). The brightness values of the panel side LED and the frame side LED are also changed (step S385). At this time, the stage of the brightness value of the backlight and the stage of the brightness value of the panel side LED and the frame side LED are also common. For example, if the stage of the brightness value of the backlight is medium, the stage of the brightness value of the panel side LED and the frame side LED is also in the middle. As shown in FIG. 47, since the brightness update timing of the backlight and the brightness update timing of the panel side LED and the frame side LED are different, after the brightness of the backlight is updated, the panel side LED and the frame side LED The brightness of is updated. However, the brightness update timing of the backlight and the brightness update timing of the panel side LED and the frame side LED may be controlled to be the same.

The brightness of the backlight and the brightness of the panel side LED and the frame side LED are changed based on the player or the like operating the brightness setting screen displayed on the liquid crystal display device used as the display device 13. However, the present invention is not limited to this, and for example, the brightness of the backlight, the brightness of the panel side LED and the brightness of the frame side LED may be changed based on the operation of the push button for the effect. In this case, since it is necessary to determine whether or not it is a period (push button valid period) that functions as a push button for production, the brightness of the board side LED and the frame side LED is adjusted in the main flow. It is necessary to control the backlight according to the brightness of the LED.

The host control circuit 210 performs the animation construction process in step S386. In the animation construction process of step S386, an LED request is created. The created LED request is waited in the buffer and then output in the LED request control process (see step S382) of the next frame.

The host control circuit 210 repeats the processes of steps S385 and S386 according to the received packets.

When the host control circuit 210 exits the packet reception loop, the animation update process is performed (step S387), and then the bank flip / bank flip end wait is performed (step S388).

The host control circuit 210 repeats each process of steps S382 to S388 in the main loop at a cycle of 33.3 msec.

(Second Example)
For example, when the brightness adjustment operation is performed by a player or the like, the control of the board side LED and the frame side LED may be affected as described above. In this embodiment, in such a case, for example, when a player or the like performs a brightness adjustment operation, the brightness value of the backlight is changed immediately, but the control of the board side LED and the frame side LED is a special symbol. It is designed to be executed after the end of the fluctuation or between bank flips.

As described above, the host control circuit 210 performs the accessory motor control (step S371), the input state determination process (step S372), and the backlight control process (step S373) in this order in the timer interrupt process of FIG. 46. Do.

As shown in FIG. 48, the host control circuit 210 performs the initialization process (step S391), then moves to the main loop and performs the LED request control process (step S392). The LED request made in step S392 was created in the animation construction process one frame before (step S395 described later).

When the process of step S392 is performed, the host control circuit 210 generates the above-mentioned sub-device (button) input discrimination information (step S393) based on the input state of the sub-device (for example, the brightness adjustment operation by the player or the like). ), And the process proceeds to step S394.

In step S394, the host control circuit 210 sets the brightness of the backlight based on the input state of the sub-device (for example, a brightness adjustment operation by a player or the like). The brightness of the backlight is set in three stages, for example, strong, medium, and weak.

When the process of step S394 is performed, the host control circuit 210 shifts to the packet reception loop and performs the animation construction process (step S395). In the animation construction process of step S395, an LED request is created. The created LED request is waited in the buffer and then output in the LED request control process (see step S392) of the next frame.

The host control circuit 210 repeats the process of step S395 according to the received packet.

When the host control circuit 210 exits the packet reception loop, it performs animation update processing (step S396), then waits for bank flip / bank flip end (step S397), and proceeds to step S398.

In step S398, the host control circuit 210 determines whether or not the variation of the effect identification displayed on the liquid crystal display device as the display device 13 has been completed, that is, whether or not the variation time of the effect identification symbol has elapsed. (Step S398). If the variation of the effect identification symbol is completed (YES in step S398), the host control circuit 210 changes the brightness of the panel side LED and the frame side LED according to the set value at that time (step S399). On the other hand, if the variation of the special symbol is not completed (NO in step S398), the processes of steps S392 to S399 in the main loop having a cycle of 33.3 msec are repeated. The process of step S399 may be performed during the bank flip of step S397 instead of or in addition to when the change of the special symbol is completed.

As described above, in the second embodiment, the host control circuit 210 determines the brightness of the backlight that directly affects the eyes of the player based on the input state of the sub-device (for example, the brightness adjustment operation by the player or the like). Is controlled so as to be changed immediately, but the brightness of the panel side LED and the frame side LED is changed after the brightness of the backlight is changed and after the variation of the effect identification symbol is completed. To control. Further, when the brightness adjustment operation is performed by a player or the like while the identification symbol for production is fluctuating, the brightness of the panel side LED and the frame side LED needs to be changed by the LED request control process, but the backlight Can be changed immediately. Therefore, the brightness of the backlight is controlled to be changed immediately based on the input state of the sub-device, but the brightness of the panel side LED and the frame side LED is changed by the LED request control process to control the load. Can be minimized. That is, for example, it is possible to change the brightness of the backlight and the brightness of the panel side LED and the frame side LED while minimizing the control load by performing the brightness adjustment operation by a player or the like only once.

When the brightness of the backlight is changed based on the input state of the sub-device (for example, the brightness adjustment operation by a player or the like), the host control circuit 210 transmits the brightness data related to the changed brightness to the FIFO. Set in the data area.

(Third Example)
For example, when the brightness adjustment operation is performed by a player or the like, the control of the board side LED and the frame side LED may be affected as described above. In this embodiment, in such a case, for example, when a player or the like performs a brightness adjustment operation, the brightness value of the backlight is changed, and the effect of the panel side LED and the frame side LED is limited. This is what I did. The term "limited" means, for example, limiting the number of LEDs that emit light in the effect of the board-side LED and the frame-side LED, limiting the number of effects performed by the board-side LED and the frame-side LED, and the like. .. Limiting the number of effects means, for example, that the effects 1 to 5 are originally performed, but only the effects 1 to 3 are performed, and the effects 4 and 5 are not omitted. As a result, the effects of the board-side LED and the frame-side LED are restricted without directly changing the brightness value, so that the intensity of the light received by the player from the board-side LED and the frame-side LED is suppressed. Become. Further, even if the update timing of the backlight control and the update timing of the control of the panel side LED and the frame side LED are different, the processing can be facilitated.

As described above, the host control circuit 210 performs the accessory motor control (step S371), the input state determination process (step S372), and the backlight control process (step S373) in this order in the timer interrupt process of FIG. 46. Do.

As shown in FIG. 49, the host control circuit 210 performs the initialization process (step S401), then moves to the main loop and performs the LED request control process (step S402). The LED request made in step S402 was created in the animation construction process one frame before (step S407 described later).

When the process of step S402 is performed, the host control circuit 210 performs the above-mentioned subdevice (button) input determination information generation process (step S403) based on the input state of the subdevice, and proceeds to step S404.

In step S404, the host control circuit 210 sets the brightness of the backlight based on the input state of the sub-device (for example, a brightness adjustment operation by a player or the like). The brightness of the backlight is set in three stages, for example, strong, medium, and weak.

When the process of step S404 is performed, the host control circuit 210 determines whether or not the brightness setting has been changed (step S405). If there is a change in the luminance setting (YES in step S405), the host control circuit 210 limits the luminance of the panel side LED and the frame side LED according to the setting at that time (step S406), and moves to the packet reception loop. On the other hand, if there is no change in the luminance value setting (NO in step S405), the host control circuit 210 shifts to the packet reception loop without performing the process of step S406.

Moving to the packet reception loop, the host control circuit 210 performs an animation construction process (step S407). In the animation construction process of step S407, an LED request is created. The created LED request is waited in the buffer and then output in the LED request control process (see step S402) of the next frame.

The host control circuit 210 repeats the process of step S407 according to the received packet.

When the host control circuit 210 exits the packet reception loop, it performs animation update processing (step S408), and then waits for bank flip / bank flip end (step S409).

The host control circuit 210 repeats the processes of steps S402 to S409 in the main loop having a period of 33.3 msec.

Regarding the brightness adjustment of the backlight and various LEDs described above (first to third embodiments), the backlight control process of the present embodiment uses the function of the SPI asynchronous data light (SPI + DMA) as described above. For example, a signal corresponding to PWM is continuously and continuously output from the serial output terminal of SPI. On the other hand, with respect to the panel side LED and the frame side LED, for example, as shown in step S382 of FIG. 47, the LEDs are controlled based on the LED request created one frame before the main loop. Therefore, even if the brightness of the backlight and various LEDs is adjusted, the timing at which the brightness of the backlight is changed is different from the timing at which the brightness of the panel-side LED or the frame-side LED is changed.

[RTC acquisition process]
Next, the RTC acquisition process will be described with reference to FIG. As described above, the RTC acquisition process is performed both in the various initialization processes (see step S201 in FIG. 36) and in the main loop (see step S201 in FIG. 36). Note that FIG. 50 is a flowchart showing an example of the RTC acquisition process.

For example, when communication with the RTC cannot be performed, or when an abnormality has occurred in the RTC itself, or when an accurate time cannot be obtained due to the RTC abnormality, the time is not updated and remains at the previous time. Therefore, when the RTC effect (for example, an effect related to Christmas at Christmas time) is executed based on the RTC time, if an RTC abnormality occurs, the RTC effect may not be executed. Further, when the RTC or more occurs, the RTC time is not updated, so that the RTC effect may remain executed or the RTC effect may be executed at an unexpected time.

Therefore, in the RTC acquisition process of the present embodiment, when the RTC is abnormal, that is, when the previous RTC time and the current RTC time are different, the RTC effect is executed based on the current time. The RTC is provided with a secondary battery so that the time can be managed even when the power of the host control circuit 210 is turned off. Further, the host control circuit 210 acquires the time from the RTC and manages the error occurrence time and the like.

As shown in FIG. 50, in the RTC acquisition process, the host control circuit 210 first acquires the RTC time (step S412), and then proceeds to step S413.

The host control circuit 210 updates the previous time in step S413. In this update of the previous time, the current time updated in step S416 described later is updated as the previous time. After that, the host control circuit 210 determines whether or not the RTC is abnormal (step S414). If the RTC is abnormal (YES in step S414), the current time is maintained (step S415), and the process proceeds to step S417. On the other hand, if the RTC is not abnormal (NO in step S414), the current time is updated (step S416), and the process proceeds to step S417.

In the RTC acquisition process of the present embodiment, after updating the previous time (step S413), it is determined whether or not the RTC is abnormal (step S414), but instead of this, the previous time is updated. It may be determined before whether or not the RTC is abnormal, and if the RTC is not abnormal, the previous time may be updated to control so that the current time is not maintained.

In step S417, the host control circuit 210 determines whether or not the current time is a designated time (for example, a time when the RTC effect is executed). If the current time is the designated time (YES in step S417), the process proceeds to step S418, and if the current time is not the designated time (NO in step S417), the process proceeds to step S420.

In step S418, the host control circuit 210 determines whether or not the previous time and the current time do not match. If the RTC is abnormal, the previous time and the current time do not match (YES in step S418). If the previous time and the current time do not match (YES in step S418), the RTC effect execution flag is set to 1 (step S419). That is, in the case of an RTC abnormality, the RTC effect is executed when the current time reaches the designated time. Then, when the process of step S419 is performed, the host control circuit 210 ends the RTC acquisition process. On the other hand, if the previous time and the current time do not match (NO in step S418), the process proceeds to step S420.

The host control circuit 210 sets the RTC effect execution flag to 0 in step S420. Then, when the process of step S420 is performed, the host control circuit 210 ends the RTC acquisition process.

As described above, in the present embodiment, even if the RTC is abnormal, it is possible to avoid a situation in which the RTC effect is not executed by executing the RTC effect when the current time reaches the designated time. ..

[Composition playback control]
Next, composition reproduction control will be described with reference to FIGS. 51 and 52.

The composition is scene data in which material data for forming an image (movie) displayed on a liquid crystal display device used as, for example, a display device 13 is combined, and is generally composed of a plurality of layers. Layers include animations, vector graphics, still images, lights, and more.

FIG. 51 is a flowchart showing an example of the animation control main process executed by the display control circuit 230. As shown in FIG. 51, the display control circuit 230 first clears the composition reproduction information (step S431). Then, the display control circuit 230 executes the composition reproduction control process (step S432). This composition reproduction control process will be described later. After that, the display control circuit 230 executes the top-level direct drawing function (step S433), and ends the animation control main process.

FIG. 52 is a flowchart showing an example of the composition reproduction control process executed by the display control circuit 230. As shown in FIG. 52, the display control circuit 230 first determines whether or not the determined number of priorities is less than (or less than or equal to) the upper limit of the number of priorities (step S441). If the determined number of priorities is less than (or less than or equal to) the upper limit of the number of priorities (YES in step S441), the process proceeds to step S442. The number of priorities is the number of layers of the composition to be played back at the same time, and the upper limit of the number of priorities is predetermined based on the composition to be played back. Therefore, as long as the processing by the host control circuit 210 is normal, the determined number of priorities does not exceed the upper limit of the number of priorities. Therefore, when the determined priority number exceeds the upper limit of the priority number (NO in step S441), the display control circuit 230 ends the composition reproduction control process.

In step S442, the display control circuit 230 determines whether or not the determined number of displays is less than (or less than or equal to) the number of usable displays, that is, the determined number of displays is a display that can be used (for example, mounted) on the system. It is determined whether or not the number is less than (or less than or equal to) the number (step S442). If the determined number of displays is less than (or less than or equal to) the number of usable displays (YES in step S442), the process proceeds to step S443.

In step S443, the display control circuit 230 determines whether or not the used display number is not 0, that is, whether or not there is a usable display number. If the display number used is not 0 (YES in step S443), that is, if a usable display number exists, the display control circuit 230 moves to step S444. On the other hand, if the display number used is 0 (NO in step S443), that is, if there is no usable display number, the display control circuit 230 moves to step S459.

By the way, the pachinko gaming machine 1 of the present embodiment includes two frame buffers as frame buffers in which the composition is registered. These two frame buffers are used by switching the function of one frame buffer from the drawing function to the display function and switching the function of the other frame buffer from the display function to the drawing function by bank flip. Hereinafter, in this specification, a frame buffer having a display function is simply referred to as a “frame buffer”, and a frame buffer having a drawing function is referred to as a “drawing result output destination buffer”.

In step S444, the display control circuit 230 determines whether or not the composition is registered in the drawing result output destination buffer. In the determination process of step S444, it is determined whether or not all the compositions are registered (that is, whether or not there are any unregistered ones). If all the compositions are registered in the drawing result output destination buffer (YES in step S444), the display control circuit 230 sets the drawing target (step S445). Setting a drawing target is a process of setting a display to which drawing is performed. If the composition is not registered in the drawing result output destination buffer (NO in step S444), that is, if there is an unregistered composition, the display control circuit 230 moves to step S450.

In step S446, the display control circuit 230 sets the drawing result output destination buffer as the frame buffer. That is, the process of step S446 is a process of switching the drawing result output destination buffer to the frame buffer by bank flip. At this time, the composition registered in the drawing result output destination buffer switched from the frame buffer is cleared. After that, the display control circuit 230 determines whether or not the composition registered in the frame buffer switched from the drawing output destination buffer by the bank flip in step S446 has a pause flag (step S447). The pause flag is a flag of the debug function that pauses the image, and when this pause flag is present (YES in step S447), the display control circuit 230 is the drawing output destination buffer switched from the frame buffer by the bank flip in step S446. The composition reproduction information is registered in (step S448) and the composition is reproduced (step S449). On the other hand, if there is no pause flag (NO in step S447), the process proceeds to step S459. The composition reproduction information includes, for example, the frame buffer size, the composition size, the coordinates of the four vertices of the image to be reproduced, the composition registration information, the loop composition to be reproduced, the composition length, and the start frame setting. , Loop playback flag, etc. Further, the registration of the reproduction information of the composition is to collect the reproduction information of the composition, and the composition reproduction is to register the reproduction information of the collected composition. When the playback information of the composition is registered, the previous playback information is cleared.

In step S450, the display control circuit 230 determines whether or not the number of frames reproduced in the drawing result output destination buffer is equal to or greater than the upper limit (that is, whether or not the number of reproduced frames exceeds the number of frames possessed by the composition). Determine. If the number of frames reproduced in the drawing result output destination buffer is not equal to or greater than the upper limit (NO in step S450), the display control circuit 230 proceeds to step S457 and registers the composition reproduction information in the drawing result output destination buffer (step). The composition is regenerated together with S457) (step S458).

When the display control circuit 230 determines in step S450 that the number of frames reproduced in the drawing result output destination buffer is equal to or greater than the upper limit (YES in step S450), the display control circuit 230 proceeds to step S451.

In step S451, the display control circuit 230 determines whether or not the reproduction mode of the composition registered in the frame buffer is loop reproduction. If the reproduction mode of the composition registered in the frame buffer is loop reproduction (YES in step S451), the display control circuit 230 reproduces from the beginning at the time of loop reproduction (step S452), and then proceeds to step S457. .. If the reproduction mode of the composition registered in the frame buffer is not loop reproduction (NO in step S451), the display control circuit 230 shifts to step S453.

In step S453, the display control circuit 230 determines whether or not the reproduction mode of the composition registered in the frame buffer is frame continuous display. If the reproduction mode of the composition registered in the frame buffer is frame continuous display (YES in step S453), the display control circuit 230 reproduces the final frame at the time of frame continuous display (step S454), and then steps S457. Move to. If the reproduction mode of the composition registered in the frame buffer is not frame continuous display (NO in step S453), the display control circuit 230 shifts to step S455.

In step S455, the display control circuit 230 determines whether or not the reproduction mode of the composition registered in the frame buffer is shot reproduction. If the reproduction mode is shot reproduction (YES in step S455), the display control circuit 230 clears the composition at the time of shot reproduction (step S456), and then proceeds to step S459. If the reproduction mode of the composition registered in the frame buffer is not shot reproduction (NO in step S455), the display control circuit 230 shifts to step S457.

The composition reproduction information registration in step S457 is, in principle, a process performed when the composition is not registered in the drawing result output destination buffer (when NO is determined in step S444). However, as described above, the display control circuit 230 also has a pause flag in the frame buffer switched from the drawing output destination buffer in the bank flip in step S446 (YES in step S447), and the frame is framed in the bank flip in step S446. The composition reproduction information is registered in the drawing output destination buffer switched from the buffer (step S448), and the composition is reproduced (step S449). As described above, when the frame buffer switched from the drawing output destination buffer in the bank flip in step S446 has a pause flag (YES in step S447), the composition reproduction information is immediately registered in the drawing output destination buffer (YES in step S447). Since the composition is regenerated together with step S448) (step S449), quick processing can be performed.

The display control circuit 230 adds 1 to the number of displays determined in step S459, and returns to step S442.

When the display control circuit 230 determines in step S442 that the number of determined displays exceeds the upper limit of the number of usable displays (NO in step S442), the display control circuit 230 executes the direct drawing function if there is data to be directly drawn. (Step S460). After that, the display control circuit 230 adds 1 to the determined priority number (step S461), and returns to step S441.

As described above, in the composition reproduction control of the present embodiment, in principle, the reproduction information of a new composition is not registered in the state where the composition is registered in the drawing output destination buffer. However, the composition is not registered only when the specific condition is satisfied (when YES is determined in step S447, that is, when the composition registered in the drawing output destination buffer has a pause flag). It becomes possible to perform the processing (composition reproduction information registration). In other words, while the composition is registered in the drawing output destination buffer, it is possible to register the composition again at any timing, so it depends on the contents of the (newly) registered composition. , It is possible to overwrite the effect, skip the effect, and stop the effect.

Further, the process of step S441 (the process of determining whether or not the determined number of priorities is less than (or less than or equal to) the upper limit of the number of priorities (whether the number of determined displays is less than (or less than or equal to) the number of usable displays). The process of determining whether or not the display is performed) is higher than the process of step S442. Therefore, by returning to step S442 from the process of step S459 and performing the process, the number of priorities determined in step S441 is displayed on a plurality of displays. On the other hand, it can be standardized and the processing load can be reduced.

[Sound amplifier check process]
Next, the sound amplifier check process shown in FIG. 37 will be described with reference to FIGS. 53 to 55. In this sound amplifier check process, it is determined whether or not the digital audio power amplifier 262 (hereinafter referred to as "sound amplifier") is in an abnormal state (for example, overcurrent abnormality, high temperature abnormality, DC detection abnormality in which the audio signal does not change, etc.). Also, the setting information of the sound amplifier is confirmed. FIG. 53 is a flowchart showing an example of the sound amplifier check process. FIG. 54 is a flowchart showing an example of a normal amplifier check process. FIG. 55 is a flowchart showing an example of a deep bass amplifier check process.

The pachinko gaming machine 1 of the present embodiment includes, as a sound amplifier, a normal amplifier that amplifies normal audio data and a deep bass amplifier that amplifies deep bass audio data.

As shown in FIG. 53, the host control circuit 210 performs a normal amplifier check process (step S471) and a deep bass amplifier check process (step S472).

As shown in FIG. 54, in the normal amplifier check process, the host control circuit 210 first determines whether or not the setting has been made from the binary file (step S481). If there is a binary file at the time of initialization, the settings will be made from the binary file. The initialization process is executed not only when the power is turned on, but also when a problem is found in the amplifier check and the settings are reset. Further, in the present embodiment, the setting is made from the binary file, but the setting is not limited to this, and a storage area different from the read setting such as the binary file may be used.

When the host control circuit 210 determines that the setting has been made from the binary file (YES in step S481), the host control circuit 210 performs a determination process of determining whether or not the register that is the reference of the register value to be checked is normal (step S482), and then performs a determination process. , Step S483. In the determination process of step S482, the register values are checked in the order of the address, so it is determined whether or not there is a register value for starting the check, and whether or not the value is normal.

In step S483, the host control circuit 210 sorts the received data from the binary file. After that, the host control circuit 210 compares the value of the RAM of the register with the received data (step S484), and performs a determination process of determining whether or not the value of the normal amplifier is normal (step S485). When the determination process of step S485 is performed, the host control circuit 210 ends the normal amplifier check process.

On the other hand, if the setting is not made from the binary file in step S481 (NO in step S481), the host control circuit 210 performs a process of comparing the default value with the set value (step S486), and performs a normal amplifier check process. To finish. When the normal amplifier check process is completed, the host control circuit 210 performs the deep bass amplifier check process.

As shown in FIG. 55, in the deep bass amplifier check process, the host control circuit 210 first determines whether or not the setting has been made from the binary file (step S491).

When the host control circuit 210 determines that the setting has been made from the binary file (YES in step S491), the host control circuit 210 performs a process of determining whether or not the register to be checked is normal (step S492), and then proceeds to step S493. ..

In step S493, the host control circuit 210 clears the registers 0x17-0x25 with an appropriate value (binary file information) in consideration of the case where the value cannot be read due to a hardware defect.

In step S494, the host control circuit 210 sorts the received data from the binary file. After that, the host control circuit 210 compares the value of the RAM of the register with the received data (step S495), and updates the RAM address (step S496). When the update process of step S496 is performed, the host control circuit 210 ends the deep bass amplifier check process.

On the other hand, if the setting is not made from the binary file in step S491 (NO in step S491), the host control circuit 210 performs a process of comparing the default value with the set value (step S497), and checks the amplifier for deep bass. End the process.

As described above, in the present embodiment, the host control circuit 210 performs the sound amplifier check process in the interrupt process of 1 msec. By the way, such a sound amplifier check process can also be performed in the main loop. However, when the sound amplifier check process is performed in the main loop, if the sound amplifier check process takes time, it may put pressure on other processes. Therefore, by performing the sound amplifier check process in the interrupt process as in the present embodiment, it is possible to perform the sound amplifier check process without overwhelming other processes in the main loop.

Further, the sound amplifier check process shown in the timer interrupt process (see FIG. 37) is, for example, as shown in FIG. 56, in the 1 msec interrupt process, the normal amplifier / deep bass amplifier (batch) check process (step S497). ) May be performed. The normal amplifier / deep bass amplifier (collective) check process (step S497) is a process of collectively performing the normal amplifier check process (see FIG. 54) and the deep bass amplifier check process (see FIG. 55).

However, if the sound amplifier check process is performed in the interrupt process of 1 msec, it may not be possible to execute all of the sound amplifier check process. Therefore, a more preferable embodiment of the sound amplifier check process will be described with reference to FIGS. 57 to 59. FIG. 57 is a flowchart showing an example of a more preferable form of the sound amplifier check process. FIG. 58 is a flowchart showing an example of a more preferable form of the normal amplifier / deep bass amplifier check process. FIG. 59 shows an example of a more preferable form of the normal amplifier / deep bass amplifier check process, and is a flowchart continuing from FIG. 58.

In a more preferred embodiment of the sound amplifier check process, as shown in FIG. 57, the host control circuit 210 performs a normal amplifier / deep bass amplifier (division) check process (step S498). The details of the normal amplifier / deep bass amplifier (division) check processing will be described later, but the range that can be performed within 1 msec of the interrupt processing by dividing each check process of the normal amplifier and each check process of the deep bass amplifier. The check process is performed within, and the subsequent process is performed in the next and subsequent frames. In other words, out of all the check processing of the normal amplifier and all the check processing of the deep bass amplifier, only a part of the check processing is performed in the one interrupt processing, but all the checks should be performed over multiple interrupt processing. It is the one that was made. By doing so, in the interrupt processing, it is possible to execute all of the check processing of the normal amplifier and the check process of the deep bass amplifier without ending in the middle.

As shown in FIG. 58, in the normal amplifier / deep bass amplifier (division) check process, the host control circuit 210 first determines whether or not the setting has been made from the binary file (step S501).

When the host control circuit 210 determines that the setting has been made from the binary file (YES in step S501), the host control circuit 210 determines whether or not the check status is 0 (step S502). When the check status is 0 (YES in step S502), the host control circuit 210 performs a determination process of determining whether or not the register value checked by the normal amplifier is normal (step S503). After performing the process of step S503, the host control circuit 210 sets the check status to 1 (step S504), and ends the normal amplifier / deep bass amplifier (division) check process. If the host control circuit 210 determines in step S502 that the check status is not 0 (NO in step S502), the host control circuit 210 proceeds to step S505. The process of step S503 may be performed by further dividing each register into determining whether or not each register value among the plurality of registers is normal.

In step S505, the host control circuit 210 determines whether or not the check status is 1. When the check status is 1 (YES in step S505), the host control circuit 210 performs a sorting process of the received data from the binary file (step S506). After that, the host control circuit 210 compares the value of the RAM of the register of the normal amplifier with the received data (step S507), and determines whether or not the processing for the number of divisions of the normal amplifier has been executed (step S508). ). If the processing for the number of divisions of the normal amplifier is executed (YES in step S508), the host control circuit 210 sets the check status to 2 (step S509), and the normal amplifier / deep bass amplifier (division). ) End the check process. On the other hand, if the processing for the number of divisions of the normal amplifier is not executed (NO in step S508), the host control circuit 210 checks the normal amplifier / deep bass amplifier (division) without updating the check status. To finish. That is, since the check status is not updated and is maintained at 1, the host control circuit 210 performs the process when the check status is 1 again in the next and subsequent frames. If the host control circuit 210 determines in step S505 that the check status is not 1 (NO in step S505), the host control circuit 210 proceeds to step S510. The process of step S508 may be performed by further dividing the process of comparing the RAM value of each register among the plurality of registers with the received data for each register.

In step S510, the host control circuit 210 determines whether or not the check status is 2. When the check status is 2 (YES in step S510), the host control circuit 210 performs a determination process of whether or not the value of the normal amplifier is normal (step S511). After that, the host control circuit 210 determines whether or not the processing for the number of divisions of the normal amplifier has been executed (step S512). If the processing for the number of divisions of the normal amplifier is executed (YES in step S512), the host control circuit 210 sets the check status to 3 (step S513), and the normal amplifier / deep bass amplifier (division). ) End the check process. On the other hand, if the processing for the number of divisions of the normal amplifier is not executed (NO in step S512), the host control circuit 210 checks the normal amplifier / deep bass amplifier (division) without updating the check status. To finish. That is, since the check status is not updated and is maintained at 2, the host control circuit 210 performs the process when the check status is 2 again in the next and subsequent frames. When the host control circuit 210 determines in step S510 that the check status is not 2 (NO in step S510), the host control circuit 210 moves to step S514 (see FIG. 59).

With reference to FIG. 59, the host control circuit 210 determines in step S514 whether or not the check status is 3. When the check status is 3 (YES in step S514), the host control circuit 210 performs a determination process of determining whether or not the register value checked by the deep bass amplifier is normal (step S515). After that, the host control circuit 210 determines whether or not the processing for the number of divisions of the deep bass amplifier has been executed (step S516). If the processing for the number of divisions of the deep bass amplifier is executed (YES in step S516), the host control circuit 210 sets the check status to 4 (step S517), and the normal amplifier / deep bass amplifier (YES in step S516). (Split) End the check process. On the other hand, if the processing for the number of divisions of the deep bass amplifier is not executed (NO in step S516), the host control circuit 210 checks the normal amplifier / deep bass amplifier (division) without updating the check status. End the process. That is, since the check status is not updated and is maintained at 3, the host control circuit 210 performs the process when the check status is 3 again in the next and subsequent frames. If the host control circuit 210 determines in step S514 that the check status is not 3 (NO in step S514), the host control circuit 210 proceeds to step S518.

In step S518, the host control circuit 210 determines whether or not the check status is 4. When the check status is 4 (YES in step S518), the host control circuit 210 clears the register value of the deep bass amplifier with an appropriate value (step S519). After that, the host control circuit 210 sets the check status to 5 (step S520), and ends the normal amplifier / deep bass amplifier (division) check process. When the host control circuit 210 determines in step S518 that the check status is not 4, (NO in step S518), the host control circuit 210 proceeds to step S521.

The host control circuit 210 determines in step S521 whether or not the check status is 5. When the check status is 5 (YES in step S521), the host control circuit 210 performs a sorting process of the received data from the binary file (step S522). After that, the host control circuit 210 compares the value of the RAM of the register of the deep bass amplifier with the received data (step S523), and updates the RAM address (step S524). After that, the host control circuit 210 determines whether or not the processing for the number of divisions of the deep bass amplifier has been executed (step S525). If the processing for the number of divisions of the deep bass amplifier is executed (YES in step S525), the host control circuit 210 determines whether or not the update of the RAM address is completed (step S526), and sets the check status. It is set to 0 (step S527), and the normal amplifier / deep bass amplifier (division) check process is completed. When the processing for the number of divisions of the deep bass amplifier is not executed in step S525 (NO in step S525), and when it is determined in step S526 that the update of the RAM address is not completed (NO in step S526). , The host control circuit 210 ends the normal amplifier / deep bass amplifier (division) check process without updating the check status. That is, since the check status is not updated and is maintained at 5, the host control circuit 210 performs the process when the check status is 5 again in the next and subsequent frames. When the host control circuit 210 determines in step S521 that the check status is not 5 (NO in step S521), the host control circuit 210 ends the normal amplifier / deep bass amplifier (division) check process.

As described above, in a more preferable embodiment of the sound amplifier check process, each check process of the normal amplifier and each check process of the deep bass amplifier can be divided into 1 msec interrupt process (that is, within one frame). The check process is performed within the range, and the subsequent process is performed in the next and subsequent frames. In this way, since a part of the check process of the normal amplifier and the check process of the deep bass amplifier are performed over a plurality of frames within one frame, the entire check process of each amplifier can be executed over a plurality of frames. It will be possible.

When the check status is 4, the host control circuit 210 determines whether or not the processing for the number of divisions has been executed (for example, if the check status is 3, the processing in step S516 corresponds). Absent. This is because the processing of step S519 performed when the check status is 4 can be performed in a short time so as not to affect the interrupt processing of 1 msec. In other words, the process performed when the check status is 4 (step S519) is the process performed when the check status is 0 (step S503), and the process performed when the check status is 1 (step S506). And step S507), the process performed when the check status is 2 (step S511), the process performed when the check status is 3, (step S515), and the process performed when the check status is 5 (step). This is because the time required for processing is shorter than that in steps S522 to S524), and the interrupt processing of 1 msec is not affected. As described above, in the pachinko gaming machine 1 of the present embodiment, it is determined whether or not the processing for the number of divisions has been executed in consideration of the time required for the processing (whether or not it affects the interrupt processing of 1 msec). I have decided whether or not. However, whether or not the processing for the number of divisions is executed even if the processing does not affect the interrupt processing of 1 msec (for example, the processing such as step S519 performed when the check status is 4). The determination may be made.

In each process of step S503, step S511, and step S515, it may be possible to further divide each register into determine whether or not each register value among the plurality of registers is normal. In this case, the progress of the further divided determination may be managed by the second check status. That is, the check status (first check status) related to the processing of the major classification shown in FIGS. 58 and 59 and the check status (second check status) related to the processing of the minor classification obtained by further dividing the processing of the major classification. Therefore, the progress of processing can be managed. Similarly, in each of the processes of steps S506 to S507 and steps S522 to S523, the process of comparing the RAM value of each register among the plurality of registers with the received data is further divided for each register. You may. In this case, the progress of the further divided process may be managed by the second check status. That is, the check status (first check status) related to the processing of the major classification shown in FIGS. 58 and 59 and the check status (second check status) related to the processing of the minor classification obtained by further dividing the processing of the major classification. Therefore, the progress of processing can be managed. For example, even if a power failure occurs during the sub-classification process or judgment, the progress of the sub-classification process or judgment is checked by the first check status and the second check status after the power is restored. It may be controlled to restart each process and each determination.

Further, the check status can be set to 0 when the power is turned on, and when the power is cut off during processing, various settings can be made such as starting from the check status at the time of the previous power cut after the power is restored. Of course, if a power failure occurs, the power is turned on, or backup clear (ram clear) processing is performed, the check status is set to 0 after the power is restored, and all processing and judgment are performed again ( Alternatively, as one of the initialization processes, all processes or determinations or some processes or determinations may be performed again).

[Sound request control processing (when there are multiple sound requests for the same channel)]
Next, regarding the sound request control process shown in FIG. 36, a sound request control process when there are a plurality of sound requests (also referred to as SAC requests) for the same channel will be described with reference to FIG. 60. FIG. 60 is a flowchart showing an example of sound request control processing when there are a plurality of sound requests for the same channel.

In the pachinko gaming machine 1 of the present embodiment, when a plurality of SAC requests are made to the same playback channel in the same frame of the main loop performed at a cycle of 33.3 msec, for example, a mute command of 2 msec is performed between the SAC request and the SAC request. Is registered with. As a result, it is possible to prevent the game sound output based on the SAC request from being covered with other game sounds, and it is possible to output a highly accurate game sound. However, in this case, although there is an advantage that the game sound is not overwritten, there is a possibility that the processing will take time. Therefore, in the pachinko gaming machine 1 of the present embodiment, when a plurality of SAC numbers are specified (registered) in the same virtual track in the same frame of the main loop, the SAC of the second arrival is spaced apart from the first SAC request. There is a case where a request is made and a case where a second-arrival SAC request is made without a gap between the first-come-first-served SAC number. Specifically, it will be described below.

As shown in FIG. 60, in the sound request control process (when there are a plurality of sound requests for the same channel), the host control circuit 210 first confirms the SAC number and the playback channel (step S541). Then, the process proceeds to step S542.

In step S542, the host control circuit 210 determines whether or not there are a plurality of SAC requests for the same reproduction channel. For example, since the SAC numbers are different between SHOT reproduction and LOOP reproduction, a plurality of SAC numbers may be specified for the same reproduction channel without intervals. When there are a plurality of SAC requests for the same reproduction channel (YES in step S542), the host control circuit 210 moves to step S543. On the other hand, if there are not a plurality of SAC requests for the same playback channel (NO in step S542), the sound request control process ends. In this embodiment, since one virtual track corresponds to one playback channel, the determination process in step S542 is synonymous with the determination as to whether or not there is a SAC request for the same virtual track. Is. That is, the "track" is an interface for decoding and reproducing the "phrase", and the "playback channel" is a concept for reproducing the "phrase". That is, when a "playback channel" is specified and a "phrase" is requested to be played back, the phrase is played by being assigned to the corresponding "track". The "virtual track" is an "interface for controlling phrase playback". There are 128 virtual tracks, which can be automatically assigned to 32 phrase reproduction channels. However, since this function is not used in this embodiment, "virtual track" = "reproduction channel".

In step S543, the host control circuit 210 determines whether or not the SHOT reproduction and the LOOP reproduction are chain reproductions. In the case of chain reproduction of SHOT reproduction and LOOP reproduction (YES in step S543), the host control circuit 210 executes the SAC request of LOOP reproduction one frame later (33.3 msec later) (step S544), and controls the sound request. End the process. In the case of SHOT playback and LOOP playback chain playback, by executing the LOOP playback SAC request with a delay of one frame, the SHOT playback sound is not overwritten and the SHOT playback sound is prevented from becoming difficult to hear. It becomes possible. On the other hand, if it is not a chain reproduction of SHOT reproduction and LOOP reproduction (NO in step S543), the host control circuit 210 moves to step S545.

In step S545, the host control circuit 210 determines whether or not the mute command between SACs is a mute setting for all playback channels. For example, when the variable display of a special symbol or a decorative symbol ends, a mute command is uniformly set between SACs for all playback channels. Then, when the mute command between SACs is the mute setting of all the reproduction channels (YES in step S545), the host control circuit 210 performs the SAC data corresponding to the first-come-first-served SAC request so that the mute is executed. The SAC data corresponding to the subsequent SAC request is set (step S546) without overwriting the mute command, and the sound request control process is terminated. On the other hand, when the mute command between SACs is not set to mute all the playback channels (NO in step S545), the mute command of each playback channel corresponds to the later SAC request so that quick processing is performed. Overwrite with SAC data and set (step S547), and the sound request control process ends.

As described above, in the pachinko gaming machine 1 of the present embodiment, when a plurality of SAC requests are made to the same playback channel in the same frame of the main loop, when the plurality of SAC requests are SHOT playback and LOOP playback chain playback. , The SAC number of the LOOP reproduction is delayed by one frame (for example, 33.3 msec) so as not to cover the sound of the LOOP reproduction with respect to the SHOT reproduction. SHOT reproduction is, for example, one-time reproduction of a phrase, and LOOP reproduction is, for example, LOOP reproduction (reproduction of a plurality of times) of a phrase.

In addition, when the mute command between SACs is the mute setting of all playback channels, the SAC data corresponding to the SAC number is input to the mute command without overwriting the SAC data of the subsequent arrival so that the mute is executed. sign up. As a result, for example, when the variable display of the special symbol is completed, it is possible to secure the period until the variable display of the next special symbol is started. Further, when the mute command between SACs is not set to mute all the reproduction channels, the mute command of each reproduction channel is overwritten with the SAC data corresponding to the later SAC request so that the mute is not executed. In this way, by executing or not executing muffling depending on the situation, it is possible to ensure the speed of processing (quickness by overwriting the muffling) while making the best use of the game sound effect of muffling. ing.

[Sound request control processing (when volume adjustment is performed)]
Next, with respect to the sound request control process shown in FIG. 36, variations of the sound request control process when the volume adjustment is performed will be described. In the present specification, as variations of the sound request control process when the volume is adjusted, five variations of the first embodiment to the fifth embodiment will be described with reference to FIGS. 61 to 65, respectively. FIG. 61 is a flowchart showing a first embodiment of the sound request control process when the volume is adjusted. FIG. 62 is a flowchart showing a second embodiment of the sound request control process when the volume is adjusted. FIG. 63 is a flowchart showing a third embodiment of the sound request control process when the volume is adjusted. FIG. 64 is a flowchart showing a fourth embodiment of the sound request control process when the volume is adjusted. FIG. 65 is a flowchart showing a fifth embodiment of the sound request control process when the volume is adjusted.

(First Example)
As shown in FIG. 61, in the first embodiment of the sound request control process (when the volume is adjusted), the host control circuit 210 first performs the input process of the voice data specified by the SAC number (when the volume is adjusted). Step S551). Then, the process proceeds to step S552. The SAC number is registered in each channel by the host control circuit 210.

In step S552, the host control circuit 210 designates the output destination speaker based on the voice data designated by the SAC number, and proceeds to step S553. In this first embodiment, the audio data designated by the SAC number incorporates information on which speaker to output from. Speakers are, for example, a shared speaker that is used for general purposes (used to output normal sounds that are sounds other than specific sounds) and dedicated speakers that are used to output specific sounds (error sounds, warning sounds, etc.). It has a speaker (for example, a speaker for deep bass). The host control circuit 210 sets which of the plurality of speakers is to be the dedicated speaker in various initialization processes (see, for example, various initialization processes in FIG. 36 (step S201)).

In step S553, the host control circuit 210 determines whether or not the volume is controlled by the hardware switch. If the volume is controlled by the hardware switch (YES in step S553), the volume is controlled by the hardware switch (see reference numeral 281 in FIG. 9) (step S554), and the process proceeds to step S556. On the other hand, if the volume is not controlled by the hardware switch (NO in step S553), the user volume control (see reference numeral 282 in FIG. 9) is performed (step S555), and the process proceeds to step S556.

In step S556, the host control circuit 210 performs debug volume control during debugging (see reference numeral 283 in FIG. 9), and then proceeds to step S557.

In step S557, the host control circuit 210 determines whether or not the volume control of the specific sound is performed. The specific sound corresponds to a sound that is not affected by the volume adjustment, such as an error sound. In addition, the voice data commanded by the SAC number incorporates information that the output destination of the normal sound is a shared speaker and information that the output destination of the specific sound is a dedicated speaker. There is.

When it is determined in step S558 that the volume control of the specific sound is not performed (NO in step S557), the host control circuit 210 performs volume control (see reference numeral 284 in FIG. 9) for the normal sound set in the channel (step S558). ), The process proceeds to step S560. In the volume control in step S558, control is performed to change the volume according to the volume adjustment.

On the other hand, when it is determined in step S557 that the volume control of the specific sound is performed (YES in step S557), the host control circuit 210 performs volume control (reference numeral 285 in FIG. 9) for the specific sound set in the channel (reference numeral 285 in FIG. 9). Step S559) and step S560. In the volume control in step S559, regardless of whether or not the volume adjustment has been performed, a constant volume is output without being affected by the volume adjustment (that is, even if the volume change operation is performed, the operation is concerned. Control to output a constant volume before and after the operation) is performed.

The host control circuit 210 determines in step S560 whether or not volume control for the number of channels (32 channels of 1CH to 32CH in the present embodiment) has been performed.

If the volume is set for the number of channels in step S560 (YES in step S560), the volume control incorporated in the voice data specified by the SAC number is performed (step S561), and the sound request control process is completed. To do.

If the volume control for the number of channels is not performed in step S560 (NO in step S560), the host control circuit 210 returns to step S557 and determines YES until the volume control for the number of channels is performed (YES in step S560). Until this is done), the processes of steps S557 to S560 are performed. Although not shown in FIG. 61, considering that the SAC number is specified corresponding to each channel, the volume control for the number of channels is also performed in the process of step S561. good.

(Second Example)
As shown in FIG. 62, in the second embodiment of the sound request control process (when the volume is adjusted), the host control circuit 210 first performs the input process of the voice data specified by the SAC number (when the volume is adjusted). Step S571). Then, the process proceeds to step S572. The SAC number is registered in each channel by the host control circuit 210.

In this second embodiment, for example, a shared channel used for general purposes (used for outputting a normal sound that is a sound other than a specific sound) and a specific sound (error sound, warning sound, etc.) There is a dedicated channel used for output. The host control circuit 210 includes a dedicated channel (CH31, CH32) used for outputting a specific sound among a plurality of channels (CH1 to 32) and a shared channel (CH1) used for a sound other than the specific sound. ~ CH30) are set in various initialization processes (see, for example, various initialization processes in FIG. 36 (step S201)).

In step S572, the host control circuit 210 determines whether or not the volume is controlled by the hardware switch. If the volume is controlled by the hardware switch (YES in step S572), the volume is controlled by the hardware switch (see reference numeral 281 in FIG. 9) (step S573), and the process proceeds to step S575. On the other hand, if the volume is not controlled by the hardware switch (NO in step S572), the user volume control (see reference numeral 282 in FIG. 9) is performed (step S574), and the process proceeds to step S575.

In step S576, the host control circuit 210 performs debug volume control during debugging (see reference numeral 283 in FIG. 9), and then proceeds to step S576.

In step S576, the host control circuit 210 determines whether or not the volume control of the specific sound is performed. Also in the second embodiment, the specific sound corresponds to a sound that is not affected by the volume adjustment, such as an error sound.

When it is determined in step S576 that the volume control of the specific sound is not performed (NO in step S576), the host control circuit 210 performs volume control (see reference numeral 284 in FIG. 9) for the normal sound set in the channel (step S577). ), The process proceeds to step S578. In the volume control in step S577, control is performed to change the volume according to the volume adjustment.

On the other hand, when it is determined in step S576 that the volume control of the specific sound is performed (YES in step S576), the host control circuit 210 performs volume control (reference numeral 285 in FIG. 9) for the specific sound set in the channel (reference numeral 285 in FIG. 9). Step S579) and step S582. In the volume control in step S579, regardless of whether or not the volume adjustment has been performed, a constant volume is output without being affected by the volume adjustment (that is, even if the volume change operation is performed, the operation is concerned. Control to output a constant volume before and after the operation) is performed.

In step S578, the host control circuit 210 determines whether or not the reproduction is performed on the reproduction channel that is not affected by the volume adjustment. If the playback is on a playback channel (for example, CH31, CH32) that is not affected by the volume adjustment (YES in step S578), a constant volume is specified (step S580). If the playback is on a playback channel (for example, CH1 to CH30) that receives volume adjustment (NO in step S578), the volume according to the user volume is set (step S581). When the process of step S580 is completed or the process of step S581 is completed, the host control circuit 210 moves to step S582.

In step S582, the host control circuit 210 determines whether or not volume control for the number of channels (32 channels of 1CH to 32CH in this embodiment) has been performed.

If the volume is set for the number of channels in step S632 (YES in step S582), the volume control incorporated in the voice data specified by the SAC number is performed (step S583), and the sound request control process is completed. To do.

If the volume control for the number of channels is not performed in step S582 (NO in step S582), the host control circuit 210 returns to step S576 and determines YES in step S582 until the volume control for the number of channels is performed. Until this is done), the processes of steps S576 to S582 are performed. Although not shown in FIG. 62, it is preferable that the volume control for the number of channels is also performed in the process of step S583.

(Third Example)
As shown in FIG. 63, in the third embodiment of the sound request control process (when the volume is adjusted), the host control circuit 210 first performs the input process of the voice data specified by the SAC number (when the volume is adjusted). Step S591). Then, the process proceeds to step S592.

In step S592, the host control circuit 210 determines whether or not the volume is controlled by the hardware switch. If the volume is controlled by the hardware switch (YES in step S592), the volume is controlled by the hardware switch (see reference numeral 281 in FIG. 9) (step S593), and the process proceeds to step S595. On the other hand, if the volume is not controlled by the hardware switch (NO in step S592), the user volume control (see reference numeral 282 in FIG. 9) is performed (step S594), and the process proceeds to step S595.

In step S595, the host control circuit 210 performs debug volume control during debugging (see reference numeral 283 in FIG. 9), and then proceeds to step S596.

In step S596, the host control circuit 210 determines whether or not the volume control of the specific sound is performed. Also in the third embodiment, the specific sound corresponds to a sound that is not affected by the volume adjustment, such as an error sound.

When it is determined in step S596 that the volume control of the specific sound is not performed (NO in step S596), the host control circuit 210 performs volume control (see reference numeral 284 in FIG. 9) for the normal sound set in the channel (step S597). ), The process proceeds to step S599. In the volume control in step S597, control is performed to change the volume according to the volume adjustment.

On the other hand, when it is determined in step S596 that the volume control of the specific sound is performed (YES in step S596), the host control circuit 210 performs volume control (reference numeral 285 in FIG. 9) for the specific sound set in the channel (reference numeral 285 in FIG. 9). Step S598) and step S599. In the volume control in step S598, regardless of whether or not the volume adjustment has been performed, a constant volume is output without being affected by the volume adjustment (that is, even if the volume change operation is performed, the operation is concerned. Control to output a constant volume before and after the operation) is performed.

In step S599, the host control circuit 210 determines whether or not the data currently in the reproduction channel (data being reproduced) is data that is not affected by the volume adjustment. If the data in the reproduction channel is not affected by the volume adjustment (YES in step S599), the next time, a constant volume is specified for the reproduction channel (step S600). If the data in the reproduction channel is the data to be adjusted in volume (NO in step S599), the next time, the volume in the reproduction channel is set according to the volume adjustment (step S601). When the process of step S600 is completed or the process of step S601 is completed, the host control circuit 210 moves to step S602.

The host control circuit 210 determines in step S602 whether or not volume control for the number of channels (32 channels of 1CH to 32CH in the present embodiment) has been performed.

If the volume is set for the number of channels in step S602 (YES in step S602), the volume control incorporated in the voice data specified by the SAC number is performed (step S603), and the sound request control process is completed. To do.

If the volume control for the number of channels is not performed in step S602 (NO in step S602), the host control circuit 210 returns to step S599 and determines YES as the volume control for the number of channels is performed (YES in step S602). Until this is done), the processes of steps S599 to S602 are performed. Although not shown in FIG. 63, it is preferable that the volume control for the number of channels is also performed in the process of step S603.

In this third embodiment, in step S599, it is determined whether or not the data currently in the reproduction channel (data being reproduced) is data that is not affected by the volume adjustment, and the determination result in step S599 is obtained. If YES, a constant volume is set for the next playback channel (step S600), and if the determination result in step S599 is NO, the volume according to the volume adjustment is set for the next playback channel. Alternatively, the modification described below may be used. That is, in this modified example, as the processing of the next step of step S597 and step S598, the audio data set this time and the audio data already being reproduced on the reproduction channel in which the audio data is set are volume-adjusted. After performing the process of checking whether the data is not affected, the process of determining whether the volume adjustment setting of the current audio data and the volume adjustment setting of the previous audio data are the same. I do. If the volume adjustment setting of the current audio data and the volume adjustment setting of the previous audio data are the same, a process of determining whether or not the data is not affected by the volume adjustment is performed. If the volume adjustment setting for the current audio data and the volume adjustment setting for the previous audio data are not the same, the volume adjustment will not be affected after the volume adjustment setting for the audio data set this time. Move on to the process of determining whether or not the data is data. Move on to the process of determining whether or not the data is not affected by the volume adjustment. Then, if the data is not affected by the volume adjustment, a process of setting a constant volume is performed on the playback channel, and if the data is affected by the volume adjustment, the volume adjustment is applied to the playback channel. Performs the process of setting the volume. After that, it is advisable to move to the process of determining whether or not the number of channels has been set, as in step S602. In this modified example, the processing different from that of the third embodiment is only the processing described above, and the other processing is the processing of the third embodiment (processes of steps S592 to S598 shown in FIG. 63, processing of step S602, and so on. And the process of step S603).

(Fourth Example)
As shown in FIG. 64, in the fourth embodiment of the sound request control process (when the volume adjustment is performed), the host control circuit 210 first determines whether the SAC number is the SAC number affected by the volume adjustment. Confirm whether or not (step S611). Then, the process proceeds to step S612.

In step S612, the host control circuit 210 updates the flag indicating whether or not the SAC number is affected by the volume adjustment, and inputs the voice data specified by the SAC number (step S613). Specifically, the flag is set to ON when the SAC number is affected by the volume adjustment (the flag is OFF when the SAC number is not affected by the volume adjustment).

In step S614, the host control circuit 210 determines whether or not the volume is controlled by the hardware switch. If the volume is controlled by the hardware switch (YES in step S614), the volume is controlled by the hardware switch (see reference numeral 281 in FIG. 9) (step S615), and the process proceeds to step S617. On the other hand, if the volume is not controlled by the hardware switch (NO in step S614), the user volume control (see reference numeral 282 in FIG. 9) is performed (step S610), and the process proceeds to step S617.

In step S617, the host control circuit 210 performs debug volume control during debugging (see reference numeral 283 in FIG. 9), and then proceeds to step S618.

In step S618, the host control circuit 210 determines whether or not the volume control of the specific sound is performed. Also in the fourth embodiment, the specific sound corresponds to a sound that is not affected by the volume adjustment, such as an error sound.

When it is determined in step S618 that the volume control of the specific sound is not performed (NO in step S618), the host control circuit 210 performs volume control (see reference numeral 284 in FIG. 9) for the normal sound set in the channel (step S619). ), The process proceeds to step S620. In the volume control in step S619, control is performed to change the volume according to the volume adjustment.

On the other hand, when it is determined in step S618 that the volume control of the specific sound is performed (YES in step S618), the host control circuit 210 performs volume control (reference numeral 285 in FIG. 9) for the specific sound set in the channel (reference numeral 285 in FIG. 9). Step S622) and step S624. In the volume control in step S622, regardless of whether or not the volume adjustment has been performed, a constant volume is output without being affected by the volume adjustment (that is, even if the volume change operation is performed, the operation is concerned. Control to output a constant volume before and after the operation) is performed.

In step S620, the host control circuit 210 determines whether or not the reproduction is performed on the reproduction channel that is not affected by the volume adjustment. That is, it is determined in step S612 whether or not the flag is set to ON. When the reproduction is performed on the reproduction channel that is not affected by the volume adjustment (YES in step S620), a constant volume is specified for the reproduction channel (step S621), and the process proceeds to step S624. When the reproduction is not performed on the reproduction channel that is not affected by the volume adjustment (NO in step S620), the volume corresponding to the volume adjustment is set in the reproduction channel (step S623), and the process proceeds to step S624.

In step S624, the host control circuit 210 determines whether or not volume control for the number of channels (32 channels of 1CH to 32CH in this embodiment) has been performed.

If the volume is set for the number of channels in step S624 (YES in step S624), the volume control incorporated in the voice data specified by the SAC number is performed (step S625), and the sound request control process is completed. To do.

If the volume control for the number of channels is not performed in step S624 (NO in step S624), the host control circuit 210 returns to step S618 and determines YES in step S624 until the volume control for the number of channels is performed. Until this is done), the processes of steps S618 to S624 are performed. Although not shown in FIG. 64, it is preferable that the volume control for the number of channels is also performed in the process of step S625.

(Fifth Example)
As shown in FIG. 65, in the fifth embodiment of the sound request control process (when the volume is adjusted), the host control circuit 210 first performs the input process of the voice data specified by the SAC number (when the volume is adjusted). Step S631). Then, the process proceeds to step S632.

The host control circuit 210 confirms whether the audio data is audio data for which each channel undergoes volume adjustment (step S633). Specifically, when the audio data specified by the SAC number is the audio data affected by the volume adjustment, the flag is set to ON (the audio data specified by the SAC number is not affected by the volume adjustment). If it is voice data, the flag is OFF).

In step S633, the host control circuit 210 determines whether or not the volume is controlled by the hardware switch. If the volume is controlled by the hardware switch (YES in step S633), the volume is controlled by the hardware switch (see reference numeral 281 in FIG. 9) (step S634), and the process proceeds to step S636. On the other hand, if the volume is not controlled by the hardware switch (NO in step S633), the user volume control (see reference numeral 282 in FIG. 9) is performed (step S635), and the process proceeds to step S636.

In step S636, the host control circuit 210 performs debug volume control during debugging (see reference numeral 283 in FIG. 9), and then proceeds to step S637.

In step S637, the host control circuit 210 determines whether or not the volume control of the specific sound is performed. Also in the fifth embodiment, the specific sound corresponds to a sound that is not affected by the volume adjustment, such as an error sound.

When it is determined in step S637 that the volume control of the specific sound is not performed (NO in step S637), the host control circuit 210 performs volume control (see reference numeral 284 in FIG. 9) for the normal sound set in the channel (step S638). ), The process proceeds to step S639. In the volume control in step S638, control is performed to change the volume according to the volume adjustment.

On the other hand, when it is determined in step S637 that the volume control of the specific sound is performed (YES in step S637), the host control circuit 210 performs volume control (reference numeral 285 in FIG. 9) for the specific sound set in the channel (reference numeral 285 in FIG. 9). Step S640) and step S643. In the volume control in step S640, regardless of whether or not the volume adjustment has been performed, a constant volume is output without being affected by the volume adjustment (that is, even if the volume change operation is performed, the operation is concerned. A constant volume is output before and after the operation) is performed.

In step S639, the host control circuit 210 determines whether or not the channel is not affected by the volume adjustment. That is, it is determined in step S632 whether or not the flag is set to ON. If the channel is not affected by the volume adjustment (YES in step S639), a constant volume is set for the playback channel (step S641). If the channel is affected by the volume adjustment (NO in step S639), the volume according to the volume adjustment is set in the playback channel (step S642). When the process of step S641 is completed or the process of step S642 is completed, the host control circuit 210 moves to step S643.

In step S643, the host control circuit 210 determines whether or not volume control for the number of channels (32 channels of 1CH to 32CH in this embodiment) has been performed.

If the volume is set for the number of channels in step S643 (YES in step S643), the volume control incorporated in the voice data specified by the SAC number is performed (step S644), and the sound request control process is completed. To do.

If the volume control for the number of channels is not performed in step S643 (NO in step S643), the host control circuit 210 returns to step S637 until the volume control for the number of channels is performed (YES in step S643). Until this is done), the processes of steps S637 to S643 are performed. Although not shown in FIG. 65, it is preferable that the volume control for the number of channels is also performed in the process of step S644.

According to the sound request control process (1st to 5th examples) when the volume adjustment is performed as described above, when the volume adjustment is performed, the volume corresponding to the volume adjustment is output for the normal sound. On the other hand, for a serious specific sound such as an error sound, even if the volume is adjusted, it is possible to easily perform voice control such as outputting a constant volume from the speaker.

[LED brightness adjustment processing]
Next, the brightness adjustment of the LED will be described with reference to FIGS. 36 and 66. FIG. 66 is an attenuation table showing an example of the luminance attenuation values of each color (red, green, blue) according to the emission intensity of the strong, medium, and weak LEDs. This attenuation table is stored in the sub-main ROM 205 (see, for example, FIG. 6).

The pachinko gaming machine 1 of the present embodiment is configured so that the brightness of the LED can be adjusted in three stages by, for example, an operation of a player or the like. Specifically, when the brightness adjustment operation is performed on the brightness setting screen displayed on the liquid crystal display device used as the display device 13, the host control circuit 210 performs the attenuation table switching process shown in FIG. 66. For example, when an operation of changing from strong to medium among the three levels of brightness is performed, the host control circuit 210 performs a process of switching the reference table from strong to medium in the attenuation table of FIG.

The LED whose brightness can be adjusted by the operation of a player or the like may be, for example, an LED provided on a glass door 4 (see, for example, FIG. 3), or may be, for example, a backlight of a liquid crystal display device used as a display device 13. It may be. The brightness adjustment of the LED is not limited to three steps, and may be configured so that the LED brightness can be adjusted in more steps, for example.

The output value of the LED is represented by the following equation (1).
LED output value = brightness value based on LED data x (100-luminance attenuation value) / 100 ... Equation (1)
The output value of the LED of the above formula (1) can also be set for each reproduction channel of the LED. The parameter changed by the player's operation is the luminance attenuation value. For example, when the brightness attenuation value is 0, the brightness is the strongest, and when the brightness attenuation value is 100, the brightness is the weakest and the light is turned off. Further, the calculation of the output value of the LED is performed inside the sequencer 226b (see FIG. 7).

For the LED data table that defines LED data and playback patterns, a BLD file (LED animation) is created using tools such as ActiveLED (UE) and LEDMaker (UE), and information is added to the created BLD file. While doing so, it is created by converting with the LED list (Excel macro) (UE).

By the way, in the case of a three-primary-color full-color LED, if the brightness attenuation values of red, green, and blue are uniformly the same, the white balance may be lost, and for example, what was white may turn yellow. For example, when the brightness of the LED is reduced, it is necessary to make the brightness attenuation value of blue the largest among red, green and blue, and it is preferable to make the brightness attenuation value of red the smallest.

Therefore, in the pachinko gaming machine 1 of the present embodiment, for example, even when the brightness of the LED is changed by the operation of a player or the like, the brightness attenuation value is set for each of the 1024 ports, for example, so that the white is white. It is configured to maintain the balance as much as possible.

Specifically, when the brightness of the LED is adjusted to one of strong, medium, and weak by the operation of a player or the like, the voice / LED control circuit 220 refers to the attenuation table of FIG. The brightness of the LED is controlled based on the brightness attenuation values set for each of green and blue. Since the attenuation table is prepared for each of 1024 ports (for each LED), for example, the attenuation value can be set for each port.

For example, when the brightness of the LED is set to be strong by the operation of a player or the like, the sequencer 226b of the voice / LED control circuit 220 has a red brightness attenuation value of 0, a green brightness attenuation value of 5, and a blue brightness attenuation value of 25. Is substituted into the above equation (1) to calculate the output value of the LED. Similarly, in the sequencer 226b of the voice / LED control circuit 220, when the brightness of the LED is set to the middle by the operation of a player or the like, the brightness attenuation value 50 for red, the brightness attenuation value 53 for green, and the brightness attenuation value for blue are set. When 63 is substituted into the above equation (1) and the brightness of the LED is set to be weak by an operation of a player or the like, the brightness attenuation value 80 of red, the brightness attenuation value 81 of green, and the brightness attenuation value of blue 85 are obtained. Substituting into the above equation (1), the output value of the LED is calculated. Then, the voice / LED control circuit 220 controls the light emission of the LED based on the output value of the LED calculated in this way.

In this way, the audio / LED control circuit 220 calculates the LED output value based on the luminance attenuation values set corresponding to each of red, green, and blue, and based on the calculated LED output value. By controlling the light emission of the LED, it is possible to maintain the white balance as much as possible even if the brightness of the LED is changed by an operation of, for example, a player or the like.

[Accessory solenoid control process]
Next, the accessory solenoid control process will be described with reference to FIGS. 36, 37, and 67. FIG. 67 is a block diagram showing an example of a connection state between the LED port and the LED and the solenoid.

In the pachinko gaming machine 1 of the present embodiment, for example, the movements of the movable body (role) provided in the game area are diversified, and the control of the movable body is complicated accordingly. Therefore, for simple movements among a wide variety of movements of the movable body, the control load of the movable body is suppressed by operating the members constituting the accessory with a solenoid or by providing the accessory with a locking mechanism. I am trying to. Upon receiving the motor operation request, the accessory driver outputs the contents of the motor operation data in order. The output of the motor driver and the determination of the end of the motor operation are performed by a timer interrupt process of 1 msec as shown in FIG. 37. In the timer interrupt process, the output determination and the end determination (that is, the determination of the start and end) of the accessory motor are performed, and the synchronous control of a plurality of motors is also performed.

Further, as shown in FIG. 67, the voice / LED control circuit 220 of the pachinko gaming machine 1 of the present embodiment includes the LED on the frame side connected to each LED port and the LED on the frame side based on the command from the host control circuit 210. The light emission of the LED on the board surface side (for example, the LED arranged on the game board 12 or the backlight of the liquid crystal display device used as the display device 13) is controlled via the LED driver. Then, among the LED ports (Port 0 to Port 23) controlled by the LED driver, the above solenoid is connected to Port 6, and the LED is connected to the other Port.

The voice / LED control circuit 220 receives a command from the host control circuit 210 to emit light from the LEDs connected to the ports of the frame-side LED and the board-side LED via the LED driver. By connecting the solenoid to the port 6, the operation of the solenoid can also be executed via the LED driver. As a result, even if the number of solenoids increases due to the diversification of the movement of the accessory, it is possible to suppress the control load for operating the accessory while maintaining the diversity of the movement of the accessory. ..

By the way, when the operation of the solenoid is executed via the LED driver as shown in FIG. 67, it is necessary to synchronously control the operation of the motor for operating the accessory and the operation of the solenoid. It should be noted that the operation of the accessory is performed by interrupt processing of 1 msec including synchronous control of a plurality of motors.

Therefore, in the pachinko gaming machine 1 of the present embodiment, a control code is added to the accessory sequence table, and when it is desired to synchronously control the solenoid and a plurality of motors that operate the accessory, a value larger than 0 is added to the control code. I try to set it. Then, the host control circuit 210 acquires the control code of the accessory being reproduced by the accessory device in the processing of the main loop (see step S204 of FIG. 36), and the acquired control code has a value larger than 0. In this case, the control of the LED port corresponding to the control code (for example, Port 6 to which the above solenoid is connected) is executed (see step S205 of FIG. 36). This makes it possible to execute synchronous control between the solenoid and a plurality of motors that operate the accessory.

The control of the LED port corresponding to the control code is executed in the main loop so as not to affect the normal LED control executed by the interrupt process of 1 msec.

Further, in the pachinko gaming machine 1 of the present embodiment, since the solenoid is connected to some of the LED ports (Port0 to Port23), for example, the brightness of the LED described above is adjusted by an operation of a player or the like. Then, the voltage to the solenoid is also reset, but it is considered that the influence on the solenoid is small because the operation of the solenoid is only ON / OFF. Further, when the synchronization effect for synchronizing the light emission of the LED and the operation of the solenoid is executed, it is possible to easily execute such a synchronization effect.

[Data load processing]
In the pachinko gaming machine 1 of the present embodiment, a data load process is performed as one of various initialization processes (see step S201 in FIG. 36) executed when the power is turned on. In addition, data loading processing may be performed during the game. These data load processes include data transfer from the ROM to the RAM or buffer (for example, data transfer from the sub-main ROM 205 to the SRAM 210b, data transfer from the CGROM 206 to the built-in VRAM 237 (for example, see FIG. 6)), that is. , A process of loading the data stored in the ROM into the RAM or buffer (data load process).

If the amount of data to be transferred is large, the above data load process takes a long time to load, and the watchdog may be reset to end the data load process. When the watchdog is reset, it is difficult to determine whether the cause of the reset is simply because the amount of data is large and it takes time, or because an error has occurred during data loading. Further, when the data loading process is completed, the host control circuit 210 cannot determine whether the loading is completed or the loading is unsuccessful, and continues to wait for the loading completion, so that the automatic recovery cannot be performed. There is a risk of becoming.

Therefore, in the present embodiment, when the time required for the data load processing exceeds a predetermined upper limit value, the data load process is terminated as an error and the data is reloaded. Hereinafter, the data loading process will be described with reference to FIG. 68. FIG. 68 is a flowchart showing an example of a data load process executed as one of various initialization processes by the host control circuit 210.

As shown in FIG. 68, the host control circuit 210 first sets the upper limit of the transfer time (step S651). The transfer time is the time required to load data from the ROM to the RAM. The upper limit of the transfer time varies depending on the amount of data to be transferred, but in the present embodiment, it is determined by the following equation (2).
Upper limit of transfer time = (transfer data amount per unit time) x (transfer time guideline + α) ... Equation (2)
The transfer data amount and transfer time guideline per unit time of the above equation (2) may be set in advance based on the transfer data amount, or may be set in advance based on the transfer data amount, for example, the host control circuit 210. It may be calculated by. Note that α is a time for allowing a margin for data loading.

When the process of step S651 is completed, the host control circuit 210 moves to step S652 and starts loading data from the ROM to the RAM.

After starting the data loading (step S652), the host control circuit 210 determines whether or not the data loading is completed (step S653). If the data loading is not completed (NO in step S653), the host control circuit 210 moves to step S654. On the other hand, if the data loading is completed (YES in step S653), the host control circuit 210 ends the data loading process.

In step S654, the host control circuit 210 determines whether or not the data transfer time exceeds the upper limit value. If the data transfer time exceeds the upper limit value (YES in step S654), the watchdog timer is cleared at regular intervals (step S655). On the other hand, if the data transfer time exceeds the upper limit value (NO in step S654), the host control circuit 210 determines that an error has occurred and executes error processing. The error processing executed here is a processing of resetting the load data by watchdog reset (step S656) and reloading without performing the watchdog timer clearing processing. After that, the host control circuit 210 returns to step S654. That is, when the data transfer time exceeds the upper limit value (NO in step S654), the data is reloaded as an error process.

In this way, when performing data load processing, the host control circuit 210 should continue to clear the watchdog timer at regular intervals while waiting for the completion of loading so that the watchdog reset does not occur during normal loading. I have to. However, when the data load process exceeds a predetermined upper limit value, the host control circuit 210 resets the load data and reloads the data. As a result, even if it takes time to load the data, it will be automatically restored by reloading.

[Sub-random number processing]
Next, the sub-random number processing executed in the main loop by the host control circuit 210 will be described.

The sub-random number processing includes a random number initialization process executed as one of various initialization processes (see step S201 in FIG. 36) when the power is turned on, a random number periodic update process executed periodically, and a random number periodic update process. It includes a random number acquisition process that is executed when a random number is used. The sub-random number processing is different from the lottery of special symbols by the main CPU 71 (for example, see FIG. 5) related to the ball ejection, and is a process for random numbers used for determining the production mode, for example, which does not affect the ball ejection. However, the sub-random number processing described below may be applied to the random number processing executed by the main CPU 71. The above-mentioned sub-random number processing will be described with reference to FIGS. 69 to 72. FIG. 69 is a flowchart showing an example of a random number initialization process executed as one of various initialization processes by the host control circuit 210. FIG. 70 is a flowchart showing an example of the random number periodic update process. FIG. 71 shows (a) a flowchart showing an example of random number 1 acquisition processing, (b) a flowchart showing an example of random number 2 acquisition processing, (c) a flowchart showing an example of random number 3 acquisition processing, and (d) random number 4 acquisition processing. It is a flowchart which shows an example. FIG. 72 is a flowchart showing an example of a random number acquisition process executed when a random number is used.

In the pachinko gaming machine 1 of the present embodiment, four random numbers are used (random numbers 1 to 4), and the initialization processing for these four random numbers is performed by clearing the game data RAM as shown in FIG. It is executed at the same timing.

As shown in FIG. 69, in the random number initialization process, the host control circuit 210 first acquires the RTC time (minutes / seconds) (step S671), and then enters the loop for the number of random numbers.

In the loop for the number of random numbers, the host control circuit 210 first creates a random number SEED (step S672). The random number SEED creation in the random number initialization process is executed based on the following equation (3).
SEED (random numbers 1 to 4) = (RTC time (seconds) + (RTC time (minutes) x 60) + random number number (random numbers 1 to 4)) x initial prime number ... Equation (3)

After creating the random number SEED in step S672, the host control circuit 210 stores the random number SEED created in step S672 in the random number backup, that is, SRAM 210b (see, for example, FIG. 6) (step S673). The random number SEED backed up here is the random number SEED created this time, but the information backed up up to the previous time may be deleted or may be continuously stored.

When the host control circuit 210 executes the processes of steps S672 and S673 for the number of random numbers (four random numbers 1 to 4 in this embodiment), the host control circuit 210 exits the loop for the number of random numbers and ends the random number initialization process.

As described above, the minutes and seconds of the RTC time are used in the random number initialization process. Therefore, the random number SEED at the time of initialization is involved in the time when the power is turned on in units of minutes and seconds.

Next, the random number periodic update process will be described with reference to FIG. 70. The random number periodic update process is a process of periodically updating the random numbers 1 to 4 even if none of the random numbers 1 to 4 is used in the waiting for the end of the bank flip shown in FIG. 36.

As shown in FIG. 70, in the random number periodic update process, the host control circuit 210 acquires a random number 1 (step S681), a random number 2 acquisition process (step S682), a random number 3 acquisition process (step S683), and a random number 4 acquisition. The processing (step S684) is performed in this order. The random number periodic update process is always executed while waiting for the end of the bank flip. Further, even if the bank flip end wait does not occur due to any processing failure in the main loop, the host control circuit 210 performs random number periodic update processing once in one frame.

As shown in FIG. 71 (a), the random number 1 acquisition process updates the random number 1 (step S685), that is, after acquiring the random number 1, the random number 1 is updated. After that, the acquired random number 1 is stored in the random number 1 backup, that is, SRAM 210b (see, for example, FIG. 6) (step S686). Similarly, as shown in FIG. 71 (b), the random number 2 acquisition process updates the random number 2 (step S687) and backs up the random number 2 (step S688). Similarly, as shown in FIG. 71 (c), the random number 3 acquisition process updates the random number 3 (step S689) and backs up the random number 3 (step S690). Similarly, as shown in FIG. 71 (d), the random number 4 acquisition process updates the random number 4 (step S691) and backs up the random number 4 (step S692). The random numbers backed up in step S686, step S688, step S690 and step S692 are the random numbers acquired this time, but the information backed up up to the previous time may be deleted or may be continuously stored. ..

Note that any of the random numbers 1 to 4 is obtained from the random numbers generated in the range of 0 to 32767, but the range of the generated random numbers is not limited to this.

As shown in FIG. 72, in the random number acquisition process executed when the random number is used, the host control circuit 210 first performs the random number 3 acquisition process (step S693). This random number 3 acquisition process is a process of acquiring a random number to be used for determining the random number to be used among the random number 1, the random number 2, and the random number 4. When the random number 3 acquisition process of step S693 is executed, the host control circuit 210 moves to step S694.

In step S694, the host control circuit 210 determines whether or not the remainder number (hereinafter, simply referred to as “remainder number”) when the random number acquired in the random number 3 acquisition process of step S693 is divided by 4 is 0 or 1. To determine. If the number of remainders is 0 or 1 (YES in step S694), the random number 1 acquisition process is performed (step S695). On the other hand, if the remainder number is neither 0 nor 1 (NO in step S694), the process proceeds to step S696.

In step S696, the host control circuit 210 determines whether or not the remainder number is 2. If the number of remainders is 2 (YES in step S696), the random number 2 acquisition process is performed (step S697). On the other hand, if the remainder number is not 2 (NO in step S696), the process proceeds to step S698.

In step S698, the host control circuit 210 determines whether or not the remainder number is 3. If the number of remainders is 3 (YES in step S698), the random number 4 acquisition process is performed (step S699). On the other hand, if the remainder number is not 3 (NO in step S698), this means that there is no remainder number 0 to 3, so the process is repeated from step S693.

The random number 1 acquisition process (step S695), the random number 2 acquisition process (step S697), the random number 3 acquisition process (step S693), and the random number 4 acquisition process (step S699) are all as shown in FIG. 71. ..

In this way, in the random number acquisition process executed when a random number is used, the selected random number among the random numbers 1, the random number 2, and the random number 4 is updated, but the unselected random number is updated. Not done.

Further, in the pachinko gaming machine 1 of the present embodiment, a random number initialization process is performed when the power is turned on, and when a random number is used, a random number acquisition process is performed for the selected random number, waiting for the end of the bank flip or the end of the bank flip. Even if the wait does not occur, the random number periodic update process is performed.

The calculation formula at the time of random number update is as shown in the following formula (4).
This update value = (previous update value x prime number of each random number) + 1 ... Equation (4)
Here, the return value of the random number acquisition process is a value of 0 to 32767 that is right-shifted and returned from 32 bits to 16 bits. That is, the current update value calculated based on the above equation (4) is represented by 32 bits, and the current update value of the 32 bits is right-shifted and returned from 32 bits to 16 bits. Then, the 16th bit is masked, and the value shown in 1 to 15 bits (any of 0 to 32767) is determined as the update value this time.

By performing the above-mentioned sub-random number processing, the acquired random numbers can be made random, and it is possible to suppress the occurrence of bias in the acquired random numbers. In particular, since the random number SEED at the time of initialization is involved in the time when the power is turned on in units of minutes and seconds, it is possible to make the initial value different each time.

[Modification example of sub-random number processing]
Although the sub-random number processing in the present embodiment has been described above, the sub-random number processing (modification example) described below may be performed in place of or in combination with the above-mentioned sub-random number processing. Further, the sub-random number processing (modification example) described below may be applied to the random number processing executed by the main CPU 71. A modification of this sub-random number processing will be described with reference to FIGS. 73 and 74. Note that FIG. 73 is a sub-control main process (overall flow) executed by the host control circuit 210 for explaining a modified example of the sub-random number process. However, FIG. 73 shows only the processing necessary for the explanation, and omits the other processing. FIG. 74 is a flowchart showing an example of the reception interrupt process executed by the host control circuit 210.

The host control circuit 210 first performs a random number initialization process executed as one of various initialization processes (see step S201 in FIG. 36) (step S701). In this random number initialization process, for example, a random number seed of a power of 2 (a perfect power) and a current random number seed number are prepared, and a predetermined initial value is set in the stack pointer.

When the random number initialization process of step S701 is performed, the host control circuit 210 enters the main loop, performs input processing of the subdevice (step S702), and then performs various request control processes (step S703). In this various request control process (step S703), the output is output to various devices based on the request created in step S705 described later one frame before.

When the input process of the subdevice (step S702) and various request control processes (step S703) are performed, the host control circuit 210 performs a random number table creation process (step S704). In the random number table creation process of step S704, a new random number table is created by updating the random numbers registered in the random number table having a power of 2 size at the drawing timing. For the acquisition of the random numbers registered in the random number table, for example, among the random number seeds of powers of 2, the random number seed determined based on the current random number seed number is used. For example, if the random number seed a~h 2 3 ⁽⁸⁾ are prepared, the current random number seed number if 4, the random number seed d is used.

In step S704, the host control circuit 210 ^{can create, for example, a random number table having a size of 25} (32), and 32 random numbers are registered in this random number table. When the random number is registered in the random number table, the host control circuit 210 updates the value of the random number seed. The random number seed is updated by adding 1 after multiplying the previous update value × the prime number, as in the above equation (4). In this modification, the size of the random number table may be a power of 2 (pieces), and ²⁵ (32) is used, but any power of 2 (pieces) can be used. good.

As shown in FIG. 74, the random number seed used for creating the random number table in step S704 is, for example, the value of the CPU counter by the CPU processor of the host control circuit 210 when a serial command is received (step S801). It is updated using (step S802). In the random number seed update process of step S802, the random number seed number used for creating the random number table is updated by incrementing the random number seed number and using the incremented random number seed number as the current random number seed number.

Returning to FIG. 73 and performing the random number table creation process in step S704, the host control circuit 210 enters the packet reception loop.

In the packet reception loop, the host control circuit 210 performs an animation construction process (step S705) for creating a request for animation for moving image production, and performs a random number acquisition process when a random number is used (step S706). The request created in step S705 waits in the buffer and then is output in the next frame.

The host control circuit 210 acquires a random number from the random number table created in step S704 in the random number acquisition process of step S706. The random numbers acquired here are used for a lottery related to the effect executed by the host control circuit 210 (for example, a lottery for determining an animation for moving image effect). When the host control circuit 210 acquires a random number from the random number table in step S706, the host control circuit 210 updates (increments) the reference position of the random number table. The reference position of the random number table is only performed when a random number is acquired from the random number table, and is not performed in the random number table creation process in step S704.

The host control circuit 210 repeats the processes of steps S705 and S706 for the number of received packets. When the processing of step S705 and step S706 is performed for the packet reception, the host control circuit 210 exits the packet reception loop.

Upon exiting the packet reception loop, the host control circuit 210 performs animation update processing (step S707), and then waits for bank flip / bank flip end (step S708).

The host control circuit 210 repeats the processes of steps S702 to S708 in the main loop having a period of 33.3 msec.

According to the above-mentioned modification of the sub-random number processing, even if there are multiple random number acquisition opportunities in the packet reception loop, only the random number is acquired by changing the reference position using the same random number table already created. Therefore, it is possible to reduce the control load of the host control circuit 210 while giving irregularity to the acquired random numbers.

[Other extended examples]
The pachinko gaming machine 1 of the present embodiment can apply the present invention to all gaming machines in which a game is played using a game medium and benefits are given based on the result of the game. That is, not only is the game played by the game medium being launched or thrown in by the physical movement of the player, and the game medium is paid out based on the result of the game, but the main control circuit 100 itself is The game medium owned by the player may be electromagnetically managed to enable a game performed by circulating the enclosed game ball or a game performed without a medal. Further, it may be a game medium management device that is mounted (connected) to the main control circuit 100 and manages the game medium that electromagnetically manages the game medium owned by the player.

When the game media management device connected to the main control circuit 100 manages the game media management device, the game media management device has a ROM and an RWM (or RAM) and is provided in the game machine, and is an external game (not shown). It is connected to a two-way communication function via a medium handling device and a predetermined interface, and provides a game medium necessary for a game medium lending operation (that is, a player performs a game medium loading operation). Operation) or when a winning combination related to the payout of the game medium is won (the winning combination is established), the payout action of the game medium (that is, the payout of the game medium to the player is performed, and the necessary game medium is acquired. It is sufficient that the operation of electromagnetically recording the game medium used for the game can be performed. Further, the game media management device not only manages the actual number of game media, but also displays the number of game media held on the front surface of the pachinko game machine 1 based on, for example, the management result of the number of game media. A game medium number display device (not shown) may be provided, and the number of game media displayed on the possessed game medium number display device may be managed. That is, the game medium management device may be capable of recording and displaying the total number of game media that the player can use for the game by an electromagnetic method.

Further, in this case, the game medium management device has a performance that allows the player to freely transmit a signal indicating the number of recorded game media to an external game medium handling device, and also has a game. In addition to the case where a person directly operates the game medium, the number of recorded game media cannot be reduced, and an external connection terminal plate (not shown) is provided between the device and an external game medium handling device. In some cases, it is desirable that the player has the ability to transmit a signal indicating the number of recorded game media only through the external connection terminal plate.

In addition to the above, the game machine is provided with a lending operation means, a return (payment) operation means, and an external connection terminal plate that can be operated by the player, and the game medium handling device is provided with a slot for valuable value such as banknotes and a recording medium. (For example, IC card) insertion slot, non-contact communication antenna for depositing electronic money etc. from mobile terminals, other various operation means such as lending operation means, return operation means, external connection terminal board on the game media handling device side It may be provided (neither is shown).

As a flow of the game at that time, for example, the player deposits valuable value to the game medium handling device by any method, and subtracts a predetermined number of valuable values based on the operation of any of the above lending operation means. Then, the number of game media corresponding to the valuable value subtracted from the game media handling device to the game media management device is increased. Then, the player plays a game, and if a game medium is required, the above operation is repeated. After that, a predetermined number of game media are acquired as a result of the game, and when the game is finished, the number of game media is transmitted from the game media management device to the game media handling device by operating one of the return operation means, and the game is played. The medium handling device discharges a recording medium on which the number of game media is recorded. The game medium management device clears the number of game media stored by itself when the number of game media is transmitted. The player takes the discharged recording medium to a prize counter or the like for exchanging prizes, or moves the game table to play a game based on the game medium recorded on another table.

In the above example, all the game media are transmitted to the game medium handling device, but only the number of game media desired by the player is transmitted on the game machine or the game medium handling device side, and the game medium possessed by the player is transmitted. It may be divided and processed. Further, not only the recording medium is discharged, but cash or a cash equivalent may be discharged, or the recording medium may be stored in a mobile terminal or the like. Further, the game medium handling device may be capable of inserting a member recording medium of the game hall and storing the member recording medium in the member recording medium so that the game can be played again at a later date.

Further, in the game machine or the game medium handling device, a lock operation for locking the game medium or valuable value data communication can be executed on the game medium handling device or the game medium management device by operating a predetermined operating means (not shown). May be good. In that case, information such as a one-time password that only the player can know may be set, or the player may be recorded by an imaging means provided in the game medium handling device.

Further, in the above, the case where the game medium management device is applied to the pachinko game machine is described, but the game medium management device is also used in the pachislot machine, the slot machine using the game ball, and the enclosed game machine. It can also be provided so that the player's game medium is managed.

As described above, by providing the above-mentioned game medium management device, the number of parts inside the game machine can be reduced as compared with the case where the game medium is physically used for the game, and the cost and manufacturing cost of the game machine can be reduced. Not only can it be reduced, but it is also possible to prevent the player from coming into direct contact with the gaming medium, improving the gaming environment, reducing noise, and reducing the power consumption of the gaming machine by reducing the number of parts. It will also be. In addition, it is possible to prevent fraudulent acts through the game medium and the slot and payout port of the game medium. That is, it is possible to provide a gaming machine that can improve various environments surrounding the gaming machine.

In addition, a communication cable is used to transmit data on an enclosed game machine configured so that the game medium can be played without being discharged to the outside, and an increase / decrease in the game medium due to consumption, lending, and payout of the game medium to the game machine. When the present invention is applied to a game system having a game medium management device connected so as to be able to transmit and receive by an optical signal via an optical signal, the game system may be configured as follows.

The outline of the enclosed gaming machine will be described below. In the enclosed gaming machine, the launching device is located above the gaming area and launches a gaming ball as a gaming medium from above with respect to the gaming area. When the player operates the handle, the payout control circuit drives the ball feed solenoid, and the ball feed punch pushes the game ball in the standby state toward the launch pad. As a result, the game ball moves to the launch pad. In addition, a subtraction sensor is provided on the path from the standby position to the launch pad, and detects a game ball moving to the launch pad. When a game ball is detected by the subtraction sensor, the number of balls held is subtracted by 1. In this way, since the gaming ball as the gaming medium is launched from above with respect to the gaming area, the so-called return ball (foul ball) can be avoided in the enclosed gaming machine. Then, the game ball discharged from the game area after rolling in the game area is polished by the ball polishing device. The game ball polished by the ball polishing device is transported upward by the lifting device and guided to the launching device. The gaming balls are not discharged to the outside of the enclosed gaming machine, and a certain number (for example, 50) of gaming balls are configured to circulate in a series of paths in the gaming machine.

In the enclosed gaming machine, since the gaming ball is not discharged to the outside of the gaming machine, an upper plate or a lower plate for temporarily holding the gaming ball is not provided. Since the gaming ball is not discharged to the outside in the enclosed gaming machine, the gaming ball is not actually in the player's hand, and the gaming ball does not actually increase or decrease by playing the game. In the enclosed gaming machine, the player starts the game after obtaining a ball by lending from the gaming medium management device. Here, obtaining a possession ball means that the player obtains a game medium in terms of data management. Then, when the game ball is launched from the launching device, the possessed ball is consumed and the number of possessed balls decreases. In addition, as the game balls pass through each winning opening or the like provided in the game area, the number of balls held is increased by paying out the number according to the conditions set according to the winning opening. Furthermore, the number of balls held will increase by lending from the game media management device. In addition, "consumption, lending and payout of game media" means that the ball is consumed, lent and paid out. In addition, "increase / decrease in game media" means that the number of balls held increases / decreases due to consumption, lending, and payout. In addition, "data on increase / decrease in game media due to consumption, lending, and payout of game media" is data on a decrease in the number of balls held due to the launch of a game ball and an increase in the number of balls held due to lending and paying out.

The enclosed gaming machine has a payout control circuit and a touch panel type liquid crystal display device. The payout control circuit is connected to various sensors that detect the passage of the game ball through each winning opening or the like. The payout control circuit manages the number of balls held. For example, when a game ball passes through each winning opening, the number of game balls paid out due to this is added to the number of balls held. Also, when the game ball is launched, the number of balls held is subtracted. The payout control circuit transmits data regarding the number of balls held to the game medium management device by the operation of the player. Further, the above-mentioned liquid crystal display device is located at the upper part of the game machine, and receives a request for conversion from the game value managed by the game medium management device to a ball held (ball lending) and counting of balls held (return). Then, these requests are transmitted to the payout control circuit via the game medium management device, and the payout control circuit is instructed to transmit data regarding the current number of balls held to the game medium management device. Here, the "game value" refers to money / banknotes, prepaid media, tokens, electronic money, tickets, etc., which can be converted into holding balls by the game media management device. In the present embodiment, the game medium management device is a so-called CR unit, and is configured to be able to accept banknotes, prepaid media, and the like. In addition, the counted balls can be used for prize exchange and the like at a game hall where a game system is installed.

In addition, the enclosed gaming machine has a backup power supply. As a result, even when the power is turned off at night or the like, the data immediately before the power is turned off can be retained. Further, with this backup power supply, for example, the door frame opening detection by the door opening sensor may be continuously executed. As a result, it is possible to prevent cheating at night. In this case, information such as the number of times the door frame is opened may be stored. Further, when the power is turned on, information such as the number of times the door frame is opened may be output to the liquid crystal display device of the gaming machine or the like.

The game medium management device has a game machine connection board. The game medium management device is configured to transmit / receive data (transmission signal) to / from the game machine via the game machine connection board. The data to be transmitted and received includes the unique ID of the CPU provided in the main control circuit, the unique ID of the CPU provided in the payout control circuit, the game machine manufacturer code stored in the game machine, the security chip manufacturer code, and the game. Information such as the model code of the machine. Then, when one of the gaming machine and the gaming medium management device is used as a transmission source and the other is used as a transmission destination, and the transmission source transmits a transmission signal, the transmission destination that receives the transmission signal is the same signal as the transmission signal. The confirmation signal is transmitted to the transmission source, and the transmission source compares the transmission signal with the confirmation signal to determine whether or not they are the same.

In this way, the transmission source compares the confirmation signal transmitted from the transmission destination with the transmission signal to determine whether or not they are the same, so that the signal transmitted from the transmission source is not tampered with. It can be confirmed that the signal has been sent to the sender. As a result, it is possible to suppress fraudulent acts such as falsification of transmission / reception signals between the gaming machine and the gaming medium management device.

Further, in the game system, the transmission source has a modulation unit that modulates a signal, the signal modulated by the modulation unit is transmitted as the transmission signal, and the transmission destination transmits the signal modulated by the modulation unit. It may have a demodulation unit for demodulation.

As a result, even if the transmission / reception signal between the game machine and the game medium management device is read, it is difficult to decipher this signal, and the transmission / reception signal between the game machine and the game medium management device is transmitted. It is possible to suppress fraudulent acts such as falsification.

Further, in the game system, when the transmission destination receives the transmission signal from the transmission source, the approval signal, which is a signal indicating that the transmission signal has been received, is set in addition to the confirmation signal. It may be transmitted to the source.

As a result, by comparing the transmission signal and the confirmation signal, it is confirmed not only that the normal signal has been transmitted / received, but also that the normal signal has been transmitted / received based on the approval signal. Therefore, it is possible to further strengthen the suppression of fraudulent activities.

[Additional Notes]
[First gaming machine]
Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when a game ball wins a prize at the starting port, and a big hit game is performed when the result of this lottery is a big hit.

As this type of gaming machine, a long-press effect is performed on the operating means to change the execution mode of the specific game effect on condition that the player performs a predetermined long-press operation, which is shorter than the long-press operation. There is known a gaming machine capable of executing a continuous striking effect on condition that a continuous striking operation of performing a pressing operation a plurality of times is performed (see, for example, Japanese Patent Application Laid-Open No. 2015-055977). In the gaming machine of Japanese Patent Application Laid-Open No. 2015-065977, if the long-press operation is performed within the long-press operation acceptance valid period for determining whether or not the long-press operation is performed, the long-press effect is executed.

(First issue)
It is not preferable to control by determining whether a long press operation is performed or a continuous striking effect is performed on the operating means as in the gaming machine described in Japanese Patent Application Laid-Open No. 2015-065977, because the control load becomes large. ..

However, in recent years, there has been a demand for a gaming machine that can enhance the interest by producing a production that can give a further visual impact.

In order to solve the first problem, the first gaming machine having the following configuration is provided.

The first gaming machine is
A gaming machine capable of executing a main process (for example, a main loop process) in which various processes (for example, various request control processes) are performed every predetermined time (for example, 33.3 msec).
With a predetermined operating means (for example, main button),
A control capable of performing interrupt processing every time shorter than the predetermined time (for example, 1 msec) and generating input information in the main process based on the input state of the operating means detected by the interrupt process. Means (eg, host control circuit 210) and
With
The control means
As the input information, after the input state of the operating means changes from the OFF state to the ON state, and as the input information, after the input state of the operating means changes from the OFF state to the ON state, the ON state remains for a certain period of time. After it is determined that the operation means has continued (for example, 10 frames), as long as the input state of the operating means continues for a time shorter than the fixed time (for example, 4 frames), the ON state occurs periodically. An input information generating means (for example, a host control circuit 210 that executes the process of step S309) that generates information that can be determined (for example, ON edge information with a repeat function), and
Having a device control means (for example, a host control circuit 210) capable of executing control of a predetermined device based on the information generated by the input information generation means (for example, the ON edge information with a repeat function). It is a feature.

According to the first gaming machine, after the input state of the operating means changes from the OFF state to the ON state based on the input state of the operating means (for example, the input information of the sub-device), the ON state continues for a certain period of time. Sub-devices by generating information that can be determined to have occurred periodically as long as the input state of the operating means continues to be ON for a period of time shorter than a certain period of time after it is determined that the ON state has occurred. It is possible to easily perform control such as control of continuous hitting effect and control of long press effect.

Further, according to the first gaming machine, it is possible to execute control according to the mode of the operating means while reducing the control load.

[Second game machine, third game machine]
Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when a game ball wins a prize at the starting port, and based on the result of this lottery, an effect image is displayed on, for example, a liquid crystal display.

As this type of gaming machine, a gaming machine including a display device that emits light by a backlight is disclosed (see, for example, Japanese Patent Application Laid-Open No. 2016-159026).

(Second issue)
However, for example, if the brightness of the light emitting means of the backlight is unstable, the display of the effect image on the display device may become unstable, which is not preferable.

In order to solve the second problem, a second gaming machine and a third gaming machine having the following configurations are provided.

The second gaming machine is
A light emitting means (for example, a backlight) capable of emitting light in a predetermined embodiment,
A data storage means (for example, a FIFO data area) that stores drive data (for example, luminance data) corresponding to a light emitting mode emitted by the light emitting means in a predetermined area, and
A light emitting drive means (for example, LSI) that outputs a control signal based on the drive data stored in the data storage means to the light emitting means, and
A data setting means (for example, a host control circuit 210 that executes the process of step S346) for setting the drive data in a predetermined area of the data storage means, and
With
The data setting means is
When the number of drive data set in the predetermined area of the data storage means reaches the reference number of drive data that can be set in the predetermined area, a new drive data is set. And.

According to the second gaming machine, when the number of drive data set in the predetermined data area reaches the reference number of drive data that can be stored in the predetermined area, new drive data is set, so that light is emitted. A control signal output by the drive means (for example, a signal equivalent to PWM continuously output from the serial data output terminal of SPI) can be output, and the light emitting means can emit light stably without going through a driver. It becomes possible.

The above-mentioned "reference data number" corresponds to 1 to 64 data if the number of data that can be set in a predetermined area of the data storage means (for example, the FIFA data area) is up to 64, for example. Considering that it is necessary to prevent the number of data set in a predetermined area of the storage means from becoming 0, it is preferable that the number of data is two or more. Further, the number of luminance data that can be set in the FIFO data area is not limited to 64, and it is sufficient that at least two or more luminance data can be set. When the number of brightness data set in the FIFA data area is, for example, two or more, and the number of brightness data set in the FIFA data area is less than the first number (for example, two), the second number is obtained. The brightness data (for example, one) may be supplemented.

The third gaming machine is
A light emitting means (for example, a backlight) capable of emitting light in a predetermined embodiment,
A data storage means (for example, a FIFO data area) that stores drive data (for example, luminance data) corresponding to a light emitting mode emitted by the light emitting means in a predetermined area (for example, a FIFO data area).
A light emitting drive means (for example, LSI) that outputs a control signal based on the drive data stored in a predetermined area of the data storage means to the light emitting means, and
A data setting means (for example, a host control circuit 210 that executes the process of step S346) for setting the drive data in a predetermined area of the data storage means, and
A timekeeping means capable of measuring the elapsed time since the drive data is set in a predetermined area of the data storage means (for example, a host control circuit 210 that executes the process of step S356).
With
The data setting means is
It is characterized in that the driving data can be set in a predetermined area of the data storage means (the process of step S354 can be executed) based on the elapse of a predetermined time or more by the time counting means. And.

According to the third gaming machine, the drive data is stored in the predetermined area of the data storage means based on the elapsed time from the setting of the drive data in the predetermined area of the data storage means to the predetermined time or more. Set. For example, when some processing takes time, the driving data set in the predetermined area of the data storage means disappears until the timing of setting the driving data in the predetermined area of the data storage means is reached. There is a risk that it will end up. In this regard, according to this gaming machine, even if it is not the timing to set the drive data in the predetermined area of the data storage means, the drive data is determined by the data storage means based on the elapse of the above time or more. Since it is set in the area of, it is possible to prevent the drive data set in the predetermined data area from becoming empty. Therefore, a control signal output by the light emitting driving means (for example, a signal equivalent to PWM continuously output from the serial data output terminal of SPI) can be output, and the light emitting means can be stably output without using a driver. It is possible to make it emit light.

Further, according to the second gaming machine and the third gaming machine, it is possible to suppress the unstable light emission of the light emitting means.

[Fourth game machine, fifth game machine]
Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when a game ball wins a prize at the starting port, and a production image is displayed on a liquid crystal display or the like based on the result of this lottery.

As this type of gaming machine, there is known a gaming machine used for directing or decorating by emitting light in a predetermined mode from a light emitting device composed of a plurality of light emitting bodies such as LEDs provided on the front side. .. Further, there is disclosed a gaming machine in which the brightness of these light emitting devices can be adjusted by a player or the like within a preset range (see, for example, Japanese Patent Application Laid-Open No. 2008-295551).

(Third issue)
By the way, in recent years, the production has become flashy, including a light emitting device composed of a plurality of light emitting bodies such as LEDs provided on the front side. Therefore, if the brightness of the light emitting device is high, it may be stressful for some players. If the brightness of the light emitting device can be operated by the player or the like, the player can adjust the brightness to a desired brightness, but that alone may not be sufficient.

In order to solve the third problem, a fourth gaming machine and a fifth gaming machine having the following configurations are provided.

(1) The fourth gaming machine is
A first light emitting means (for example, a backlight) capable of emitting light in a predetermined embodiment,
An operating means (for example, a brightness setting screen displayed on a liquid crystal display device used as a display device 13) capable of changing the brightness of the first light emitting means to any one of a plurality of stages, and
A host control circuit that executes the process of step S384 (for example, a host control circuit) capable of changing the brightness of the first light emitting means to any one of a plurality of stages based on the operation of the operating means. 210) and
A second light emitting means (for example, a panel side LED or a frame side LED) provided separately from the first light emitting means,
A second light emitting control means (for example, a host control circuit 210 that executes the process of step S385) capable of changing the brightness of the second light emitting means, and
With
The second light emission control means
The brightness of the second light emitting means is changed to one of the plurality of steps at a timing different from the timing at which the brightness of the first light emitting means is changed based on the operation of the operating means. It is characterized by being configured to be possible.

According to the fourth gaming machine of (1) above, when the operating means capable of changing the brightness of the first light emitting means is operated, the timing is different from the timing at which the brightness of the first light emitting means is changed. While the brightness of the second light emitting means is also changed, the brightness of the second light emitting means is also changed to one of a plurality of stages, so that the degree of freedom for the player to change the brightness can be further increased. It will be possible.

(2) In the fourth gaming machine described in (1) above,
A data storage means (for example, a FIFO data area) that stores drive data corresponding to a light emitting mode emitted by the first light emitting means in a predetermined area, and
A light emitting drive means (for example, LSI) that outputs a control signal based on the drive data stored in the data storage means to the first light emitting means, and
A data setting means (for example, a host control circuit 210 that executes the process of step S346) for setting the drive data in a predetermined area of the data storage means, and
With
The data setting means is
When the number of drive data set in the predetermined area of the data storage means reaches the reference number of drive data that can be stored in the predetermined area, new drive data is set and new drive data is set.
When the operating means is operated, the driving data after the brightness is changed is set as the new driving data.

According to the fourth game machine of (2) above, when the number of drive data set in the predetermined data area becomes the reference data number, new drive data is set. Therefore, it is possible to output a control signal output by the light emitting driving means (for example, a signal equivalent to PWM continuously output from the serial data output terminal of SPI), and the light emitting means is stabilized without going through a driver. It becomes possible to make it emit light. Moreover, when the brightness is changed, the changed drive data is set as new drive data, so that the first light emitting means can be stably emitted according to the set brightness.

The above-mentioned "reference data number" corresponds to 1 to 64 data if the number of data that can be set in a predetermined area of the data storage means (for example, the FIFA data area) is up to 64, for example. Considering that it is necessary to prevent the number of data set in a predetermined area of the storage means from becoming 0, it is preferable that the number of data is two or more. Further, the number of luminance data that can be set in the FIFO data area is not limited to 64, and it is sufficient that at least two or more luminance data can be set. When the number of brightness data set in the FIFA data area is, for example, two or more, and the number of brightness data set in the FIFA data area is less than the first number (for example, two), the second number is obtained. The brightness data (for example, one) may be supplemented.

(1) The fifth gaming machine is
A lottery means (for example, the main CPU 71 that executes the process of step S45) that draws a lot based on the satisfaction of a predetermined condition, and
A display means for displaying a predetermined effect image (for example, a liquid crystal display device used as the display device 13) and
Based on the result of the lottery, the variable display control means (for example, the display control circuit 230) that displays the variable of the symbol (for example, the identification symbol for effect) in the display means,
A first light emitting means (for example, a backlight) capable of emitting light in a predetermined embodiment,
An operating means (for example, a brightness setting screen displayed on a liquid crystal display device used as a display device 13) capable of changing the brightness of the first light emitting means to any one of a plurality of stages, and
Host control for executing the process of the first light emitting control means (for example, step S394) in which the brightness of the first light emitting means can be changed to any one of a plurality of stages based on the operation of the operating means. Circuit 210) and
A second light emitting means (for example, a panel side LED or a frame side LED) provided separately from the first light emitting means,
A second light emitting control means (host control circuit 210 that executes the process of step S392) that controls the light emitting mode of the second light emitting means based on a predetermined request, and
With
The second light emission control means
Based on the operation of the operating means, the brightness of the second light emitting means is changed after the brightness of the first light emitting means is changed and after the variation display of the symbol is completed. (For example, the process of step S399 is executed).

According to the fifth gaming machine of the above (1), the brightness of the first light emitting means can be changed when the operating means is operated. Further, the brightness of the second light emitting means is changed after the brightness of the first light emitting means is changed and after the variation display of the symbol is completed. Here, since the light emitting mode of the second light emitting means is controlled based on a predetermined request, the control load is minimized by changing the brightness of the second light emitting means after the variable display of the symbol is completed. It is possible to change the brightness of the first light emitting means and the second light emitting means while suppressing the limit.

(2) In the fifth gaming machine described in (1) above,
A data storage means (for example, a FIFO data area) that stores drive data corresponding to a light emitting mode emitted by the first light emitting means in a predetermined area, and
A light emitting drive means (for example, LSI) that outputs a control signal based on the drive data stored in the data storage means to the first light emitting means, and
A data setting means (for example, a host control circuit 210 that executes the process of step S346) for setting the drive data in a predetermined area of the data storage means, and
With
The data setting means is
When the number of drive data set in the predetermined area of the data storage means reaches the reference number of drive data that can be stored in the predetermined area, new drive data is set and new drive data is set.
When the operating means is operated, the driving data after the brightness is changed is set as the new driving data.

According to the fourth game machine of (2) above, when the number of drive data set in the predetermined data area becomes the reference data number, new drive data is set. Therefore, it is possible to output a control signal output by the light emitting driving means (for example, a signal equivalent to PWM continuously output from the serial data output terminal of SPI), and the light emitting means is stabilized without going through a driver. It becomes possible to make it emit light. Moreover, when the brightness is changed, the changed drive data is set as new drive data, so that the first light emitting means can be stably emitted according to the set brightness.

The above-mentioned "reference data number" corresponds to 1 to 64 data if the number of data that can be set in a predetermined area of the data storage means (for example, the FIFA data area) is up to 64, for example. Considering that it is necessary to prevent the number of data set in a predetermined area of the storage means from becoming 0, it is preferable that the number of data is two or more. Further, the number of luminance data that can be set in the FIFO data area is not limited to 64, and it is sufficient that at least two or more luminance data can be set. When the number of brightness data set in the FIFA data area is, for example, two or more, and the number of brightness data set in the FIFA data area is less than the first number (for example, two), the second number is obtained. The brightness data (for example, one) may be supplemented.

Further, according to the fourth gaming machine and the fifth gaming machine, it is possible to provide a gaming machine in which the player or the like can more preferably adjust the brightness of the light emitting device.

[Sixth game machine]
Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when a game ball wins a prize at the starting port, and a production image is displayed on a liquid crystal display or the like based on the result of this lottery.

As this type of gaming machine, there is known a gaming machine used for directing or decorating by emitting light in a predetermined mode from a light emitting device composed of a plurality of light emitting bodies such as LEDs provided on the front side. .. Further, there is disclosed a gaming machine in which the brightness of these light emitting devices can be adjusted by a player or the like within a preset range (see, for example, Japanese Patent Application Laid-Open No. 2008-295551).

(Fourth issue)
By the way, in recent years, the production has become flashy, including a light emitting device composed of a plurality of light emitting bodies such as LEDs provided on the front side. Therefore, if the intensity of the light received from the light emitting device is high, it may be stressful for some players.

In order to solve the fourth problem, a sixth gaming machine having the following configuration is provided.

(1) The sixth gaming machine is
The gaming machine according to the present invention
A first light emitting means (for example, a backlight) capable of emitting light in a predetermined embodiment,
An operating means (for example, a brightness setting screen displayed on a liquid crystal display device used as a display device 13) capable of changing the brightness of the first light emitting means to any one of a plurality of stages, and
A host control circuit that executes the process of step S394 (for example, a host control circuit that can change the brightness of the first light emitting means to any one of a plurality of stages based on the operation of the operating means. 210) and
A second light emitting means (for example, a panel side LED or a frame side LED) provided separately from the first light emitting means,
A second light emitting control means (for example, a host control circuit 210 that executes the process of step S406) capable of changing the light emitting mode of the second light emitting means, and
With
The second light emission control means
The mode of the light emitting effect executed by the second light emitting means is limited and executed at a timing different from the timing at which the brightness of the first light emitting means is changed based on the operation of the operating means. It is characterized by being configured to be possible.

According to the sixth gaming machine of the above (1), when the operating means capable of changing the brightness of the first light emitting means is operated, the mode of the light emitting effect executed by the second light emitting means is limited. .. Therefore, it is possible to suppress the intensity of the light received from the second light emitting means by a simple process.

(2) In the sixth gaming machine described in (1) above,
A data storage means (for example, a FIFO data area) that stores drive data corresponding to a light emitting mode emitted by the first light emitting means in a predetermined area, and
A light emitting drive means (for example, LSI) that outputs a control signal based on the drive data stored in the data storage means to the first light emitting means, and
A data setting means (for example, a host control circuit 210 that executes the process of step S346) for setting the drive data in a predetermined area of the data storage means, and
With
The data setting means is
When the number of drive data set in the predetermined area of the data storage means reaches the reference number of drive data that can be stored in the predetermined area, new drive data is set and new drive data is set.
When the operating means is operated, the driving data after the brightness is changed is set as the new driving data.

According to the fifth game machine of (2) above, when the number of drive data set in the predetermined data area becomes the reference data number, new drive data is set. Therefore, it is possible to output a control signal output by the light emitting driving means (for example, a signal equivalent to PWM continuously output from the serial data output terminal of SPI), and the light emitting means is stabilized without going through a driver. It becomes possible to make it emit light. Moreover, when the brightness is changed, the changed drive data is set as new drive data, so that the first light emitting means can be stably emitted according to the set brightness.

The above-mentioned "reference data number" corresponds to 1 to 64 data if the number of data that can be set in a predetermined area of the data storage means (for example, the FIFA data area) is up to 64, for example. Considering that it is necessary to prevent the number of data set in a predetermined area of the storage means from becoming 0, it is preferable that the number of data is two or more. Further, the number of luminance data that can be set in the FIFO data area is not limited to 64, and it is sufficient that at least two or more luminance data can be set. When the number of brightness data set in the FIFA data area is, for example, two or more, and the number of brightness data set in the FIFA data area is less than the first number (for example, two), the second number is obtained. The brightness data (for example, one) may be supplemented.

As described above, according to the sixth gaming machine, it is possible to provide a gaming machine in which the player or the like can suitably adjust the intensity of the light received from the light emitting device.

[7th game machine]
Conventionally, in a gaming machine such as a pachinko machine, for example, a gaming machine in which an effect depending on an RTC (real-time clock) is performed is known.

In this type of gaming machine, the RTC abnormality is determined when the power is turned on, and if there is an abnormality, the date and time are notified, and if an RTC abnormality is found, a gaming machine that can quickly deal with this is available. It is known (see, for example, Japanese Patent Application Laid-Open No. 2017-51853 (for example, paragraph [0094])).

(Fifth issue)
According to the gaming machine described in JP-A-2017-51853, if there is an abnormality in the RTC, the date and time will be notified, so there is a possibility that it can be dealt with quickly. There is a risk that it will not be possible to perform the production.

In order to solve the fifth problem, a seventh gaming machine having the following configuration is provided.

The seventh game machine is
A real-time clock (for example, RTC) that can output time information,
A time information management means (for example, a host control circuit 210 that executes the process of step S413) capable of acquiring time information from the real-time clock and updating the acquired time to the current time information.
An effect executing means (for example, host control circuit 210) capable of executing a specific effect (for example, RTC effect) based on the current time information being specific time information (for example, a designated time).
An abnormality determining means for determining an abnormality of the real-time clock (for example, a host control circuit 210 that executes the process of step S414) and
With
The time information management means
When it is determined that the real-time clock is abnormal, the previous time information previously acquired by the time information management means is maintained as the current time information (for example, step S415), and it is determined that the real-time clock is normal. Then, the previous time information can be updated to the current time information (for example, the process of step S416).
The effect executing means is
The specific effect is executed on the condition that the current time information is the specific time information (YES in step S417) and the previous time information and the current time information do not match (YES in step S418). ) Is characterized.

According to the seventh gaming machine, even if the RTC is abnormal, it is possible to preferably perform an effect depending on the RTC.

[8th game machine, 9th game machine]
Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when a game ball wins a prize at the starting port, and an effect image is displayed on a display device or the like based on the result of this lottery. If the result of the lottery is a big hit, the big hit game is started.

As this type of gaming machine, there is known a gaming machine that decodes compressed image data, appropriately converts the decoded image data, stores it in a frame buffer, and outputs it to a display device. (For example, Japanese Patent Application Laid-Open No. 2014-87402 (see, for example, paragraph [0100])).

(Sixth issue)
In recent years, the variation of the effect image displayed on the display device has increased, and the control of the effect image tends to be complicated. In such a case, it is desired to efficiently control the effect image.

In order to solve the sixth problem, the eighth gaming machine and the ninth gaming machine having the following configurations are provided.

The eighth gaming machine is
A gaming machine capable of executing a process of switching between functions (for example, bank flip) between a drawing output destination buffer having a drawing function and a frame buffer having a display function.
A registration means (for example, a display control circuit 230 capable of executing steps S449 and S458) capable of registering image information (for example, composition) related to an effect image displayed on a predetermined display means in the drawing output destination buffer). When,
After the drawing output destination buffer is switched to the frame buffer (for example, after the process of step S446 is performed), the effect image is displayed on the predetermined display means based on the image information registered by the registration means. An effect image display control means (for example, display control circuit 230) that controls the display, and
With
The registration means
When the image information registered in the frame buffer switched from the drawing output destination buffer includes image information for pausing the image (for example, when it is determined to be YES in step S447), the said. A first registration means (for example, a display control circuit 230 that executes the process of step S449) for registering image information in the drawing output destination buffer, and
Even if there is no image information registered in the drawing output destination buffer (for example, even if NO is determined in step S444), the effect image displayed in the predetermined display means is registered in the frame buffer. When the upper limit of the image information is reached (for example, when YES is determined in step S450), the second registration means (for example, step S458) for registering the image information in the drawing output destination buffer can be executed. It is characterized by having a display control circuit 230).

According to the eighth gaming machine, while the image information is registered on the condition that the image information is not registered, even if the image information is registered, the specific image information is included in the registered image information. Since the image information is registered when is included, it is possible to efficiently control the effect image.

The ninth gaming machine is
A plurality of display means (for example, a display) capable of reproducing a predetermined effect image, and
Display control means (for example, display control circuit 230) capable of controlling image information related to the effect image reproduced by the plurality of display means, and
With
The display control means
A layer number determination means (for example, a display control circuit 230 that executes the process of step S441) for determining the appropriateness of the number of layers related to the image information reproduced at the same time in the display means, and
When the number of layers is appropriate (for example, when YES is determined in step S441), the number of display means determining means (for example, step) for determining the appropriateness of the number of display means used for reproducing the effect image. The display control circuit 230) that executes the processing of S442 and
When the number of display means used for reproducing the effect image is appropriate (for example, when YES is determined in step S442), there is a display means for determining the existence of the display means for which the image information is to be registered. The determination means (for example, the display control circuit 230 that executes the process of step S443) and
When there is a display means for which the image information is to be registered (for example, when YES is determined in step S443), the image information registration means for registering the image information to be reproduced in the display means (for example, step S449). And a display control circuit 230) that executes the process of step S458, and
After the image information to be reproduced in one of the plurality of display means is registered by the image information registration means, the image information is registered in another display means different from the one display means. It is characterized in that the determination by the display means number determination means and the determination by the display means existence determination means (the process of step S459 is executed and then the process of returning to step S442 is performed).

According to the ninth gaming machine, when there are a plurality of display means and the number of layers required for the image information is appropriate, the image information related to the effect image displayed on one display means is registered, and then one. Since the image information related to the effect image displayed on the other display means different from the display means of is registered, the image information determined to have an appropriate number of layers can be efficiently registered.

As described above, according to the eighth gaming machine and the ninth gaming machine, it is possible to provide a gaming machine capable of efficiently controlling the effect image.

[10th game machine, 11th game machine]
Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when a game ball wins a prize at the starting port, and based on the result of this lottery, an effect image is displayed on, for example, a liquid crystal display. In addition to such an effect image, an audio effect is also output.

As this type of gaming machine, it is determined whether or not the timing for determining an abnormality of the digital amplifier has been reached. For example, when the operation determination timing determined at a time interval of about several seconds has been reached, the input port Pi2 is used. A gaming machine that acquires an abnormality notification signal ERR and determines whether or not the digital amplifier is at an abnormal level is known (see Japanese Patent Application Laid-Open No. 2016-209723 (for example, paragraphs [0178] and [0179])).

(7th issue)
In recent years, the content of the production has become more sophisticated and the interest has been improved by increasing the variation of the production image displayed on the liquid crystal display or the like. However, as the production content has become more sophisticated, the production content of the game sound has also tended to become more sophisticated, and in order to output a normal game sound, it is necessary to appropriately perform the determination process of the amplification device that amplifies the game sound. There is.

In order to solve the seventh problem, the tenth gaming machine and the eleventh gaming machine having the following configurations are provided.

(1) The tenth gaming machine is
A gaming machine capable of executing predetermined processing (for example, main processing, interrupt processing, etc.) every time a predetermined time elapses.
An output means capable of outputting game sounds (for example, a speaker 11) and
Amplifying means (for example, a digital audio power amplifier 262) capable of amplifying the game sound output from the output means, and
An abnormality determination means (for example, a host control circuit 210 that executes processing such as step S503, step S511, and step S515) that performs abnormality determination processing as to whether or not the amplification hand is normal, and
With
The abnormality determination means is
The abnormality determination process can be divided into a plurality of abnormality determination processes (for example, processes such as step S503, step S511, and step S515) and can be executed.
In one predetermined process (for example, one frame) executed within the predetermined time, a part of the abnormality determination process (for example, step S503, step S511, step S515) divided into a plurality of times is executed. It is characterized in that a part or all of the remaining abnormality determination processing can be executed in the predetermined processing from the next time onward.

According to the tenth gaming machine of the above (1), a part of the abnormality determination process of the amplification means (for example, a normal amplifier or a deep bass amplifier) is performed over a plurality of frames within a predetermined process (for example, one frame). Since this is performed, it is possible to execute all of the abnormality determination processing of each amplification means over a plurality of frames.

(2) Another example of the tenth gaming machine is
A gaming machine capable of executing predetermined processing (for example, main processing, interrupt processing, etc.) every time a predetermined time elapses.
An output means capable of outputting game sounds (for example, a speaker 11) and
Amplifying means (for example, a digital audio power amplifier 262) capable of amplifying the game sound output from the output means, and
A setting information confirmation means (for example, a host control circuit 210 that executes processing such as steps S506 to S507 and steps S522 to S523) for confirming setting information about the amplification means.
With
The setting information confirmation means is
The confirmation process can be divided into a plurality of confirmation processes and executed, and the confirmation process can be executed.
A part of the confirmation process (for example, the host control circuit 210 that executes the processes of steps S506 to S507, steps S522 to S523, etc.) in the one predetermined process executed within the predetermined time. Is executed, and a part or all of the remaining confirmation processing can be executed in the predetermined processing from the next time onward.

According to another example of the tenth gaming machine in (2) above, a part of the confirmation processing of the setting information of the amplification means (for example, a normal amplifier or a deep bass amplifier) within a predetermined process (for example, one frame). Since each is performed over a plurality of frames, it is possible to execute all of the confirmation processing of the setting information of each amplification means over a plurality of frames.

(1) The eleventh gaming machine is
A gaming machine capable of executing predetermined processing (for example, main processing, interrupt processing, etc.) every time a predetermined time elapses.
An output means capable of outputting game sounds (for example, a speaker 11) and
Amplifying means (for example, a digital audio power amplifier 262) capable of amplifying the game sound output from the output means, and
The abnormality determination process of whether or not the amplification means is normal can be executed by dividing it into a plurality of abnormality determination processes (for example, processing of check status = 0, 2, 3), and the plurality of abnormalities can be executed. An abnormality determination means (for example, a host control circuit 210 that executes processes such as step S503, step S511, and step S515) that performs the determination process a plurality of times over the predetermined process.
A progress management means for managing the progress of the abnormality determination process (for example, a host control circuit 210 for managing the check status) and
With
The progress management means
It is possible to determine whether or not one of the plurality of abnormality determination processes (for example, check status = 0, 2, and 3 processes) is completed in one predetermined process.
The abnormality determination means is
When the one abnormality determination process (for example, the process of check status 0) is completed in the one predetermined process, another abnormality determination process different from the one abnormality determination process is performed in the next and subsequent predetermined processes (for example, after the next frame). When the abnormality determination process (for example, the process of check status 2) is executed and the abnormality determination process (for example, the process of check status 0) is not completed in the one predetermined process, in the next and subsequent predetermined processes. It is characterized in that the one abnormality determination process (for example, the process of check status 0) can be executed again.

According to the eleventh gaming machine of the above (1), a part of the abnormality determination process of the amplification means (for example, a normal amplifier or a deep bass amplifier) is performed over a plurality of frames within a predetermined process (for example, one frame). Since this is performed, it is possible to execute all of the abnormality determination processing of each amplification means over a plurality of frames. Moreover, when one abnormality determination process is not completed in one predetermined process (for example, one frame main process or interrupt process), the one abnormality determination is performed in the next or subsequent (for example, next frame or later) predetermined process. Since the processing is executed again, any abnormality determination processing will be executed until it is completed.

(2) Another example of the eleventh gaming machine is
A gaming machine capable of executing predetermined processing (for example, main processing, interrupt processing, etc.) every time a predetermined time elapses.
An output means capable of outputting game sounds (for example, a speaker 11) and
Amplifying means (for example, a digital audio power amplifier 262) capable of amplifying the game sound output from the output means, and
The confirmation process of the setting information about the amplification means can be executed by dividing it into a plurality of confirmation processes (for example, a process of check status = 1, 5), and the plurality of confirmation processes can be performed a plurality of times of the predetermined process. Setting information confirmation means (for example, a host control circuit 210 that executes processing such as steps S506 to S507 and steps S522 to S523) and
A progress management means for managing the progress of the confirmation process of the setting information (for example, a host control circuit 210 for managing the check status) and
With
The progress management means
It is possible to determine whether or not one of the plurality of confirmation processes (for example, check status = 1,5 processes) is completed in one predetermined process.
The setting information confirmation means is
When the one confirmation process (for example, the process of check status = 1) is completed in the one predetermined process, another confirmation process different from the one confirmation process (for example, check status = 1) in the next and subsequent predetermined processes. 5) is executed, and when the one confirmation process is not completed in the one predetermined process, the one confirmation process can be executed again in the next and subsequent predetermined processes. ..

According to another example of the eleventh gaming machine in (2) above, a part of the confirmation processing of the setting information of the amplification means (for example, a normal amplifier or a deep bass amplifier) within a predetermined process (for example, one frame). Since each is performed over a plurality of frames, it is possible to execute all of the confirmation processing of the setting information of each amplification means over a plurality of frames. Moreover, when one confirmation process is not completed in one predetermined process (for example, main process or interrupt process of one frame), the one confirmation process is performed in the next or later (for example, next frame or later) predetermined process. Since it is executed again, each confirmation process will be executed until it is completed.

As described above, according to the tenth game machine and the eleventh game machine, it is possible to provide a game machine capable of appropriately performing the determination process of the amplification device.

[12th game machine, 13th game machine]
Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when a game ball wins a prize at the starting port, and based on the result of this lottery, an effect image is displayed on, for example, a liquid crystal display. In addition to such an effect image, a game sound is also output from the speaker.

As this type of gaming machine, there is disclosed a gaming machine that operates a simple access controller by writing a SAC number to a voice control register and outputs voice data such as game sounds from a voice memory (for example, Japanese Patent Application Laid-Open No. 2017-97971 (see).

(8th issue)
In recent years, as the variation of the production image has increased, the variation of the game sound has also increased. However, for example, when a plurality of game sounds overlap, the effect of the game sound may be halved.

In order to solve the eighth problem, a twelfth gaming machine and a thirteenth gaming machine having the following configurations are provided.

(1) The twelfth gaming machine is
Setting means (for example, host control circuit 210) that can assign and set sound information (for example, SAC number) related to game sound data to a channel, and
A sound output means (for example, a voice / LED control circuit) capable of outputting a game sound based on the sound information assigned to the channel, and
With
The setting means is
When allocating sound information to one channel, when a plurality of sound information is set to the one channel (for example, when it is determined to be YES in the process of step S542),
When the plurality of sound information is specific sound information (for example, SHOT reproduction and LOOP reproduction chain reproduction), the sound information of any one of the plurality of sound information (for example, loop reproduction) is provided for at least a predetermined time. A first setting means (for example, a host control circuit 210 that executes the process of step S544) for setting with a delay of (for example, one frame) or more, and
On condition that the plurality of sound information is non-specific sound information different from the specific sound information (for example, it is determined as NO in the process of step S543), the sound information is not delayed for the predetermined time or more (for example). For example, it is characterized by having a second setting means (for example, a host control circuit 210 that executes the processing of step S546 and step S547) for setting the plurality of sound information (in the frame).

According to the twelfth gaming machine of the above (1), when a plurality of sound information is set in one channel and the plurality of sound information is specific sound information, one of the sound information is used. Since it is set with a delay, the sound effect due to the delay (for example, the sound effect due to the muffling) can be enjoyed. On the other hand, if the plurality of sound information is non-specific sound information, the plurality of sound information is set without delay, so that the processing can be performed quickly. That is, by delaying or not delaying depending on the situation, it is possible to ensure the speed of processing while utilizing the game sound effect due to the delay.

(2) In the twelfth gaming machine described in (1) above,
The specific sound information is
It includes at least the first sound information (for example, SHOT reproduction) that is reproduced only once and the second sound information (LOOP reproduction) that is reproduced multiple times.
The first setting means is
It is characterized in that the second sound information can be set with a delay of a predetermined time or more after the first sound information is set.

According to the twelfth gaming machine of the above (2), the second sound information to be reproduced a plurality of times is set with a delay of a predetermined time or more after the first sound information to be reproduced only once is set. Therefore, it is possible to prevent the first sound information, which is reproduced only once, from becoming difficult to hear.

The thirteenth gaming machine is
Setting means (for example, voice / LED control circuit) that can assign sound information (for example, SAC number) related to game sound data to a channel and set it,
A sound output means capable of outputting a game sound based on the sound information assigned to the channel, and
With
The setting means is
When allocating sound information to one channel, when a plurality of sound information is set to the one channel (for example, when it is determined to be YES in the process of step S542),
When the plurality of sound information is specific sound information (for example, SHOT + loop chain reproduction), the sound information of any one of the plurality of sound information (for example, loop reproduction) is provided for at least a predetermined time (for example, loop reproduction). The first setting means (for example, the host control circuit 210 that executes the process of step S544) for setting with a delay of one frame or more, and
On condition that the plurality of sound information is non-specific sound information different from the specific sound information (for example, it is determined as NO in the process of step S543), the sound information is not delayed for the predetermined time or more (for example). For example, a second setting means (for example, a host control circuit 210 that executes the processing of step S546 or step S547) for setting the plurality of sound information (in the frame), and
Have,
The second setting means is
When mute is set for all channels (for example, when it is determined to be YES in the process of step S545), sound information is set without overwriting the mute setting (for example, the process of step S546 is performed). On the other hand, when the muffling setting is not for all channels but for one channel (for example, when NO is determined in step S545), the muffling setting is overwritten and the sound information is set (for example, step S547). It is characterized by being configured so that it can be processed.

According to the thirteenth gaming machine, when a plurality of sound information is set in one channel, if the plurality of sound information is specific sound information, one of the sound information is set with a delay. Therefore, it is possible to enjoy the sound effect by delaying (for example, the sound effect by muting). On the other hand, if the plurality of sound information is non-specific sound information, the plurality of sound information is set without delay, so that the processing can be performed quickly. That is, by delaying or not delaying depending on the situation, it is possible to ensure the speed of processing while utilizing the game sound effect due to the delay. Furthermore, when a plurality of sound information is non-specific sound information, when the mute setting is set for all channels, the sound information is set without overwriting the mute setting, and the mute setting is not set for all channels but one. When the mute setting is for a channel, the mute setting is overwritten and the sound information is set, so that the sound information is set for the required time (for example, until the change display of the next special symbol is started when the change display of the special symbol ends. ) Can be secured.

As described above, according to the twelfth gaming machine and the thirteenth gaming machine, it is possible to provide a gaming machine capable of suitably outputting the gaming sound.

[14th game machine]
Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when a game ball wins a prize at the starting port, and based on the result of this lottery, an effect image is displayed on, for example, a liquid crystal display. In addition to such an effect image, a game sound is also output from the speaker.

As this type of gaming machine, a gaming machine that outputs a sound that excites the game in conjunction with an effect image displayed on a liquid crystal display or the like is disclosed (see, for example, Japanese Patent Application Laid-Open No. 2014-144066).

(9th issue)
However, in the gaming machine described in Japanese Patent Application Laid-Open No. 2014-144066, the secondary volume is maintained at a fixed value and the volume of the production sound is controlled by the primary volume. Therefore, in order to increase the variation in the volume of the production sound. There is a limit.

In order to solve the ninth problem, a fourteenth gaming machine having the following configuration is provided.

(1) The 14th gaming machine is
An output means (for example, a speaker 11) capable of outputting a predetermined game sound, and
Sound data setting means (for example, host control circuit 210) capable of setting sound data (for example, voice data) related to the game sound output from the output means, and
A volume control means (for example, a host control circuit 210 that executes a sound request) having a plurality of playback channels (for example, CH1 to CH31) and capable of controlling the volume output from the output means,
With
The volume control means
A first volume control means (for example,) capable of changing information related to volume for all of the plurality of playback channels based on a predetermined operation (for example, a hardware switch operation or a screen operation by a user). , Volume control 281 by hardware switch, user volume control 282 by volume setting screen, and host control circuit 210) that executes debug volume control 283 during debugging.
A second volume control means (for example, a first playback channel primary control 284, a second playback channel primary control 285, and a second playback channel primary control 285,) capable of changing information related to the volume for each of the plurality of playback channels. The host control circuit 210)) that executes the volume control 286, 287, 288 built into the voice data, and
The volume output from the output means can be changed by multiplying the information related to the volume by the first volume control means and the information related to the volume by the second volume control means. ,
The second volume control means
Volume control (first playback channel primary control 284) that controls information related to the volume to be changed when the predetermined operation is performed for each playback channel, and
A volume that controls the output of information related to a certain volume (for example, an error sound or an alarm sound at the time of illegal activity) before and after the predetermined operation is performed for each playback channel. It is characterized in that the control (second reproduction channel primary control 285) and the control (second reproduction channel primary control 285) can be executed.

According to the 14th gaming machine of the above (1), the gaming sound output from the output means is a combination of the information related to the volume by the first volume control means and the information related to the volume by the second volume control means. Therefore, it is possible to give diversity to the volume of the game sound. Moreover, the second volume control means controls each reproduction channel so that even if a predetermined operation is performed, information related to a certain volume is output before and after the operation is performed. As a result, even if a predetermined operation is performed, it is possible to control the output of information related to a certain volume before and after the operation is performed only on a specific playback channel instead of the entire channel. ..

(2) In the 14th gaming machine described in (1) above,
The first volume control means
The feature is that the information related to the volume can be controlled by the debug volume control at the time of debugging.

According to the 14th gaming machine of the above (2), the gaming sound data used in the game can be used as it is at the time of debugging, and the work efficiency at the time of debugging can be improved.

Further, according to the fourteenth gaming machine, it is possible to provide a gaming machine capable of giving a variety of variations in the volume of the effect sound.

[15th to 19th gaming machines]
Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when a game ball wins a prize at the starting port, and based on the result of this lottery, an effect image is displayed on, for example, a liquid crystal display. In addition to such an effect image, a game sound is also output from the speaker.

As this type of gaming machine, a gaming machine capable of adjusting the volume of the gaming sound output from the speaker by the operation of the player is disclosed (see, for example, Japanese Patent Application Laid-Open No. 2011-229766).

(10th issue)
However, if the volume of the game sound output from the speaker can be adjusted by operating the game sound, it may affect sounds that you do not want to change, such as error sounds and warning sounds. , Not preferable.

In order to solve the tenth problem, the fifteenth to nineteenth gaming machines having the following configurations are provided.

(1) The fifteenth gaming machine is
A plurality of output means (for example, a speaker 11) capable of outputting a predetermined game sound, and
An operating means (for example, a volume setting screen) capable of controlling the volume output from the output means,
A sound control means (for example, a host control circuit 210 that executes a sound request control process) capable of controlling the volume based on the operation of the operation means, and
With
The volume output from the output means is output by at least the first information (for example, the second reproduction channel primary control 285) having constant volume information before and after the operation is performed even if the operation means is operated. (Audio signal to be output) and second information (for example, an audio signal output by the first playback channel primary control 284) having volume information changed based on the operation of the operating means. Being done
The plurality of output means include a dedicated output means used for outputting a specific sound (for example, a dedicated speaker) and a shared output means used for outputting sounds other than the specific sound (for example, a shared speaker). And at least are included,
The sound control means
Regarding the dedicated output means, even if the operation means is operated, the specific sound control means (for example, a step) capable of executing control to output the first information so that a constant volume is output before and after the operation is performed. The host control circuit 210) that executes S559 and
Regarding the shared output means, a non-specific sound control means (for example, a host that executes step S558) that can execute control to output the second information so that the volume is changed based on the operation of the operation means. It is characterized by having a control circuit 210).

According to the fifteenth gaming machine of (1) above, the dedicated output means used for outputting a specific sound is constant before and after the operation is performed even if the operator who can control the volume is operated. The volume is controlled to be output. That is, although the volume can be controlled, a constant volume is output without changing the volume before and after the operation of the operating means. Further, as for the shared output means used for outputting sounds other than a specific sound, the second information whose volume information is changed based on the operation of the operator who can control the volume is output. It becomes possible to preferably adjust the volume.

(2) In the fifteenth gaming machine described in (1) above,
The dedicated output means is a speaker for vibration.

According to the fifteenth gaming machine of the above (2), it is possible to output a specific sound (for example, an error sound, a warning sound, etc.) from the vibration speaker at a constant volume.

(3) In the gaming machine of (1) or (2) above
When the power is turned on (for example, during various initialization processes of step S201), the dedicated output setting means (for example, the process of step S201) for setting which of the plurality of output means is to be the dedicated output means is executed. Host control circuit 210)
The data related to the specific sound (for example, the voice data related to the specific sound specified by the SAC number) is characterized in that it is specified that the output destination of the specific sound is the dedicated output means. And.

According to the gaming machine of (3) above, when the power is turned on, the output destination of the data related to a specific sound is defined by the dedicated output means, so it is possible to set which output means is used as the dedicated output means. At the same time, since it is stipulated that the audio data related to a specific sound to which a constant volume is output is output from the dedicated output means, it is possible to enhance the versatility.

(1) The 16th gaming machine is
An output means (for example, a speaker 11) capable of outputting a predetermined game sound, and
An operating means (for example, a volume setting screen) capable of controlling the volume output from the output means,
A sound control means (for example, a host control circuit 210 that executes a sound request control process) having a plurality of playback channels and capable of controlling the volume based on the operation of the operation means.
With
The volume output from the output means is output by at least the first information (for example, the second reproduction channel primary control 285) having constant volume information before and after the operation is performed even if the operation means is operated. (Audio signal to be output) and second information (for example, an audio signal output by the first playback channel primary control 284) having volume information changed based on the operation of the operating means. Being done
The plurality of playback channels include at least a dedicated channel used for outputting a specific sound and a shared channel used for outputting sounds other than the specific sound.
The sound control means
Regarding the dedicated channel, even if the operation means is operated, the specific sound control means (for example, step S580) that can execute the control to output the first information so that a constant volume is output before and after the operation is performed. Host control circuit 210) that executes
Regarding the shared channel, a non-specific sound control means (for example, a host control for executing step S581) capable of executing control to output the second information so that the volume is changed based on the operation of the operation means. It is characterized by having a circuit 210).

According to the 16th gaming machine of (1) above, even if the operating means is operated for the dedicated channel used for outputting a specific sound, a constant volume is output before and after the operation is performed. Be controlled. That is, although the volume can be controlled, constant volume information is output without changing the volume before and after the operation of the operating means. In addition, for shared channels used to output sounds other than specific sounds, it is preferable to adjust the volume because the volume is controlled so that it is changed based on the operation of the operator who can control the volume. It becomes possible to do it.

(2) In the 16th gaming machine described in (1) above,
When the power is turned on, a dedicated channel (for example, CH31, CH32) used for outputting the specific sound and a shared channel (for example, CH1 to CH30) used for outputting sounds other than the specific sound are set. Channel setting means (for example, host control circuit 210 that executes the process of step S201) and
Sound information registration means (for example, a host for registering a SAC number) for registering sound information (for example, SAC number) related to data of the specific sound and sounds other than the specific sound to the dedicated channel or the shared channel. Control circuit 210) and
Is further provided.

According to the 16th game machine of (2) above, when the power is turned on, a dedicated channel used for outputting a specific sound and a shared channel used for outputting a sound other than the specific sound are set. At the same time, since the sound information related to the data of the specific sound and the sound other than the specific sound is registered in each channel, it is possible to enhance the versatility.

The 17th gaming machine is
An output means (for example, a speaker 11) capable of outputting a predetermined game sound, and
An operating means (for example, a volume setting screen) capable of controlling the volume output from the output means,
A sound control means (for example, a host control circuit 210 that executes a sound request control process) having a playback channel and capable of controlling the volume based on the operation of the operation means.
With
The volume output from the output means is output by at least the first information (for example, the second reproduction channel primary control 285) having constant volume information before and after the operation is performed even if the operation means is operated. (Audio signal to be output) and second information (for example, an audio signal output by the first playback channel primary control 284) having volume information changed based on the operation of the operating means. Being done
The sound control means
A data determination means (for example, a host control circuit 210 that executes step S599) for determining whether or not the data of the game sound being reproduced on the reproduction channel is the specific data of the specific sound, and
When the data discriminating means determines that the data of the game sound being played on the playback channel is the specific data, a constant volume is output before and after the operation even if the operating means is operated. Specific sound control means (for example, a host control circuit 210 that executes step S600) capable of executing control to output the first information, and
When the data discriminating means determines that the data of the game sound being played on the playback channel is non-specific data, the second information is changed so that the volume is changed based on the operation of the operating means. It is characterized by having a non-specific sound control means (for example, a host control circuit 210 that executes step S601) capable of executing output control.

According to the seventeenth gaming machine, when it is determined that the data of the gaming sound being played is specific data, even if the operating means is operated, a constant volume is output before and after the operation is performed. At the same time, when it is determined that the data of the gaming sound being played is non-specific data, the volume is controlled to be changed based on the operation of the operating means, so that the volume adjustment is preferable. It becomes possible to do.

The 18th gaming machine is
An output means (for example, a speaker 11) capable of outputting a predetermined game sound, and
An operating means (for example, a volume setting screen) capable of controlling the volume output from the output means,
A sound control means (for example, a host control circuit 210 that executes a sound request control process) having a playback channel and capable of controlling the volume based on the operation of the operation means.
With
The volume output from the output means is output by at least the first information (for example, the second reproduction channel primary control 285) having constant volume information before and after the operation is performed even if the operation means is operated. (Audio signal to be output) and second information (for example, an audio signal output by the first playback channel primary control 284) having volume information changed based on the operation of the operating means. Being done
The sound control means
When the sound information (for example, SAC number) corresponding to the sound output reproduced in the reproduction channel is specific sound information, a constant volume is output before and after the operation is performed even if the operation means is operated. The specific sound control means (for example, the host control circuit 210 that executes step S621) capable of setting the first information in the reproduction channel, and
When the sound information (for example, SAC number) corresponding to the game sound reproduced on the reproduction channel is non-specific sound information, the reproduction is performed so that the volume is changed based on the operation of the operation means. It is characterized by having a non-specific sound control means capable of setting the second information in a channel (for example, a host control circuit 210 for executing step S623).

According to the eighteenth gaming machine, if the sound information (for example, SAC number) corresponding to the sound output reproduced on the reproduction channel is specific sound information, a constant volume is output even if the operating means is operated. If the sound information (for example, SAC number) corresponding to the game sound played on the playback channel is non-specific sound information, the volume is changed based on the operation of the operating means. Therefore, it is possible to preferably adjust the volume.

The 19th gaming machine is
An output means (for example, a speaker 11) capable of outputting a predetermined game sound, and
An operating means (for example, a volume setting screen) capable of controlling the volume output from the output means,
A sound control means (for example, a host control circuit 210 that executes a sound request control process) having a playback channel and capable of controlling the volume based on the operation of the operation means.
With
The volume output from the output means is output by at least the first information (for example, the second reproduction channel primary control 285) having constant volume information before and after the operation is performed even if the operation means is operated. (Voice signal to be output), second information having volume information changed based on the operation of the operation means (for example, an audio signal output by the first reproduction channel primary control 284), and the above. Third information having volume information incorporated in the sound data specified from the sound information registered in the reproduction channel (for example, an audio signal output by volume control 286, 287, 288 incorporated in the audio data. ) And
The sound control means
When the sound data specified from the sound information (for example, SAC number) registered in the reproduction channel is specific sound data (for example, sound data that is not affected by the volume adjustment), the specific sound data is used. With identification information setting means (for example, a host control circuit 210 that executes the process of step S632) that presets identification information (for example, a flag indicating whether or not each channel is affected by volume adjustment) that can be identified as being present. ,
When setting the volume of the playback channel, when the sound data specified from the sound information (for example, SAC number) can be identified as the specific sound data by the identification information (for example, YES in step S637). (When), even if the operation means is operated, the first volume setting means (for example, step) in which the first information can be set to the playback channel so that a constant volume is output before and after the operation is performed. A host control circuit 210) capable of executing the processing of S641 and
When setting the volume of the playback channel, when the sound data specified from the sound information can be identified by the identification information if it is not the specific sound data (for example, when it is determined as NO in step S637), the operation. A second volume setting means (for example, a host control circuit 210 capable of executing the process of step S638) capable of setting the second information to the reproduction channel so that the volume is changed based on the operation of the means.
When setting the volume in the reproduction channel, it is characterized by having a third volume setting means (for example, a host control circuit 210 capable of executing the process of step S644) for setting the third information in the reproduction channel.

According to the nineteenth game machine, identification information that can identify that the sound data specified from the sound information registered in the reproduction channel is the specific sound data is set in advance, and the sound information specified from the sound information is set. When it can be identified by the identification information that is specific sound data, it is set so that a constant volume is output even if the operating means is operated. In addition, the volume is set to be changed based on the sound data specified from the sound information registered in the playback channel. Further, the third information having the volume information incorporated in the sound data specified from the sound information registered in the reproduction channel is set in the reproduction channel. In this way, the volume can be preferably adjusted.

In the above-mentioned gaming machine, when the sound data specified from the sound information (for example, SAC number) registered in the reproduction channel can be identified as the specific sound data by the identification information (for example, YES in step S637). Even if the operating means is operated, a constant volume is output before and after the operation is performed. However, the constant volume in this case is always information related to the maximum volume. Is also good. However, even if the sound data specified from the sound information registered in the playback channel is specific sound data (first information related to a certain volume), the sound information registered in the playback channel (for example, SAC number). The output volume may not be constant because it is multiplied by the volume embedded in the sound data specified from).

As described above, according to the fifteenth to nineteenth gaming machines, it is possible to provide a gaming machine capable of suitably adjusting the volume.

[20th gaming machine]
Conventionally, in a game machine such as a pachinko machine, a game is known in which a light emitting means composed of a light emitting body such as an LED is provided on the front side of the game machine, and the light emitting means is turned on or blinked in a predetermined mode. ing.

As this type of gaming machine, there is known a gaming machine in which the brightness of the light emitting means can be adjusted by, for example, an operation by a player or the like (see, for example, Japanese Patent Application Laid-Open No. 2008-295551).

(11th issue)
According to the gaming machine described in JP-A-2008-295551, the brightness of the light emitting means can be challenged by an operation by a player or the like, but when the light emitting means can emit light in full color, it emits light when the brightness is changed. Even the color may change significantly.

In order to solve the eleventh problem, the twentieth gaming machine having the following configuration is provided.

The 20th gaming machine is
With a predetermined light emitting means (for example, lamp (LED) group 18),
An operating means that can be operated so that the brightness of the light emitting means can be selected (for example, a brightness setting screen displayed on a liquid crystal display device used as the display device 13).
A storage means (for example, an attenuation table) that stores a luminance information table (for example, an attenuation table) in which luminance information is set for each of a plurality of colors (for example, RGB) as the luminance information (for example, the luminance attenuation factor) related to the luminance of the light emitting means. Sub-main ROM205) and
When the luminance is selected by the operating means, the luminance control means (for example, the host control circuit 210) capable of controlling the luminance of the light emitting means based on the luminance information table, and
With
The storage means
A luminance information table in which the luminance information is set for each of the plurality of colors is stored according to the luminance that can be selected by the operating means.
The brightness control means is
Based on the luminance information table corresponding to the luminance selected by the operating means, the luminance of the light emitting means can be controlled so that the attenuation rate of blue is the largest and the attenuation rate of red is the smallest among the plurality of colors. It is characterized by being configured in.

According to the twentieth game machine, light emission of the light emitting means is made so that the blue attenuation rate is the largest and the red attenuation rate is the smallest among the plurality of colors based on the luminance information set for each of the plurality of colors. Is controlled, for example, even if the brightness of the light emitting means is changed by an operation of a player or the like, it is possible to suppress the change in the light emitting color, that is, to maintain the white balance.

As described above, according to the twentieth gaming machine, it is possible to provide a gaming machine capable of changing the brightness while suppressing the change in the emission color.

[21st game machine]
Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when a game ball wins a prize at the starting port, and based on the result of this lottery, an effect image is displayed on, for example, a liquid crystal display.

As this type of gaming machine, a gaming machine in which a movable body is arranged on a gaming board and the movable body is operated to give an impact to the player and increase the motivation for the game has been proposed. (See, for example, Japanese Patent Application Laid-Open No. 2006-288649).

(12th issue)
For example, in a gaming machine in which a movable body is operated as in JP-A-2006-288649, the movement of the movable body has been diversified in recent years, and the control for operating the movable body has become complicated accordingly. Therefore, in recent years, there has been a demand for a gaming machine capable of suppressing a control load while giving diversity to the movement of a movable body.

In order to solve the 21st problem, the 21st gaming machine having the following configuration is provided.

The 21st gaming machine is
With the prescribed character
A control means (for example, a host control circuit 210) capable of controlling the operation of the predetermined accessory, and
An operating member (for example, a solenoid) capable of operating a member constituting the accessory, and
With multiple light emitting means (eg, LEDs),
A plurality of connection portions (for example, Port0 to Port23) capable of transmitting a signal to the connected light emitting means by being connected to any of the plurality of light emitting means.
A light emitting control means (for example, a voice / LED control circuit 220) capable of controlling the light emitting means by transmitting a signal to the light emitting means through the connecting portion, and
With
The operating member
It is connected to any one of the plurality of connecting portions, and is configured to be able to operate a member constituting the accessory by a signal from the light emitting control means.
The control means
It is characterized in that the operating member connected to any one of the plurality of connecting portions can be operated in synchronization with the predetermined accessory.

According to the 21st gaming machine, even if the number of operating members increases due to the diversification of the movement of the accessory, the control load for operating the accessory is maintained while maintaining the diversity of the movement of the accessory. While suppressing it, it becomes possible to synchronize the accessory and the operating member.

As described above, according to the 21st gaming machine, it is possible to provide a gaming machine capable of suppressing the control load.

[22nd game machine]
Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when a game ball wins a prize at the starting port, and based on the result of this lottery, an effect image is displayed on, for example, a liquid crystal display.

As this type of gaming machine, image data to be read from a CGROM that stores compressed data of still images and moving images displayed on a liquid crystal display, decompress the read compressed data, and output to the liquid crystal display. Is known (see, for example, Japanese Patent Application Laid-Open No. 2016-159026).

(13th issue)
However, as described in Japanese Patent Application Laid-Open No. 2016-159026, for example, when the compressed data is read from the CGROM and the image data to be output is generated, if the amount of data is large, the loading process takes time. .. In this case, the watchdog reset may be applied even though the load process is proceeding normally, which is not preferable.

In order to solve the thirteenth problem, a twelfth gaming machine having the following configuration is provided.

(1) The 22nd gaming machine is
A read-only storage area (for example, sub-main 205 or CGROM 206) in which game data related to the game is stored, and
A volatile storage area (for example, SRAM 210b or built-in VRAM 237) that can read and write game data related to the game, and
A transfer execution means (for example, a host control circuit 210 that executes the data load process of FIG. 68) that executes a load process that reads the game data stored in the read-only storage area and writes the game data to the volatile storage area.
Watchdog timer and
A clearing means (for example, a host control circuit 210 having a CPU processor) that clears the clock of the watchdog timer after a lapse of a predetermined time, and
With
The transfer executing means is
It is characterized by having a load reprocessing means (host control circuit 210 that executes the process of step S656) that resets the watchdog timer when the load process exceeds a predetermined time and executes the load process again.

According to the 22nd gaming machine of (1) above, when the time required for the load processing by the transfer executing means exceeds a predetermined upper limit, the load process is terminated and the load process is executed again. Even if it takes time for the load process, it can be automatically restored.

As described above, according to the 22nd gaming machine, even when the loading process takes time, the loading process can be suitably advanced.

(2) In the 22nd gaming machine described in (1) above,
The clearing means
When the load process does not exceed the predetermined time, the watchdog timer is cleared (for example, the process of step S655), and only when the load process exceeds the predetermined time, the watchdog timer is clocked. It is configured so that error processing (for example, processing in step S656) is executed without clearing.
The transfer executing means is
It is characterized in that the load process is executed again as the error process.

According to the 22nd gaming machine of (2) above, the watchdog timer is cleared when the load process does not exceed the predetermined time, while the watchdog timer is set only when the load process exceeds the predetermined time. Since the error processing is executed without clearing, it is possible to grasp that the loading processing could not be completed due to the occurrence of the error.

[23rd game machine, 24th game machine]
Conventionally, in a gaming machine such as a pachinko machine, a lottery is performed when a game ball wins a prize at the starting port, and a big hit game is performed when the result of the lottery is a big hit. Further, for example, a liquid crystal display for displaying the effect image is provided, and the effect image determined by lottery is displayed on the liquid crystal display.

In this type of gaming machine, lottery is performed in various situations, and the lottery is performed by generating and acquiring random numbers. For example, in Japanese Patent Application Laid-Open No. 2017-023629, the number of digits of a newly acquired random number value is determined, one digit is calculated from the reference random number value by the determined number of digits, and the calculated value is used as each digit. It describes how to place and get new numbers.

(14th issue)
In the random number acquisition process for acquiring random numbers, it is required that the acquired random numbers are less likely to have regularity. However, if the processing is complicated, the control load becomes large, which is not preferable. Therefore, it is preferable to perform a random number acquisition process in which regularity is unlikely to occur while suppressing an increase in the control load.

In order to solve the 14th problem, the 23rd gaming machine and the 24th gaming machine having the following configurations are provided.

The 23rd gaming machine is
A gaming machine that draws lots using a predetermined random number.
A real-time clock (for example, RTC) that can output time information,
A random number generating means for generating a random number used in a predetermined lottery (for example, a host control circuit 210 that executes the processes of FIGS. 70 and 71) and
With
The random number generating means
An initialization means (for example, a host control circuit 210 that executes a random number initialization process) that acquires time information from the real-time clock and generates an initial value of a random number using the acquired time information.
A non-stationary update means (host control circuit 210 that executes the process of FIG. 71) that updates the random number when the generated random number is used in the lottery, and
A steady-state update means (host control circuit 210 that executes the process of FIG. 70) that periodically updates the random numbers even if the generated random numbers are not used in the lottery.
It is characterized by that.

According to the 23rd gaming machine, since the initial value of the random number is generated using the time information acquired from the real-time clock, the acquired random number can be randomized, and the acquired random number is biased. Can be suppressed. In particular, since the initial value of the random number is involved in the time when the power is turned on in units of minutes and seconds, it is possible to make the initial value different each time.

The 24th gaming machine is
A gaming machine that draws lots using a predetermined random number.
A random number table creating means (for example, step S704) for creating a random number table in which a plurality of random numbers are registered by using one of a plurality of random number seeds (for example, random number seeds a to h) is executed. Host control circuit 210) and
Random number acquisition means for acquiring random numbers to be subjected to a predetermined lottery with reference to the random number table created by the random number table creation means (for example, in the random number acquisition process of step S706, from the random number table created in step S704). Host control circuit 210) that acquires random numbers and
Reference position updating means for updating the reference position of the random number table at a timing different from the timing at which the random number table is created (in step S706, when a random number is acquired from the random number table, the host control circuit updates the reference position of the random number table. 210) and
With
The random number acquisition means
After acquiring a random number by referring to the random number table, it is possible to acquire a random number to be subjected to the predetermined lottery by referring to the same random number table whose reference position has been updated without creating the random number table (for example). It is characterized in that it is configured in the packet reception loop of FIG. 73 and the random number acquisition process of step S706 can be executed).

According to the 24th gaming machine, even if there are multiple random number acquisition opportunities, the reference position is only updated using the same random number table that has already been created to acquire the random numbers. It is possible to reduce the control load while maintaining irregularity.

As described above, according to the twelfth gaming machine and the thirteenth gaming machine, it is possible to provide a gaming machine capable of suitably outputting the gaming sound.

As described above, according to the 23rd and 24th gaming machines, it is possible to provide a gaming machine capable of performing processing in which regularity is unlikely to occur while suppressing an increase in the control load.

Further, according to the first to 24th gaming machines, it is possible to preferably provide a gaming machine capable of suppressing a decrease in interest.

1 Pachinko game machine (game machine)
2 Main body 3 Base door 4 Glass door 11 Speaker 11a Speaker box 11b Connection terminal group 12 Game board 13 Display device 15 Launcher 16 Payout device 18 Lamp (LED) group 20 Accessory 43 Ball passage detector 44 1st start port 45th 2 Starting port 46 Ordinary electric accessory 51, 52 General winning opening 53 1st big winning opening 54 2nd big winning opening 55 Out opening 56 Game nail 61 Special symbol display device 62 Ordinary symbol display device 63 Ordinary symbol holding display device 64 1 Special symbol hold display device 65 2nd special symbol hold display device 70 Main control circuit 71 Main CPU
72 Main ROM
73 Main RAM
77 One-chip microcomputer 123 Payout / launch control circuit 200 Sub control circuit 201 Relay board 202 Sub board 203 Control ROM board 204, 204a, 204b CG ROM board 205 Sub main ROM
206, 206a, 206b CGROM
210 Host control circuit 210a Subwork RAM
210b SRAM
220 Audio / LED control circuit 230 Display control circuit 262 Digital audio power amplifier

Claims (1)

A gaming machine that draws lots using a predetermined random number.
A real-time clock that can output time information and
Random number generation means that generates random numbers used in a predetermined lottery,
With
The random number generating means
An initialization means that acquires time information from the real-time clock and generates an initial value of a random number using the acquired time information.
A steady update means that periodically updates the random number at a predetermined cycle regardless of whether or not the generated random number is used in the lottery.
An unsteady update means for updating a random number when the generated random number is used in the lottery even if the period is not the predetermined period.
A gaming machine characterized by having.

Images