JP6829665B2 - リードフレーム、半導体装置、及びリードフレームの製造方法 - Google Patents
リードフレーム、半導体装置、及びリードフレームの製造方法 Download PDFInfo
- Publication number
- JP6829665B2 JP6829665B2 JP2017134746A JP2017134746A JP6829665B2 JP 6829665 B2 JP6829665 B2 JP 6829665B2 JP 2017134746 A JP2017134746 A JP 2017134746A JP 2017134746 A JP2017134746 A JP 2017134746A JP 6829665 B2 JP6829665 B2 JP 6829665B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- lead frame
- silver
- metal plate
- silver film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017134746A JP6829665B2 (ja) | 2017-07-10 | 2017-07-10 | リードフレーム、半導体装置、及びリードフレームの製造方法 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2017134746A JP6829665B2 (ja) | 2017-07-10 | 2017-07-10 | リードフレーム、半導体装置、及びリードフレームの製造方法 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019016740A JP2019016740A (ja) | 2019-01-31 |
| JP2019016740A5 JP2019016740A5 (enExample) | 2020-04-09 |
| JP6829665B2 true JP6829665B2 (ja) | 2021-02-10 |
Family
ID=65356567
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017134746A Active JP6829665B2 (ja) | 2017-07-10 | 2017-07-10 | リードフレーム、半導体装置、及びリードフレームの製造方法 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP6829665B2 (enExample) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP7293682B2 (ja) * | 2018-12-12 | 2023-06-20 | 株式会社三洋物産 | 遊技機 |
| JP2020093053A (ja) * | 2018-12-12 | 2020-06-18 | 株式会社三洋物産 | 遊技機 |
| JP2020093052A (ja) * | 2018-12-12 | 2020-06-18 | 株式会社三洋物産 | 遊技機 |
| JP2020093050A (ja) * | 2018-12-12 | 2020-06-18 | 株式会社三洋物産 | 遊技機 |
| JP2020093049A (ja) * | 2018-12-12 | 2020-06-18 | 株式会社三洋物産 | 遊技機 |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0613516A (ja) * | 1992-05-26 | 1994-01-21 | Nippon Steel Corp | リードフレームの製造方法 |
| JP4269595B2 (ja) * | 2002-08-23 | 2009-05-27 | トヨタ自動車株式会社 | 酸化物半導体電極及びその製造方法 |
| US20080318061A1 (en) * | 2007-06-20 | 2008-12-25 | Akira Inaba | Insulation paste for a metal core substrate and electronic device |
| TW201250964A (en) * | 2011-01-27 | 2012-12-16 | Dainippon Printing Co Ltd | Resin-attached lead frame, method for manufacturing same, and lead frame |
| JP5456209B2 (ja) * | 2011-08-01 | 2014-03-26 | 株式会社Steq | 半導体装置及びその製造方法 |
-
2017
- 2017-07-10 JP JP2017134746A patent/JP6829665B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| JP2019016740A (ja) | 2019-01-31 |
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