JP6829665B2 - リードフレーム、半導体装置、及びリードフレームの製造方法 - Google Patents

リードフレーム、半導体装置、及びリードフレームの製造方法 Download PDF

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Publication number
JP6829665B2
JP6829665B2 JP2017134746A JP2017134746A JP6829665B2 JP 6829665 B2 JP6829665 B2 JP 6829665B2 JP 2017134746 A JP2017134746 A JP 2017134746A JP 2017134746 A JP2017134746 A JP 2017134746A JP 6829665 B2 JP6829665 B2 JP 6829665B2
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JP
Japan
Prior art keywords
film
lead frame
silver
metal plate
silver film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017134746A
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English (en)
Japanese (ja)
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JP2019016740A (ja
JP2019016740A5 (enrdf_load_html_response
Inventor
陽子 中林
陽子 中林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
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Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2017134746A priority Critical patent/JP6829665B2/ja
Publication of JP2019016740A publication Critical patent/JP2019016740A/ja
Publication of JP2019016740A5 publication Critical patent/JP2019016740A5/ja
Application granted granted Critical
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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
JP2017134746A 2017-07-10 2017-07-10 リードフレーム、半導体装置、及びリードフレームの製造方法 Active JP6829665B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2017134746A JP6829665B2 (ja) 2017-07-10 2017-07-10 リードフレーム、半導体装置、及びリードフレームの製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2017134746A JP6829665B2 (ja) 2017-07-10 2017-07-10 リードフレーム、半導体装置、及びリードフレームの製造方法

Publications (3)

Publication Number Publication Date
JP2019016740A JP2019016740A (ja) 2019-01-31
JP2019016740A5 JP2019016740A5 (enrdf_load_html_response) 2020-04-09
JP6829665B2 true JP6829665B2 (ja) 2021-02-10

Family

ID=65356567

Family Applications (1)

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JP2017134746A Active JP6829665B2 (ja) 2017-07-10 2017-07-10 リードフレーム、半導体装置、及びリードフレームの製造方法

Country Status (1)

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JP (1) JP6829665B2 (enrdf_load_html_response)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7293682B2 (ja) * 2018-12-12 2023-06-20 株式会社三洋物産 遊技機
JP2020093053A (ja) * 2018-12-12 2020-06-18 株式会社三洋物産 遊技機
JP2020093052A (ja) * 2018-12-12 2020-06-18 株式会社三洋物産 遊技機
JP2020093050A (ja) * 2018-12-12 2020-06-18 株式会社三洋物産 遊技機
JP2020093049A (ja) * 2018-12-12 2020-06-18 株式会社三洋物産 遊技機

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0613516A (ja) * 1992-05-26 1994-01-21 Nippon Steel Corp リードフレームの製造方法
JP4269595B2 (ja) * 2002-08-23 2009-05-27 トヨタ自動車株式会社 酸化物半導体電極及びその製造方法
US20080318061A1 (en) * 2007-06-20 2008-12-25 Akira Inaba Insulation paste for a metal core substrate and electronic device
TW201250964A (en) * 2011-01-27 2012-12-16 Dainippon Printing Co Ltd Resin-attached lead frame, method for manufacturing same, and lead frame
JP5456209B2 (ja) * 2011-08-01 2014-03-26 株式会社Steq 半導体装置及びその製造方法

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Publication number Publication date
JP2019016740A (ja) 2019-01-31

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