JP6775193B2 - Multi-phase power conversion circuit - Google Patents

Description

The present invention relates to a polyphase power conversion circuit.

In a high-power DC-DC conversion circuit, when high-frequency switching is difficult due to the restrictions of the switching device used, an interleaved circuit configuration may be used in order to improve the quality of the input current and output voltage of the conversion circuit. In an interleaved DC-DC converter, the current of each phase may become unbalanced due to variations in elements such as switches and coils that make up the circuit of each phase. Therefore, as in the example of the n-phase interleaved bidirectional DC-DC conversion circuit shown in FIG. 16 and the three-phase interleaved bidirectional DC-DC conversion circuit shown in FIG. 17, a current sensor is usually attached to each phase. current value _i 1 obtained from the _sensor, i _2, i 3, the current control is performed using a ... _{i n.} Regarding the current balance control of the inductor of each phase concerning the three-phase interleaved boost chopper circuit, for example, there is a method shown in Non-Patent Document 1.

By the way, in an inverter for driving an AC motor, a method of detecting a value of a DC link current by a current sensor or a shunt resistor to obtain a three-phase current has been proposed in Patent Document 1 and the like. In the case of a general AC motor, the sum of the three-phase currents becomes zero on the connection, so estimation is easy.

In recent years, residential electric systems and electric vehicles have become widespread, and the batteries of electric vehicles can be used as household power sources or as household power sources on a daily basis not only in emergencies such as power outages but also in normal times. It is considered to charge the battery of an electric vehicle.

Takahiro Kawashima, Masayoshi Yamamoto, Shigeyuki Funabiki, Mamoru Tsuruya: "Current Equilibrium Control of Interleaved Chopper Circuit", 2006 Annual Meeting of the Chugoku Chapter of the Electrical and Information Society, p.484

Japanese Unexamined Patent Publication No. 2003-219678

In an interleaved DC-DC power conversion circuit, due to variations in the characteristics of the elements constituting the circuit, even if the switches of each phase are driven with the same duty ratio, the current of each phase becomes unbalanced. As a countermeasure, a method of detecting and controlling the current flowing through each phase by a current sensor has been proposed (see FIGS. 16 and 17). However, this method has a problem that the cost increases by attaching a current sensor to each phase.

In order to solve this problem, a method of reproducing a three-phase AC current can be considered as a method of driving the AC motor by considering the DC link current and the conduction / non-conduction state of the switch proposed in Patent Document 1. However, in an interleaved DC-DC conversion circuit or a circuit that has multiple power supplies and has a common high-voltage side bus, unlike a general AC motor, the sum of the three-phase currents is not always zero. Therefore, the method of Patent Document 1 cannot be applied as it is.

In addition, when connecting the battery of an electric vehicle to an electric system of a house, the voltage is stepped down when discharging (battery of the car → electric system of the house) and boosted when charging (electric system of the house → battery of the car). Not only that, there is a demand to boost the voltage when discharging and to lower the voltage when charging.

The present invention has been made based on such a request, and relates to a multi-phase power conversion circuit capable of both bidirectional step-up operation and step-down operation between a first DC power supply and a second DC power supply. The purpose is to control the current of each phase using one current sensor.

In the multi-phase power conversion circuit of the present invention, the first converter and the second converter are connected in common by connecting their inductors and provided for each phase, and the duty ratio d _a of the upper switch of the first converter. and a controller for PWM controlling the first converter and the second converter determines the duty ratio d _b of the upper switch of the second converter, the measured current i _h measured at the common bus of the first converter to the controller a current sensor for supplying the controller, the bidirectional step-up between the first converter connection side of the connection end of the common bus and common bus of the second converter by adjusting the duty ratio d _a, the d _b together to perform the operation and step-down operation, the current through the inductor based on the first converter of the measured current i _h sampled at a timing determined in accordance with the relationship between the carrier wave and the duty ratio d _a of the PWM control The value is estimated and the first converter and the second converter are PWM-controlled.

According to the present invention, both bidirectional step-up operation and step-down operation are possible between the first DC power supply and the second DC power supply. For example, when it is installed between the battery of an electric vehicle (first DC power supply) and the electric system of a house (second DC power supply), the voltage is boosted and lowered when the battery of the electric vehicle is discharged to the electric system of the house. At the same time, step-up and step-down are possible when charging the battery of an electric vehicle from the electric system of a house.

Moreover, the current of each phase can be controlled independently with only one current sensor. For example, even when the characteristics of the circuit elements constituting each phase vary, it is possible to control the balance of the current of each phase with only one current sensor. By sampling the value of the current sensor connected to the high voltage side in synchronization with the carrier wave of each phase (for example, at the valley of the carrier wave or at the peak of the peak and valley), and obtaining the current value of each phase from that value. , The effect that it is not necessary to provide a current sensor for each phase can be obtained.

It is a figure which illustrates the n-phase interleaved bidirectional DC-DC conversion circuit which was constructed as the 1st example of the multi-phase power conversion circuit of this invention. It is a figure which illustrates the n-phase interleave bidirectional DC-DC conversion circuit when the current sensor is provided at another position. It is a figure which illustrates the three-phase interleave bidirectional DC-DC conversion circuit which was constructed as the 2nd example of the multi-phase power conversion circuit of this invention. It is a circuit diagram which illustrates the controller for the three-phase interleave bidirectional DC-DC conversion circuit. It is a figure for _{demonstrating} the carrier wave and the sampling signal generated by shifting the phase by 120 (= 360/3) degrees, (A) is the carrier wave V _{carr_a1} and V _{carr_a2} for driving each switch of the 1st converter. , V _{carr_a3} , and the sampling signal smpl, (B) is a diagram illustrating carrier waves V _{carr_b1} , V _{carr_b2} , and V _{carr_b3} for driving each switch of the second converter. It is a figure explaining the estimation principle (estimation method 1) of the current value flowing through an inductor. It is a figure explaining the estimation principle (estimation method 2) of the current value flowing through an inductor. It is a figure explaining the estimation principle (estimation method 3) of the current value flowing through an inductor. It is a figure explaining the estimation principle (estimation method 4) of the current value flowing through an inductor. It is a figure which shows the result of Example 1 performed for confirming the effect of this invention. It is a figure which shows the result of Example 2 performed for confirming the effect of this invention. It is a figure which shows the result of Example 3 performed for confirming the effect of this invention. It is a figure which shows the result of Example 4 performed for confirming the effect of this invention. It is a figure which shows the result of Example 5 performed for confirming the effect of this invention. It is a figure which shows the result of Example 6 performed for confirming the effect of this invention. It is a figure which shows the conventional n-phase interleaved bidirectional DC-DC conversion circuit. It is a figure which shows the conventional three-phase interleaved bidirectional DC-DC conversion circuit.

Hereinafter, the present invention will be described with reference to examples. FIG. 1 is a diagram illustrating an n-phase interleaved bidirectional DC-DC conversion circuit configured as a first embodiment of the multi-phase power conversion circuit of the present invention. The multi-phase power conversion circuit of the present embodiment is used, for example, in a HEMS (Home Energy Management System), for example, for connecting an electric vehicle and a residential electric system.

As shown in FIG. 1, the first converter 1 and the second converter 2 are connected in common with inductors L ₁ , L ₂ , ..., L _n . The first converter 1 and the second converter 2 are provided for each phase. The connection side of the first converter 1 of the common bus 1a first DC power supply V _{in (e.g.,} the electric vehicle battery) is connected, on the connection side of the second converter 2 of the common bus 2a of the second A DC power source (for example, a residential electrical system) 3 is connected. The first common bus 1a of the converter 1 and the current sensor 4 is provided, the controller to be described later by using the value i _h obtained by the current sensor 4, each phase of the inductor current (each phase inductor L _1, L _2. Estimate the currents flowing through L _n ). Switches of the n-phase interleaved power conversion circuit S _a1u , S _a2u , ..., _Sanu , S _a1l , S _a2l , ..., _Sanl , S _b1u , S _b2u , ..., S _bnu , S _b1l , S _b2l , ... , S _bnl on / off signals can be generated by PWM (pulse width modulation) control. At this time, a triangular wave is generally used as the carrier wave. Further, the carrier waves of each phase are shifted by 360 / n degrees from each other.

Here, of the two converters 1 and 2, the converter in which the current sensor 4 is provided on the common buses 1a and 2a is designated as the first converter 1, and the current sensor 4 is provided on the common buses 1a and 2a. The one that does not exist is referred to as the second converter 2. Therefore, as shown in FIG. 1, when the current sensor 4 is provided on the common bus of the converter on the first DC power supply Vin side, the converter on the first DC power supply Vin side is the first converter 1, and the first converter 1 is used. The converter on the DC power supply 3 side of 2 is the second converter 2. Further, as shown in FIG. 2, when the current sensor 4 is provided on the common bus of the converter on the second DC power supply 3 side, the converter on the second DC power supply 3 side is the first converter 1, and the second converter 1 The converter on the Vin side of the DC power supply of 1 is the second converter 2.

If necessary, a subscript "a" is added to the component of the first converter 1, and a subscript "b" is added to the component of the second converter 2, so that the component of the first converter 1 is configured. Distinguish between the elements and the components of the second converter 2.

First converter 1 of each phase, the upper switch _{S a1u, S a2u, ...,} S anu and the upper switch _{S a1u, S a2u, ...,} S anu serially connected the lower switch _{S A1L, S A2L,} ... includes a _{S anl,} and the upper switch _{S a1u, S a2u, ...,} S anu a lower switch _{S A1L,} S A2L, _..., inductor _{L 1,} L 2 at the midpoint of the _{S anl,} ..., a _{L n} The first converter of each phase is connected in common to both ends of the upper switches S _a1u , S _a2u , ..., _Sanu and the lower switches S _a1l , S _a2l , ..., _Sanl , which are connected in series with one end connected. It is the outer connection end of 1. Further, the second converter 2 of each phase is a lower switch S _b1l , S _b2l connected in series to the upper switches S _b1u , S _b2u , ..., S _bnu and the upper switches S _b1u , S _b2u , ..., S _bnu. , ..., S _bnl , and upper switches S _b1u , S _b2u , ..., S _bnu and lower switches S _b1l , S _b2l , ..., S _bnl midpoint inductors L ₁ , L ₂ , ..., L with connecting _n other end of the upper switch _S B1u connected in _{series, S b2u, ...,} S _bnu and lower switch _{S b1l, S b2l, ...,} the respective phases commonly connected at both ends of the _{S BNL} It is the outer connection end of the converter 2 of 2.

In the following, a three-phase circuit in the case of n = 3 will be described as an example. FIG. 3 is a diagram illustrating a three-phase interleaved bidirectional DC-DC conversion circuit configured as a third example of the multi-phase power conversion circuit of the present invention. 3, the first converter 1, the inductor _{L 1} and the lower switch _{S A1L} and the upper switch _{S A1U,} constitute a converter of phase 1. The inductor L ₂ , the lower switch S _a2l, and the upper switch S _{a2u form} a phase 2 converter. The inductor _{L 3} and the lower switch _{S A3L} and upper switch _{S A3U,} constitute a converter phase 3. The outer ends of the phase 1 to phase 3 converters are connected to each other to form an interleaved converter.

Further, with respect to the second converter 2, the inductor L ₁ , the lower switch S _b1l, and the upper switch S _{b1u form} a phase 1 converter. The inductor L ₂ , the lower switch S _b2l, and the upper switch S _{b2u form} a phase 2 converter. The inductor L ₃ , the lower switch S _b3l, and the upper switch S _{b3u form} a phase 3 converter. The outer ends of the phase 1 to phase 3 converters are connected to each other to form an interleaved converter.

That is, the first converter 1 and the second converter 2 is connected to those of the inductor L ₁ ~L ₃ in common for each phase.
The first converter 1 of the lower switch _{S a1l, S a2l, S a3l} the outer end and the second converter 2 of the lower switch _{S B1L,} S _B2L, the outer end of the _{S B3l} are connected.

Phase 1 phase 3 inductor _(reactor) one end of L 1 ~L _3, the first converter 1 of the upper switch _S A1U that three-phase bridge _connection, S _{A2U, S A3U} and lower switch _{S A1L, S A2L,} Connect to each midpoint of S _a3l . The other end of the inductor _L 1 ~L ₃ is a three-phase bridge connection and a second converter 2 of the upper switch _{S b1u, S b2u, S b3u} and lower switch _{S B1L,} S _B2L, the midpoint of the _{S B3l} Connect to each. These switches are composed of, for example, switching elements such as MOSFETs and freewheeling diodes, but are not limited thereto.

The outer end of the first converter 1 power V _in as a first DC power source, the outer end of the second converter 2 Load as a second DC power supply 3 are connected. Further, a capacitor C is connected to the outer end of the second converter 2 on the Load side. The output current ih detected by the current sensor 4 provided in the common bus 1a of the first converter 1 is guided to a controller (see FIG. 4) described later. This controller includes the upper switches S _a1u , S _a2u , S _a3u , S _b1u , S _b2u , S _b3u and the lower switches S _a1l , S _a2l , S _a3l , S _{b1l of} the first and second converters 1 and 2. A drive signal for driving S _b2l and S _b3l is generated and output to the gate of the corresponding switch.

FIG. 4 is a circuit diagram illustrating a controller for a three-phase interleaved bidirectional DC-DC converter circuit. The controller shown in the figure controls the output voltage of the three-phase interleaved bidirectional DC-DC converter circuit and controls the current of each phase. The controller inputs the output current i _h and the output voltage v _h , and outputs a drive signal to the gate of each switching element constituting the three-phase bridge. The output voltage _{v h} is supplied from a host controller (HEMS controller). The controller includes a first control unit 5 that controls the first converter 1 and a second control unit 6 that controls the second converter 2. The first control unit 5 includes a voltage controller AVR (for example, a PI controller, but P control and other control methods can be applied as well as PI) 7, an inductor current estimator 8, a carrier, and a sampling signal generation. Instrument 9, current controller ACR (for example, PI controller, but not limited to PI, P control and other control methods can also be applied) 10, limiter 11, PWM circuit (comparator) 12, and dead time generator. It is equipped with 13.

The voltage controller AVR 7 amplifies the error between the output voltage v _h and the reference voltage V _h ^* (supplied from the upper control device), and outputs an error amplification signal to the current controller ACR10. When the value (difference) obtained by subtracting the high-voltage side output voltage v _h from the reference voltage V _h ^* is positive, the error amplification signal increases as the absolute value of the difference increases, and the value change decreases as the difference decreases. Become. On the other hand, when the difference is negative, it decreases as the absolute value of the difference increases, and the change in the value decreases as the difference decreases. Thus, high-voltage output voltage v _h duty ratio of the switch to stabilize is controlled. The current controller ACR10, the limiter 11, and the PWM circuit 12 are provided for each phase. The error amplification signal from the voltage controller AVR7 is branched for each phase via a 1/3 divider (not shown) if necessary, and the same error amplification signal is used as the current command value of each inductor for each phase. Output toward the current controller ACR10. The carrier wave and sampling signal generator 9 outputs the sampling signal smpl to the inductor current estimator 8 and outputs the carrier wave (for example, a triangular wave) created in synchronization with the sampling signal to each phase PWM circuit 12.

FIG. 5A is a diagram illustrating carrier waves V _{carr_a1} , V _{carr_a2} , V _{carr_a3} , and sampling signal smpl generated by the carrier wave and sampling signal generator 9 with a phase shift of 120 (= _360/3 ) degrees. is there. The inductor current estimator 8 measures the output current i _h of the current sensor 4 based on the carrier and the sampling signal smpl supplied from the sampling signal generator 9, and the duty ratios d _{a1 to} d _a3 of the upper switches of each phase. switch the estimation method as described below to determine an estimate _i est1 _{through i est3} of each phase inductor current in accordance with the value. The output current estimated for each phase is output to the current controller ACR10.

The current controller ACR10 provided for each phase inputs an error amplification signal from the voltage controller AVR7 and a difference signal of each phase estimated output current (estimated values of each phase inductor current _{iest1 to iest3} ), and this difference signal Is amplified as necessary to perform PI control and the like. That is, the value obtained by integrating the deviation signal and multiplying it by the integrated gain is added and the value obtained by multiplying the deviation signal by the proportional gain is output. The output voltage from the current controller ACR10 is a voltage signal corresponding to the voltage command signals V _{ref_a1} , V _{ref_a2} , and V _{ref_a3} (duty ratios d _a1 , d _a2 , d _a3 ) after limiting the upper limit value via the limiter 11. ), In the comparator (PWM circuit 12), when the carrier voltage exceeds the output voltage of the PI controller (current controller ACR10) as compared with the carrier (triangular wave) voltage, the upper switches S _a1u , S _a2u , ... , _Sanu is turned off (see FIG. 6 to be described later), and the lower switches S _a1l , S _a2l , ..., _Sanl are turned on. A drive signal is generated from the drive circuit (dead time generator 13). That is, PWM control is performed in which the pulse width at which the switch is turned on is controlled by the output voltage from the PI controller. The lower switches S _a1l , S _a2l , and S _a3l are signals _obtained by inverting the upper switches S _a1u , S _a2u , and S _{a3u on} and off, respectively. Dead time generator 13, if necessary, to insert lower switch _{S A1L,} S _A2L, and _{S A3L,} upper switches _{S A1U,} S _A2U, the dead time between the on and off of the _{S A3U.} The dead time generator 13 generates a drive signal for driving the switch based on the comparison signal from the PWM circuit 12, and of the corresponding switches S _a1u , S _a2u , S _a3u , S _a1l , S _a2l , S _a3l . Output to the gate.

FIG. 6 is a diagram illustrating how the PWM circuit 12 generates a switch drive signal. In FIG. 6, the description of S _a side and S _b side means the first converter 1 side and the second converter 2 side, and the carrier _{a1 of} S _a1 , carrier _{a2 of} S _a2 , carrier _{a3 of} S _a3 , and carrier. _{b1 ofS b1, carrier b2 ofS b2} , carrier b3 ofS described with _b3 is _{V carr_a1, V carr_a2, V carr_a3} , V carr_b1, V carr_b2, means _{V carr_b3, S a1, S a2} , S a3, S b1, The description of S _b2 and S _b3 means S _a1u , S _a2u , S _a3u , S _b1u , S _b2u , and S _b3u . The PWM circuit 12 compares the duty ratios d _{a1 to} d _a3 (V _{ref_a1} , V _{ref_a2} , V _{ref_a3} ) with the carrier waves (triangular wave V _{carr_a1} , V _{carr_a2} , V _{carr_a3} ) for each phase of the first converter 1. When the carrier wave exceeds the duty ratio (when the voltage value is exceeded), a drive signal is generated in which the upper switches S _a1u , S _a2u , and S _a3u are turned off and the lower switches S _a1l , S _a2l , and S _a3l are turned on. That is, PWM control is performed in which the pulse width at which the switch is turned on is controlled by the output voltage from the current controller ACR10. The lower switches S _a1l , S _a2l , and S _a3l are signals _obtained by inverting the upper switches S _a1u , S _a2u , and S _{a3u on} and off, respectively. The dead time generator 13 inserts a dead time between the on / off of the lower switches S _a1l , S _a2l , S _a3l and the upper switches S _a1u , S _a2u , S _a3u , if necessary.

In FIG. 6, for ease understanding, although expressed as _{d a} collectively each phase of the duty ratio _d a1 _{to d a3,} indeed the duty ratio for each phase to _d a1 _{to d a3} and carrier V _{Comparison with carr_a1} , V _{carr_a2} , and V _{carr_a3} is performed. There follows, represents a _{d a} collectively phase duty ratio _d a1 _{to d a3} of the first converter 1, also be expressed as _{d b} are collectively phase duty ratio _d b1 _{to d b3} of the second converter 2 ..

Inductor current estimator 8, by calculating sampling vital output current i _h by the supplied sampled signal smpl, estimates the phase inductor current. Estimate _i est1 _{through i est3} of each phase estimated inductor current is output to the current controller ACR10.

As shown in FIG. 5, since the carrier waves of each phase are shifted by 360/3 degrees from each other, when the characteristics of the circuit elements constituting each phase are the same and the values of the estimated output currents of each phase are the same, Although the duty ratio is different in phase driving signals one by and each phase 360/3 degrees the same, the estimated value i _est1 through i _est3 of each phase inductor current, switch-off phase is adjusted for each switch.

The duty ratios d _{a1 to} d _a3 are values of 0.0 to 1.0 and are actually indicated by the voltage. The duty ratio is 0.0 for the same voltage as the valley portion of the carrier voltage waveform generated by the PWM circuit 12, and the duty ratio is 1.0 for the same voltage as the peak portion of the carrier voltage waveform. To.

The second control unit 6 includes a carrier wave generator 14, a limiter 15, a PWM circuit (comparator) 16, and a dead time generator 17. The limiter 15 and the PWM circuit 16 are provided for each phase. A difference signal between the output voltage from the current controller ACR10 of the first control unit 5 and the command voltage 18 is input to the limiter 15. After the upper limit of the difference signal is limited via the limiter 15, the voltage command signals V _{ref_b1} , V _{ref_b2} , and V _{ref_b3} (voltage signals corresponding to the duty ratios d _b1 , d _b2 , and d _b3 ) are used as a comparer. In (PWM circuit 16), when the carrier voltage exceeds the output voltage of the PI controller (current controller ACR10) as compared with the carrier (triangular wave) voltage, the upper switches S _b1u , S _b2u , and S _b3u are turned off ( A drive signal for turning on the lower switches S _b1l , S _b2l , and S _b3l is generated from the dead time generator 17 (see FIG. 6 to be described later). That is, PWM control is performed in which the pulse width at which the switch is turned on is controlled by the output voltage from the PI controller. The lower switches S _b1l , S _b2l , and S _b3l are signals _obtained by inverting the upper switches S _b1u , S _b2u , and S _{b3u on} and off, respectively. The dead time generator 17 inserts a dead time between the on / off of the lower switches S _b1l , S _b2l , S _b3l and the upper switches S _b1u , S _b2u , S _b3u , if necessary. The dead time generator 17 generates a drive signal for driving the switch based on the comparison signal from the PWM circuit 16, and of the corresponding switches S _b1u , S _b2u , S _b3u , S _b1l , S _b2l , S _b3l . Output to the gate.

The command voltage 18 is supplied from a higher-level control device (not shown). In the example of FIG. 4, 0.8 is set as the duty ratio db of the upper switches S _b1u , S _b2u , and S _b3u of the second converter 2 by the upper control device, and the command voltage of the value corresponding to this value is set. 18 is supplied to the PWM circuit 16 via the limiter 15.

FIG. 5B is a diagram illustrating carrier waves V _{carr_b1} , V _{carr_b2} , and V _{carr_b3} generated by the carrier wave generator 14 with a phase shift of 120 (= _360/3 ) degrees.

FIG. 6 is a diagram illustrating how the PWM circuit 16 generates a switch drive signal. The PWM circuit 16 compares the duty ratios d _{b1 to} d _b3 (V _{ref_b1 to} V _{ref_b3} ) with the carrier waves (triangular wave V _{carr_b1} , V _{carr_b2} , V _{carr_b3} ) for each phase of the first converter 2, and the carrier wave is the duty. When the ratio is exceeded (when the voltage value is exceeded), a drive signal is generated that turns off the upper switches S _b1u , S _b2u , and S _b3u and turns on the lower switches S _b1l , S _b2l , and S _b3l . That is, PWM control is performed in which the pulse width at which the switch is turned on is controlled by a voltage. The lower switches S _b1l , S _b2l , and S _b3l are signals _obtained by inverting the upper switches S _b1u , S _b2u , and S _{b3u on} and off, respectively. The dead time generator 17 inserts a dead time between the on / off of the lower switches S _b1l , S _b2l , S _b3l and the upper switches S _b1u , S _b2u , S _b3u , if necessary.

During discharge from the first DC power supply V _in to the second DC power source 3, it converts the voltage is represented by Equation 4.
[Number 4]
_{V b = (d a / (} 1-d b)) V a
As for the charging from the second DC power supply 3 to the first DC power supply V _in, the conversion of the voltage is represented by Equation 5.
[Number 5]
_{V a = ((1-d} b) / d a) V b
Here, _{V a:} the voltage of the first DC power supply _{V in, V b:} the second voltage of the DC power source 3, _{d a:} duty ratio of the first converter 1, _{d b:} the second converter 2 duty The ratio.

That is, the duty ratio d _a, by setting d _b, in both during charging and during discharging, capable of performing both step-up operation and the step-down operation. Switching between discharging and charging is controlled by a higher-level control device.

FIG. 6 is a diagram for explaining the estimation principle of the inductor current (estimated output current). As shown in the upper and middle stages of FIG. 6, in the case of three phases, the carriers V _{carr_a1} , V _{carr_a2} , V _{carr_a3} , V _{carr_b1} , V _{carr_b2} , V _{carr_b3} (V _{carr_a1} , V _{carr_a2} , V _{carr_a3} , V _{carr_b2} , V _{carr_b3} ) are phase-shifted by 120 (= _360/3 ) degrees. In the figure, carriers _a1 ofS _a1 , carrier _a2 ofS _a2 , carrier _a3 ofS _a3 , carrier _b1 ofS _b1 , carrier _b2 ofS _b2 , carrier _b3 ofS _b3 ) are used. V _{carr_a1} and V _{carr_b1} are carriers corresponding to phase 1, V _{carr_a2} and V _{carr_b2} are carriers corresponding to phase 2, and V _{carr_a3} and V _{carr_b3} are carriers corresponding to phase 3. The illustrated _d a, _{d b} is the duty ratio of the first and second converters 1 and 2. However, the duty ratio _d a, _{d b} described in FIG. 6 is actually be a different _{d a1 ~d a3, d b1 ~d} b3 each phase is as described above.

Further, the upper switches S _b1u , S _b2u , S _b3u , S _a1u , S _a2u , S _a3u (in the figure, S _a1 , S _a2 , S _a3) of the phases 1 to 3 of the second converter 2 and the first converter 1 , S _b1 , S _b2 , and S _b3 ) are shown in the lower part of FIG. The lower switches S _b1l , S _b2l , S _b3l , S _a1l , S _a2l , and S _a3l (not shown on / off signals) of the phases 1 to 3 are the upper switches S _b1u , S _b2u , S _b3u , and S, respectively. _{It is} an on / off signal in which _a1u , S _a2u , and S _a3u are inverted.

In the present invention, the first converter 1 of each phase of the carrier wave synchronized with the phase, sampling the measured current i _h of the current sensor 4. This sampling is performed at least once in one cycle of the carrier wave for each phase. _{I D1, i D2, i D3} , i 'D1, i' D2, i 'D3 shown in the drawing, the timing indicated by vertical lines measured current _{i h} in each view, i.e. the first converter 1 carrier It represents the current value sampled at the timing of the valley of the waveform. The present invention uses the sampled current value _{i D1, i D2, i D3} , i 'D1, i' D2, i 'D3, the inductor current flowing through each phase of the inductor _{L 1,} L 2, _{L 3} Estimate by calculating the values i ₁ , i ₂ , and i ₃ .

[Estimation method 1]
In the estimation method 1, the number of phases is an integer n of 2 or more, and when da <((n-1) / n), the measurement is sampled at the timing of the valley of the carrier wave of the first converter 1 of each phase. estimated that the current flowing through the current i _h to each phase of the inductor.

As shown in FIG. 6, when the number of phases is an integer n of 2 or more and da <((n-1) / n), the measurement is performed at the timing of the valley waveform of the carrier wave of each phase of the first converter 1. When the current _ih is sampled, the estimation calculation of the inductor current (estimated output current) becomes easy.

The measured current i _h is the sum of the inductor current values i ₁ , i ₂ , and i ₃ of each phase. In the waveform of the valley of the timing of the carrier wave _{V Carr_a1} in FIG 6 _{(i D1, i 'D1} and display the vertical lines), the first upper switch of the converter 1, only the switch _{S A1U} phase 1 is on, the phase The switches S _a2u and S _a3u of the 2nd and 3rd phases are turned off. Therefore, when the sampling timing _{i D1,} i _'D1 of the valley portions of the waveform of the carrier _{V Carr_a1} phases 1, can detect only the inductor current _{i 1} of the inductor _{L 1} phase 1. Similarly, phase 2, the carrier _{V Carr_a2} phase 3, when sampled at the valley of the waveform of _{V Carr_a3} timing _{i D2, i D3, i '} D2, i' D3, phase 2, the inductor _L 2 phases 3, _{L 3} Inductor current values i ₂ and i ₃ can be detected.

Thus, if da <a ((n-1) / n ), the timing of the valley of the first converter 1 carrier wave, the value of the value of the inductor current of that phase measured current i _h matches ing. At this timing, it can be confirmed that only the switches of the corresponding phase are conducting in the upper switches S _a1u , S _a2u , and S _a3u of the first converter 1. Accordingly, the waveform of the carrier samples the measured current i _h of the current sensor 4 at the timing of the valley can be detected value of the inductor current of that phase.

_V carr_a1, V carr_a2, the value obtained by the current sensor 4 sampled at the timing of the valley of the waveform of the _{V carr_a3,} respectively _{i h1b, i h2b,} When _{i H3B,} the value _i 1 of each phase of the inductor current, i _{2, i 3} may be obtained by equation 6 equation 8.
[Number 6]
i ₁ = i _h1b
[Number 7]
i ₂ = i _h2b
[Number 8]
i ₃ = i _h3b

In the case of n phase, the value obtained by the current sensor 4, when i _HKB, it is possible to obtain the inductor current i _k phase k in Equation 9.
[Number 9]
i _k = i _hkb

であると推定する。 [Estimation method 2]
In estimation method 2, and 3 or more integer n the number of phases, (1 / n) ≦ d For _a, the measured current i _h measured in angle of the timing of the first converter 1 carrier waveform of each phase _Is i _hkt, and the output current ik flowing through the inductor of phase k is

Presumed to be.

Figure 7 is a three or more integer n the number of phases is a diagram for explaining the estimation principle of the inductor current when the _{(1 / n) ≦ d a} . In FIG. 7, the description of S _a side and S _b side means the first converter 1 side and the second converter 2 side, and the carrier _{a1 of} S _a1 , carrier _{a2 of} S _a2 , carrier _{a3 of} S _a3 , and carrier. _{b1 ofS b1, carrier b2 ofS b2} , carrier b3 ofS described with _b3 is _{V carr_a1, V carr_a2, V carr_a3} , V carr_b1, V carr_b2, means _{V carr_b3, S a1, S a2} , S a3, S b1, The description of S _b2 and S _b3 means S _a1u , S _a2u , S _a3u , S _b1u , S _b2u , and S _b3u . Similar to FIG. 6, in the case of three phases, 120 (= 360/3) degrees each carrier _{V Carr_a1} shifted _{phase, V carr_a2, V carr_a3, V} carr_b1, V carr_b2, V carr_b3 is used.

As shown in FIG. 7, and 3 or more integer n the number of phases, (1 / n) ≦ d For _a, the mountains of the timing of the first converter 1 of each phase of the carrier wave, measured current i _h Is sampled, the inductor current value can be estimated.

Mountain timing of the first converter 1 carrier waveform of FIG. 7 when sampling the measurement current _{i h} in _{(i U1, i U2, i} U3 and the indicated vertical line), the first converter 1 of the upper switch S _{In a1u} , _Sa2u , and _Sa3u , the upper switches of the phases other than the phase corresponding to the peak timing of the shape of the carrier wave are in the conductive state. For example, the timing of the mountain shape of the carrier phase 1 _{(i U1} and display the vertical lines), upper switch _S A2U excluding the upper switch _{S A1U} phase _1, becomes _{S A3U} conductive state, the measured current at this time When i _h is sampled, the sum of the inductance currents (i ₂ + i ₃ ) excluding the inductance current i ₁ of the phase 1 is obtained.

Measurements Similarly, the mountain timing of the shape of the carrier phase 2 _{(i U2} and display the vertical lines), upper switch _S A1U excluding the upper switch _{S A2U} phase _{2, S A3U} becomes conductive, this time When the current i _h is sampled, the sum of the inductance currents (i ₁ + i ₃ ) excluding the inductance current i ₂ of the phase 2 is obtained, and the timing of the peak of the shape of the carrier of the phase 3 (vertical line indicated as i _U3 ). in the upper switch _S A1U excluding the upper switch _{S A3U} phase _{3, S A2U} is conductive, the sum of the sampling the measured current _{i h} this time, inductance current excluding the inductance current _{i 3} phase 3 ( i ₁ + i ₂ ) is obtained.

_Here, the measurement current _{i h} sampled at _{i U1 i h1t, i U2} of sampled measured current _{i h} a _{i H2T,} when the measured current _{i h} sampled at _{i U3} and _{i H3T,} each phase of The inductor current values i ₁ , i ₂ , and i ₃ can be obtained by Equation 11, Equation 12, and Equation 13.
[Number 11]
i ₁ = (i _h2t + i _h3t −i _h1t ) / 2
[Number 12]
i ₂ = (i _h1t + i _h3t −i _h2t ) / 2
[Number 13]
i ₃ = (i _h1t + i _h2t −i _h3t ) / 2

In the case of n-phase, the inductor current of phase k can be obtained by Equation 14.

[Estimation method 3]
In the estimation method 3, assuming that the number of phases is an integer n of 3 or more and the switching points S1 and S2 are (1 / n) ≤ S1 <S2 <((n-1) / n), the controller has a duty ratio. If d _a is ready for d _{a <S2} S2 ≦ d _a from the state by an increase in d _a of the measured current i _h measured in angle of the timing of the first converter 1 carrier waveform of each phase When the the _{i HKT,} the output current _{i k} flowing through the inductor of phase k estimated to be equation 15, the state of _{d a} ≦ S1 by a reduction in _{d a} from the state of the duty ratio _{d a} is S1 _{<d a} and when, is estimated to be the value of the current flowing through the measured current i _h measured at the timing of the valley of the first converter 1 carrier waveform of each phase to each phase of the inductor.

That _is, in the case of d a <((n-1 ) / n) can be applied estimation method 1 described above can be applied estimation method 2 described above in the case of _{(1 / n) ≦ d a} . This relationship is shown in FIG. For example in the case of a three-phase (n = 3) _{are, d a <0.66 (= 2} /3) in the applicable estimation method 1, 0.33 a _{(= 1/3) ≦ d} a The estimation method 2 Applicable. Therefore, in 0.33 (= 1/3) ≦ d a <0.66 (= 2/3), can be applied both estimation methods 1 and 2.

In estimation method 3, to set the two switching points S1, S2 ranges applicable both estimation method 1, the duty ratio d _a exceeds the switch point S2 to the arrow A direction (increasing direction) in FIG. 8 In the case, the estimation method is switched from the estimation method 1 to the estimation method 2, but the estimation method 2 is maintained without switching the estimation method even if the switching point S2 is crossed in the arrow B direction (decrease direction). Although it switches the estimation method in the case where the duty ratio d _a exceeds the switching points S1 in the direction of arrow B (decreasing direction) in FIG. 8 to estimation method 2 → estimation method 1, in the direction of arrow A (increasing direction) Even if the switching point S1 is exceeded, the estimation method is not switched and the estimation method 1 is maintained.

Thus, the estimation method 1 → switching point S1 of the switching point S2 of the estimation method 2 to estimation method 2 → estimation 1 by setting different values, can have a hysteresis characteristic, d _a is Frequent estimation method switching can be prevented even if the number is finely increased or decreased near the switching point, and the control of the bidirectional buck-boost DC-DC conversion circuit can be stabilized.

であると推定する。 [Estimation method 4]
In the estimation method 4, assuming that the number of phases is an integer n of 3 or more and the switching point S3 is (1 / n) ≤ S3 ≤ ((n-1) / n), the controller has a duty ratio d _a d. for _{a <S3,} estimated to be the value of the current flowing through the measured current i _h measured at the timing of the valley of the first converter 1 carrier waveform of each phase to each phase of the inductor, the duty ratio d _a is for S3 ≦ d _a, when the measured current i _h measured in angle of the timing of the first converter 1 carrier waveform of each phase and i _HKT, the output current i _k flowing through the inductor of phase k,

Presumed to be.

As described above, in (1 / n) ≤ d _a <((n-1) / n), both the estimation methods 1 and 2 can be applied. In estimation method 4, to set the switching point S3 is a range that can be applied both estimation method 1, estimation method when the duty ratio d _a exceeds the switch point S3 is the direction of arrow A (increasing direction) in FIG. 9 Is switched from the estimation method 1 to the estimation method 2, and conversely, when the switching point S3 is crossed in the arrow B direction (decrease direction), the estimation method is switched from the estimation method 2 to the estimation method 1. In the example of FIG. 9, the switching point S3 is set to 0.5. When the number of switching points is one in this way, the control can be simplified.

FIGS. 10 to 15 show simulation results when the estimation method 1 is applied to the three-phase interleaved bidirectional DC-DC conversion circuit (see FIG. 3) during charging. In FIGS. 10 to 15, the frequency of the carrier wave of the first converter 1 and the frequency of the carrier wave of the second converter 2 are the same, but they do not necessarily have to be the same. For example, the frequency of the carrier wave of the first converter 1 may be twice, four times, or the like the frequency of the carrier wave of the second converter 2. Further, in FIGS. 10 to 15, the phases of the carrier wave of the first converter 1 and the carrier wave of the second converter 2 are shifted by 180 degrees, but the phase is not limited to this.

In each figure, the upper row is the carrier of the first converter 1 (phase 1: 1 dashed line, phase 2: dashed line, phase 3: dashed line) and duty ratio da (solid line), and the middle is the carrier of the second converter 2. (Phase 1: 1 dash-dotted line, phase 2: 2-dot chain line, phase 3: dashed line) and duty ratio db (solid line), lower row is inductor current (phase 1: 1 dash-dotted line, phase 2: 2-dot chain line, phase 3: (Dashed line) and measured current ih (solid line).

[Example 1]
FIG. 10 is a simulation result when the duty ratio d _a : 0.3 of the first converter 1 and the duty ratio d _b : 0.9 of the second converter 2 are set. In the relationship between _da and n (= 3), _da <((n-1) / n) to which the estimation method 1 can be applied.

The timing of the valley of the first converter 1 phase 1 of the carrier wave, measured current i _h is the phase 1 inductor current of the inductor L _1, the timing of the valley of the carrier wave phase 2, the measured current i _h is phase 2 of the inductor current of the inductor L _2, the timing of the valley of the carrier wave phase 3, the measured current i _h is the inductor current of the phase 3 of the inductor L _3. Therefore, by applying the estimation method 1, it was confirmed to be able to estimate the value of current flowing through each phase inductor based on the measured current i _h of one current sensor 4.

[Example 2]
FIG. 11 is a simulation result when the duty ratio d _a : 0.5 of the first converter 1 and the duty ratio d _b : 0.9 of the second converter 2 are set. To Example 1, by changing the duty ratio d _a. In the relationship between _da and n (= 3), _da <((n-1) / n) to which the estimation method 1 can be applied.

Similarly to Example 1, at the timing of the valley of the first converter 1 phase 1 of the carrier wave, measured current i _h is the phase 1 inductor current of the inductor L _1, the trough carrier in the waveform of the phase 2 in the timing, the measurement current i _h is the phase 2 of the inductor current of the inductor L _2, the timing of the valley of the carrier wave phase 3, the measured current i _h is the inductor current of the phase 3 of the inductor L _3. Therefore, by applying the estimation method 1, it was confirmed to be able to estimate the value of current flowing through each phase inductor based on the measured current i _h of one current sensor 4.

[Example 3]
FIG. 12 shows a simulation result when the duty ratio d _a : 0.7 of the first converter 1 and the duty ratio d _b : 0.9 of the second converter 2 are set. To Examples 1 and 2, and by changing the duty ratio _{d a.} In the relationship between d _a and n (= 3), the estimation method 2 can be applied (1 / n) ≦ d _a .

The mountain timing of the first converter 1 phase 1 of the carrier wave, measured current i _h is the sum of the phase 2 of the inductor L ₂ inductor current and the inductor current of the inductor L ₃ phase 3, phase 2 the mountain timing of the carrier wave, measured current i _h is the sum of the phase 1 inductor current and the inductor current of the inductor L ₃ phase 3 of the inductor L _1, the timings of the peaks of the carrier wave phase 3 in the measurement current i _h is the sum of the phase 1 inductor current and the phase 2 of the inductor L ₂ inductor current of the inductor L _1. Therefore, by applying the estimation method 2, it was confirmed to be able to estimate the value of current flowing through each phase inductor based on the measured current i _h of one current sensor 4.

[Example 4]
FIG. 13 is a simulation result when the duty ratio d _a : 0.3 of the first converter 1 and the duty ratio d _b : 0.1 of the second converter 2 are set. And varying the duty ratio d _b to Example 1. In the relationship between _da and n (= 3), _da <((n-1) / n) to which the estimation method 1 can be applied.

The timing of the valley of the first converter 1 phase 1 of the carrier wave, measured current i _h is the phase 1 inductor current of the inductor L _1, the timing of the valley of the carrier wave phase 2, the measured current i _h is phase 2 of the inductor current of the inductor L _2, the timing of the valley of the carrier wave phase 3, the measured current i _h is the inductor current of the phase 3 of the inductor L _3. Therefore, by applying the estimation method 1, it was confirmed to be able to estimate the value of current flowing through each phase inductor based on the measured current i _h of one current sensor 4.

[Example 5]
FIG. 14 is a simulation result when the duty ratio d _a : 0.5 of the first converter 1 and the duty ratio d _b : 0.1 of the second converter 2 are set. To Example 2, by changing the duty ratio d _a. In the relationship between _da and n (= 3), _da <((n-1) / n) to which the estimation method 1 can be applied.

Similarly to Example 4, the timing of the valley of the first converter 1 phase 1 of the carrier wave, measured current i _h is the phase 1 inductor current of the inductor L _1, the trough carrier in the waveform of the phase 2 in the timing, the measurement current i _h is the phase 2 of the inductor current of the inductor L _2, the timing of the valley of the carrier wave phase 3, the measured current i _h is the inductor current of the phase 3 of the inductor L _3. Therefore, by applying the estimation method 1, it was confirmed to be able to estimate the value of current flowing through each phase inductor based on the measured current i _h of one current sensor 4.

[Example 6]
FIG. 15 is a simulation result when the duty ratio d _a : 0.7 of the first converter 1 and the duty ratio d _b : 0.1 of the second converter 2 are set. To Examples 4 and 5, and by changing the duty ratio _{d a.} In the relationship between d _a and n (= 3), the estimation method 2 can be applied (1 / n) ≦ d _a .

The mountain timing of the first converter 1 phase 1 of the carrier wave, measured current i _h is the sum of the phase 2 of the inductor L ₂ inductor current and the inductor current of the inductor L ₃ phase 3, phase 2 the mountain timing of the carrier wave, measured current i _h is the sum of the phase 1 inductor current and the inductor current of the inductor L ₃ phase 3 of the inductor L _1, the timings of the peaks of the carrier wave phase 3 in the measurement current i _h is the sum of the phase 1 inductor current and the phase 2 of the inductor L ₂ inductor current of the inductor L _1. Therefore, by applying the estimation method 2, it was confirmed to be able to estimate the value of current flowing through each phase inductor based on the measured current i _h of one current sensor 4.

Further, from Examples 1 to 6, it was confirmed that it is possible to apply the same estimation method by changing _{d b} 0.1 0.9. The same applies when d _b is changed to another value. Accordingly, without being affected by the value of d _b, it was confirmed to be able to determine the estimation method based on the value of d _a.

1: First converter 1a: Common bus of the first converter 1 2: Second converter 2a: Common bus of the second converter 2 4: Current sensor 5: First control unit of the controller 6: First controller 2 Controllers L ₁ , L ₂ , L ₃ , L _n : Inductors of each phase

Claims (6)

The first converter and the second converter are connected in common with their inductors and provided for each phase.
A controller for PWM controlling said first converter upper switch of the duty ratio d _a and the second converter of the first to determine the duty ratio d _b of the upper switches of the converter and the second converter, the the measured current i _h measured at the common bus of the first converter includes a current sensor to supply to said controller,
Wherein the controller, the duty ratio d _a, a bi-directional boost operation between the connection side of the common bus of the second converter and to adjust the d _b connection side of the common bus of said first converter Buck together to perform the operation, through the inductor based on the first converter the measured current i _h sampled at a timing determined in accordance with the relationship between the carrier wave of the PWM control and the duty ratio d _a of A multi-phase power conversion circuit characterized in that a current value is estimated and PWM control is performed on the first converter and the second converter. The number of phases is two or more integer n, when a _{d a <((n-1} ) / n), wherein the controller is sampled at the timing of the valley of each phase of the first converter carrier wave the multiphase power conversion circuit of claim 1, wherein the estimating and the measured current i _h is a value of current flowing through each phase of the inductor. The number of phases and an integer of three or more n, (1 / n) ≦ d For _a, the controller, the measured current i _h measured in angle of the timing of each phase of the first converter carrier waveform _Is i _hkt, and the output current i _k flowing through the inductor of phase k is

The multi-phase power conversion circuit according to claim 1, wherein the power conversion circuit is presumed to be. The number of phases is three or more integer n, when the switching point S1, S2 is assumed to be (1 / n) ≦ S1 < S2 <((n-1) / n), the controller, the duty ratio _{d a} is d a _<If consisted state S2 of the state of S2 ≦ d _a by increased d _a, the measured current i _h measured in angle of the timing of each phase of the first converter carrier waveform i When _HKT, the output current _{i k} flowing through the inductor of phase k,

Presumed to be
If the duty ratio d _a is ready for d _a ≦ S1 by a reduction in d _a from the state of S1 <d _a, the measured timing of the valley of each phase of the first converter carrier waveform multiphase power conversion circuit of claim 1, wherein the estimating and the measured current i _h is a value of current flowing through each phase of the inductor. The number of phases is three or more integer n, the switching point S3 is assumed to be (1 / n) ≦ S3 ≦ ((n-1) / n), the controller, the duty ratio _{d a} is _d a <S3 cases, estimates that a current value flowing in the measurement current i _h measured at the timing of the valley of each phase of the first converter carrier waveforms to each phase of the inductor, the duty ratio d _a is S3 for ≦ d _a, when the measuring current i _h measured at the timings of the peaks of each phase of the first converter carrier waveform and i _HKT, the output current i _k flowing through the inductor of phase k,

The multi-phase power conversion circuit according to claim 1, wherein the power conversion circuit is presumed to be. The first converter of each phase includes an upper switch and a lower switch connected in series to the upper switch, and one end of the inductor is connected in series to the midpoint between the upper switch and the lower switch. Both ends of the connected upper switch and lower switch are commonly connected to form the outer connection end of the first converter of each phase.
The second converter of each phase includes an upper switch and a lower switch connected in series with the upper switch, and connects the other end of the inductor to the midpoint between the upper switch and the lower switch. The multiple according to any one of claims 1 to 5, wherein both ends of the upper switch and the lower switch connected in series are commonly connected to form the outer connection end of the second converter of each phase. Phase power conversion circuit.

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