M258493 八、新型說明： 【新型所屬之技術領域】 本創作係有關於一種電壓轉換器，更具體的是關於一種 具有改良型暫態響應、精確性和穩定性的直流（DC)至直流 (DC)轉換器。 & 【先前技術】 直流至直流轉換器（converter)在電子領域中已熟知。這些 電路或裝置通常將一個直流電壓位準轉換為另一個直流電 ⑽。它們用於各種用途。例如，一些種類的轉換器用 來給微處理器的Μ供核心電|。一種轉換器稱作固定頻率 轉換器，又稱作脈寬調變（PWM)轉換器。脈寬調變轉換器 包括電壓型轉換器和電流型轉換器。 電壓型脈寬調變轉換器包括—個控制迴路，該控制迴路 包括-個誤差放大器；一個脈寬調變比較器；和一個或多 個驅動器。該轉換器通常與一個同步整流器搞接來改進其 性能。該誤差放大器將該轉換器的輸出電壓與一個參考電 壓進仃比較。該脈寬調變比較器接收該誤差放大器的輸出 乍第輸人’並接收由—個鑛齒波或三纽信號作為 ^第輸入脈寬D周變比較器的輸出為一個脈寬調變信 由驅動器放大後驅動電源開關。這種轉換器的優點 ，於結構間早，精確度高。它的主要缺點是由於誤差放大 盗所需的補償而造成它對負載的暫態響應緩慢。 A電流型脈寬調變轉換器包括兩個控制迴路··-個内部電 机迴路和-個控制該内部電流迴路的外部電塵迴路。内部 93586.doc M258493 電流迴路之組成包括：-個電流放大器；一個比較器，該 比，器採用—個來自該外部電壓迴路的誤差電壓和電流放 大器的輸出作為輸入；-個正反器，該正反器每次均:時 j信號設置，並由比較器的輸出重設；和一個或多個驅動 裔。外部電壓迴路包括一個電壓誤差放大器，該電壓誤差 放大器將該輪出電壓和一個參考電壓進行比較。該誤差放 大:的輸出作為該内部電流迴路的一個參考信號。這種轉 :器的優點在於穩定性高、精確度高、並適用於多相結構。 它的主要缺點是由於該外部電塵迴路的補償而造成 載的暫態響應緩慢。 、、 ^-種已知直流至直流轉換器為—種導通時間固定的轉 換器（constant on time converter)，又稱作脈衝頻率調變 (PFM)轉換器。脈衝頻率調變轉換器之組成包括一個控制迴 路，該控制迴路包括：一冑誤差放大器；一個比較器；和一 個或多個驅動器。該轉換器通常與—個同步整流器搞接來 改進其性能。誤差放大器將該轉換器的輸出電麼與一個參 考電壓進行比較。該誤差比較器的輸出與—個參考值進^ 比較’從而獲得一個單觸發的觸發信號，該觸發信號設置 固定的導通時間。這種轉換器的優點在於結構簡單、精確 度高、和對負載的暫態響應相對較快。它的主要缺點是頻 率不固定和不適用於多相應用。 另種直流至直流轉換器為一種滞後轉換器 議ve贈），該轉換器包括··電壓型滞後轉換器和電流型滞 後轉換器。電塵型滯後轉換器包括一個控制迴路，該控制 93586.doc M258493 通常盥個滯後比較器和-個或多個驅動器。該轉換器 :1較，同步整流器，接來改進其性能。具有滯後效應M258493 8. Description of the new type: [Technical field to which the new type belongs] This creation relates to a voltage converter, more specifically, a direct current (DC) to direct current (DC) with improved transient response, accuracy and stability. )converter. & [Prior art] DC-to-DC converters are well known in the electronics field. These circuits or devices usually convert one DC voltage level to another DC voltage. They are used for various purposes. For example, some types of converters are used to power the core of a microprocessor |. One type of converter is called a fixed frequency converter, also known as a pulse width modulation (PWM) converter. PWM converters include voltage converters and current converters. The voltage type pulse width modulation converter includes a control loop including an error amplifier; a pulse width modulation comparator; and one or more drivers. The converter is usually interfaced with a synchronous rectifier to improve its performance. The error amplifier compares the converter's output voltage with a reference voltage. The pulse width modulation comparator receives the output of the error amplifier, and receives a pulse signal or a three-dimensional signal as the first input pulse width D. The output of the cycle comparator is a pulse width modulation signal. Drive the power switch after being amplified by the driver. The advantages of this converter are early in the structure and high accuracy. Its main disadvantage is its slow response to load transients due to the compensation required for error amplification. The A current type pulse width modulation converter includes two control loops-an internal motor loop and an external electric dust loop that controls the internal current loop. The internal 93586.doc M258493 current loop consists of:-a current amplifier; a comparator, the ratio, the comparator uses an error voltage from the external voltage loop and the output of the current amplifier as inputs;-a flip-flop, the The flip-flop each time: the j signal is set and reset by the output of the comparator; and one or more drivers. The external voltage loop includes a voltage error amplifier that compares the wheel-out voltage with a reference voltage. The error is amplified: the output serves as a reference signal for the internal current loop. The advantages of this converter are high stability, high accuracy, and suitability for multi-phase structures. Its main disadvantage is the slow transient response of the load due to the compensation of the external electric dust circuit. A known DC-DC converter is a constant on time converter, also known as a pulse frequency modulation (PFM) converter. The composition of the pulse frequency modulation converter includes a control circuit, which includes: an error amplifier; a comparator; and one or more drivers. The converter is usually interfaced with a synchronous rectifier to improve its performance. The error amplifier compares the output voltage of the converter with a reference voltage. The output of the error comparator is compared with a reference value to obtain a single-trigger trigger signal. The trigger signal sets a fixed on-time. The advantages of this converter are simple structure, high accuracy, and relatively fast transient response to the load. Its main disadvantages are its variable frequency and unsuitability for multiphase applications. Another type of DC-to-DC converter is a hysteresis converter (recommended by ve). The converter includes a voltage-type hysteresis converter and a current-type hysteresis converter. The electric dust type hysteresis converter includes a control loop, which is usually controlled by a hysteresis comparator and one or more drivers. The converter: 1 compared to a synchronous rectifier to improve its performance. Lag effect
比較器的輪的輪出與一個參考電壓進行比較。該 妗播1乍為驅動器的輸入。這種轉換器的優點在於 Fe早、精確度高、和對負載的暫態響應快 點是：率不固定和不適用於多相結構。 W 器。該比較器的輸出作為該驅動器的輸入。這種轉換器的 優點在於結構簡單、精確度高。它的缺點是對負載的暫態 響應緩慢’頻率不固定和不適用於多相結構。 因此，直流至直流轉換需要一種更為簡單和相對經濟有 效的解決方案，並具有對負載的暫態響應快、精確度高、 電^•滞後轉換器包括一個控制迴路。該控制迴路包括： 個電[块差放大器；一個滯後電流比較器；和一個或多 個驅動ϋ轉換器通常與__個同步整流器㈣來改進其 性月b :该電壓誤差比較器將該轉換器的輸出電壓與一個參 考電壓進仃比較，從而提供一個偏移信號給該電流比較 頻率固定和適用於多相結構等特性。 【創作内容】 本創作的一種直流至直流轉換器包括一第一比較器，該 第一比較器配置用以將一第一信號與一第二信號進行比 較。該第一信號有一直流偏移（DC offset)，該直流偏移至 少部分地由一直流參考電壓源決定。該第二信號表示該直 流至直流轉換器的一輸出電壓位準。該比較器還配置用以 根據該第一信號和該第二信號之間的差值提供一控制信號 93586.doc M258493 給一驅動器，該驅動器驅動該直流至直流轉換器的輸出電 :0亥直k至直流轉換逛包括一精確性電路（accuracy circuit)，該精確性電路配置用以根據直流參考電壓源的直 w電壓位準和直流至直流轉換器的輸出電壓之間的差值提 供一預定的偏移電壓值給第一信號和第二信號中之一。 在另一個實施例中，本創作的一種直流至直流轉換器包 括一配置用以將一第一信號和一第二信號進行比較的第一 比較器。該第一信號有一直流偏移，該直流偏移至少部分 地由一直流參考電壓源決定。該第二信號表示該直流至直 流轉換器的一輸出電壓位準。該比較器還配置用以根據該 第一信號和該第二信號之間的差值提供一控制信號給一驅 動器’該驅動器驅動至少一個開關，從而控制該直流至直 流轉換器的輸出電壓的位準。該直流至直流轉換器還包 括·與至少一開關麵接的電感和一穩定性電路（stability circuit) ’該穩定性電路配置用以根據流經該電感的電流位 準提供該第二信號給該比較器。 【實施方式】 圖1所示為本創作的一種快速暫態響應的直流至直流轉 換器100的電路圖。通常，直流至直流轉換器1〇〇根據比較 器118的輸入端的參考信號使輸出電壓v〇ut U2穩定。暫態 響應中’在從一個直流狀態切換到另一個直流狀態的過程 中需要輸出負載。直流至直流轉換器1⑽通過調整工作週期 (duty cycle)有效地減小了暫態響應的恢復時間，從而控制 Voutll2至理想的穩定狀態。 93586.doc M258493 直流至直流轉換器100包括：一個參考直流電壓源 (Vref)114、一個參考信號產生器116、一個比較器118、一 個驅動器120和一對開關122。信號產生器1丨6產生一個參考 信號126，該信號較佳可為300千赫茲的鋸齒波信號，或者 是任何波形的週期性信號（例如三角波信號或正弦波信 號），並具有一個由Vref 114產生的直流電壓所決定的直流 偏移。比較器118接收參考信號126作為其第一輸入。輸出 電壓（Vout)112通過回授迴路124作為比較器118的第二輸 入。比較器11 8將Vout 112和參考信號126進行比較並產生一 個脈寬調變信號128，脈寬調變信號128的工作週期可決定 增大或減小Voutll2。進一步的說，若v〇utU2小於或大於信 號126，比較器11 8則通過增大或減小其輸出脈寬調變信號 128的脈寬以使Vout 112跟隨參考信號126。更詳細地說，驅 動器120接收脈寬调變信號128作為它的輸入，並驅動開關 122。該開關122較佳可由金屬氧化物半導體場效電晶體 (MOSFETs)來實現，利用高低位準的變換施加在m〇SFETs 上來父替導通控制Vout 112。最好是v〇utl 12接近Vref，並保 持在參考#號12 6的限制範圍内。例如，參考信號產生器116 在一個特定的直流Vref電壓處產生一個鋸齒波參考信號 126，該鋸齒波信號的峰對峰波動為ι〇〇毫伏，即Vref_5〇毫 伏<Vout<Vref+50毫伏。另外，輸出負載（vout)112與一個低 通濾波器串聯耗接。低通濾波器中的電感13 0的電感應盡可 能地小，從而減小對負載暫態響應的恢復時間。 圖2所示為一個應用圖1中的直流至直流轉換器電路1 〇〇 93586.doc M258493 的示範性應用電路200。電路200採用一個參考電壓產生器 202(例如，D1(TL431))以對輸入電麼114的變化進行補償， 從而確保比較器118產生的脈寬調變信號128根據如上所述 的參考電壓調整輸出電壓Vout。斜波信號產生器116(由元件 U3(LM311)204構成，並產生一個夸·聲幅度約為1〇〇毫伏的 三角波信號126。如上所述的比較器i j 8由叫⑽i! )2〇6構 成，接收輸出電塵Vout 112和三角波信號126作為輸入，並 產生-個脈寬調變信號128。該示範性應用中的驅動器12〇 由U1(TPS2830)208構成。最後，電源模組21〇驅動輸出電壓 Vout 122之組成包括：M〇SFETs Q1和Q2m;電感li， 130;電阻RH);和電容C4。該直流至直流轉換器電路用來 改進對負載暫態響應的恢復時間。值得注意的是該創作包 括但不受限於圖2中的應用示意圖的元件和電路。 本創作的另—個實施例為在多相結構中可包括兩個或多 個轉換态電路100，其中兩個電路之間的相移角根據所採用 的相數而不同。例如，在一個四相結構中，相移角為90度。 二相'·。構的問題是在兩個相之間有不期望的電流。例如， 當-個負載施加於輸出’若一個相傳送至負載的電流遠遠 ，於另-個相輸出至負載的電流，轉換效率將受到嚴重影 響。這種問題類似於將兩個電壓源並聯。若兩個電壓源Ζ 電壓不同’將有電流流經它們之間。為了解決多相直流至 直机轉換器的這種問題’則需—個電流平衡機制。例如， 在個^相直流至直流轉換器中採用―個電流平衡模㈣ 調整該第二相的輪出電壓’使其與該第一相的輸出電壓相 93586.doc -10- M258493 等。通過採用電流檢測電阻’該電流平衡模组得到該電流 資訊，並產生一個偏移電壓來調整該第二相的輸出電壓。 實現該電流平衡機制有兩種選擇方法：⑴通過修改該第二 相的參考電壓；或⑺通過修改該第二相的回授電壓。 圖3所示為一個具有一個電流平衡模組的兩相直流至直 流轉換器300的實施例，該電流平衡模組作用於該第二相的 參考信號。第一相l〇〇a根據比較器118的輸入端的參考信號 126a產生輸出電壓112。電流平衡模組3〇1將參考信號ιΐ6的 直流部分調整後傳送給第二相10肋，從而使得每相傳送的 相等的電流幅值。假設流經第一相1〇〇a的電流大於流經第 一相100b的電流，則誤差放大器302的同相輸入端的電壓將 大於其反相輸入端的電壓。誤差放大器302的作用是減小偏 移電壓303的值，這樣，第二相i〇〇b的參考電壓的直流部分 將增大。因此，第二相l〇〇b的工作週期將增大。如此，第 二相100b傳送的電流值大於以前的電流值。當每相傳送的 電流都相等時，偏移電壓303將保持該值，從而達到各相的 電流平衡。 圖4所示為另一個具有一個電流平衡模組的兩相直流至 直流轉換器400的實施例，該電流平衡模組作用於第二相的 回授部分。第一相100a根據比較器128輸入端的參考信號 126a產生輸出電壓Vout 112。電流平衡模組401將回授電壓 的直流部分平移給第二相100b，從而使得每相傳送相等的 電流振幅。假設流經第一相1 〇〇a的電流大於流經第二相 100b的電流，則誤差放大器402的反相輸入端的電壓大於其 93586.doc -11 - M258493 同相輸人端的電壓。誤差放大器嫩的作用是增大偏移電壓 403的值，攻樣，第二相1〇叽的回授電壓之Dc值將減小。 因此，第二相100b的工作週期將增大。如此，第二相忉叽 產生的電流值大於先前的電流值。當每相產生的電流都相 等N· ’偏移電壓403將保持該值不變，；足而達到電流平衡。 值得注意的是由於圖4中的電流平衡模組作用於回授電 壓所以圖4中的電流平衡模組的反相和同相輸入端與圖3 中的電流平衡模組的反相和同相輸入端相反。 圖3和圖4所示的轉換器所採用的電流平衡機制的主要優 點在於當負載的變化產生暫態時，兩相都動作，使輸出電 壓恢復至穩定狀態。由於暫態中的每相的特性幾乎相同（由 於所採用的元件值的不同而只存在小的差異），電流平衡電 路只需要通過細微的修正圖3中的參考部分或圖4中的回俨 部分的偏移電壓’而使兩相的電流平衡至新的較狀態。又 值得注意的是兩種類型的電流平衡方法均可用於多相妹 構中，其中電流平衡模組將來自相的電流資訊和輪出 壓作為輸人，並提供偏移電壓給第2至第_，從而與 相的電流相平衡。 Λ 一圖5Α所示為輸出電壓隨著輸入電壓變化的示意圖。對於 一個特定的輸入電壓Vin，由於參考信號為常數，所以工、 週期Dl=V0utl/Vin。即工作週期由電壓v〇uU與參考卜作 交得到。例如，若輸入電麼減小至k*Vin(其中k<1)，^虎相 的工作週期為D2=V〇ut2/k*Vin，所以輸出電壓將減小=新 大工作週期。因此，輸出電㈣著（D2_D1)*⑽齒波參^ 93586.doc -12- M258493 號的幅值）的值而減小。甚至對於幅值很低的參考信號，由 於輸入電壓可在較大的範圍内變化，所以輸出電壓仍隨著 輸入電壓而變化。 圖5B所示為一種在輸入電壓變化的情況下補償輸出電壓 的方法。一種防止輸出電壓隨著輸入電壓變化的方法為產 生一個振幅與輸入電壓成比例、峰值保持在一個固定的直 流電壓位準Vref的锯齒波信號。這意味著對於與Vin相等的 輸入電壓，輸出電壓Vout 1與工作週期相對應，其中工作週 期由輸出電壓與參考信號相交得到，為Dl=Voutl/Vin。因 此，若鋸齒波信號的振幅為Asawtooth、峰值為Vref，那麼 Voutl=Vref-Dl * Asawtooth ， 即Comparator wheels are compared with a reference voltage. The podcast 1 is the input for the drive. The advantages of this converter are early Fe, high accuracy, and fast transient response to the load: the rate is not fixed and it is not suitable for multi-phase structures. W device. The output of the comparator is used as the input to the driver. The advantages of this converter are its simple structure and high accuracy. Its disadvantages are the slow response to load transients. The frequency is not fixed and it is not suitable for multiphase structures. Therefore, DC-to-DC conversion requires a simpler and relatively cost-effective solution with fast transient response to the load, high accuracy, and electrical hysteresis converters including a control loop. The control loop includes: an electric [block-difference amplifier; a lagging current comparator; and one or more drive converters usually with __ synchronous rectifiers to improve their performance. B: the voltage error comparator converts The output voltage of the converter is compared with a reference voltage, so as to provide an offset signal to the current comparison frequency, which is fixed and suitable for multi-phase structures. [Creation content] A DC-to-DC converter of the present invention includes a first comparator configured to compare a first signal with a second signal. The first signal has a DC offset, which is at least partially determined by a DC reference voltage source. The second signal indicates an output voltage level of the DC-to-DC converter. The comparator is also configured to provide a control signal 93586.doc M258493 to a driver based on the difference between the first signal and the second signal, the driver drives the output voltage of the DC-to-DC converter: The k-to-DC conversion circuit includes an accuracy circuit configured to provide a predetermined value based on the difference between the direct voltage level of the DC reference voltage source and the output voltage of the DC-to-DC converter. The offset voltage value is given to one of the first signal and the second signal. In another embodiment, a DC-to-DC converter of the present invention includes a first comparator configured to compare a first signal with a second signal. The first signal has a DC offset that is determined at least in part by a DC reference voltage source. The second signal indicates an output voltage level of the DC-to-DC converter. The comparator is further configured to provide a control signal to a driver according to a difference between the first signal and the second signal. The driver drives at least one switch to control a bit of the output voltage of the DC-to-DC converter. quasi. The DC-to-DC converter further includes an inductor connected to at least one switching surface and a stability circuit. The stability circuit is configured to provide the second signal to the inductor according to a current level flowing through the inductor. Comparators. [Embodiment] FIG. 1 shows a circuit diagram of a DC-DC converter 100 with a fast transient response of the present invention. Generally, the DC-to-DC converter 100 stabilizes the output voltage vout U2 according to a reference signal at the input of the comparator 118. Transient response 'requires an output load in the process of switching from one DC state to another. The DC-to-DC converter 1⑽ effectively reduces the recovery time of the transient response by adjusting the duty cycle, thereby controlling Voutll2 to an ideal stable state. 93586.doc M258493 DC-to-DC converter 100 includes a reference DC voltage source (Vref) 114, a reference signal generator 116, a comparator 118, a driver 120, and a pair of switches 122. The signal generator 1 丨 6 generates a reference signal 126, which may be a sawtooth wave signal of 300 kHz, or a periodic signal of any waveform (such as a triangular wave signal or a sine wave signal), and has a signal generated by Vref 114. The DC offset determined by the generated DC voltage. The comparator 118 receives a reference signal 126 as its first input. The output voltage (Vout) 112 is used as the second input of the comparator 118 through the feedback loop 124. The comparator 118 compares Vout 112 with the reference signal 126 and generates a pulse width modulation signal 128. The duty cycle of the pulse width modulation signal 128 can decide to increase or decrease Voutll2. Further, if v0utU2 is smaller than or larger than the signal 126, the comparator 118 will increase or decrease the pulse width of its output pulse width modulation signal 128 to make Vout 112 follow the reference signal 126. In more detail, the driver 120 receives the PWM signal 128 as its input, and drives the switch 122. The switch 122 is preferably implemented by metal-oxide-semiconductor field-effect transistors (MOSFETs), and a high-low level conversion is applied to the mSFETs to control the Vout 112 on-state. It is best if v〇utl 12 is close to Vref and kept within the limit of reference # 12 6. For example, the reference signal generator 116 generates a sawtooth wave reference signal 126 at a specific DC Vref voltage, and the peak-to-peak fluctuation of the sawtooth wave signal is ιιιοmV, that is, Vref_50 mV < Vout < Vref + 50 millivolts. In addition, the output load (vout) 112 is connected in series with a low-pass filter. The inductance of the inductor 130 in the low-pass filter is as small as possible, thereby reducing the recovery time to the transient response of the load. FIG. 2 shows an exemplary application circuit 200 using the DC-to-DC converter circuit 10093586.doc M258493 in FIG. 1. The circuit 200 uses a reference voltage generator 202 (for example, D1 (TL431)) to compensate for changes in the input voltage 114, so as to ensure that the pulse width modulation signal 128 generated by the comparator 118 adjusts the output according to the reference voltage as described above. Voltage Vout. The ramp wave signal generator 116 (consisting of the element U3 (LM311) 204 and generates a triangular wave signal 126 with an amplitude of about 100 millivolts. The comparator ij 8 described above is called ⑽i!) 2. 6 configuration, receiving and outputting the electric dust Vout 112 and the triangle wave signal 126 as inputs, and generating a pulse width modulation signal 128. The driver 120 in this exemplary application is composed of U1 (TPS2830) 208. Finally, the composition of the power module 21o driving output voltage Vout 122 includes: MoSFETs Q1 and Q2m; inductance li, 130; resistance RH); and capacitor C4. This dc-to-dc converter circuit is used to improve the recovery time to load transient response. It is worth noting that the creation includes but is not limited to the components and circuits of the application schematic in FIG. 2. Another embodiment of the present invention is that two or more transition state circuits 100 may be included in the polyphase structure, wherein the phase shift angle between the two circuits is different according to the number of phases used. For example, in a four-phase structure, the phase shift angle is 90 degrees. Two phases' ·. The problem with the structure is that there is an undesired current between the two phases. For example, when one load is applied to the output, if the current delivered to the load by one phase is far away, the current output to the load by the other phase will seriously affect the conversion efficiency. This problem is similar to connecting two voltage sources in parallel. If the two voltage sources Z have different voltages', a current will flow between them. In order to solve this problem of a multi-phase DC-to-DC converter, a current balancing mechanism is needed. For example, in a single-phase DC-to-DC converter, a current balancing mode is used to adjust the wheel-out voltage of the second phase to be in phase with the output voltage of the first phase. 93586.doc -10- M258493 and so on. The current information is obtained by using a current detection resistor ', and the current balance module is used to generate an offset voltage to adjust the output voltage of the second phase. There are two options for implementing the current balancing mechanism: ⑴ by modifying the reference voltage of the second phase; or ⑺ by modifying the feedback voltage of the second phase. FIG. 3 shows an embodiment of a two-phase DC-to-DC converter 300 having a current balancing module, and the current balancing module acts on the second phase reference signal. The first phase 100a generates an output voltage 112 based on a reference signal 126a at the input of the comparator 118. The current balancing module 3101 adjusts the DC portion of the reference signal ιΐ6 and transmits it to the 10 ribs of the second phase, so that each phase transmits an equal current amplitude. Assuming that the current flowing through the first phase 100a is larger than the current flowing through the first phase 100b, the voltage at the non-inverting input terminal of the error amplifier 302 will be greater than the voltage at its inverting input terminal. The role of the error amplifier 302 is to reduce the value of the offset voltage 303, so that the DC portion of the reference voltage of the second phase i00b will increase. Therefore, the duty cycle of the second phase 100b will increase. In this way, the current value transmitted by the second phase 100b is larger than the previous current value. When the current delivered by each phase is equal, the offset voltage 303 will maintain this value, so that the current balance of each phase is reached. Fig. 4 shows another embodiment of a two-phase DC-to-DC converter 400 having a current balancing module which acts on the feedback portion of the second phase. The first phase 100a generates an output voltage Vout 112 according to a reference signal 126a at the input of the comparator 128. The current balancing module 401 translates the DC portion of the feedback voltage to the second phase 100b, so that each phase transmits an equal current amplitude. Assuming that the current flowing through the first phase 100a is larger than the current flowing through the second phase 100b, the voltage at the inverting input terminal of the error amplifier 402 is greater than the voltage at the non-inverting input terminal of 93586.doc -11-M258493. The role of the error amplifier tender is to increase the value of the offset voltage 403. After sampling, the Dc value of the feedback voltage of the second phase 101 will decrease. Therefore, the duty cycle of the second phase 100b will increase. In this way, the current value generated by the second phase 大于 is greater than the previous current value. When the current generated by each phase is equal, the N · 'offset voltage 403 will keep the value unchanged, and the current balance is reached. It is worth noting that because the current balancing module in FIG. 4 acts on the feedback voltage, the inverting and non-inverting inputs of the current balancing module in FIG. 4 and the inverting and non-inverting inputs of the current balancing module in FIG. 3 in contrast. The main advantage of the current balancing mechanism used by the converters shown in Figures 3 and 4 is that when the load changes to a transient state, both phases act to restore the output voltage to a stable state. Because the characteristics of each phase in the transient state are almost the same (there are only small differences due to the different component values used), the current balancing circuit only needs to slightly modify the reference part in Figure 3 or the loopback in Figure 4 Partial offset voltage 'causes the currents of the two phases to balance to a new state. It is also worth noting that both types of current balancing methods can be used in multi-phase sister structures. The current balancing module takes the current information from the phases and the output voltage of the wheel as input, and provides the offset voltage to the second to the second. _, So as to balance with the current of the phase. Λ-Figure 5A shows the output voltage changes with the input voltage. For a particular input voltage Vin, since the reference signal is constant, the period Dl = V0utl / Vin. That is, the duty cycle is obtained by the voltage vOuU and the reference. For example, if the input voltage is reduced to k * Vin (where k < 1), the duty cycle of the ^ Tiger phase is D2 = Vout / k * Vin, so the output voltage will decrease = the new large duty cycle. Therefore, the output voltage decreases (D2_D1) * (tooth wave parameter ^ 93586.doc -12- M258493 amplitude). Even for a very low-amplitude reference signal, since the input voltage can vary over a wide range, the output voltage still varies with the input voltage. Figure 5B shows a method for compensating the output voltage when the input voltage changes. One method to prevent the output voltage from changing with the input voltage is to generate a sawtooth wave signal whose amplitude is proportional to the input voltage and whose peak is held at a fixed DC voltage level Vref. This means that for an input voltage equal to Vin, the output voltage Vout 1 corresponds to the duty cycle, where the duty cycle is obtained by intersecting the output voltage with a reference signal, as Dl = Voutl / Vin. Therefore, if the amplitude of the sawtooth wave signal is Asawtooth and the peak value is Vref, then Voutl = Vref-Dl * Asawtooth, that is,
Vout 1 = Vref-Vout 1 * Asawtooth/Vin ， 或 Vout 1 =Vref/ (1+Asawtooth/Vin) 〇 當輸入電壓隨著係數k<l減小時，鋸齒波的振幅隨著同一 係數k減小，同時錯齒波信號的峰值保持在Vref。根據新的 輸入電壓值，工作週期為D2 = Vout2/(k*Vin)。然而由於 Vout2 = Vref - D2 * (k * Asawtooth) = Vref - Vout2 * k * Asawtooth / (k * Vin)，Vout2 = Vref /(1 + Asawtooth / Vin) 〇 即Vout 1 =Vout2。因此，輸出電壓並不隨著輸入電壓變化。 如上所述的方法的主要優點在於··（1)輸出電壓與輸入電 壓無關；（2)迴路的增益與輸入電壓無關，如此，對於各種 輸入電壓，直流至直流轉換器的特性仍保持相同。迴路的 增益實際上為Vin /Asawtooth。由於Asawtooth與Vin成比 例，所以增益為常數；和（3)輸入電壓較高時，由於切換而 93586.doc -13- M258493 造成輸出端有較高的雜訊。當鋸齒波信號振幅增大時，脈 寬調變比較器正常工作，而不會由於輸出電壓的雜訊而產 生寄生脈衝。 圖6所不為一種在輸入電壓的變化的情況下補償輸出電 壓的方法的電路圖。時脈脈衝6〇1將開關602閉合一極小段 時間，該時間足夠將電容603充電至Vref值。這樣，鋸齒波 信號的峰值正好是Vref。開關6〇2斷開，電容603以一個與 輸入電壓成比例的恒定電流放電。該電路的元件將被調整 以獲得所期望的鋸齒波振幅。該電路可以在輸入電壓變化 情況下補償輸出電壓。該電路的一種應用是在筆記型電腦 中’其中輸入電壓可以為電池電壓或配接器電壓。配接器 電壓通常為20V，其中放電電池電壓可低至8V或更小。該 系統需要在整個範圍内工作。 圖7所示為當一個負載施加於一個兩相直流至直流轉換 器或從該轉換器移除時的暫態波形圖。負載電流的步階為 20安培。CH1為輸出電壓（vout)的波形。CH2為第一相 (PWM1)的脈寬調變信號的波形。〇113為第二相（pwM2)的脈 寬调變信號的波形。CH4為％負載電流的波形。當加上該負 載（即電流從0安培增加到20安培）時，v〇ut下降。由於該轉 換器的工作週期增大，一極小段時間（該轉換器的暫態響應 約為100奈秒，這使得恢復時間小於1〇微秒）之後輸出電壓 回到其穩定狀態。當該負載被移除時，該轉換器減小工作 週期來恢復Vout。如圖7所示，每相都調整自己的脈寬調變 化號以便從暫態狀態恢復V〇ut。因此，當採用一個多相結 93586.doc M258493 構時，Vout的暫態的恢復取決於相的數目。Vout 1 = Vref-Vout 1 * Asawtooth / Vin, or Vout 1 = Vref / (1 + Asawtooth / Vin) 〇 When the input voltage decreases with the coefficient k < l, the amplitude of the sawtooth wave decreases with the same coefficient k, At the same time, the peak value of the staggered wave signal is maintained at Vref. Based on the new input voltage value, the duty cycle is D2 = Vout2 / (k * Vin). However, since Vout2 = Vref-D2 * (k * Asawtooth) = Vref-Vout2 * k * Asawtooth / (k * Vin), Vout2 = Vref / (1 + Asawtooth / Vin) 〇 That is, Vout 1 = Vout2. Therefore, the output voltage does not change with the input voltage. The main advantages of the method described above are (1) the output voltage is independent of the input voltage; (2) the gain of the loop is independent of the input voltage, so the characteristics of the DC-to-DC converter remain the same for various input voltages. The gain of the loop is actually Vin / Asawtooth. Because Asawtooth is proportional to Vin, the gain is constant; and (3) When the input voltage is high, 93586.doc -13- M258493 causes high noise at the output due to switching. When the amplitude of the sawtooth wave signal increases, the pulse width modulation comparator works normally without generating parasitic pulses due to noise from the output voltage. Figure 6 is not a circuit diagram of a method for compensating the output voltage in the case of a change in the input voltage. The clock pulse 601 closes the switch 602 for a very short period of time, which is sufficient to charge the capacitor 603 to the Vref value. Thus, the peak value of the sawtooth wave signal is exactly Vref. The switch 602 is opened, and the capacitor 603 is discharged with a constant current proportional to the input voltage. The components of this circuit will be adjusted to obtain the desired sawtooth wave amplitude. This circuit can compensate the output voltage when the input voltage changes. One application of this circuit is in a notebook computer 'where the input voltage can be battery voltage or adapter voltage. The adapter voltage is usually 20V, and the discharge battery voltage can be as low as 8V or less. The system needs to work across the entire range. Figure 7 shows a transient waveform when a load is applied to or removed from a two-phase DC-to-DC converter. The load current step is 20 amps. CH1 is the waveform of the output voltage (vout). CH2 is the waveform of the PWM signal of the first phase (PWM1). 〇113 is the waveform of the pulse width modulation signal of the second phase (pwM2). CH4 is the waveform of the% load current. When this load is added (that is, the current is increased from 0 amps to 20 amps), vout decreases. Due to the increased duty cycle of the converter, the output voltage returns to its stable state after a very short period of time (the transient response of the converter is about 100 nanoseconds, which makes the recovery time less than 10 microseconds). When the load is removed, the converter reduces the duty cycle to recover Vout. As shown in Figure 7, each phase adjusts its own pulse width modulation number to recover Vout from the transient state. Therefore, when a multiphase junction 93586.doc M258493 structure is adopted, the transient recovery of Vout depends on the number of phases.
圖8所示為本創作的一個直流至直流轉換器8〇0的另一個 實施例，其中可採用一種方法來修改信號12(5的直流電壓位 準’從而提高直流至直流轉換器8〇〇的輸出電壓的精確性。 通常’一個包括一個精確性電路802的直流迴路可調整由參 考直流電壓源114產生的參考信號126的電壓位準。偏移電 壓源806也可根據輸出電壓112端的輸出電壓位準v〇ut和參 考直流電壓源114產生的電壓位準之間的差值調整參考信 號的電壓位準。除了偏移電壓源之外，精確性電路⑽2還可 包括一個誤差放大器804。FIG. 8 shows another embodiment of a DC-to-DC converter 800, which is a creation, in which a method can be used to modify the DC voltage level of the signal 12 (5) to improve the DC-to-DC converter 800. The accuracy of the output voltage. Usually a DC circuit including an accuracy circuit 802 can adjust the voltage level of the reference signal 126 generated by the reference DC voltage source 114. The offset voltage source 806 can also be based on the output of the output voltage 112 The difference between the voltage level vout and the voltage level generated by the reference DC voltage source 114 adjusts the voltage level of the reference signal. In addition to the offset voltage source, the accuracy circuit ⑽2 may also include an error amplifier 804.
個表示直流至直流轉換器8〇〇的輸出電壓位準的信號 可經由路徑810回授至誤差放大器8〇4的一個輸入端（例如 反相輸入端）。另一個表示參考直流電壓源114的信號可經 由路徑812提供給誤差放大器8〇4的另一個輸入端(例如同 相輸入端）。誤差放大器8〇4將這兩個信號進行比較，並根 據它們的差值輸出一個控制信號至偏移電壓源8〇6。 若112端的轉換器輸出電壓位準小於參考直流電壓源… 產生的電Μ位準，則誤差放大器8〇4將輸出一個控制信號指 示偏移電壓源806產生一個正偏移電壓位準，該正偏移電： 位準將加至參考直流電壓源114產生的電壓位準。斜波參考 信號126的直流位準將相應地增大。由於斜波參考信號 的直流值較高，所以比較器118將增大其輪出脈寬調變㈣ 128的工作週期。如此，112端的轉換器輸出電壓將增二 直到達到參考直流電塵源114產生的參考直流電塵值曰。 93586.doc •15- M258493 的電壓可缓慢地變化，例如，該迴路的補償可完成，而使 得具有小於-個單位的頻率增益及至少低於電感電 雙極的十分之-。現在參考圖9,為本創作的—個直流至直 流轉換器9GG的另-個實施例’其中可調整從Vqu⑴2端到 比較118的回授值，從而提高直流至直流轉換器刚的精 確性。通常，一個包括一個精確性電路9〇2的直流迴路可根 據轉換器輸出電壓位準Vout和參考直流電壓源114產生的X 電壓位準之間的差值調整一個回授信號，該回授信號表示 轉換器900的輸出電壓。精確性電路9〇2可包括一個爷差放 大器904和一個偏移電壓源906。 若112端的轉換器輸出電麼位準大於參考直流電屋源m 產生的電壓位準，那麼誤差放大器8〇4將輸出一個控制信號 指示偏_源806產生一個負偏移電屋位準，該負偏移電 壓位準將加至參考直流電壓源114產生的電屢位準。斜波參 考信號126的直流位準將相應地減小。由於斜波參考信號 的直流值較低，所以比較器128將減小其輸出脈寬調變 4唬128的工作週期。如此，112端的轉換器輸出電壓將減 小’直到達到參考直流電壓源114產生的參考直流電壓值。 該直流精確性迴路調整直流電屡源114產生的參考信號直 流位準，正如偏移電麼源_調整該參考信號直流位準，該 直流精確性迴路為-個慢速迴路，這樣，偏移電壓源8〇6 一個表示直流至直流轉換器的輸出電壓位準的信號可經 由路徑910饋回誤差放大器904的一個輸入端（例如同相= 入端）。另一個表示參考直流電壓源114的直流輪出電壓2 93586.doc -16- M258493 準的信號可經由路徑912提供給誤差放大器904的另-個輸 入端（例如反相輸人端）。誤差放大器9()4將這兩個信號進: 比較’並根據這兩個信號的差值提供一個控制信號至偏移 電壓源906。值得注意的是由於圖9中的精確性電路9〇2係作 用於回授電壓，所以圖9誤差放大器9〇4的反相和同相輸入 端與圖8中的誤差放大器8〇4的反相和同相輸入端相反。 若112端的轉換器輸出電壓位準小於參考直流電屡源114 產生的電壓位準，那麼誤差放大器9〇4將輸出一個控制信號 指不偏移電壓源9G6產生-個負偏移電壓位準，該負偏移電 壓位準將加至與㈣授信號，使該回授錢相應地減小。 由於經由路徑914饋至比較器118的信號小於該回授信號 (否則在這種情況下無需負偏移），所以比較器ιΐ8的脈寬調 變信號128的工作週期將增大。接著，增大的工作週期使轉 換盗900的輸出端112處的輸出電壓增大，直到達到參考直 流電壓源114產生的參考值。 / 相反地，若112端的轉換器輸出電壓位準大於參考直流電 壓源m產生的電壓位準，那麼誤差放大器類將輸出丄個 控制信號指示偏移電壓源906產生一個正偏移電壓位準，該 正偏移電壓位準將加至回授信號’使該回授信號相應地增 大。由於經由路徑914至比較器118的信號大於該回授信號 (否則在這種情況下無需正偏移），所以比較器118輸出的脈 寬凋k 唬128的工作週期將減小。接著，減小的工作週期 使轉換器900的輸出端112處的輸出電壓減小’直到達到參 考直流電Μ源114產生的參考值。調整比較器118的回授電 93586.doc M258493 壓位準的直流精確性迴路9 1 2為一個慢速迴路，從而偏移電 壓源906的電壓可緩慢地變化。 本創作直流至直流轉換器的穩定性可通過採用電感電流 資訊（圖10至圖11)或交流電流資訊（圖12至圖13)來改進。圖 10所示為本創作直流至直流轉換器10〇〇的另一個實施例， 该貫施例採用電感電流資訊來改進穩定性。通常，V〇ut 112 端的回授電壓值經由一個回授路徑至比較器11 8，該回授電 壓可通過一個穩定性電路1022來改進，從而增強直流至直 流轉換器1000的穩定性。 穩定性電路1022可包括一個運算放大器1〇26，以及電阻 R1和R2。檢測電阻1〇3〇還可與電感L1串聯。檢測電阻1〇3〇 兩端的電壓表示流經電感L1的電流。流經電感L1的電流由 電阻R1和電阻R2設置的係數放大，且等於 Acmrent=l+R2/Rl。如此，在圖1〇的實施例中，回授至比 較器118的反相輸入端的回授電壓VPWM值由等式（1)給出。 (l)VPWM comparator=V〇ut+(l+R2/Rl)*Iinductor*RCS ； 在等式（1)中，Vout為直流至直流轉換器looo的輸出電 壓，R1和R2分別為電阻ri和R2的歐姆電阻值，Iinduct〇r為 流經電感L1的電感電流，和rCS為檢測電阻1〇3〇的電阻 值。如此，穩定性由於電感電流只平移9〇度而得到改進。 另外，輸出電壓Vout隨著電感電流增大而減小，從而減小 了在暫態期間輸出電壓的範圍。 圖11所示的穩定性電路1103還可包括一個由電阻114〇和 電容1142組成的電阻電容電路11〇2。如此，穩定性還 93586.doc -18- M258493 可通過在由電感L1和電容C 1組成的雙重極點的頻率範圍中 增加零點來改進。 穩定性還可通過利用交流電流資訊來改進。例如，圖^ 2 所示的穩定性電路1203可包括一個電感電容（rc)電路 1226，該電感電容電路1226在由電感L1和電容C1組成的雙 重極點的頻率範圍内加入一個零點。電感電容電路丨226可 包括並聯的電阻R1和R2和電容Ccomp。由電阻R1和R2組成 的分壓器將輸出電壓按比例減小至一個期望值。應當選擇 電容Ccomp的值，使得電感電容電路1226在電感L1和電容 C1組成的雙重極點的頻率範圍内可以加入一個零點。電感 電容電路1226的電感電容雙重極點位置和電感電容時間常 數之間的關係由實驗得出，並得到仿真驗證，並由等式（2) 給出。 (2)3 RC= Vzc 圖13所示為將一個放大因數為n的放大器1324加入穩定 性電路1342。放大器1324的輸入可與節點1346相連，而放 大^§ 13 2 4的輸出可與電容Ccomp相連。如此，放大器1 3 2 4 的輸出通過電容Ccomp與電阻R1和R2並聯組成的回授分壓 器相連。電感電容電路1326包括電容C comp和並聯的電阻 R1和R2。如此，直流至直流轉換器1300的穩、定彳生還可通過 放大交流電流資訊來改進。然而，為了保持比較器11 8產生 清晰、穩定的脈寬調變脈衝，放大因數N的大小有一個特定 的範圍。例如，回授信號交流峰-峰振幅應當小於斜波參考 信號126的振幅。如此，就要通過限制放大因數N來滿足這 93586.doc -19- M258493 個要求。例如，若節點1346處的電壓漣波的峰-峰值為丨〇毫 伏且斜波參考信號126的振幅為1〇〇毫伏，那麼放大器1324 的放大因數應小於10。放大器1324放大的漣波流經電容 Ccomp，且在漣波頻率處，該漣波電壓將與電阻汉丨和们和 Ccomp的公共節點處的振幅幾乎相同。在一個實施例中， 放大因數N約為5或6較為合適。 本領域的技術人員瞭解雖然圖9至圖13所示的對精確性 和穩定性的改進應用于—個單相直流至直流轉換器，但是 這些改進同樣也適用於多相直流至直流轉換器。 在此所述的實施例只是㈣本創作的其中幾個，但並不 受限於本創作。顯而易i，還存在其他本領域的技術人員 瞭解的並不脫離附加申請專利範圍所定義的本創作 和範圍的實施例。 【圖式簡單說明】 換器的一個實施例的電路圖； 圖2所示為圖1中的直流至 的電路圖； 二所示為本創作的一種快速暫態響應的直流至直流轉 個示範性應月 器的一個實施例的 個作用於該第二相 圖3所示為一種兩相直流至直流轉換 電路圖，該兩相直流至直流轉換器與一 的參考信號的電流平衡模組耦接； 圖4所示為一種兩相直流至直流轉換器 的電路圖，該兩相直流至直流轉換器與固個實她例 相的回授側的電流平衡模組耦接； 、以弟一 93586.doc -20- M258493 圖5A所示為該直流至直流轉換器的輸出電壓隨著輸入電 壓而變化的示意圖； 圖5B所示為一種採用輸入電壓補償輸出電壓的方法的示 意圖； 圖6所示為根據輸入電壓的變化而補償輸出電壓的機制 之電路圖； 圖7所示為當一個負載施加於一個兩相直流至直流轉換 器或從該轉換器移除時的輸出電壓、負載電流和脈寬調變 信號的波形圖； 圖8所示為一種具有一個精確性電路的示範性直流至直 流轉換器，言亥精確十生電路作用於一個#考電壓來改進該直 至直轉換為輸出電壓的精確性； 圖9所示為-種具有—個精確性電路的示範性直流至直 流轉換器，該精確性電路仙於—個回授信號來改進該直 至直&L轉換輸出電壓的精確性。 圖10所#為-種具有—個敎性電路的示範性直流至直 流轉換器’該穩定性電路採用電感電流資訊來改進該直流 至直流轉換器的穩定性； 圖11所示為圖1G中的示範性直流至直流轉換器，其中該 穩定性電路包括一個電阻電容（RC)電路； 圖12所不為-種具有—個穩定性電路的示範性直流至直 流轉換器’該穩定性電路採用電感的交流(AC)電流資訊來 改進該直流至直流轉換器的穩定性；及 圖13所示為圖12中的示範性直流至直流轉換器，其中該 93586.doc M258493 穩定性電路包括一個放大器。 【主要元件符號說明】 100 > 800 - 900 > 1000 ' 1300 直流至直流轉換器 100a 第一相 100b 第二相 112 輸出電壓（Vout) 114 直流參考電壓源（Vref) 116 斜波信號產生器 118 、 206 比較器 120 > 208 驅動器 122 開關 124 回授迴路 126 、 126a 參考信號 128 脈寬調變信號 130 電感 200 應用電路 202 參考電壓產生器 204 斜波產生器 210 電源模組 300 、 400 兩相直流至直流轉換器 301 、 401 電流平衡模組 302 、 402 誤差放大器 303 、 403 偏移電壓 601 時脈脈衝 93586.doc -22- M258493 602 開關 603、 1142 電容 802、 902 精確性電路 804、 904 誤差放大器 806、 906 偏移電壓源 810、 812 、 910 、 912 、 914 路徑 1022 ^ 1203 、 1342 穩定性電路 1026 運算放大器 1030 檢測電阻 1102 電阻電容電路 1103 穩定性電路 1140 電阻 1226 、1326 電感電容電路 1324 放大器 1346 節點 93586.doc -23-A signal representing the output voltage level of the DC-to-DC converter 800 may be fed back to one input terminal (for example, an inverting input terminal) of the error amplifier 800 through a path 810. Another signal representing the reference DC voltage source 114 may be provided via path 812 to the other input (e.g., non-inverting input) of the error amplifier 804. The error amplifier 804 compares the two signals and outputs a control signal to the offset voltage source 806 based on their difference. If the output voltage level of the converter at terminal 112 is lower than the reference voltage level generated by the reference DC voltage source, the error amplifier 804 will output a control signal to instruct the offset voltage source 806 to generate a positive offset voltage level. Offset: The level will be added to the voltage level generated by the reference DC voltage source 114. The DC level of the ramp reference signal 126 will increase accordingly. Because the DC value of the ramp reference signal is high, the comparator 118 will increase the duty cycle of its round-out pulse width modulation ㈣ 128. In this way, the output voltage of the converter at terminal 112 will increase by two until it reaches the reference DC dust value generated by the reference DC dust source 114. 93586.doc • The voltage of 15-M258493 can change slowly. For example, the compensation of this loop can be completed to have a frequency gain of less than -units and at least less than one-tenth of the -inductive bipolar. Referring now to FIG. 9, another DC-DC converter 9GG another embodiment of the present invention is created, in which the feedback value from the Vqu⑴ 2 terminal to the comparison 118 can be adjusted, thereby improving the accuracy of the DC-DC converter. Generally, a DC circuit including a precision circuit 902 can adjust a feedback signal according to the difference between the converter output voltage level Vout and the X voltage level generated by the reference DC voltage source 114. The feedback signal The output voltage of the converter 900 is shown. The precision circuit 902 may include a differential amplifier 904 and an offset voltage source 906. If the output level of the converter at terminal 112 is greater than the voltage level generated by the reference DC power source m, the error amplifier 804 will output a control signal indicating that the bias source 806 generates a negative offset power level. The offset voltage level is added to the electrical level generated by the reference DC voltage source 114. The DC level of the ramp reference signal 126 will decrease accordingly. Because the DC value of the ramp reference signal is low, the comparator 128 will reduce the duty cycle of its output pulse width modulation. In this way, the output voltage of the converter at terminal 112 will decrease 'until it reaches the reference DC voltage value generated by the reference DC voltage source 114. The DC accuracy loop adjusts the DC level of the reference signal generated by the DC source 114, just as the offset current source_adjusts the DC level of the reference signal. The DC accuracy loop is a slow loop. In this way, the offset voltage Source 806 A signal representing the output voltage level of the DC-to-DC converter may be fed back to one input terminal (eg, non-inverting = input terminal) of the error amplifier 904 via the path 910. Another standard signal representing the DC wheel output voltage 2 93586.doc -16- M258493 of the reference DC voltage source 114 can be provided to the other input terminal of the error amplifier 904 via the path 912 (for example, the inverting input terminal). The error amplifier 9 () 4 inputs these two signals: compare 'and provides a control signal to the offset voltage source 906 based on the difference between the two signals. It is worth noting that because the precision circuit 902 in FIG. 9 acts on the feedback voltage, the inverting and non-inverting input terminals of the error amplifier 904 in FIG. 9 and the inversion of the error amplifier 804 in FIG. 8 The opposite of the non-inverting input. If the output voltage level of the converter at terminal 112 is lower than the voltage level generated by the reference DC power source 114, the error amplifier 904 will output a control signal indicating that the non-offset voltage source 9G6 generates a negative offset voltage level. The negative offset voltage level will be added to the feedback signal, so that the feedback money will be reduced accordingly. Since the signal fed to the comparator 118 via path 914 is smaller than the feedback signal (otherwise a negative offset is not required in this case), the duty cycle of the pulse width modulation signal 128 of the comparator 8 will increase. Then, the increased duty cycle increases the output voltage at the output terminal 112 of the converter 900 until it reaches the reference value generated by the reference DC voltage source 114. / Conversely, if the output voltage level of the converter at terminal 112 is greater than the voltage level generated by the reference DC voltage source m, the error amplifier class will output a control signal to instruct the offset voltage source 906 to generate a positive offset voltage level. The positive offset voltage level will be added to the feedback signal 'to increase the feedback signal accordingly. Since the signal via the path 914 to the comparator 118 is greater than the feedback signal (otherwise a positive offset is not required in this case), the duty cycle of the pulse width output 128 of the comparator 118 will be reduced. Next, the reduced duty cycle reduces the output voltage at the output 112 of the converter 900 'until it reaches the reference value generated by the reference DC power source 114. The feedback accuracy of the comparator 118 is adjusted. 93586.doc M258493 The DC accuracy loop 9 1 2 of the voltage level is a slow loop, so the voltage of the offset voltage source 906 can be changed slowly. The stability of this creative DC-DC converter can be improved by using inductor current information (Figures 10 to 11) or AC current information (Figures 12 to 13). FIG. 10 shows another embodiment of the creative DC-to-DC converter 100, which uses the inductor current information to improve stability. In general, the feedback voltage value at the VOUT terminal 112 passes through a feedback path to the comparator 118, and the feedback voltage can be improved by a stability circuit 1022, thereby enhancing the stability of the DC-to-DC converter 1000. The stability circuit 1022 may include an operational amplifier 1026, and resistors R1 and R2. The sense resistor 1030 can also be connected in series with the inductor L1. The voltage across the sense resistor 1030 represents the current flowing through the inductor L1. The current flowing through the inductor L1 is amplified by the coefficients set by the resistors R1 and R2, and is equal to Acmrent = l + R2 / Rl. Thus, in the embodiment of FIG. 10, the feedback voltage VPWM value fed back to the inverting input terminal of the comparator 118 is given by equation (1). (l) VPWM comparator = V〇ut + (l + R2 / Rl) * Iinductor * RCS; In equation (1), Vout is the output voltage of the DC-to-DC converter looo, and R1 and R2 are the resistances ri and R2, respectively. The ohmic resistance value, Iinductor is the inductor current flowing through the inductor L1, and rCS is the resistance value of the detection resistor 1030. In this way, stability is improved because the inductor current is only translated by 90 degrees. In addition, the output voltage Vout decreases as the inductor current increases, thereby reducing the range of the output voltage during the transient state. The stability circuit 1103 shown in FIG. 11 may further include a resistance-capacitance circuit 1102 composed of a resistor 114o and a capacitor 1142. In this way, the stability is also 93586.doc -18- M258493 can be improved by adding a zero point in the frequency range of the double pole composed of the inductor L1 and the capacitor C 1. Stability can also be improved by using AC current information. For example, the stability circuit 1203 shown in FIG. 2 may include an inductor-capacitor (rc) circuit 1226. The inductor-capacitor circuit 1226 adds a zero point in the frequency range of the double poles composed of the inductor L1 and the capacitor C1. The inductive capacitor circuit 226 may include resistors R1 and R2 and a capacitor Ccomp in parallel. A voltage divider consisting of resistors R1 and R2 reduces the output voltage proportionally to a desired value. The value of the capacitor Ccomp should be selected so that the inductor-capacitor circuit 1226 can add a zero point in the frequency range of the double pole composed of the inductor L1 and the capacitor C1. The relationship between the double pole position of the inductor and capacitor and the time constant of the inductor and capacitor of the inductor and capacitor circuit 1226 is obtained experimentally, verified by simulation, and given by equation (2). (2) 3 RC = Vzc Figure 13 shows that an amplifier 1324 with an amplification factor of n is added to the stability circuit 1342. The input of the amplifier 1324 can be connected to the node 1346, and the output of the amplifier ^ § 13 2 4 can be connected to the capacitor Ccomp. In this way, the output of the amplifier 1 3 2 4 is connected through a capacitor Ccomp to a feedback divider composed of resistors R1 and R2 in parallel. The inductive capacitor circuit 1326 includes a capacitor C comp and resistors R1 and R2 connected in parallel. In this way, the stability and stability of the DC-to-DC converter 1300 can also be improved by amplifying the AC current information. However, in order to keep the comparator 118 to produce a clear and stable pulse width modulation pulse, the magnitude of the amplification factor N has a specific range. For example, the AC signal peak-to-peak amplitude of the feedback signal should be smaller than the amplitude of the ramp reference signal 126. In this way, it is necessary to satisfy these 93586.doc -19- M258493 requirements by limiting the amplification factor N. For example, if the peak-to-peak voltage ripple at node 1346 is 100 millivolts and the amplitude of the ramp reference signal 126 is 100 millivolts, the amplification factor of amplifier 1324 should be less than ten. The ripple amplified by the amplifier 1324 flows through the capacitor Ccomp, and at the ripple frequency, the ripple voltage will be almost the same as the amplitude at the common node of the resistors and Ccomp. In one embodiment, an amplification factor N of about 5 or 6 is more appropriate. Those skilled in the art understand that although the improvements in accuracy and stability shown in FIGS. 9 to 13 are applied to a single-phase DC-to-DC converter, these improvements are also applicable to multi-phase DC-to-DC converters. The embodiments described here are just a few of the examples, but are not limited to this example. Obviously, there are other embodiments known to those skilled in the art that do not depart from the scope of the present invention as defined by the scope of the appended patent application. [Brief description of the diagram] A circuit diagram of an embodiment of the converter; FIG. 2 shows a circuit diagram of the DC-to-DC converter in FIG. 1; One embodiment of the moon device acts on the second phase. FIG. 3 shows a two-phase DC-to-DC conversion circuit diagram. The two-phase DC-to-DC converter is coupled to a current balance module of a reference signal. 4 shows a circuit diagram of a two-phase DC-to-DC converter, which is coupled to a current-balance module on the feedback side of a solid phase; 弟 一 93586.doc- 20- M258493 Figure 5A shows the output voltage of the DC-to-DC converter as a function of input voltage; Figure 5B shows a schematic diagram of a method that uses input voltage to compensate the output voltage; Figure 6 shows a method based on the input Circuit diagram of the mechanism of compensating the output voltage with the change in voltage; Figure 7 shows the output voltage, load current, and load current when a load is applied to or removed from a two-phase DC-to-DC converter. Waveform diagram of pulse width modulation signal; Figure 8 shows an exemplary DC-to-DC converter with a precision circuit. The Yan Hai precision circuit works on a #test voltage to improve this until it is directly converted to the output voltage. Figure 9 shows an exemplary DC-to-DC converter with a precision circuit based on a feedback signal to improve the accuracy of the output voltage up to DC & L Sex. FIG. 10 # is an exemplary DC-DC converter with a flexible circuit. The stability circuit uses inductor current information to improve the stability of the DC-DC converter; FIG. 11 is shown in FIG. 1G An exemplary DC-to-DC converter, wherein the stability circuit includes a resistor-capacitor (RC) circuit; FIG. 12 does not show an exemplary DC-to-DC converter with a stability circuit. Inductive alternating current (AC) current information to improve the stability of the DC-to-DC converter; and FIG. 13 shows an exemplary DC-to-DC converter in FIG. 12, where the 93586.doc M258493 stability circuit includes an amplifier . [Description of main component symbols] 100 > 800-900 > 1000 '1300 DC-DC converter 100a first phase 100b second phase 112 output voltage (Vout) 114 DC reference voltage source (Vref) 116 ramp signal generator 118, 206 comparator 120 > 208 driver 122 switch 124 feedback circuit 126, 126a reference signal 128 pulse width modulation signal 130 inductor 200 application circuit 202 reference voltage generator 204 ramp generator 210 power module 300, 400 two Phase DC-to-DC converters 301, 401 current balancing modules 302, 402 error amplifiers 303, 403 offset voltage 601 clock pulses 93586.doc -22- M258493 602 switches 603, 1142 capacitors 802, 902 accuracy circuits 804, 904 Error amplifiers 806, 906 Offset voltage sources 810, 812, 910, 912, 914 Path 1022 ^ 1203, 1342 Stability circuit 1026 Operational amplifier 1030 Detection resistor 1102 Resistor capacitor circuit 1103 Stability circuit 1140 Resistor 1226, 1326 Inductance capacitor circuit 1324 Amplifier 1346 node 93586.doc -23-