JP6749591B2 - Display device and method of manufacturing display device - Google Patents

Description

The present disclosure relates to a display device and a method for manufacturing the display device.

An organic light emitting display device displays an image using an organic light emitting element (OLED) (see Patent Document 1). Note that an OLED display device is referred to as a display device.

A pixel forming an image display portion of a display device has a stacked body of an organic light emitting element which is a self light emitting element and a pixel circuit. The pixel circuit supplies a driving current to the organic light emitting element. The pixel circuit includes a TFT (Thin Film Transistor) and a storage capacitor. The display device determines the brightness of each of the plurality of pixels based on an image signal acquired from the outside. The display device controls the pixel circuit so as to supply a driving current according to the brightness to the organic light emitting element.

JP, 2014-163991, A

In some cases, the current corresponding to the image signal and the drive current actually supplied to the organic light emitting element do not match. Due to such a mismatch, the brightness of the organic light emitting element in the display panel may become non-uniform (so-called brightness unevenness). When uneven brightness occurs, the image quality deteriorates.

In one aspect, it is an object to provide a display device that suppresses deterioration of image quality.

One aspect of a display device of the present disclosure includes a light emitting element in which a first electrode, a light emitting layer, and a second electrode are stacked, and a current supplied to the light emitting element, which has a source electrode connected to the first electrode. A pixel circuit provided with a driving transistor for controlling, disposed below the light emitting element, a first metal plate and a second metal plate disposed facing the light emitting layer with the first electrode interposed therebetween, A first metal plate and a second metal plate, and a first insulating layer arranged between the first metal plate and the first electrode, wherein the first metal plate is connected to a gate electrode of the drive transistor, The second metal plate is connected to the wiring of the first voltage, and the first metal plate and the second metal plate are arranged on the same surface.

According to one aspect, it is possible to provide a display device that suppresses deterioration of image quality.

It is an external view of a display device. It is a schematic diagram which shows arrangement|positioning of a pixel. It is an equivalent circuit diagram which shows the circuit which makes one organic light emitting element emit light. It is a schematic cross section of a display device. It is a schematic plan view of a pixel. It is a schematic plan view of a second insulating layer. It is a model top view of the pixel which removed the 2nd insulating layer. It is a schematic plan view of a 1st electrode. It is a schematic plan view of a metal plate layer. It is explanatory drawing which shows the method of producing an insulating film. 6 is a graph illustrating unevenness in the thickness of an insulating film. It is a top view of a unit insulating film. It is a sectional view of a unit insulating film. It is a flow chart which shows a flow of manufacture of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is a hardware block diagram of a display device. FIG. 6 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element of Embodiment 2 to emit light. 7 is a time chart showing an input voltage Vinput of the second embodiment. FIG. 11 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element of Embodiment 3 to emit light. FIG. 9 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element of Embodiment 4 to emit light. FIG. 13 is a schematic cross-sectional view of the display device in the fifth embodiment. FIG. 16 is a schematic plan view of a pixel according to the fifth embodiment. FIG. 13 is a schematic plan view of a second insulating layer according to the fifth embodiment. FIG. 17 is an explanatory diagram showing a manufacturing process of the display panel of the fifth embodiment. FIG. 17 is an explanatory diagram showing a manufacturing process of the display panel of the fifth embodiment. FIG. 17 is an explanatory diagram showing a manufacturing process of the display panel of the fifth embodiment. FIG. 17 is an explanatory diagram showing a manufacturing process of the display panel of the fifth embodiment. FIG. 17 is an explanatory diagram showing a manufacturing process of the display panel of the fifth embodiment. FIG. 17 is an explanatory diagram showing a manufacturing process of the display panel of the fifth embodiment. FIG. 17 is an explanatory diagram showing a manufacturing process of the display panel of the fifth embodiment. FIG. 16 is a schematic cross-sectional view of the display device in the sixth embodiment. FIG. 16 is a schematic plan view of a pixel according to the sixth embodiment. FIG. 16 is a schematic cross-sectional view of the display device in the seventh embodiment. FIG. 19 is a schematic plan view of a pixel according to the seventh embodiment. FIG. 16 is a schematic cross-sectional view of the display device in the eighth embodiment. FIG. 16 is a schematic cross-sectional view of a display device of a comparative example of the eighth embodiment. It is an equivalent circuit diagram which shows the circuit which makes one organic light emitting element of Embodiment 9 light-emit. 23 is a time chart relating to the driving of the circuit of the ninth embodiment. 23 is a graph showing changes in VD and VS in the circuit according to the ninth embodiment.

Hereinafter, embodiments of the display device will be described with reference to the drawings. Note that ordinal numbers such as “first” and “second” in the specification and claims are given to clarify the relationship between elements and to prevent confusion between elements. Therefore, these ordinal numbers do not numerically limit the elements.

In addition, the dimensions and ratios of the illustrated components may not be illustrated to match the actual components. In addition, for the convenience of illustration and description of the drawings, components included in the actual product may be omitted, or dimensions of the illustrated components may be exaggerated relative to the components included in the actual product.

The term “connection” means that the objects to be connected are electrically connected. "Electrically connected" also includes the case where the connection targets are connected via electrical elements such as electrodes, wirings, resistors, and capacitors. Note that the terms "electrode" and "wiring" do not functionally limit these components. For example, the "wiring" can be used as a part of the "electrode". On the contrary, the “electrode” can be used as a part of the “wiring”.

[Embodiment 1]
FIG. 1 is an external view of the display device 10. FIG. 1 is a view of the display device 10 as seen from the front side, that is, the side on which an image is displayed. The display device 10 is a device that displays a still image and a moving image. The display device 10 is used by incorporating it into an electronic device. The electronic device is, for example, a smartphone, a tablet terminal, a personal computer, a television, or the like. The display device 10 of the present embodiment is an OLED display panel (hereinafter abbreviated as a display panel). In the following description, the upper, lower, left and right sides of each figure will be used.

The display device 10 includes a second substrate 12, a driver IC 13, FPCs (Flexible Printed Circuits) 14, and a display substrate 16. The display substrate 16 is a glass substrate provided on one surface with the image display unit 15, the drive circuit 20, wiring (not shown), and the like.

The second substrate 12 is, for example, a glass substrate that covers the image display unit 15 and the drive circuit 20. The second substrate 12 may be a flexible substrate. A space 27 (see FIG. 4) between the second electrode 19 and the second substrate 12 is hermetically sealed by a sealing unit 25 that surrounds the image display unit 15 and the drive circuit 20. The space 27 is filled with an inert gas such as nitrogen gas.

The driver IC 13 is an integrated circuit which is mounted on the display substrate 16 using an anisotropic conductive film and is electrically connected to the display substrate 16. The function of the driver IC 13 will be described later.

The FPC 14 is a flexible substrate connected to the display substrate 16. The FPC 14, the driver IC 13, and the drive circuit 20 included in the display substrate 16 are connected via wiring (not shown). The display device 10 acquires an image signal from the control device of the electronic device via the FPC 14.

The image display unit 15 includes a large number of regularly arranged pixels 90 (see FIG. 2 ). The image display unit 15 is covered with the second electrode 19. The pixel 90 has three sub-pixels 99 (see FIG. 5). The relationship between the pixel 90 and the sub pixel 99 will be described later.

The sub-pixel 99 includes an organic light emitting element 97 (see FIG. 3) and a pixel circuit that controls a current supplied to the organic light emitting element 97. The organic light emitting element 97 emits light based on the current supplied by the pixel circuit. The pixel circuit will be described later.

The second electrode 19 is a common electrode connected to each sub-pixel 99. The second electrode 19 is a semi-transparent electrode made of, for example, ITO (Indium Tin Oxide), transparent conductive ink, or graphene. Further, the material of the second electrode 19 may be, for example, silver (Ag), magnesium (Mg), calcium (Ca), or the like laminated in a very thin film, or an alloy thereof (for example, a MgAg alloy). The second electrode 19 is the cathode electrode of the organic light emitting device 97 of this embodiment.

The drive circuit 20 includes a scan driver 21, a data voltage driver 22, an emission control driver 23, and a protection circuit 24. The drive circuit 20 is formed by a semiconductor process. It should be noted that part of the drive circuit 20 does not have to be formed on the display substrate 16 by incorporating the function in the driver IC 13. Further, the data voltage driver 22 may not be formed on the display substrate 16. The outline of the drive circuit 20 will be described below.

The scan driver 21 is located outside the image display unit 15 along the left side of the image display unit 15. The scan driver 21 sequentially drives the plurality of pixels 90 arranged in each row in units of rows to control light emission. In other words, the scan driver 21 controls the light emission of the pixel 90 by driving the wiring (see FIG. 2) extending in the lateral direction from the scan driver 21. Hereinafter, this wiring will be appropriately referred to as a scanning line.

Thick line arrows in the vertical direction in FIG. 1 indicate the scanning direction. The scan driver 21 displays an image on the image display unit 15 by switching the scanning line to be driven in the scanning direction. Note that the scan driver 21 may switch the scan lines either from the upper side to the lower side of the image display unit 15 or from the lower side to the upper side. Further, the scan driver 21 may switch the scan lines in any order. Further, depending on the application, there are cases in which two or more scanning lines are simultaneously selected and driven, and the combination of the selected scanning lines is switched.

The data voltage driver 22 is located outside the image display unit 15 along the lower side of the image display unit 15. The data voltage driver 22 outputs a signal indicating the brightness of the pixel 90 based on the image signal acquired via the FPC 14 to the data line of the image display unit 15. The signal voltage is simultaneously stored in the capacitance of each pixel 90 arranged on one scanning line.

The emission control driver 23 is located outside the image display unit 15 along the right side of the image display unit 15. The emission control driver 23 is a circuit that controls the light emission time of each organic light emitting element 97 in the image display unit 15.

The protection circuit 24 is located outside the image display unit 15 along the upper side of the image display unit 15. The protection circuit 24 is a circuit that prevents damage to the display panel due to electrostatic discharge or the like.

FIG. 2 is a schematic diagram showing the arrangement of the pixels 90. The pixels 90 are arranged in a matrix on the image display unit 15. The scan driver 21 and the data voltage driver 22 are located outside the image display unit 15. A wiring extending in the horizontal direction from the scan driver 21 is connected to each pixel 90. A wiring extending in the vertical direction from the data voltage driver 22 is also connected to each pixel 90. That is, each pixel 90 is connected to the scan driver 21 and the data voltage driver 22.

As described above, each pixel 90 has three sub-pixels 99. The signals output from the scan driver 21 and the data voltage driver 22 to each pixel 90 are input to the three sub-pixels 99. The signals output from the scan driver 21 and the data voltage driver 22 to each pixel 90 will be described later.

FIG. 3 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element 97 to emit light. In FIG. 3, one organic light emitting element 97 is described by using a symbol of OLED (Organic Light Emitting Diode) which means an organic light emitting diode. Each pixel 90 shown by a rectangle in FIG. 2 includes three circuits shown in FIG. That is, each sub-pixel 99 includes one circuit shown in FIG. The circuit shown in FIG. 3 is an example of a pixel circuit included in one sub-pixel 99.

The pixel circuit shown in FIG. 3 is a circuit that controls the light emission of the organic light emitting element 97, and includes a first capacitor 91, a second capacitor 92, a switch transistor 96, and a drive transistor 98. The source electrode of the driving transistor 98 is an example of the source electrode of this embodiment. The gate electrode of the driving transistor 98 is an example of the gate electrode of this embodiment.

A high power supply line ELVDD, a low power supply line ELVSS, an input line Vinput, a switch line S1 and a fixed potential line VFIX are connected to the circuit. Here, the low power supply line is a power supply line to which a voltage whose voltage value is lower than that of the high power supply line is supplied. The input line Vinput is connected to the data voltage driver 22. The voltage of the input line Vinput alternates between the reference voltage Vref (an example of the third voltage) and the data voltage. The data voltage is a voltage indicating the light emission luminance when the organic light emitting element 97 emits light. The switch line S1 is connected to the scan driver 21.

The input line Vinput is connected to the drain electrode of the switch transistor 96. The switch line S1 is connected to the gate electrode of the switch transistor 96. The high power supply line ELVDD is connected to the drain electrode of the drive transistor 98. The low power supply line ELVSS is connected to the cathode electrode of the organic light emitting element 97. The fixed potential line VFIX (in other words, the wiring for the first voltage) is connected to the first terminal of the second capacitor 92. The first terminal of the second capacitor 92 is, for example, the second metal plate 352 described in FIG. The drive transistor 98 and the switch transistor 96 of this embodiment are N-type TFTs.

The source electrode of the switch transistor 96 is connected to the first terminal of the first capacitor 91 and the gate electrode of the drive transistor 98. The first terminal of the first capacitor 91 is connected to the gate electrode of the drive transistor 98. The source electrode of the drive transistor 98 is connected to the second terminal of the first capacitor 91, the second terminal of the second capacitor 92, and the anode electrode of the organic light emitting element 97. The first terminal of the first capacitor 91 is, for example, the first metal plate 351 described in FIG.
Here, the first electrode 18 described in FIG. 4 (for example, the anode electrode of the organic light emitting element 97) is used as the second terminal of the first capacitor 91 and the second terminal of the second capacitor 92.

The organic light emitting element 97 emits light based on a signal input from the switch line S1 and the input line Vinput. Details of operations of the switch transistor 96 and the drive transistor 98 will be described later.

FIG. 4 is a schematic cross-sectional view of the display device 10. FIG. 4 is an enlarged view showing a portion including one organic light emitting element 97. In the following description, the upper side of the schematic cross-sectional view shows the front side of the display device 10.

The display device 10 may have a TFE sealing structure in which the image display unit 15 is covered with a multilayer TFE (Thin Film Encapsulation) stack in which an inorganic film and an organic film are alternately stacked. In this case, the display device 10 does not include the second substrate 12 and the space 27.

The display substrate 16 includes a first stacked body 61 and a second stacked body 62. The first stacked body 61 has an organic light emitting element 97 in which the first electrode 18, the organic light emitting layer 47, and the second electrode 19 are stacked. More specifically, the first stacked body 61 includes the first electrode 18, the second insulating layer 46, the organic light emitting layer 47, and the second electrode 19. The first stacked body 61 is also referred to as an OLED layer. The second stacked body 62 is also called a TFT layer or a pixel circuit layer. The first transistor 371 in the second stacked body 62 corresponds to, for example, the drive transistor 98 (see FIG. 3) that controls the current supplied to the organic light emitting element 97. The second transistor 372 in the second stacked body 62 corresponds to the switch transistor 96 (see FIG. 3) that controls the operation of the drive transistor 98. As described above, the display device 10 includes the pixel circuit (see FIG. 3) arranged below the organic light emitting element 97. It should be noted that the lower side means the lower side of the drawing in FIG.

The first electrode 18 is an electrode separated for each organic light emitting element 97. The first electrode 18 has a planar shape. The first electrode 18 is, for example, an electrode having a three-layer structure in which ITO, silver and ITO are laminated. The first electrode 18 is an anode electrode of the organic light emitting device 97 of this embodiment.

The second insulating layer 46 is located on the first electrode 18. The second insulating layer 46 has an opening 461 that does not cover the first electrode 18. In the following description, the insulating layer 46 excluding the opening 461 is referred to as a non-opening 462. The second insulating layer 46 is a layer made of an organic material.

The organic light emitting layer 47 is located around the opening 461 and the opening 461. The organic light emitting layer 47 is a layer of an organic compound that emits light when a current flows. The organic light emitting layer 47 is a multi-layer such as HIL (Hole Injection Layer)/HTL (Hole Transport Layer)/EL/ETL (Electron Transport Layer)/EIL (Electron Injection Layer). Here, "/" means that the front and rear layers are laminated. The second electrode 19 is located on the organic light emitting layer 47 and the second insulating layer 46.

The second stacked body 62 includes a first substrate 11, a gate 32 (also referred to as a gate portion 32 and a gate electrode 32 ), a third insulating layer 42, a semiconductor portion 31, a source drain 33 (including a source drain portion 33 and a source drain electrode 33). ), the etching stop portion 34, the flattening layer 45, the metal plate layer 35, and the first insulating layer 43. The first substrate 11 is, for example, a rectangular glass substrate. The first substrate 11 may be a flexible substrate, for example.

The gate 32 is located on the first substrate 11. The gate 32 partially covers the first substrate 11. The gate 32 has a predetermined shape described later. The material of the gate 32 is a pure metal such as molybdenum or aluminum. The material of the gate 32 may be, for example, molybdenum/aluminum, titanium/aluminum/titanium, ITO, or an alloy containing these. Here, “/” means both a laminated body of front and rear metals and an alloy of front and rear metals. Further, the gate 32 may be a laminated body of pure metal and alloy. The materials listed here are examples, and the material of the gate 32 is not limited to the materials listed here.

The third insulating layer 42 covers the gate 32 and the entire surface of the first substrate 11 not covered by the gate 32. The third insulating layer 42 is a layer made of an insulator such as silicon oxide.

The semiconductor portion 31 is located on the third insulating layer 42. The semiconductor portion 31 partially covers the third insulating layer 42. The semiconductor portion 31 has a predetermined shape described later. The semiconductor portion 31 is a layer made of a semiconductor such as an oxide semiconductor. The oxide semiconductor is, for example, InGaZnO.

The etching stop portion 34 is located on the semiconductor portion 31. Although not shown in the cross section shown in FIG. 4, the etching stop portion 34 is also located on the third insulating layer 42 around the semiconductor portion 31. The etching stop portion 34 partially covers the semiconductor portion 31 and the third insulating layer 42. The etching stop portion 34 has a predetermined shape described later. The etching stop portion 34 is, for example, a layer made of silicon oxide.

The source/drain 33 is located on the etching stop portion 34, the semiconductor portion 31 not covered by the etching stop portion 34, and the third insulating layer 42 not covered by the semiconductor portion 31 or the etching stop portion 34. The source/drain 33 partially covers the etching stop part 34, the semiconductor part 31, and the third insulating layer 42. The source/drain 33 has a predetermined shape described later.

The source/drain 33 of the second transistor 372 and the gate 32 of the first transistor 371 are connected via the first conductive portion 65.

The source/drain 33 is made of a conductor. The material of the source/drain 33 is a pure metal such as molybdenum or aluminum. The material of the source/drain 33 may be, for example, molybdenum/aluminum, titanium/aluminum/titanium, ITO, or an alloy containing these. Further, the source/drain 33 may be a laminated body of pure metal and alloy. The materials listed here are examples, and the materials of the source/drain 33 are not limited to the materials listed here.

The material of the source/drain 33 may be different from the material of the gate 32. The material of the source/drain 33 may be the same as the material of the gate 32.

The planarization layer 45 covers the entire surfaces of the source/drain 33, the etching stop portion 34 not covered by the source/drain 33, and the third insulating layer 42 not covered by the etching stop portion 34 or the source/drain 33. An inorganic insulating layer (not shown) is interposed between the flattening layer 45 and the source/drain 33, the etching stop portion 34, and the third insulating layer 42.

The flattening layer 45 is a layer made of an organic material. The material of the flattening layer 45 is, for example, a photosensitive acrylic resin. The material of the inorganic insulating layer is, for example, SiNx, SiOx or SiNx/SiOx.

The metal plate layer 35 is located on the flattening layer 45. The metal plate layer 35 includes a first metal plate 351 and a second metal plate 352. That is, the metal plate layer 35 is not a layer that covers the entire surface of the flattening layer 45, but a layer that partially covers the flattening layer 45. Therefore, the flattening layer 45 has both a portion on which the metal plate layer 35 is located and a portion on which the metal plate layer 35 is not located. The shape of the metal plate layer 35 will be described later.

The first metal plate 351 is connected to the source/drain 33 of the second transistor 372 via the second conductive portion 66. Therefore, the first metal plate 351 is connected to the gate 32 of the first transistor 371 via the second conductive portion 66, the source/drain 33 of the second transistor 372, and the first conductive portion 65. That is, the first metal plate 351 and the gate 32 of the first transistor 371 are connected.

The thickness of the metal plate layer 35 is, for example, about 100 nanometers to 300 nanometers. The total area of the metal plate layer 35 is slightly smaller than the total area of the first electrode 18. The area of the second metal plate 352 is preferably larger than the area of the first metal plate 351. The reason for this will be described later.

The metal plate layer 35 is a plate made of pure metal such as molybdenum or aluminum. The metal plate layer 35 may be, for example, a plate made of molybdenum/aluminum, titanium/aluminum/titanium, ITO, or an alloy containing these. Further, the metal plate layer 35 may be a plate of a laminated body of pure metal and alloy. The materials listed here are examples, and the material of the metal plate layer 35 is not limited to the materials listed here.

As described above, the first metal plate 351 and the second metal plate 352 of the display device 10 are arranged in the same layer. In other words, the first metal plate 351 and the second metal plate 352 are arranged on the same surface (for example, the surface of the flattening layer 45).

The first insulating layer 43 covers the entire surface of the metal plate layer 35 and the flattening layer 45 not covered with the metal plate layer 35. The thickness of the first insulating layer 43 is, for example, about 100 nanometers to 300 nanometers. The first insulating layer 43 on the upper side of the first metal plate 351 and the first insulating layer 43 on the upper side of the second metal plate 352 have the same thickness. The first insulating layer 43 is a layer made of silicon nitride, for example.

The first electrode 18 is located on the first insulating layer 43. The first electrode 18 partially covers the first insulating layer 43. The first electrode 18 has a predetermined shape described later. The distance between the first electrode 18 and the first metal plate 351 is equal to the thickness of the first insulating layer 43 between the first electrode 18 and the first metal plate 351. The distance between the first electrode 18 and the second metal plate 352 is equal to the thickness of the first insulating layer 43 between the first electrode 18 and the second metal plate 352. Therefore, the distance between the first electrode 18 and the first metal plate 351 is equal to the distance between the first electrode 18 and the second metal plate 352.

As described above, the organic light emitting layer 47 is located above the first electrode 18. The first metal plate 351 and the second metal plate 352 face (also referred to as facing) the organic light emitting layer 47 with the first insulating layer 43 and the first electrode 18 interposed therebetween.

As described above, the first insulating layer 43 is arranged between the first metal plate 351 and the second metal plate 352 and the first electrode 18. That is, the display device 10 has the same first insulating layer 43 between the first metal plate 351 and the first electrode 18 and between the second metal plate 352 and the first electrode 18. Further, the distance between the first metal plate 351 and the first electrode 18 is equal to the distance between the second metal plate 352 and the first electrode 18.

The first metal plate 351 and the second metal plate 352 are arranged in the first stacked body 61 so as to face (also referred to as) the organic light emitting layer 47 with the first electrode 18 interposed therebetween. The second insulating layer 46 is arranged in a layer different from the layer in which the first metal plate 351 and the second metal plate 352 are arranged. Although not shown in FIG. 4, the second metal plate 352 is connected to the wiring of the first voltage (for example, the fixed potential line VFIX) as described in FIG. Further, the first metal plate 351 and the second metal plate 352 are in an electrically non-contact state (in other words, insulated).

The first electrode 18 and the source/drain 33 are connected via the third conductive portion 67. The third conductive portion 67 has a structure in which a conductor connecting the first electrode 18 and the first metal plate 351 is connected on the second conductive portion 66 connecting the first metal plate 351 and the source/drain 33. .. The source/drain 33 connected to the third conductive portion 67 functions as the source electrode of the present embodiment.

The semiconductor part 31, the gate 32, and the source/drain 33 form a transistor 37. Note that the transistor 37 in FIG. 4 is a schematic diagram for the purpose of explaining the outline of the structure of the display device 10. The transistor 37 includes a first transistor 371 and a second transistor 372. The above-mentioned source electrode and gate electrode are, for example, the source electrode and gate electrode of the drive transistor 98.

As described above, the first transistor 371 that controls the current supplied to the organic light emitting device 97 is arranged in the second stacked body 62. The first metal plate 351 is connected to the gate electrode of the first transistor 371 via the second conductive portion 66, the source/drain 33 of the second transistor 372, and the first conductive portion 65. The second stacked body 62 has a source electrode (also referred to as a first transistor electrode) of the first transistor 371 connected to the first electrode 18 via the third conductive portion 67.

FIG. 5 is a schematic plan view of the pixel 90. The pixels 90 are arranged in a matrix on the image display unit 15. In the display device 10 for color display, for example, the emission brightness of the organic light emitting elements 97 of three colors of red, green, and blue is combined to express the color of one pixel in the image signal. Therefore, a portion including the organic light emitting element 97 of one color is referred to as a sub pixel 99, and a group of three sub pixels 99 is referred to as a pixel 90.

The sub-pixels 99 of each color are the same except for the emission color. The sub-pixel 99 has a rectangular shape. The sub-pixel 99 includes a light emitting portion 17 having a square shape (also referred to as a square shape).

6 to 9 described below show the same range as FIG. FIG. 6 is a schematic plan view of the second insulating layer 46. The second insulating layer 46 has a planar shape. The opening 461 provided in the second insulating layer 46 is rectangular. The non-opening portion 462 of each sub-pixel 99 is connected.

FIG. 7 is a schematic plan view of the pixel 90 from which the second insulating layer 46 has been removed. FIG. 7 shows the first electrode 18 and the metal plate layer 35.

FIG. 8 is a schematic plan view of the first electrode 18. The first electrode 18 is L-shaped. One sub-pixel 99 has one first electrode 18. The first electrode 18 is larger than the opening 461. That is, the first electrode 18 is located below the opening 461.

FIG. 9 is a schematic plan view of the metal plate layer 35. The metal plate layer 35 includes a rectangular first metal plate 351 and a second metal plate 352 that is not connected to the first metal plate 351. One sub pixel 99 has one first metal plate 351. The second metal plate 352 of each sub-pixel 99 is connected.

The description of the structure of the display device 10 will be continued with reference to FIGS. 4 to 9.

The light emitting unit 17 will be described. The first transistor 371 controls the current supplied to the organic light emitting device 97. The current flows from the first electrode 18 toward the second electrode 19. That is, holes enter the organic light emitting layer 47 from the first electrode 18 side and electrons enter from the second electrode 19 side.

Inside the organic light emitting layer 47, excitons (excitons) generated by recombination of holes and electrons generate light when returning to the ground state. That is, the organic light emitting layer 47 emits light by the current flowing between the first electrode 18 and the second electrode 19.

The second insulating layer 46 will be described. The second insulating layer 46 has two roles of preventing color mixing of the organic light emitting layer 47 and of eliminating unnecessary light emitting regions. The role of preventing color mixing will be described. The organic light emitting layer 47 of one color is located in one opening 461 of the second insulating layer 46. The range in which the organic light emitting layer 47 is formed may shift due to an error or the like in the manufacturing apparatus. However, the shift remains within the range covered by the non-opening portion 462, and the organic light emitting layer 47 reaches the other adjacent opening portions 461. There is no cover. As described above, since the non-opening portion 462 is located at the boundary of each color, the second insulating layer 46 plays a role of preventing color mixture.

The role of eliminating unnecessary light emitting areas will be described. In the portion where the second insulating layer 46 is interposed between the first electrode 18 and the organic light emitting layer 47, the current does not flow because the first electrode 18 and the organic light emitting layer 47 are insulated by the second insulating layer 46. Therefore, the organic light emitting layer 47 does not emit light. Therefore, the light emitting portion 17 of the organic light emitting layer 47 that actually emits light is a portion of the organic light emitting layer 47 corresponding to the opening 461. In this way, by blocking the light emission of the organic light emitting layer 47 in the non-opening portion 462, the second insulating layer 46 plays a role of eliminating an unnecessary light emitting area.

As described above, the display device 10 has the planar second insulating layer 46 including the opening 461 for emitting the light emitted from the organic light emitting element 97 to the outside and the non-opening 462 that is not opened.

The formation of capacitance by the metal plate layer 35 and the first electrode 18 will be described. The first metal plate 351 faces (is opposed to) the first electrode 18 via the first insulating layer 43. The first metal plate 351, the first insulating layer 43, and the first electrode 18 form a first capacitor 91 (see FIG. 3). The capacitance of the first capacitor 91 is determined by the area where the first metal plate 351 and the first electrode 18 face each other, the thickness of the first insulating layer 43, and the dielectric constant.

Similarly, the second metal plate 352, the first insulating layer 43, and the first electrode 18 form the second capacitor 92 (see FIG. 3 ). The capacity of the second capacitor 92 is determined by the area where the second metal plate 352 and the first electrode 18 face each other, the thickness of the first insulating layer 43, and the dielectric constant. The first capacitor 91 and the second capacitor 92 are connected in series via the first electrode 18. As described above, the first electrode 18 is connected to the source/drain 33 via the third conductive portion 67. The third conductive portion 67 is located below the non-opening portion 462.

As described above, the first electrode 91, the first insulating layer 43, and the first metal plate 351 form the first capacitor 91. A second capacitor 92 is formed by the first electrode 18, the first insulating layer 43, and the second metal plate 352. The first capacitor 91 and the second capacitor 92 are connected in series. The connection point between the first capacitor 91 and the second capacitor 92 is connected to the source electrode. The first electrode 18 is connected to the source electrode at the portion covered by the non-opening portion 462.

Ｉｏｌｅｄ（ＩＭＤ）は、有機発光素子９７のアノード電極とカソード電極との間に流れる駆動電流である。
βは、利得係数である。
Ｃ１は、第１容量９１の容量である。
Ｃ２は、第２容量９２の容量である。
Ｖｄａｔａは、有機発光素子９７を発光させる際の発光輝度を示すデータ電圧である。
Ｖｒｅｆは、参照電圧である。
μは、キャリア移動度である。
Ｃｏｘは、単位容量である。
Ｗは、駆動トランジスタ９８のチャンネル幅である。
Ｌは、駆動トランジスタ９８のチャンネル長である。 The operation of the first capacitor 91 and the second capacitor 92 will be described. When the organic light emitting element 97 emits light, the drive current Ioled (see FIG. 3) flows between the anode electrode and the cathode electrode of the organic light emitting element 97. The drive current Ioled is the same as the output current IMD flowing between the source electrode of the drive transistor 98 and the drain electrode of the drive transistor 98. The output current IMD will be described later. The drive current Ioled can be obtained by using the equation (1). A method of deriving the equation (1) will be described in the second embodiment.

Ioled (IMD) is a drive current flowing between the anode electrode and the cathode electrode of the organic light emitting device 97.
β is a gain coefficient.
C1 is the capacity of the first capacity 91.
C2 is the capacity of the second capacity 92.
Vdata is a data voltage indicating the light emission luminance when the organic light emitting element 97 emits light.
Vref is a reference voltage.
μ is the carrier mobility.
Cox is a unit capacity.
W is the channel width of the drive transistor 98.
L is the channel length of the drive transistor 98.

From the equation (1), the current Ioled flowing through the organic light emitting element 97 is not affected by the characteristics (for example, threshold voltage) of the drive transistor 98. Then, from the formula (1), it is understood that the variation in the drive current Ioled can be suppressed by reducing the variation in the capacitance C1 of the first capacitance 91 and the capacitance C2 of the second capacitance 92. By suppressing the variation of the drive current Ioled, it is possible to suppress the uneven brightness of the display device 10.

The variation in the thickness and the dielectric constant of the first insulating layer 43 in each sub-pixel 99 can be reduced by forming the first insulating layer 43 by using, for example, CVD (Chemical Vapor Deposition). Further, the variation in the area of the first metal plate 351 and the variation in the area of the second metal plate 352 in each sub-pixel 99 are created by simultaneously forming the first metal plate 351 and the second metal plate 352 by the photolithography method. Therefore, it can be reduced. The details of the method of manufacturing the display device 10 according to the present embodiment will be described later.

By reducing the variation in the area and the variation in the area ratio between the first metal plate 351 and the second metal plate 352 in each sub-pixel 99, the capacitance C1 and the second capacitance 91 of the first capacitance 91 of each sub-pixel 99 can be reduced. The variation of the capacitance C2 of 92 can be reduced. The reason will be described below.

FIG. 10 is an explanatory diagram showing a method of forming the insulating film 74. The insulating film 74 is used as the first insulating layer 43, for example. The mounting table 71 is a table on which the substrate 72 is mounted. The substrate fixing portion 73 fixes the substrate 72 to the mounting table 71. The substrate 72 is also called a mother substrate 72, and the substrate fixing portion 73 is also called a substrate retainer 73.

Hereinafter, for example, a case where the insulating film 74 having a uniform thickness is formed on the plate-shaped substrate 72 will be described as an example.

The manufacturing apparatus supplies a gas raw material to deposit the insulating film 74 on one surface of the substrate 72. The symbol C in FIG. 10 indicates the center of the insulating film 74. Further, reference signs E1 and E2 in FIG. 10 indicate the ends of the range in which the insulating film 74 is formed. The substrate 72 is a flat plate having a size that can be divided into a plurality of first substrates 11 by cutting. The insulating film 74 outside the first end E1 and the second end E2 is not used. In the following description, the insulating film 74 having a size corresponding to one first substrate 11 is referred to as a unit insulating film 75. The one first substrate 11 is, for example, one display panel mounted on one display device 10 (see FIG. 1 ). The unit insulating film on the second end E2 side is referred to as a unit insulating film 76.

FIG. 11 is a graph illustrating unevenness in the thickness of the insulating film 74. Note that the graph diagram of FIG. 11 is an example. The horizontal axis of FIG. 11 represents the distance from the center C of the insulating film 74. The vertical axis in FIG. 11 indicates the thickness of the insulating film 74. A thin solid line indicates the ideal thickness of the insulating film 74. The thick curve shows the thickness of the insulating film 74 that is actually completed.

As shown by the thin solid line in FIG. 11, it is ideal that the insulating film 74 has the same thickness from the center C to the first end E1 and the second end E2. However, in reality, the insulating film 74 becomes thinner from the center C toward the first end E1 and the second end E2.

The graph shown in FIG. 11 is a conceptual diagram for explaining the thickness unevenness of the insulating film 74. The shape of the graph shown in FIG. 11 differs depending on the model and settings of the manufacturing apparatus. In general, the film thickness of the insulating film 74 may deviate from the ideal film thickness as the distance from the center C of the substrate 72 increases. That is, the film thickness of the insulating film 74 may be slightly different from the ideal film thickness.

FIG. 12 is a plan view of the unit insulating film 75. FIG. 13 is a sectional view of the unit insulating film 75. 12 and 13, the left side of the drawing shows the direction of the center C, and the right side of the drawing shows the direction of the second end E2.

The unit insulating film 75 in the first region 751 has a film thickness of d1. In addition, the film thickness of the unit insulating film 75 in the second region 752 is d2. The case where the film thickness d1 is the ideal film thickness of the unit insulating film 75 will be described as an example. For the sake of explanation, the first region 751 and the second region 752 are largely illustrated in FIG. The areas of the first region 751 and the second region 752 are the pixel areas of a large number of sub-pixels 99 (for example, 100 vertical pixels and 100 horizontal pixels). Then, it is assumed that the film thickness of the unit insulating film 75 is constant inside the first region 751 and inside the second region 752.

Ｃ１は、第１容量９１の容量である。
Ｃ２は、第２容量９２の容量である。
Ａ１は、第１金属板３５１の面積である。
Ａ２は、第２金属板３５２の面積である。
εは、単位絶縁膜７５の比誘電率である。
ｄ１は、第１領域７５１内の単位絶縁膜７５の膜厚である。 The case where the unit insulating film 75 is used for the first insulating layer 43 (see FIG. 4) will be described as an example. In the calculation formula (see Formula (1)) of the drive current of one sub-pixel 99 in the first region 751, C2/(C2+C1) of this calculation formula can be expressed by Formula (3).

C1 is the capacity of the first capacity 91.
C2 is the capacity of the second capacity 92.
A1 is the area of the first metal plate 351.
A2 is the area of the second metal plate 352.
ε is the relative dielectric constant of the unit insulating film 75.
d1 is the film thickness of the unit insulating film 75 in the first region 751.

As is clear from the formula (3), the film thickness d1 of the unit insulating film 75 in the first region 751 is canceled, and C2/(C2+C1) has the same value as A2/(A2+A1).

ｄ２は、第２領域７５２内の単位絶縁膜７５の膜厚である。 On the other hand, in the calculation formula (see Formula (1)) of the drive current of one sub-pixel 99 in the second region 752, C2/(C2+C1) of this calculation formula can be expressed by Formula (4).

d2 is the film thickness of the unit insulating film 75 in the second region 752.

As is clear from the equation (4), the film thickness d2 of the unit insulating film 75 in the second region 752 is canceled, and C2/(C2+C1) is the same value as A2/(A2+A1).

As described above, in the second region 752, the film thickness d2 of the unit insulating film 75 is different from the ideal film thickness d1. However, the same relational expression as that of the first region 751 holds between the capacitance C1, the capacitance C2, the area A1, and the area A2.

Therefore, by reducing the variation in the area A1 of the first metal plate 351 and the area A2 of the second metal plate 352 and the variation in the ratio of the areas, it is possible to reduce the variation in C2/(C2+C1) of each sub-pixel 99. it can.

In other words, according to the present embodiment, the equations (3) and (4) are the same, and it is possible to cancel the variation in the film thickness. Then, if the area A1 of the first metal plate 351 and the area A2 of the second metal plate 352 are accurately defined so that the data voltage Vdata and the reference voltage Vref are the same, the driving in each sub-pixel 99 of the first region 751 is performed. The current and the drive current in each sub-pixel 99 in the second region 752 are substantially the same. As a result, it is possible to suppress variations in light emission brightness. For example, when the emission brightness of each sub-pixel 99 in the first area 751 and the emission brightness of each sub-pixel 99 in the second area 752 are controlled to be the same, variation in the emission brightness can be further suppressed, so that uneven brightness occurs. It gets harder.

A comparative example will be described. In the comparative example, the capacitance corresponding to the first capacitance 91 of FIG. 3 is referred to as a first capacitance X, and the capacitance corresponding to the second capacitance 92 of FIG. 3 is referred to as a second capacitance Y. In the comparative example, it is assumed that the insulating layer having the first capacitance X and the insulating layer having the second capacitance Y are formed in different layers in different steps. In the comparative example, for example, the insulating layer of the first capacitor X is formed in a layer including a TFT such as a driving TFT, and the insulating layer of the second capacitor Y is formed in the OLED layer.
An example will be described in which the insulating layer of the first capacitor X and the insulating layer of the second capacitor Y are made of the same material and have the same dielectric constant ε.

The insulating layer of the first capacitor X has an ideal film thickness d1 in the first region 751 and a film thickness d2 different from d1 in the second region 752, as in FIG. The case where the insulating layer of the second capacitor Y has an ideal film thickness d1 in the first region 751 but has a film thickness d2' different from d1 in the second region 752 will be described as an example. It is assumed that d2 and d2' are different.

In the sub-pixel in the first region 751 of the comparative example, since the thicknesses of the insulating films forming the two capacitors are both d1, the relationship of Expression (3) is established. On the other hand, the capacitance C1 of the first capacitance X and the capacitance C2 of the second capacitance X of the sub-pixel in the second region 752 of the comparative example can be expressed by Expression (5).

As described above, in the comparative example in which the insulating layer of the first capacitance X and the insulating layer of the second capacitance Y are formed in different steps, the value of C2/(C2+C1) of each subpixel is set in each subpixel 99. In order to control only the area A1 of the first metal plate 351 and the area A2 of the second metal plate 352, d2 and d2′ should be the same, that is, the insulating layer of the first capacitance X and the second capacitance Y of The difficulty of manufacturing the insulating layer with the same film thickness distribution must be overcome.

In other words, when the formula (3) and the formula (5) are not the same, even if the data voltage Vdata and the reference voltage Vref are the same, the driving current in each sub-pixel of the first region 751 of the comparative example and the comparative example. The drive current in each sub-pixel of the second region 752 is different. As a result, even if it is attempted to control the emission brightness of each sub-pixel in the first area 751 of the comparative example and the emission brightness of each sub-pixel in the second area 752 of the comparative example to be the same, the emission brightness may vary.

In the above description, the unit insulating film 75 has been described, but the same description applies to other unit insulating films (for example, the unit insulating film 76).

In summary, in this embodiment, if the variation in the area and the variation in the area ratio between the first metal plate 351 and the second metal plate 352 in each sub-pixel 99 are reduced, the first capacitance of each sub-pixel 99 is reduced. It is possible to reduce variations in the capacitance C1 of 91 and the capacitance C2 of the second capacitance 92. In other words, in the present embodiment, even if a variation in the film thickness of the insulating layer occurs, this variation in the film thickness can be canceled. On the other hand, the comparative example does not obtain the same effect.

As described above, according to the configuration of the present embodiment, it is possible to reduce the variation of C2/(C2+C1) among the sub-pixels 99. Therefore, according to the configuration of the present embodiment, it is possible to provide the display device 10 with reduced luminance unevenness.

The technical significance of this embodiment will be described.

In order to suppress the brightness unevenness of the display device 10, it is necessary to accurately control the drive current Ioled of the organic light emitting element 97. As described above, the drive transistor 98 controls the drive current Ioled. However, the characteristics of the drive transistor 98 are likely to vary. Therefore, even when a plurality of sub-pixels 99 are illuminated with the same luminance, the drive current Ioled varies among the sub-pixels 99. This variation causes uneven brightness.

Patent Document 1 proposes a pixel circuit including a plurality of capacitors in order to prevent uneven brightness due to the characteristics of the drive transistor 98, in particular, variations in threshold voltage. In this pixel circuit, when there is a variation in the capacitance value, the variation is rather the cause of uneven brightness.

When forming two capacitors in different layers, it is necessary to manufacture a plurality of capacitors by different manufacturing processes.

The accuracy of the capacitance when the two capacitances are formed in different layers will be described in more detail. A capacitor is a circuit component including three components, two conductor plates facing each other and an insulator arranged between them. The characteristics of the capacitance are determined by the area of the portion where the two conductor plates face each other, the thickness of the insulator, and the dielectric constant of the insulator.

The description will be continued with reference to FIG. First, one capacitance formed in the layer in which the TFT circuit is formed will be described. For example, it can be used for two conductor plates facing the gate 32 and the semiconductor portion 31. In this case, the third insulating layer 42 acts as an insulator. The capacitor formed by the anode electrode and the intermediate metal for forming the capacitor can be formed by the first metal plate 351, the first insulating layer 43, and the first electrode 18 as in the present embodiment.

For example, the insulator having the first capacitance is the insulating layer X, and the insulator having the second capacitance is the insulating layer Y. For example, due to variations in the manufacturing process, a phenomenon may occur in which the insulating layer X is thickly finished and the insulating layer Y is thinly finished. When such a phenomenon occurs, the first capacity becomes a smaller capacity and the second capacity becomes a larger capacity. Since the changes of the two capacitors act in opposite directions, the fluctuation of the drive current Ioled becomes large. As a result, the uneven brightness becomes large. In order to prevent such a phenomenon, it is necessary to make the accuracy of each manufacturing process high.

Further, as described using the comparative example, the formula (3) and the formula (5) are not equal. Therefore, when the film thickness d1 of the insulating film (insulator) in the first region 751 and the film thickness d2 of the insulating film in the second region 752 in the display panel are different, C2/(C2+C1) of each sub-pixel 99 It is difficult to reduce variations.

Therefore, when the two capacitors are formed in different layers, it is difficult to suppress variations in these capacitors, and uneven brightness still occurs.

On the other hand, in the display device 10 of the present disclosure, as described using the formula (1), the formula (3), and the formula (4), the film thickness d1 of the insulating film (insulator) 74 in the first region 751 and the film thickness d1 Even if the film thickness d2 of the insulating film 74 in the second region 752 is different, it is possible to reduce variations in the drive current Ioled flowing through the organic light emitting element 97 of each sub-pixel 99. As a result, it is possible to reduce uneven brightness of the display device 10.

Further, in the display device 10, the insulating layer forming the capacitance is not arranged in the second stacked body 62 in which the TFT circuit is formed. Therefore, since the first insulating layer 43 can be used exclusively for the capacitor insulator, it is not necessary to consider the withstand voltage performance of the TFT. That is, as the first insulating layer 43, a layer having an optimum thickness and material for obtaining a desired capacitance can be used.

Therefore, the first insulating layer 43 can be made thinner than the third insulating layer 42 of the TFT circuit. For example, the relationship between the capacitances of the first capacitance 91 and the second capacitance 92 and the parasitic capacitance of the TFT circuit can be expressed by equation (6).
C1, C2 >> Parasitic capacitance (6)
C1 is the capacity of the first capacity 91.
C2 is the capacity of the second capacity 92.
The parasitic capacitance is, for example, the capacitance between the gate source and gate drain terminals of the drive transistor 98 or the switch transistor 96.

By setting the capacitance C1 of the first capacitance 91 and the capacitance C2 of the second capacitance 92 so as to satisfy the equation (6), it is possible to suppress the uneven brightness caused by the influence of the parasitic capacitance.

In addition, according to the display device 10 of the present disclosure, various effects described below can be further obtained.

If the first metal plate 351 is too small, that is, if the capacitance C1 is too small, the influence of the parasitic capacitance of the TFT circuit becomes remarkable. Further, during the light emitting period of the organic light emitting element 97, the leakage current may reduce the GS (Gate-Source) voltage of the drive transistor 98. When the GS voltage of the drive transistor 98 decreases, the drive current Ioled decreases and the brightness of the organic light emitting element 97 decreases. Therefore, the first metal plate 351 needs to have an area larger than a certain level.

That is, by securing the necessary capacitance C1, it is possible to prevent the decrease in the GS voltage of the drive transistor 98 and the decrease in the brightness of the organic light emitting element 97.

Furthermore, it is desirable that the second metal plate 352 be as large as possible after ensuring the above area in the first metal plate 351. That is, it is desirable to secure the necessary capacity C1 and make C2 as large as possible. By doing so, the voltage applied to the drive transistor 98 when data is input from the input line Vinput can be lowered. Therefore, the loss of the data voltage input from the input line Vinput can be suppressed.

Further, by using the first electrode 18 of the organic light emitting element 97 for the terminals of the first capacitor 91 and the second capacitor 92, a dedicated wiring for connecting the first capacitor 91 and the second capacitor 92 in series is unnecessary. can do.

Furthermore, since the second stacked body 62 in which the TFT circuit is formed has no capacitor, the area of the TFT circuit can be reduced. Therefore, the subpixel 99 can be downsized and the high-definition display device 10 can be provided.

FIG. 14 is a flowchart showing the flow of manufacturing the display panel. 15 to 33 are explanatory views showing the manufacturing process of the display panel. An outline of a method of manufacturing the display panel used in the display device 10 of the present embodiment will be described with reference to FIGS. 14 to 33. Manufacturing of vapor deposition equipment, sputtering equipment, coating equipment such as slit coaters, exposure equipment, developing equipment, etching equipment, sealing equipment, cutting equipment used for manufacturing display panels, and transport equipment connecting these equipments, etc. The device is not shown. These devices operate according to a predetermined program.

In addition, in the following description, one sub-pixel 99 will be described as an example for the schematic cross-sectional view. The manufacturing apparatus of the display device 10 forms the pixel circuit and the drive circuit 20 using a semiconductor process on the front side of the first substrate 11 which is a translucent substrate such as a glass substrate (step S501).

The outline of the process of step S501 will be described. First, it demonstrates using FIG. FIG. 15 is a schematic cross-sectional view of the display device 10 during the manufacturing process. The manufacturing apparatus forms the gate 32 having a predetermined shape on one surface of the first substrate 11 by a sputtering method, a photolithography method, or the like.

As shown in the cross-sectional view of FIG. 16, the manufacturing apparatus forms the third insulating layer 42 having a uniform thickness by the CVD method or the like.

As shown in the cross-sectional view of FIG. 17, the manufacturing apparatus forms the semiconductor portion 31 having a predetermined shape by a sputtering method, a photolithography method, or the like.

As shown in the cross-sectional view of FIG. 18, the manufacturing apparatus forms the etching stop portion 34 having a predetermined shape by the CVD method, the photolithography method, or the like.

As shown in the cross-sectional view of FIG. 19, the manufacturing apparatus forms a first hole 651 reaching the gate 32 from the surface of the third insulating layer 42 by a dry etching method or the like.

As shown in the cross-sectional view of FIG. 20, the manufacturing apparatus forms the source/drain 33 having a predetermined shape by a sputtering method, a photolithography method, or the like. As described above, the material of the source/drain 33 is a conductor. The conductor that is the material of the source/drain 33 also covers the inner surface of the first hole 651 to form the first conductive portion 65 that connects the source/drain 33 and the gate 32.

FIG. 21 is a schematic plan view of the display device 10 at the stage shown in FIG. 21 shows the same part as FIG. Note that FIG. 21 also shows the second conductive portion 66 and the third conductive portion 67 that will be created in the subsequent steps.

The gate 32, the semiconductor section 31, the etching stop section 34, and the source/drain 33 are formed by the steps described with reference to FIGS. The gate 32 has an L-shaped portion and a rectangular portion. The rectangular portion is continuous with a strip portion extending in the left-right direction. The semiconductor part 31 is a rectangle that is long in the left-right direction. The semiconductor portion 31 overlaps the gate 32. The etching stop portion 34 is also rectangular. The etching stop portion 34 covers the central portion of the semiconductor portion 31 in the left-right direction. The source/drain 33 has a shape in which rectangular portions that cover both ends of the semiconductor portion 31 in the left-right direction are connected by belt-shaped portions.

As shown in the sectional view of FIG. 22, the manufacturing apparatus forms an inorganic insulating layer (not shown) having a uniform thickness by the CVD method or the like. The coating device creates the flattening layer 45 by a slit coating method or the like (step S503).

As shown in the cross-sectional view of FIG. 23, the manufacturing apparatus creates a second hole 661 that penetrates from the surface of the planarization layer 45 to the source/drain 33 by a dry etching method or the like.

As shown in the cross-sectional view of FIG. 24, the manufacturing apparatus forms the metal plate layer 35 having a predetermined shape by a sputtering method, a photolithography method, or the like (step S504). FIG. 25 is a schematic plan view of the display device 10 at the stage shown in FIG. FIG. 25 shows the same part as FIG. The metal plate layer 35 includes a first metal plate 351 and a second metal plate 352. As described above, the metal plate layer 35 is a conductor.

The inside of the second hole 661 of FIG. 23 is filled with the same conductor as the metal plate layer 35 to form a second conductive portion 66 connecting the metal plate layer 35 and the source/drain 33. In addition, in the present embodiment, the manufacturing apparatus employs manufacturing conditions in which the upper surface of the second conductive portion 66 is a flat surface.

As shown in the cross-sectional view of FIG. 26, the manufacturing apparatus forms the first insulating layer 43 by the CVD method or the like (step S505). In the present embodiment, the manufacturing apparatus employs manufacturing conditions such that the upper surface of the first insulating layer 43 including the portion between the first metal plate 351 and the second metal plate 352 is flat.

As shown in the cross-sectional view of FIG. 27, the manufacturing apparatus creates a third hole 671 penetrating from the surface of the first insulating layer 43 to above the second conductive portion 66 on the right side by a dry etching method or the like.

As shown in the sectional view of FIG. 28, the manufacturing apparatus forms the first electrode 18 having a predetermined shape by a sputtering method, a photolithography method, or the like (step S506). FIG. 29 is a schematic plan view of the display device 10 at the stage shown in FIG. 28. FIG. 29 shows the same part as FIG. The material of the first electrode 18 is a conductor.

The inside of the third hole 671 in FIG. 27 is filled with a conductor. The conductor filling the inside of the third hole 671 is connected to the second conductive portion 66 on the lower side to form the third conductive portion 67 that connects the first electrode 18 and the source/drain 33. In the present embodiment, the manufacturing apparatus employs manufacturing conditions such that the upper surface of the third conductive portion 67 is a flat surface.

The description will be continued using the flowcharts shown in FIGS. 30, 31, and 14. FIG. 30 is a schematic view of the display device 10 during the manufacturing process.

As shown in the cross-sectional view of FIG. 30, the manufacturing apparatus forms the second insulating layer 46 having a predetermined shape by the CVD method, the dry etching method, or the like (step S507). 31 is a schematic plan view of the display device 10 at the stage shown in FIG. FIG. 31 shows the same part as FIG. As described above, the second insulating layer 46 includes the opening 461 and the non-opening 462. The opening 461 covers the central portion of the first electrode 18. The non-opening portion 462 covers the boundary portion between the sub-pixels 99 and the edge of the first electrode 18.

As shown in the cross-sectional view of FIG. 32, the manufacturing apparatus forms the organic light emitting layer 47 by a vapor deposition method or a coating method (step S508). The organic light emitting layer 47 covers the opening 461.

As shown in the cross-sectional view of FIG. 33, the manufacturing apparatus forms the second electrode 19 by vapor deposition or sputtering (step S509).

As described above, the manufacturing apparatus arranges the transistor 37 having the source electrode, the drain electrode, and the gate electrode on the one surface of the first substrate 11. In the manufacturing apparatus, the third insulating layer 42 that covers the transistor 37 is arranged above the transistor 37. The manufacturing apparatus sets the first metal plate 351 connected to the gate electrode through the first conductive portion 65 penetrating the third insulating layer 42 and the second metal plate 352 insulated from the first metal plate 351 to the third metal plate 351. It is arranged on the same layer above the insulating layer 42. The manufacturing apparatus arranges the first insulating layer 43 above the layers of the first metal plate 351 and the second metal plate 352. The manufacturing apparatus arranges the first electrode 18 connected to the source electrode via the second conductive portion 66 penetrating the first insulating layer 43 and the third insulating layer 42 above the first insulating layer 43. The manufacturing apparatus arranges the organic light emitting layer 47 on the upper side of the first electrode 18. The manufacturing apparatus arranges the second electrode 19 on the upper side of the organic light emitting layer 47.

FIG. 34 is a hardware configuration diagram of the display device 10. The display device 10 has an FPC 14, a driver IC 13, and a display substrate 16. The display substrate 16 has a drive circuit 20 and an image display unit 15. The drive circuit 20 includes, for example, a scan driver 21, a data voltage driver 22, an emission control driver 23, and a protection circuit 24.

The driver IC 13 processes the image signal acquired via the FPC 14 and outputs the image signal to the drive circuit 20 of the display substrate 16. The drive circuit 20 controls the image display unit 15.

The emission control driver 23 and the scan driver 21 control the brightness of the organic light emitting element 97 (see FIG. 3) of each sub-pixel 99. The image display unit 15 displays the image by this control.

A voltage corresponding to an image signal is input from the data voltage driver 22 to the input line Vinput. When the scan driver 21 selects a scan line, that is, when the switch transistor 96 is in a conductive state, a voltage corresponding to a voltage input from the input line Vinput is a gate electrode of the drive transistor 98 via the switch transistor 96. Join in.

An output current IMD flows between the source electrode and the drain electrode of the drive transistor 98 according to the voltage Vgs between the gate electrode and the source electrode of the drive transistor 98. A drive current Ioled equal to the output current IMD flows between the anode electrode and the cathode electrode of the organic light emitting device 97. The organic light emitting element 97 emits light with a brightness according to the drive current Ioled. That is, the organic light emitting element 97 emits light with the brightness according to the image signal.

Note that the pixel circuit illustrated in FIG. 3 is an example. The pixel circuit may have a configuration in which a larger number of TFTs and capacitors are combined. For example, the pixel circuit may include a second switch transistor between the anode electrode of the organic light emitting device 97 and the control signal line. Further, the pixel circuit may include a third switch transistor between the drive transistor 98 and the high power supply line ELVDD. The operation of the first capacitor 91 and the second capacitor 92 will be described using the second embodiment.

The shapes of the semiconductor portion 31, the gate 32, the source/drain 33, the first metal plate 351, the second metal plate 352, the first electrode 18, and the like described above are all examples, and schematic diagrams simplified for explanation. Is. Moreover, the manufacturing process and the manufacturing apparatus used in each process are also illustrated.

In the present embodiment, the structure, operation, and manufacturing method have been described by taking the display device 10 that uses a top emission type OLED panel that emits light on the surface on the second substrate 12 side, as an example. The display device 10 may use a panel of a bottom emission type OLED that emits light to the first substrate 11 side.

In this embodiment, the case where the transistor 37 is an oxide TFT bottom-gate TFT has been described as an example. The transistor 37 may be a TFT using amorphous silicon or polysilicon. Further, the transistor 37 may be a top gate type TFT.

In this embodiment, the case where the drive transistor 98 is an N-type transistor has been described as an example. In this case, the first electrode 18 is the anode electrode of the organic light emitting device 97. The second electrode 19 is a cathode electrode of the organic light emitting device 97. As described above, the drive transistor 98 is an N-type transistor, the first electrode 18 is an anode electrode, and the second electrode 19 is a cathode electrode.

[Second Embodiment]
The present embodiment relates to the display device 10 in which the fixed potential line VFIX (see FIG. 3) connected to the second capacitor 92 is shared with the low power supply line ELVSS. Descriptions of portions common to the first embodiment will be omitted.

FIG. 35 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element 97 of the second embodiment to emit light. The circuit shown in FIG. 35 is part of a pixel circuit included in the sub-pixel 99. Note that the switch transistor 96 (see FIG. 3) is omitted in FIG.

The circuit shown in FIG. 35 includes an organic light emitting element 97, a first capacitor 91, a second capacitor 92, and a driving transistor 98. A high power supply line ELVDD, a low power supply line ELVSS and an input line Vinput are connected to the circuit shown in FIG. The input line Vinput is connected to the data voltage driver 22. The voltage of the input line Vinput alternately changes between the reference voltage Vref and the data voltage Vdata, which is a voltage indicating the light emission luminance when the organic light emitting element 97 emits light.

The input line Vinput is connected to the gate electrode of the drive transistor 98 and the first terminal of the first capacitor 91. The high power supply line ELVDD is connected to the drain electrode of the drive transistor 98. The low power supply line ELVSS is connected to the cathode electrode of the organic light emitting element 97 and the first terminal of the second capacitor 92. The low power supply line ELVSS is an example of a wiring of the first voltage. The source electrode of the drive transistor 98 is connected to the second terminal of the first capacitor 91, the second terminal of the second capacitor 92, and the anode electrode of the organic light emitting element 97.

The organic light emitting element 97 emits light based on a signal input from the input line Vinput.

According to the present embodiment, the fixed potential line VFIX and the low power supply line ELVSS can be shared, so that the display device 10 in which the layout of the pixel circuit is easy can be provided.

In the present embodiment, the second capacitor 92 can be formed by the first electrode 18, the first insulating layer 43, and the second metal plate 352. In this case, the second metal plate 352 is connected to the low power supply line ELVSS. Therefore, the second metal plate 352 is connected to the cathode electrode of the organic light emitting device 97. The second electrode 19 is, for example, a cathode electrode of the organic light emitting device 97. As described above, the second metal plate 352 is connected to the second electrode 19.

FIG. 36 is a time chart showing the input voltage Vinput of the second embodiment. The horizontal axis of FIG. 36 is time. The vertical axis of FIG. 36 represents the voltage of the input voltage Vinput. During the threshold compensation period T1, the input voltage Vinput is the reference voltage Vref. In the data voltage writing period T2, the input voltage Vinput is the data voltage Vdata. The data voltage Vdata is a voltage indicating the emission brightness of the organic light emitting element 97.

The operation of the sub-pixel 99 and the method of deriving the formula (1) will be described with reference to FIGS. 35 and 36.

In the following description, the point where the gate electrode of the drive transistor 98, the first terminal of the first capacitor 91, and the input line Vinput are connected is referred to as point G. Further, a portion where the source electrode of the drive transistor 98, the first capacitor 91 and the second capacitor 92, and the anode electrode of the organic light emitting element 97 are connected is referred to as point S. Further, the potential at the S point is described as VS, and the potential at the G point is described as VG.

The threshold compensation period T1 will be described. During the threshold compensation period T1, the reference voltage Vref is input to Vinput. A current flows from the high power supply line ELVDD to the point S via the drive transistor 98. The electric potential and the electric charge at the point S converge in a state where the expressions (7) to (9) are satisfied.
VG=Vref (7)
VS=VG-Vth
=Vref-Vth (8)
Q1=(VS-VG)×C1+(VS-ELVSS)×C2
=-Vth x C1 + (Vref-Vth-ELVSS) x C2 (9)
VG is the potential at point G.
Vref is a reference voltage.
VS is the potential at the S point.
Vth is a threshold voltage of the drive transistor 98.
Q1 is the electric charge at the S point at the time of convergence.
C1 is the capacity of the first capacity 91.
C2 is the capacity of the second capacity 92.
ELVSS is the potential of the cathode electrode of the organic light emitting device 97.

The data voltage writing period T2 will be described. In the data voltage writing period, the data voltage Vdata is input to Vinput. That is, VG=Vdata. VS has a potential obtained by distributing (Vdata-ELVSS) by the first capacitor 91 and the second capacitor 92 connected in series.

The electric charge at the point S is in a state that satisfies the expression (10). It should be noted that the same symbols as those used in the above-mentioned formulas have the same meanings, and hence their explanations are omitted.
Q2=(VS-VG)*C1+(VS-ELVSS)*C2
=(VS-Vdata)*C1+(VS-ELVSS)*C2 (10)
Q2 is the electric charge at the point S during the data voltage writing period T2.
Vdata is a data voltage input from the input line Vinput during the data voltage writing period T2.

Due to the law of conservation of charge, the charge at the point S does not change during the threshold compensation period T1 and the data voltage writing period T2. That is, Q1=Q2 holds. From Expression (9) and Expression (10), Expression (11) is established.
−Vth×C1+(Vref−Vth−ELVSS)×C2
=(VS-Vdata)*C1+(VS-ELVSS)*C2 (11)

Therefore, the expressions (12) and (13) are established.
VS=C1/(C1+C2)×Vdata+C2/(C1+C2)×Vref−Vth
(12) VGS=VG-VS
=C2/(C1+C2)×(Vdata−Vref)+Vth (13)
VGS is the potential difference between points G and S. That is, the GS potential of the drive transistor 98.

The light emission period T3 will be described. During the light emission period T3, the first capacitor 91 retains electric charges, so that the GS potential VGS of the drive transistor 98 maintains the state shown by the expression (13). VGS is a potential according to the brightness of the organic light emitting element 97. That is, the first capacitor 91 holds at least an electric charge according to the brightness of the organic light emitting element 97.

The output current IMD flowing between the source electrode and the drain electrode of the driving transistor 98 flows through the organic light emitting element 97 as it is. At this time, the drive transistor 98 operates in the saturation region. Here, since the output current IMD and the drive current Ioled of the organic light emitting element 97 are the same, the equation (14) is established.

By the above, the above-mentioned formula (1) is established.

[Third Embodiment]
This embodiment relates to the display device 10 in which the fixed potential line VFIX (see FIG. 3) connected to the second capacitor 92 is shared with the high power supply line ELVDD. Descriptions of parts common to the second embodiment will be omitted.

FIG. 37 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element 97 of the third embodiment to emit light. The circuit shown in FIG. 37 is part of a pixel circuit included in the sub-pixel 99.

The circuit shown in FIG. 37 includes an organic light emitting element 97, a first capacitor 91, a second capacitor 92, and a driving transistor 98. A high power supply line ELVDD, a low power supply line ELVSS, and an input line Vinput are connected to the circuit shown in FIG. The input line Vinput is connected to the data voltage driver 22. The voltage of the input line Vinput alternately changes between the reference voltage Vref and the data voltage Vdata, which is a voltage indicating the light emission luminance when the organic light emitting element 97 emits light.

The input line Vinput is connected to the gate electrode of the drive transistor 98 and the first terminal of the first capacitor 91. The high power supply line ELVDD is connected to the drain electrode of the drive transistor 98 and the first terminal of the second capacitor 92. The low power supply line ELVSS is connected to the cathode electrode of the organic light emitting element 97. The low power supply line ELVSS is an example of a wiring of the first voltage. The source electrode of the drive transistor 98 is connected to the second terminal of the first capacitor 91, the second terminal of the second capacitor 92, and the anode electrode of the organic light emitting element 97.

The organic light emitting element 97 emits light based on a signal input from the input line Vinput.

Also in the present embodiment, the second capacitor 92 is formed by the first electrode 18, the first insulating layer 43, and the second metal plate 352. The second metal plate 352 is connected to the high power line ELVDD. The high power supply line ELVDD is connected to the drain electrode of the drive transistor 98. As described above, the second metal plate 352 is connected to the drain electrode of the drive transistor 98.

According to the present embodiment, the fixed potential line VFIX and the high power supply line ELVDD can be shared, so that it is possible to provide the display device 10 in which the layout of the pixel circuit is easy.

[Embodiment 4]
This embodiment relates to a display device 10 in which a P-type transistor is used as a driving transistor 98. Descriptions of parts common to the second embodiment will be omitted.

FIG. 38 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element 97 of the fourth embodiment to emit light. The circuit shown in FIG. 38 is a part of the pixel circuit included in the sub-pixel 99.

The circuit shown in FIG. 38 includes an organic light emitting element 97, a first capacitor 91, a second capacitor 92, and a drive transistor 98. A high power supply line ELVDD, a low power supply line ELVSS and an input line Vinput are connected to the circuit shown in FIG. The input line Vinput is connected to the data voltage driver 22. The voltage of the input line Vinput alternately changes between the reference voltage Vref and the data voltage Vdata, which is a voltage indicating the light emission luminance when the organic light emitting element 97 emits light.

The input line Vinput is connected to the gate electrode of the drive transistor 98 and the first terminal of the first capacitor 91. The high power supply line ELVDD is connected to the anode electrode of the organic light emitting element 97 and the first terminal of the second capacitor 92. The low power supply line ELVSS is connected to the drain electrode of the drive transistor 98. The source electrode of the drive transistor 98 is connected to the second terminal of the first capacitor 91, the second terminal of the second capacitor 92, and the cathode electrode of the organic light emitting element 97. The organic light emitting element 97 emits light based on a signal input from the input line Vinput.

According to the present embodiment, it is possible to provide the display device 10 using the P-type semiconductor in the pixel circuit.

As described above, the drive transistor 98 of this embodiment is a P-type transistor. In this case, the first electrode 18 is the cathode electrode of the organic light emitting device 97. The second electrode 19 is an anode electrode of the organic light emitting device 97.

[Fifth Embodiment]
When a layer (hereinafter referred to as layer A) has dents, gaps or holes, when another layer (hereinafter referred to as layer B) is formed on layer A, these dents, gaps or holes are formed. Along this, layer B is formed.

For example, there is a gap between the first metal plate 351 and the second metal plate 352 (see FIGS. 4, 24, etc.). When a layer is further formed on the portion of the gap, the layer may be formed along the gap. In the case of the above example, the first insulating layer 43 and a part of the first electrode 18 located above this gap may be dented. Due to the depression of the first electrode 18, the flatness of the first electrode 18 is lost. If the organic light emitting layer 47 is formed in the portion where the flatness is lost and this portion is used as the opening 461 (also referred to as the light emitting region), the image quality may deteriorate. Therefore, in this embodiment, a structure in which such a dent portion is covered with the non-opening portion 462 will be described. The description of the parts common to those of the first embodiment will be omitted.

FIG. 39 is a schematic sectional view of the display device 10 according to the fifth embodiment. FIG. 39 is an enlarged view showing a portion corresponding to one organic light emitting element 97. In FIG. 39, the second substrate 12, the space 27 and the second electrode 19 are not shown. In FIG. 39, a part of the first insulating layer 43 and the first electrode 18, which is located above the gap between the first metal plate 351 and the second metal plate 352, is dented.

Due to such a dent, the flatness of the first electrode 18 is lost. If the part where the flatness is lost is used as the light emitting region, the image quality may be deteriorated. Therefore, in the present embodiment, such a dent portion is not used as a light emitting region.
Specifically, the opening 461 of the second insulating layer 46 is located only above the second metal plate 352. That is, the upper side of the first metal plate 351 is located below the non-opening portion 462 of the second insulating layer 46. The first metal plate 351 is connected to the source/drain 33 by the second conductive portion 66 located below the non-opening portion 462. The source/drain 33 is connected to the gate 32 via the first conductive portion 65.

Therefore, the first metal plate 351 is connected to the gate electrode via the second conductive portion 66, the source/drain 33 and the first conductive portion 65. As described above, the first metal plate 351 is connected to the gate electrode at the portion covered by the non-opening portion 462.

In the second conductive portion 66 and the third conductive portion 67, the material of the first insulating layer 43, the material of the first electrode 18, and the material of the second insulating layer 46 are layered inside the material of the metal plate layer 35. .. This is because, as described above, if there is any dent or the like, the upper layer is formed along the dent or the like.

FIG. 40 is a schematic plan view of the pixel 90 according to the fifth embodiment. FIG. 40 shows the same range as FIG. The light emitting unit 17 is located above the sub-pixel 99.

FIG. 41 is a schematic plan view of the second insulating layer 46 according to the fifth embodiment. The second insulating layer 46 includes an opening 461 and a non-opening 462. The opening 461 has a rectangular shape. The opening 461 of the present embodiment is the upper half of the opening 461 (see FIG. 6) of the first embodiment. As described above, the position and shape of the opening 461 and the light emitting unit 17 are the same.

As described above, in the display device 10 according to the present embodiment, the entire area of the opening 461 faces the second metal plate 352 with the first electrode 18 interposed therebetween.

In the present embodiment, the entire light emitting unit 17 is located above the second metal plate 352. That is, the gap between the first metal plate 351 and the second metal plate 352 is not located below the light emitting unit 17. The second conductive portion 66 is not located below the light emitting portion 17. Therefore, each layer such as the first electrode 18 of the light emitting unit 17 and the organic light emitting layer 47 keeps a flat state.

As described above, the display device 10 has the planar second insulating layer 46 including the opening 461 for emitting the light emitted from the organic light emitting element 97 to the outside and the non-opening 462 that is not opened. The second insulating layer 46 is arranged in a layer different from the layer in which the first metal plate 351 and the second metal plate 352 are arranged. The non-opening portion 462 covers the space between the first metal plate 351 and the second metal plate 352.

According to the present embodiment, it is possible to provide the display device 10 in which the brightness of the light emitting unit 17 in one organic light emitting element 97 is uniform. Accordingly, it is possible to provide the display device 10 in which the uneven brightness is suppressed.

In the present embodiment, since the first insulating layer 43 in the light emitting unit 17 is flat, the effect of preventing the occurrence of a short circuit between the first electrode 18 and the second electrode 19 can be realized.

The manufacturing flow of the display device 10 of the present embodiment is the same as the manufacturing flow of the display device 10 of the first embodiment described with reference to FIG. 42 to 48 are explanatory views showing the manufacturing process of the display panel of the fifth embodiment. An outline of a method of manufacturing the display panel used in the display device 10 of the present embodiment will be described with reference to FIGS. 14 and 48 to 33.

Since steps up to step S503 are the same as those in the first embodiment, description thereof will be omitted.

As shown in the cross-sectional view of FIG. 42, the manufacturing apparatus forms the metal plate layer 35 having a predetermined shape by a sputtering method, a photolithography method, or the like (step S504). The metal plate layer 35 includes a first metal plate 351 and a second metal plate 352. As described above, the metal plate layer 35 is a conductor.

In the present embodiment, as described above, if there is any dent or the like, a layer is formed along the dent or the like. Therefore, a conductor layer is formed on the inner surface of the second hole 661. The conductor layer forms the second conductive portion 66 that connects the metal plate layer 35 and the source/drain 33. A hole remains in the central portion of the second conductive portion 66.

As shown in the cross-sectional view of FIG. 43, the manufacturing apparatus forms the first insulating layer 43 by the CVD method or the like (step S505).

In the present embodiment, a conductor layer is formed on the inner surface of the hole at the center of the second conductive portion 66. A hole that is shallower than the hole shown in FIG. 43 remains in the center of the second conductive portion 66. Further, between the first metal plate 351 and the second metal plate 352, a groove-shaped dent is formed in the first insulating layer 43.

As shown in the cross-sectional view of FIG. 44, the manufacturing apparatus creates a third hole 671 penetrating from the surface of the first insulating layer 43 to above the second conductive portion 66 on the right side by a dry etching method or the like. The conductor that is the material of the metal plate layer 35 is exposed on the inner surface of the third hole 671.

As shown in the sectional view of FIG. 45, the manufacturing apparatus forms the first electrode 18 having a predetermined shape by a sputtering method, a photolithography method, or the like (step S506).

In this embodiment, a conductor layer is formed on the inner surface of the hole at the center of the third hole 671. The conductor layer is connected to the lower second conductive portion 66 to form a third conductive portion 67 connecting the first electrode 18 and the source/drain 33.

As shown in the sectional view of FIG. 46, the manufacturing apparatus forms the second insulating layer 46 having a predetermined shape by the CVD method, the dry etching method or the like (step S507). 47 is a schematic plan view of the display device 10 at the stage shown in FIG. FIG. 47 shows the same portion as FIG. As described above, the second insulating layer 46 includes the opening 461 and the non-opening 462. The opening 461 covers the central portion of the upper half of the first electrode 18. The non-opening portion 462 covers the boundary between the sub-pixels 99, about the lower half of the first electrode 18 and the edge of the first electrode 18.

As shown in the cross-sectional view of FIG. 48, the manufacturing apparatus forms the organic light emitting layer 47 by a vapor deposition method or the like (step S508). The organic light emitting layer 47 covers the opening 461.

Since step S509 and subsequent steps are the same as the manufacturing flow described in the first embodiment, description thereof will be omitted.

As described above, in the present embodiment, the case where the layer having the depressed upper surface is formed on the depressed portion has been described as an example. According to the present embodiment, deterioration of image quality can be suppressed even in such a case.

[Sixth Embodiment]
The present embodiment relates to the display device 10 in which the entire area of the opening 461 faces the first metal plate 351. Descriptions of portions common to the fifth embodiment will be omitted.

FIG. 49 is a schematic sectional view of the display device 10 according to the sixth embodiment. FIG. 49 is an enlarged view of a portion corresponding to one organic light emitting element 97. In FIG. 49, the second substrate 12, the space 27 and the second electrode 19 are not shown.

The opening 461 of the second insulating layer 46 is located only above the first metal plate 351. That is, the upper side of the second metal plate 352 is located below the non-opening portion 462 of the second insulating layer 46.

FIG. 50 is a schematic plan view of the pixel 90 according to the sixth embodiment. FIG. 50 shows the same range as FIG. The light emitting unit 17 is located below the sub-pixel 99.

As described above, in the display device 10 according to the present embodiment, the entire area of the opening 461 faces the first metal plate 351 with the first electrode 18 interposed therebetween.

In the present embodiment, the light emitting unit 17 is wholly located above the first metal plate 351. That is, the gap between the first metal plate 351 and the second metal plate 352 is not located below the light emitting unit 17. The second conductive portion 66 is not located below the light emitting portion 17. Therefore, each layer such as the first electrode 18 of the light emitting unit 17 and the organic light emitting layer 47 keeps a flat state.

According to the present embodiment, it is possible to provide the display device 10 in which the brightness of the light emitting unit 17 in one organic light emitting element 97 is uniform. Accordingly, it is possible to provide the display device 10 in which the uneven brightness is suppressed.

In the present embodiment, since the first insulating layer 43 in the light emitting unit 17 is flat, the effect of preventing the occurrence of a short circuit between the first electrode 18 and the second electrode 19 can be realized.

[Embodiment 7]
This embodiment relates to the display device 10 having an area where the opening 461 faces the first metal plate 351 and an area where the opening 461 faces the second metal plate 352. Descriptions of portions common to the fifth embodiment will be omitted.

FIG. 51 is a schematic cross-sectional view of the display device 10 according to the seventh embodiment. FIG. 51 is an enlarged view showing a portion corresponding to one organic light emitting element 97. In FIG. 49, the second substrate 12, the space 27 and the second electrode 19 are not shown.

The opening 461 of the second insulating layer 46 has a first opening 4611 and a second opening 4612. The first opening 4611 is located only above the first metal plate 351. The second opening 4612 is located only above the second metal plate 352. The organic light emitting layer 47 covers both the first opening 4611 and the second opening 4612.

FIG. 52 is a schematic plan view of the pixel 90 according to the seventh embodiment. 52 shows the same range as FIG. One sub-pixel 99 has one first light emitting portion 171 and one second light emitting portion 172. The first light emitting unit 171 is located above the sub-pixel 99. The second light emitting unit 172 is located below the sub-pixel 99.

The first opening 4611 is an example of the first region of the opening 461 of this embodiment. The second opening 4612 is an example of the second region of the opening 461 of this embodiment. The first opening 4611 and the second opening 4612 do not overlap with each other.

As described above, the opening 461 of this embodiment has the first region and the second region which do not overlap with each other. In the display device 10 of the present embodiment, the first region faces the first metal plate 351 with the first electrode 18 sandwiched therebetween, and the second region has the second region sandwiched with the first electrode 18 sandwiched therebetween. Of the metal plate 352.

In the present embodiment, the light emitting unit 17 is wholly located above the first metal plate 351 or the second metal plate 352. That is, the gap between the first metal plate 351 and the second metal plate 352 is not located below the light emitting unit 17. The second conductive portion 66 is not located below the light emitting portion 17. Therefore, each layer such as the first electrode 18 of the light emitting unit 17 and the organic light emitting layer 47 keeps a flat state.

In addition, the area of the light emitting portion 17 of the present embodiment occupies a large proportion of the area of the sub-pixel 99 as compared with the light emitting portion 17 of the fifth and sixth embodiments. Therefore, the sub-pixel 99 with high emission brightness can be realized.

According to the present embodiment, it is possible to provide the display device 10 in which the brightness of the light emitting unit 17 in one organic light emitting element 97 is uniform and the light emitting brightness is high. Accordingly, it is possible to provide the display device 10 that displays a bright image with less unevenness in brightness.

In the present embodiment, since the first insulating layer 43 in the light emitting unit 17 is flat, the effect of preventing the occurrence of a short circuit between the first electrode 18 and the second electrode 19 can be realized.

[Embodiment 8]
The present embodiment relates to the display device 10 in which the second conductive portion 66 is arranged outside the first electrode 18. Descriptions of portions common to the first embodiment will be omitted. FIG. 53 is a schematic cross-sectional view of the display device 10 of the eighth embodiment. FIG. 54 is a schematic cross-sectional view of the display device 10 of the comparative example of the eighth embodiment. 53 and 54 are enlarged views showing the vicinity of the metal plate layer 35 of one organic light emitting element 97.

In the comparative example shown in FIG. 54, the first electrode 18 extends above the second conductive portion 66. Inside the second conductive portion 66 of the comparative example, the distance between the metal plate layer 35 and the first electrode 18, that is, the thickness t of the first insulating layer 43 is the original thickness T of the first insulating layer 43. Is thinner than.

On the other hand, in the present embodiment, as shown in FIG. 53, second conductive portion 66 is provided outside first electrode 18. That is, the first electrode 18 does not cover the upper side of the second conductive portion 66. By doing so, it is possible to prevent a short circuit between the metal plate layer 35 and the first electrode 18.

Here, the second conductive portion 66 connects the metal plate layer 35 and the source/drain 33 (see FIG. 4). The second conductive portion 66 shown on the left side of FIG. 53 is connected to the source electrode, which is a part of the source/drain 33, for example.

As described above, the first metal plate 351 is connected to the source electrode at the portion not covered with the first electrode 18.

[Ninth Embodiment]
The present embodiment relates to a display device 10 that uses five transistors and shares a fixed potential line VFIX (see FIG. 3) connected to the second capacitor 92 with the low power supply line ELVSS. Descriptions of portions common to the first embodiment will be omitted.

FIG. 55 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element of the ninth embodiment to emit light. The circuit shown in FIG. 55 is part of a pixel circuit included in the sub-pixel 99.

The circuit shown in FIG. 55 includes an organic light emitting element 97, a first capacitor 91, a second capacitor 92, switch transistors 96a, 96b, 96c, 96d, and a drive transistor 98. A high power supply line ELVDD, a low power supply line ELVSS, an input line Vinput, an initialization power supply line Vini, and a set power supply line V1 are connected to the circuit shown in FIG. The drive transistor 98a and the switch transistors 96a, 96b, 96c, 96d of this embodiment are N-type TFTs.

The initialization power supply line Vini is connected to the drain electrode of the switch transistor 96a. The switch line S11 is connected to the gate electrode of the switch transistor 96a. The voltage of Vini (an example of the second voltage) is lower than the sum of the voltage Vth-oled (threshold voltage of the organic light emitting element 97) corresponding to the light emission threshold of the organic light emitting element 97 and ELVSS (that is, Vini−). ELVSS<Vth-oled). Thereby, unnecessary light emission of the organic light emitting element 97 can be prevented in the initialization period.

The input line Vinput is connected to the data voltage driver 22. The input line Vinput is connected to the drain electrode of the switch transistor 96b. The switch line S12 is connected to the gate electrode of the switch transistor 96b. The voltage of the input line Vinput alternately changes between the reference voltage Vref, which is an example of the third voltage, and the data voltage Vdata, which is a voltage indicating the light emission luminance when the organic light emitting element 97 emits light. Here, Vref is a voltage having a value larger than the sum of the values of Vth (threshold voltage of the driving transistor 98) and Vini (that is, Vref>Vth+Vini). This is because the drive transistor 98 is turned on to proceed to the Vth compensation period T1.

The high power supply line ELVDD is connected to the drain electrode of the switch transistor 96d. The gate electrode of the switch transistor 96d is connected to the switch line EM. The switch line EM is connected to the emission control driver 23. A signal is input from the emission control driver 23 to the gate electrode of the switch transistor 96d via the switch line EM. This signal controls the light emission time of the organic light emitting element 97. The drain electrode of the drive transistor 98 is connected to the source electrode of the switch transistor 96c and the source electrode of the switch transistor 96d.

The set power supply line V1 is connected to the drain electrode of the switch transistor 96c. The gate electrode of the switch transistor 96c is connected to the switch line S3. The voltage of V1 (an example of a fourth voltage) is a voltage equal to or higher than a voltage obtained by subtracting Vth (threshold voltage of the driving transistor 98) from Vref (that is, V1≧Vref−Vth).

The low power supply line ELVSS is connected to the cathode electrode of the organic light emitting element 97 and the first terminal of the second capacitor 92.

The source electrode of the switch transistor 96b is connected to the first terminal of the first capacitor 91 and the gate electrode of the drive transistor 98. The first terminal of the first capacitor 91 is connected to the gate electrode of the drive transistor 98. The source electrode of the drive transistor 98 is connected to the second terminal of the first capacitor 91, the second terminal of the second capacitor 92, the source electrode of the switching transistor 96a, and the anode electrode of the organic light emitting element 97.

The organic light emitting element 97 emits light based on signals input from the switch lines S1, S2, S3, EM and the input line Vinput.

The operation of the switch transistors 96a, 96b, 96c, 96d and the drive transistor 98 will be described in detail. Here, in the following description, a point where the gate electrode of the drive transistor 98, the first terminal of the first capacitor 91, and the source electrode of the switch transistor 96b are connected is referred to as a point G. Further, a portion where the source electrode of the drive transistor 98, the first capacitor 91 and the second capacitor 92, the anode electrode of the organic light emitting element 97, and the source electrode of the switch transistor 96a are connected is referred to as point S. Further, a portion where the drain electrode of the drive transistor 98, the source electrode of the switch transistor 96c, and the source electrode of the switch transistor 96d are connected is referred to as a point D. The potential at the point S is described as VS, the potential at the point G is described as VG, and the potential at the point D is described as VD.

FIG. 56 is a time chart for driving the circuit according to the ninth embodiment. FIG. 57 is a graph showing changes in VD and VS in the circuit according to the ninth embodiment. In the present embodiment, in the light emitting operation of the organic light emitting element 97, the initialization period T0, the threshold voltage Vth compensation period T1, the data writing period T2, and the light emitting period T3 sequentially pass.

As shown in FIG. 56, in the initialization period T0, the signals input to the switch lines S11 and S12 are at high level, the signals input to the switch lines S13 and EM are at low level, and the Vinput voltage is Vref. .. In the initialization period T0, the switch transistors 96a and 96b are turned on, and the switch transistors 96c and 96d and the drive transistor 98 are turned off. At this time, VG=Vref. Further, as shown in FIG. 57, VS=Vini and VD=VS. In addition, since Vini-ELVSS<Vth-oled as described above, leakage light emission of the organic light emitting element 97 is prevented. In the initialization period T0, the potentials of the gate electrode and the source electrode of the driving transistor 98 are initialized.

During the Vth compensation period T1, the signals input to the switch lines S12 and S13 are at high level, the signals input to the switch lines S11 and EM are at low level, and the Vinput voltage is Vref. In the Vth compensation period T1, the switch transistors 96b and 96c and the drive transistor 98 are turned on, and the switch transistors 96a and 96d are turned off. When the drive transistor 98 is turned on and becomes conductive, the potential at the point S rises and the potential difference between the points G and S converges at the threshold Vth. Therefore, VG=Vref, and VS=Vref−Vth, as shown in FIG. Also, VD=V1.

In the data writing period T2, the signal input to the switch line S12 is at high level, the signals input to the switch lines S11, S13, and EM are at low level, and the Vinput voltage is Vdata. In the data writing period T2, the switch transistor 96b is turned on, and the switch transistors 96a, 96c, 96d and the drive transistor 98 are turned off. As a result, the data voltage Vdata is written between the gate electrode and the source electrode of the drive transistor 98 by dividing the voltage of the first capacitor 91 and the second capacitor 92 in series. Therefore, VS=C1/(C1+C2)×Vdata+C2/(C1+C2)×Vref−Vth (equation (12)), and VG=Vdata. Also, VD=V1. Here, VS is obtained by calculation according to the law of conservation of charge at the point S during the periods T1 and T2 as in the second embodiment, and therefore the description of the calculation procedure is omitted.

In the light emission period T3, the signal input to the switch line EM is at high level, the signals input to the switch lines S11, S12, and S13 are at low level, and the Vinput voltage is Vref. In the light emission period T3, the switch transistor 96d and the drive transistor 98 are turned on, and the switch transistors 96a, 96b, 96c are turned off. When the switch transistor 96d and the drive transistor 98 are turned on, a current Ioled flows through the organic light emitting element 97. Here, VD=ELVDD. Further, since Ioled is the same as that of the second embodiment, detailed description thereof will be omitted.

Here, normally, during the Vth compensation period, the gate-source voltage is near the threshold value (Vth+1 to 2V), and when the drain-source voltage becomes high at the same time, the kink effect is likely to occur. On the other hand, it is possible to weaken the electric field between the drain and the source and suppress the kink effect by increasing the channel length, but in this case, it is disadvantageous in high definition.

In the present embodiment, in the initialization period T0 and the Vth compensation period T1, the voltage VD on the drain side of the drive transistor 98 can be freely set by the voltage of the set power supply line V1 (provided that V1≧Vref−Vth. ). Therefore, by lowering the drain-source voltage (V1-Vini), the bias stress on the drive transistor 98 can be relaxed. As a result, the kink effect can be suppressed, and the fluctuation of the threshold Vth of the drive transistor 98 can be suppressed.

Further, in the present embodiment, since the kink effect is suppressed by lowering the drain-source voltage, the channel length can be shortened, which is advantageous in high definition.

Note that the signal input to the switch line S3 may be at a high level during the initialization period. That is, the switch transistor 96c may be turned on in the initialization period. When the switch transistor 96c becomes conductive during the initialization period, the current from the set power supply line V1 flows to the initialization power supply line Vini via the switch transistors 96c and 96d and the drive transistor 98. Since the voltage of the power supply line Vini is lower than the sum of the voltage Vth corresponding to the light emission threshold of the organic light emitting element 97 and the voltage of the low power supply ELVSS (that is, Vini<Vth+ELVSS), the current flows to the organic light emitting element 97. Does not flow, and the organic light emitting element 97 does not emit light.

In the above description of Embodiments 1 to 9, the organic light emitting element 97 having the organic light emitting layer is illustrated as an example of the light emitting element. However, the light emitting element may be, for example, an inorganic light emitting element having an inorganic light emitting layer. The inorganic light emitting element is, for example, a so-called quantum dot type light emitting element. The quantum dot type light emitting element has a quantum dot which is a material made of semiconductor crystallites and is arranged between the first electrode and the second electrode. The quantum dot emits light by a current flowing between the first electrode and the second electrode, similarly to the organic light emitting element.

The technical features (constituent elements) described in the respective embodiments can be combined with each other, and by combining them, new technical features can be formed.
It should be considered that the embodiments disclosed this time are exemplifications in all points and not restrictive. The scope of the present invention is defined not by the above meaning but by the scope of the claims, and is intended to include meanings equivalent to the scope of the claims and all modifications within the scope.

10 Display Device 11 First Substrate 12 Second Substrate 13 Driver IC
14 FPC
15 image display unit 16 display substrate 17 light emitting unit 171 first light emitting unit 172 second light emitting unit 18 first electrode (first electrode)
19 Second Electrode 20 Drive Circuit 21 Scan Driver 22 Data Voltage Driver 23 Emission Control Driver 24 Protection Circuit 25 Sealing Section 27 Space 31 Semiconductor Section 32 Gate 33 Source Drain 34 Etching Stop Section 35 Metal Plate Layer 351 1st Metal Plate ( First metal plate)
352 Second metal plate (second metal plate)
37 Transistor 371 First Transistor 372 Second Transistor 42 Third Insulating Layer 43 First Insulating Layer 45 Flattening Layer 46 Second Insulating Layer 461 Opening 4611 First Opening 4612 Second Opening 462 Non-Opening 47 Organic Light Emitting Layer 61 1st laminated body 62 2nd laminated body 65 1st electroconductive part 651 1st hole 66 2nd electroconductive part 661 2nd hole 67 3rd electroconductive part 671 3rd hole 71 Mounting table 72 Substrate (mother substrate)
73 Board fixing part (board holder)
74 insulating film 75 unit insulating film 751 first region 752 second region 76 unit insulating film 90 pixel 91 first capacitor 92 second capacitor 96, 96a, 96b, 96c, 96d switch transistor 97 organic light emitting device 98 drive transistor 99 subpixel

Claims (20)

A light emitting element in which a first electrode, a light emitting layer, and a second electrode are laminated,
A pixel circuit arranged below the light emitting element, comprising a driving transistor for controlling a current supplied to the light emitting element, the pixel circuit having a source electrode connected to the first electrode;
A first metal plate and a second metal plate arranged to face the light emitting layer with the first electrode interposed therebetween;
The first metal plate and the second metal plate, and a first insulating layer disposed between the first electrode,
The first metal plate is connected to the gate electrode of the drive transistor,
The second metal plate is connected to the wiring of the first voltage,
A display device in which the first metal plate and the second metal plate are arranged on the same surface. A first capacitor is formed by the first electrode, the first insulating layer, and the first metal plate,
A second capacitor is formed by the first electrode, the first insulating layer, and the second metal plate,
The display device according to claim 1, wherein the first capacitor and the second capacitor are connected in series, and a connection point between the first capacitor and the second capacitor is connected to the source electrode. The display device according to claim 1, wherein the first capacitor holds at least an electric charge according to the brightness of the light emitting element. The drive transistor is an N-type transistor,
The first electrode is an anode electrode,
The display device according to claim 1, wherein the second electrode is a cathode electrode. The drive transistor is a P-type transistor,
The first electrode is a cathode electrode,
The display device according to claim 1, wherein the second electrode is an anode electrode. The first electrode has a planar shape,
The same first insulating layer is provided between the first metal plate and the first electrode and between the second metal plate and the first electrode. Display device described. 7. The distance between the first metal plate and the first electrode and the distance between the second metal plate and the first electrode are equal to each other. Display device. A planar second insulating layer including an opening for emitting light emitted from the light emitting element to the outside and a non-opening not opened;
The second insulating layer is arranged in a layer different from the layer in which the first metal plate and the second metal plate are arranged,
The display device according to claim 1, wherein the non-opening portion covers a space between the first metal plate and the second metal plate. The display device according to claim 8, wherein the first metal plate is connected to the gate electrode at a portion covered by the non-opening portion. The display device according to claim 1, wherein the first metal plate is connected to the source electrode at a portion which is not covered with the first electrode. The display device according to claim 8 or 9, wherein the first electrode is connected to the source electrode at a portion covered by the non-opening portion. The display device according to claim 8, wherein the entire area of the opening faces the first metal plate with the first electrode interposed therebetween. The display device according to claim 8, wherein the entire area of the opening faces the second metal plate with the first electrode interposed therebetween. The opening has a first region and a second region that do not overlap each other,
The first region faces the first metal plate across the first electrode,
The display device according to any one of claims 8 to 11, wherein the second region faces the second metal plate with the first electrode interposed therebetween. The display device according to claim 1, wherein the second metal plate is connected to the second electrode. The display device according to claim 1, wherein the second metal plate is connected to the drain electrode. The pixel circuit applies a second voltage, which is lower than a sum of a voltage corresponding to a light emission threshold of the light emitting element and the first voltage, to the first electrode, and applies a threshold voltage of the drive transistor to the gate electrode. The display device according to claim 2, wherein a third voltage equal to or more than a sum of the second voltage and the second voltage is applied. The display device according to claim 17, wherein the pixel circuit conducts the drive transistor and applies a fourth voltage equal to or higher than a voltage obtained by subtracting the threshold voltage from the third voltage to a drain electrode of the drive transistor. 19. The display device according to claim 18, wherein the pixel circuit stops applying the fourth voltage to the drain electrode and applies a voltage corresponding to the emission brightness of the light emitting element to the gate electrode. A transistor having a source electrode, a drain electrode and a gate electrode is arranged on one surface of the substrate,
A third insulating layer overlying the transistor is disposed over the transistor,
A first metal plate connected to the gate electrode via a first conductive portion penetrating the third insulating layer and a second metal plate insulated from the first metal plate are provided on the upper side of the third insulating layer. Placed in the same layer,
Arranging a first insulating layer above the layers of the first metal plate and the second metal plate,
A first electrode connected to the source electrode via a second conductive portion penetrating the first insulating layer and the third insulating layer is disposed above the first insulating layer;
A light emitting layer is disposed on the upper side of the first electrode,
A method of manufacturing a display device, wherein a second electrode is arranged on the upper side of the light emitting layer.

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