JP2017120376A - Display and manufacturing method of display - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an organic light emitting display that has suppressed unevenness in luminance.SOLUTION: A display comprises: a first laminate 61 that includes an organic light emitting element 97 in which a first electrode 18, organic light emitting layer 47, and second electrode 19 are laminated; a second laminate 62 that includes a source electrode connected to the first electrode 18 and has a transistor 371 controlling a current supplied to the organic light emitting element 97 arranged thereon; a first metal plate 351 and a second metal plate 352 that are arranged opposite to the organic light emitting layer 47 across the first electrode 18; and a first insulating layer 43 that is arranged between the first metal plate 351 and second metal plate 352 and the first electrode 18. The first metal plate 351 is connected to a gate electrode of the transistor 371, the second metal plate 352 is connected to a wiring of a first voltage, and the first metal plate 351 and the second metal plate 352 are arranged on the same layer.SELECTED DRAWING: Figure 4

Description

  The present disclosure relates to a display device and a method for manufacturing the display device.

  The organic light emitting display device displays an image using an organic light emitting element (OLED, Organic Light Emitting Diode) (see Patent Document 1). Note that an OLED display device is referred to as a display device.

  A pixel constituting an image display unit of a display device includes a stacked body of an organic light emitting element which is a self light emitting element and a pixel circuit. The pixel circuit supplies a drive current to the organic light emitting element. The pixel circuit includes a TFT (Thin Film Transistor) and a storage capacitor. The display device determines the luminance of each of the plurality of pixels based on an image signal acquired from the outside. The display device controls the pixel circuit so as to supply a driving current corresponding to the luminance to the organic light emitting element.

JP 2014-163991 A

  There are cases where the current corresponding to the image signal and the drive current actually supplied to the organic light emitting element do not match. Due to such a mismatch, the luminance of the organic light emitting element may become non-uniform in the display panel (so-called luminance unevenness). When luminance unevenness occurs, the image quality deteriorates.

  An object of one aspect is to provide a display device that suppresses deterioration in image quality.

  One aspect of the display device of the present disclosure includes a light-emitting element in which a first electrode, a light-emitting layer, and a second electrode are stacked, and a current supplied to the light-emitting element, which includes a source electrode connected to the first electrode. A driving transistor for controlling, a pixel circuit disposed below the light emitting element, a first metal plate and a second metal plate disposed to face the light emitting layer with the first electrode interposed therebetween, A first insulating layer disposed between the first metal plate and the second metal plate, and the first electrode, the first metal plate being connected to a gate electrode of the driving transistor; The second metal plate is connected to the wiring of the first voltage, and the first metal plate and the second metal plate are arranged on the same surface.

  According to one aspect, it is possible to provide a display device that suppresses deterioration in image quality.

It is an external view of a display apparatus. It is a schematic diagram which shows arrangement | positioning of a pixel. It is an equivalent circuit diagram which shows the circuit which light-emits one organic light emitting element. It is a schematic cross section of a display device. It is a schematic plan view of a pixel. It is a schematic plan view of a 2nd insulating layer. It is a model top view of the pixel which removed the 2nd insulating layer. It is a schematic plan view of a 1st electrode. It is a schematic plan view of a metal plate layer. It is explanatory drawing which shows the method of producing an insulating film. It is a graph explaining the nonuniformity of the thickness of an insulating film. It is a top view of a unit insulating film. It is sectional drawing of a unit insulating film. It is a flowchart which shows the flow of manufacture of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is explanatory drawing which shows the manufacturing process of a display panel. It is a hardware block diagram of a display apparatus. FIG. 6 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element of Embodiment 2 to emit light. 6 is a time chart illustrating an input voltage Vinput according to the second embodiment. FIG. 5 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element of Embodiment 3 to emit light. FIG. 6 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element of Embodiment 4 to emit light. FIG. 10 is a schematic cross-sectional view of a display device according to a fifth embodiment. 6 is a schematic plan view of a pixel according to Embodiment 5. FIG. FIG. 10 is a schematic plan view of a second insulating layer in a fifth embodiment. FIG. 10 is an explanatory diagram showing a manufacturing process of the display panel of the fifth embodiment. FIG. 10 is an explanatory diagram showing a manufacturing process of the display panel of the fifth embodiment. FIG. 10 is an explanatory diagram showing a manufacturing process of the display panel of the fifth embodiment. FIG. 10 is an explanatory diagram showing a manufacturing process of the display panel of the fifth embodiment. FIG. 10 is an explanatory diagram showing a manufacturing process of the display panel of the fifth embodiment. FIG. 10 is an explanatory diagram showing a manufacturing process of the display panel of the fifth embodiment. FIG. 10 is an explanatory diagram showing a manufacturing process of the display panel of the fifth embodiment. FIG. 10 is a schematic cross-sectional view of a display device according to a sixth embodiment. 22 is a schematic plan view of a pixel according to Embodiment 6. FIG. FIG. 10 is a schematic cross-sectional view of a display device according to a seventh embodiment. FIG. 10 is a schematic plan view of a pixel according to a seventh embodiment. FIG. 10 is a schematic cross-sectional view of a display device according to an eighth embodiment. 10 is a schematic cross-sectional view of a display device of a comparative example of Embodiment 8. FIG. FIG. 10 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element of Embodiment 9 to emit light. 10 is a time chart relating to driving of a circuit according to the ninth embodiment. 22 is a graph showing changes in VD and VS in the circuit according to the ninth embodiment.

  Hereinafter, embodiments of the display device will be described with reference to the drawings as appropriate. The ordinal numbers such as “first” and “second” in the specification and claims are attached to clarify the relationship between elements and prevent confusion between elements. Therefore, these ordinal numbers do not limit the elements numerically.

  In addition, the dimensions and ratios of the illustrated components may not be illustrated so as to match the actual components. In addition, for convenience of illustration and drawing, components included in the actual product may be omitted, or dimensions of the illustrated components may be exaggerated as compared to components included in the actual product.

  Further, the term “connection” means that the connection targets are electrically connected. “Electrically connected” includes a case where the objects to be connected are connected via an electrical element such as an electrode, a wiring, a resistor, or a capacitor. Note that the terms “electrode” and “wiring” do not functionally limit these components. For example, the “wiring” can be used as a part of the “electrode”. Conversely, the “electrode” can be used as a part of the “wiring”.

[Embodiment 1]
FIG. 1 is an external view of the display device 10. FIG. 1 is a view of the display device 10 as viewed from the front side, that is, the side of the surface on which an image is displayed. The display device 10 is a device that displays still images and moving images. The display device 10 is used by being incorporated in an electronic device. The electronic device is, for example, a smartphone, a tablet terminal, a personal computer, a television, or the like. The display device 10 of the present embodiment is an OLED display panel (hereinafter abbreviated as a display panel). In the following description, the upper, lower, left and right of each figure are used.

  The display device 10 includes a second substrate 12, a driver IC 13, an FPC (Flexible Printed Circuits) 14, and a display substrate 16. The display substrate 16 is a glass substrate provided with the image display unit 15, the drive circuit 20, and wiring (not shown) on one side.

  The second substrate 12 is, for example, a glass substrate that covers the image display unit 15 and the drive circuit 20. Note that the second substrate 12 may be a flexible substrate. A space 27 (see FIG. 4) between the second electrode 19 and the second substrate 12 is hermetically sealed by a sealing portion 25 surrounding the image display portion 15 and the drive circuit 20. The space 27 is filled with an inert gas such as nitrogen gas.

  The driver IC 13 is an integrated circuit that is mounted on the display substrate 16 using an anisotropic conductive film and is electrically connected to the display substrate 16. The function of the driver IC 13 will be described later.

  The FPC 14 is a flexible substrate connected to the display substrate 16. The FPC 14, the driver IC 13 and the drive circuit 20 included in the display substrate 16 are connected via a wiring (not shown). The display device 10 acquires an image signal from the control device of the electronic device via the FPC 14.

  The image display unit 15 includes a large number of pixels 90 (see FIG. 2) regularly arranged. The image display unit 15 is covered with the second electrode 19. The pixel 90 has three sub-pixels 99 (see FIG. 5). The relationship between the pixel 90 and the subpixel 99 will be described later.

  The sub-pixel 99 includes an organic light-emitting element 97 (see FIG. 3) and a pixel circuit that controls a current supplied to the organic light-emitting element 97. The organic light emitting element 97 emits light based on a current supplied from the pixel circuit. The pixel circuit will be described later.

  The second electrode 19 is a common electrode connected to each subpixel 99. The second electrode 19 is a translucent electrode made of, for example, ITO (Indium Tin Oxide), transparent conductive ink, or graphene. Further, the material of the second electrode 19 may be, for example, a very thin film of silver (Ag), magnesium (Mg), calcium (Ca), or the like (eg, MgAg alloy). The second electrode 19 is a cathode electrode of the organic light emitting device 97 of the present embodiment.

  The drive circuit 20 includes a scan driver 21, a data voltage driver 22, an emission control driver 23, and a protection circuit 24. The drive circuit 20 is formed by a semiconductor process. Note that a part of the drive circuit 20 incorporates the function in the driver IC 13 and may not be formed on the display substrate 16. Further, the data voltage driver 22 may not be formed on the display substrate 16. The outline of the drive circuit 20 will be described below.

  The scanning driver 21 is located outside the image display unit 15 along the left side of the image display unit 15. The scanning driver 21 sequentially drives the plurality of pixels 90 arranged in each row in units of rows to perform light emission control. In other words, the scan driver 21 performs light emission control of the pixel 90 by driving a wiring (see FIG. 2) extending in the horizontal direction from the scan driver 21. Hereinafter, this wiring is appropriately referred to as a scanning line.

  The bold arrow in the vertical direction in FIG. 1 indicates the scanning direction. The scanning driver 21 displays an image on the image display unit 15 by switching the scanning line to be driven in the scanning direction. Note that the order in which the scanning driver 21 switches the scanning lines may be from the upper side to the lower side of the image display unit 15 and from the lower side to the upper side. Further, the scanning driver 21 may switch the scanning lines in an arbitrary order. Furthermore, depending on the application, there may be a case where two or more scanning lines are simultaneously selected and driven, and the combination of the selected scanning lines is switched.

  The data voltage driver 22 is located outside the image display unit 15 along the lower side of the image display unit 15. The data voltage driver 22 outputs a signal indicating the brightness of the pixel 90 based on the image signal acquired via the FPC 14 to the data line of the image display unit 15. The signal voltage is simultaneously stored in the capacity of each pixel 90 arranged on one scanning line.

  The emission control driver 23 is located outside the image display unit 15 along the right side of the image display unit 15. The emission control driver 23 is a circuit that controls the light emission time of each organic light emitting element 97 in the image display unit 15.

  The protection circuit 24 is located outside the image display unit 15 along the upper side of the image display unit 15. The protection circuit 24 is a circuit that prevents damage to the display panel due to electrostatic discharge or the like.

  FIG. 2 is a schematic diagram showing the arrangement of the pixels 90. Pixels 90 are arranged in a matrix on the image display unit 15. The scanning driver 21 and the data voltage driver 22 are located outside the image display unit 15. A wiring extending in the horizontal direction from the scanning driver 21 is connected to each pixel 90. A wiring extending in the vertical direction from the data voltage driver 22 is also connected to each pixel 90. That is, each pixel 90 is connected to the scanning driver 21 and the data voltage driver 22.

  As described above, each pixel 90 has three subpixels 99. Signals output from the scan driver 21 and the data voltage driver 22 to each pixel 90 are input to the three sub-pixels 99. Signals output to each pixel 90 by the scanning driver 21 and the data voltage driver 22 will be described later.

  FIG. 3 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element 97 to emit light. In FIG. 3, one organic light emitting element 97 is described using a graphic symbol of OLED (Organic Light Emitting Diode) meaning an organic light emitting diode. Each pixel 90 indicated by a rectangle in FIG. 2 includes three circuits shown in FIG. That is, each subpixel 99 includes one circuit shown in FIG. The circuit illustrated in FIG. 3 is an example of a pixel circuit included in one subpixel 99.

  The pixel circuit shown in FIG. 3 is a circuit that controls light emission of the organic light emitting element 97, and includes a first capacitor 91, a second capacitor 92, a switch transistor 96, and a drive transistor 98. The source electrode of the driving transistor 98 is an example of the source electrode in this embodiment. The gate electrode of the driving transistor 98 is an example of the gate electrode of this embodiment.

  A high power supply line ELVDD, a low power supply line ELVSS, an input line Vinput, a switch line S1, and a fixed potential line VFIX are connected to the circuit. Here, the low power supply line is a power supply line to which a voltage having a voltage value lower than that of the high power supply line is supplied. The input line Vinput is connected to the data voltage driver 22. The voltage of the input line Vinput changes alternately between the reference voltage Vref (an example of the third voltage) and the data voltage. The data voltage is a voltage indicating light emission luminance when the organic light emitting element 97 emits light. The switch line S1 is connected to the scanning driver 21.

  The input line Vinput is connected to the drain electrode of the switch transistor 96. The switch line S1 is connected to the gate electrode of the switch transistor 96. The high power line ELVDD is connected to the drain electrode of the drive transistor 98. The low power line ELVSS is connected to the cathode electrode of the organic light emitting element 97. The fixed potential line VFIX (in other words, the first voltage line) is connected to the first terminal of the second capacitor 92. The first terminal of the second capacitor 92 is, for example, a second metal plate 352 described with reference to FIG. Note that the drive transistor 98 and the switch transistor 96 of the present embodiment are N-type TFTs.

The source electrode of the switch transistor 96 is connected to the first terminal of the first capacitor 91 and the gate electrode of the drive transistor 98. The first terminal of the first capacitor 91 is connected to the gate electrode of the drive transistor 98. The source electrode of the driving transistor 98 is connected to the second terminal of the first capacitor 91, the second terminal of the second capacitor 92, and the anode electrode of the organic light emitting element 97. The first terminal of the first capacitor 91 is, for example, a first metal plate 351 described with reference to FIG.
Here, the first electrode 18 described in FIG. 4 (for example, the anode electrode of the organic light emitting element 97) is used as the second terminal of the first capacitor 91 and the second terminal of the second capacitor 92.

  The organic light emitting element 97 emits light based on signals input from the switch line S1 and the input line Vinput. Details of operations of the switch transistor 96 and the drive transistor 98 will be described later.

  FIG. 4 is a schematic cross-sectional view of the display device 10. FIG. 4 is an enlarged view showing a portion including one organic light emitting element 97. In the following description, the upper side of the schematic cross-sectional view indicates the front side of the display device 10.

  The display device 10 may have a TFE sealing structure in which the image display unit 15 is covered with a multilayer TFE (Thin Film Encapsulation) stack in which inorganic films and organic films are alternately stacked. In such a case, the display device 10 does not include the second substrate 12 and the space 27.

  The display substrate 16 includes a first stacked body 61 and a second stacked body 62. The first stacked body 61 includes an organic light emitting element 97 in which the first electrode 18, the organic light emitting layer 47, and the second electrode 19 are stacked. More specifically, the first stacked body 61 includes the first electrode 18, the second insulating layer 46, the organic light emitting layer 47, and the second electrode 19. The first stacked body 61 is also referred to as an OLED layer. The second stacked body 62 is also called a TFT layer or a pixel circuit layer. The first transistor 371 in the second stacked body 62 corresponds to, for example, a drive transistor 98 (see FIG. 3) that controls a current supplied to the organic light emitting element 97. The second transistor 372 in the second stacked body 62 corresponds to the switch transistor 96 (see FIG. 3) that controls the operation of the drive transistor 98. As described above, the display device 10 includes a pixel circuit (see FIG. 3) disposed below the organic light emitting element 97. In addition, this lower side has shown the downward direction of drawing in FIG.

  The first electrode 18 is an electrode separated for each organic light emitting element 97. The first electrode 18 is planar. The first electrode 18 is an electrode having a three-layer structure in which, for example, ITO, silver, and ITO are laminated. The first electrode 18 is an anode electrode of the organic light emitting device 97 of the present embodiment.

  The second insulating layer 46 is located on the first electrode 18. An opening 461 that does not cover the first electrode 18 is provided in the second insulating layer 46. In the following description, the insulating layer 46 excluding the opening 461 is referred to as a non-opening 462. The second insulating layer 46 is a layer made of an organic material.

  The organic light emitting layer 47 is located around the opening 461 and the opening 461. The organic light emitting layer 47 is a layer of an organic compound that emits light when a current flows. The organic light emitting layer 47 is a multilayer of, for example, HIL (Hole Injection Layer) / HTL (Hole Transport Layer) / EL / ETL (Electron Transport Layer) / EIL (Electron Injection Layer). Here, “/” means that the front and rear layers are laminated. The second electrode 19 is located on the organic light emitting layer 47 and the second insulating layer 46.

  The second stacked body 62 includes a first substrate 11, a gate 32 (also referred to as a gate part 32 and a gate electrode 32), a third insulating layer 42, a semiconductor part 31, and a source / drain 33 (both source / drain part 33 and source / drain electrode 33). An etching stop portion 34, a planarization layer 45, a metal plate layer 35, and a first insulating layer 43. The first substrate 11 is a rectangular glass substrate, for example. The first substrate 11 may be a flexible substrate, for example.

  The gate 32 is located on the first substrate 11. The gate 32 partially covers the first substrate 11. The gate 32 has a predetermined shape to be described later. The material of the gate 32 is a pure metal such as molybdenum or aluminum. The material of the gate 32 may be, for example, molybdenum / aluminum, titanium / aluminum / titanium, ITO, or an alloy containing these. Here, “/” means both the front and rear metal laminates and the front and rear metal alloys. The gate 32 may be a laminate of pure metal and alloy. The materials listed here are examples, and the material of the gate 32 is not limited to the materials listed here.

  The third insulating layer 42 covers the entire surface of the first substrate 11 that is not covered by the gate 32 and the gate 32. The third insulating layer 42 is a layer made of an insulator such as silicon oxide.

  The semiconductor unit 31 is located on the third insulating layer 42. The semiconductor unit 31 partially covers the third insulating layer 42. The semiconductor unit 31 has a predetermined shape to be described later. The semiconductor unit 31 is a semiconductor layer such as an oxide semiconductor. The oxide semiconductor is, for example, InGaZnO.

  The etching stop part 34 is located on the semiconductor part 31. Although not shown in the cross section shown in FIG. 4, the etching stop portion 34 is also located on the third insulating layer 42 around the semiconductor portion 31. The etching stop part 34 partially covers the semiconductor part 31 and the third insulating layer 42. The etching stop portion 34 has a predetermined shape which will be described later. Etching stop portion 34 is a layer made of, for example, silicon oxide.

  The source / drain 33 is located on the etching stop portion 34, the semiconductor portion 31 not covered with the etching stop portion 34, and the third insulating layer 42 not covered with the semiconductor portion 31 or the etching stop portion 34. The source / drain 33 partially covers the etching stop portion 34, the semiconductor portion 31, and the third insulating layer 42. The source / drain 33 has a predetermined shape to be described later.

  The source / drain 33 of the second transistor 372 and the gate 32 of the first transistor 371 are connected via the first conductive portion 65.

  The source / drain 33 is made of a conductor. The material of the source / drain 33 is a pure metal such as molybdenum or aluminum. The material of the source / drain 33 may be, for example, molybdenum / aluminum, titanium / aluminum / titanium, ITO, or an alloy containing these. The source / drain 33 may be a laminate of pure metal and alloy. The materials listed here are examples, and the material of the source / drain 33 is not limited to the materials listed here.

  The material of the source / drain 33 may be different from the material of the gate 32. The material of the source / drain 33 may be the same as the material of the gate 32.

  The planarization layer 45 covers the entire surface of the source / drain 33, the etching stop portion 34 not covered with the source / drain 33, and the third insulating layer 42 not covered with the etching stop portion 34 or the source / drain 33. An inorganic insulating layer (not shown) is interposed between the planarization layer 45, the source / drain 33, the etching stopper 34, and the third insulating layer 42.

  The planarization layer 45 is a layer made of an organic material. The material of the planarization layer 45 is, for example, a photosensitive acrylic resin. The material of the inorganic insulating layer is, for example, SiNx, SiOx, or SiNx / SiOx.

  The metal plate layer 35 is located on the planarization layer 45. The metal plate layer 35 includes a first metal plate 351 and a second metal plate 352. That is, the metal plate layer 35 is not a layer that covers the entire surface of the planarizing layer 45 but a layer that partially covers the planarizing layer 45. Accordingly, the planarization layer 45 has both a portion where the metal plate layer 35 is located and a portion where the metal plate layer 35 is not located. The shape of the metal plate layer 35 will be described later.

  The first metal plate 351 is connected to the source / drain 33 of the second transistor 372 via the second conductive portion 66. Therefore, the first metal plate 351 is connected to the gate 32 of the first transistor 371 through the second conductive portion 66, the source / drain 33 of the second transistor 372 and the first conductive portion 65. That is, the first metal plate 351 and the gate 32 of the first transistor 371 are connected.

  The thickness of the metal plate layer 35 is, for example, about 100 nanometers to 300 nanometers. The total area of the metal plate layer 35 is slightly smaller than the total area of the first electrode 18. The area of the second metal plate 352 is desirably larger than the area of the first metal plate 351. The reason for this will be described later.

  The metal plate layer 35 is a plate made of a pure metal such as molybdenum or aluminum. The metal plate layer 35 may be, for example, a plate made of molybdenum / aluminum, titanium / aluminum / titanium, ITO or an alloy containing these. Further, the metal plate layer 35 may be a laminate plate of pure metal and alloy. The materials listed here are examples, and the material of the metal plate layer 35 is not limited to the materials listed here.

  As described above, the first metal plate 351 and the second metal plate 352 of the display device 10 are arranged in the same layer. In other words, the first metal plate 351 and the second metal plate 352 are arranged on the same surface (for example, the surface of the planarization layer 45).

  The first insulating layer 43 covers the entire surface of the metal plate layer 35 and the planarization layer 45 not covered with the metal plate layer 35. The thickness of the first insulating layer 43 is, for example, about 100 nanometers to 300 nanometers. The first insulating layer 43 on the upper side of the first metal plate 351 and the first insulating layer 43 on the upper side of the second metal plate 352 have the same thickness. The first insulating layer 43 is a layer made of, for example, silicon nitride.

  The first electrode 18 is located on the first insulating layer 43. The first electrode 18 partially covers the first insulating layer 43. The first electrode 18 has a predetermined shape to be described later. The distance between the first electrode 18 and the first metal plate 351 is equal to the thickness of the first insulating layer 43 between the first electrode 18 and the first metal plate 351. The distance between the first electrode 18 and the second metal plate 352 is equal to the thickness of the first insulating layer 43 between the first electrode 18 and the second metal plate 352. Therefore, the distance between the first electrode 18 and the first metal plate 351 is equal to the distance between the first electrode 18 and the second metal plate 352.

  As described above, the organic light emitting layer 47 is located above the first electrode 18. The first metal plate 351 and the second metal plate 352 face the organic light emitting layer 47 with the first insulating layer 43 and the first electrode 18 interposed therebetween (also referred to as facing).

  As described above, the first insulating layer 43 is disposed between the first metal plate 351 and the second metal plate 352 and the first electrode 18. That is, the display device 10 includes the same first insulating layer 43 between the first metal plate 351 and the first electrode 18 and between the second metal plate 352 and the first electrode 18. Further, the distance between the first metal plate 351 and the first electrode 18 is equal to the distance between the second metal plate 352 and the first electrode 18.

  The first metal plate 351 and the second metal plate 352 are arranged in the first stacked body 61 so as to face (also referred to as facing) the organic light emitting layer 47 with the first electrode 18 interposed therebetween. The second insulating layer 46 is disposed in a layer different from the layer in which the first metal plate 351 and the second metal plate 352 are disposed. Although not shown in FIG. 4, as described in FIG. 3, the second metal plate 352 is connected to the first voltage wiring (for example, the fixed potential line VFIX). Further, the first metal plate 351 and the second metal plate 352 are in an electrically non-contact state (in other words, insulation).

  The first electrode 18 and the source / drain 33 are connected via a third conductive portion 67. The third conductive portion 67 has a structure in which a conductor that connects the first electrode 18 and the first metal plate 351 is connected to the second conductive portion 66 that connects the first metal plate 351 and the source / drain 33. . The source / drain 33 connected to the third conductive portion 67 functions as the source electrode of the present embodiment.

  The semiconductor part 31, the gate 32 and the source / drain 33 form a transistor 37. Note that the transistor 37 in FIG. 4 is a schematic diagram for the purpose of explaining the outline of the structure of the display device 10. The transistor 37 includes a first transistor 371 and a second transistor 372. The above-mentioned source electrode and gate electrode are, for example, the source electrode and gate electrode of the drive transistor 98.

  As described above, the first transistor 371 for controlling the current supplied to the organic light emitting element 97 is disposed in the second stacked body 62. The first metal plate 351 is connected to the gate electrode of the first transistor 371 through the second conductive portion 66, the source / drain 33 of the second transistor 372 and the first conductive portion 65. The second stacked body 62 has a source electrode (also referred to as a first transistor electrode) of the first transistor 371 connected to the first electrode 18 through the third conductive portion 67.

  FIG. 5 is a schematic plan view of the pixel 90. The pixels 90 are arranged in a matrix on the image display unit 15. In the display device 10 for color display, for example, the color of one pixel in the image signal is expressed by combining the light emission luminances of the organic light emitting elements 97 of three colors of red, green, and blue. Therefore, a portion including the organic light emitting element 97 of one color is referred to as a subpixel 99, and a set of three subpixels 99 is referred to as a pixel 90.

  The sub-pixels 99 for each color are the same except for the emission color. The subpixel 99 is rectangular. The subpixel 99 includes a light emitting portion 17 having a quadrangular shape (also referred to as a square shape).

  6 to 9 described below show the same range as FIG. FIG. 6 is a schematic plan view of the second insulating layer 46. The second insulating layer 46 is planar. The opening 461 provided in the second insulating layer 46 is rectangular. The non-opening portions 462 of the sub-pixels 99 are connected.

  FIG. 7 is a schematic plan view of the pixel 90 from which the second insulating layer 46 has been removed. FIG. 7 shows the first electrode 18 and the metal plate layer 35.

  FIG. 8 is a schematic plan view of the first electrode 18. The first electrode 18 is L-shaped. One sub-pixel 99 has one first electrode 18. The first electrode 18 is larger than the opening 461. That is, the first electrode 18 is located under the opening 461.

  FIG. 9 is a schematic plan view of the metal plate layer 35. The metal plate layer 35 includes a rectangular first metal plate 351 and a second metal plate 352 that is not connected to the first metal plate 351. One sub-pixel 99 has one first metal plate 351. The second metal plate 352 of each subpixel 99 is connected.

  The description of the structure of the display device 10 will be continued using FIGS. 4 to 9.

  The light emitting unit 17 will be described. The first transistor 371 controls the current supplied to the organic light emitting element 97. The current flows from the first electrode 18 toward the second electrode 19. That is, holes enter the inside of the organic light emitting layer 47 from the first electrode 18 side and electrons from the second electrode 19 side, respectively.

  Inside the organic light emitting layer 47, light is generated when excitons (excitons) generated by recombination of holes and electrons return to the ground state. That is, the organic light emitting layer 47 emits light by a current flowing between the first electrode 18 and the second electrode 19.

  The second insulating layer 46 will be described. The second insulating layer 46 has two roles of preventing the color mixture of the organic light emitting layer 47 and eliminating unnecessary light emitting regions. The role of preventing color mixing will be described. An organic light emitting layer 47 of one color is located in one opening 461 of the second insulating layer 46. The range in which the organic light emitting layer 47 is formed may be shifted due to an error of the manufacturing apparatus, but the deviation remains in the range covered by the non-opening portion 462, and the organic light emitting layer 47 extends to other adjacent opening portions 461. There is no covering. As described above, the non-opening 462 is located at the boundary between the colors, so that the second insulating layer 46 plays a role of preventing color mixing.

  The role of eliminating unnecessary light emitting areas will be described. In the portion where the second insulating layer 46 is interposed between the first electrode 18 and the organic light emitting layer 47, no current flows because the first electrode 18 and the organic light emitting layer 47 are insulated by the second insulating layer 46. Therefore, the organic light emitting layer 47 does not emit light. Therefore, the light emitting portion 17 that actually emits light in the organic light emitting layer 47 is a portion corresponding to the opening 461 in the organic light emitting layer 47. As described above, by preventing the organic light emitting layer 47 from emitting light in the non-opening portion 462, the second insulating layer 46 serves to eliminate unnecessary light emitting areas.

  As described above, the display device 10 includes the planar second insulating layer 46 including the opening 461 that emits the light emitted from the organic light emitting element 97 to the outside and the non-opening 462 that is not open.

  The formation of a capacitor by the metal plate layer 35 and the first electrode 18 will be described. The first metal plate 351 faces (opposes) the first electrode 18 with the first insulating layer 43 interposed therebetween. The first metal plate 351, the first insulating layer 43, and the first electrode 18 form a first capacitor 91 (see FIG. 3). The capacity of the first capacitor 91 is determined by the area where the first metal plate 351 and the first electrode 18 face each other, the thickness of the first insulating layer 43 and the dielectric constant.

  Similarly, the second metal plate 352, the first insulating layer 43, and the first electrode 18 form a second capacitor 92 (see FIG. 3). The capacity of the second capacitor 92 is determined by the area where the second metal plate 352 and the first electrode 18 face each other, the thickness of the first insulating layer 43 and the dielectric constant. The first capacitor 91 and the second capacitor 92 are connected in series via the first electrode 18. As described above, the first electrode 18 is connected to the source / drain 33 through the third conductive portion 67. The third conductive portion 67 is located below the non-opening portion 462.

  As described above, the first capacitor 91 is formed by the first electrode 18, the first insulating layer 43, and the first metal plate 351. A second capacitor 92 is formed by the first electrode 18, the first insulating layer 43, and the second metal plate 352. The first capacitor 91 and the second capacitor 92 are connected in series. A connection point between the first capacitor 91 and the second capacitor 92 is connected to the source electrode. The first electrode 18 is connected to the source electrode at a portion covered by the non-opening 462.

Ｉｏｌｅｄ（ＩＭＤ）は、有機発光素子９７のアノード電極とカソード電極との間に流れる駆動電流である。
βは、利得係数である。
Ｃ１は、第１容量９１の容量である。
Ｃ２は、第２容量９２の容量である。
Ｖｄａｔａは、有機発光素子９７を発光させる際の発光輝度を示すデータ電圧である。
Ｖｒｅｆは、参照電圧である。
μは、キャリア移動度である。
Ｃｏｘは、単位容量である。
Ｗは、駆動トランジスタ９８のチャンネル幅である。
Ｌは、駆動トランジスタ９８のチャンネル長である。 The operation of the first capacitor 91 and the second capacitor 92 will be described. When the organic light emitting element 97 emits light, a drive current Ioled (see FIG. 3) flows between the anode electrode and the cathode electrode of the organic light emitting element 97. The drive current Ioled is the same as the output current IMD that flows between the source electrode of the drive transistor 98 and the drain electrode of the drive transistor 98. The output current IMD will be described later. The drive current Ioled can be obtained using equation (1). Note that a method for deriving the formula (1) will be described in Embodiment 2.

Ioled (IMD) is a drive current that flows between the anode electrode and the cathode electrode of the organic light emitting device 97.
β is a gain coefficient.
C1 is the capacity of the first capacitor 91.
C2 is the capacity of the second capacitor 92.
Vdata is a data voltage indicating light emission luminance when the organic light emitting element 97 emits light.
Vref is a reference voltage.
μ is carrier mobility.
Cox is a unit capacity.
W is the channel width of the drive transistor 98.
L is the channel length of the drive transistor 98.

  From equation (1), the current Ioled flowing through the organic light emitting element 97 is not affected by the characteristics (for example, threshold voltage) of the driving transistor 98. It can be seen from the equation (1) that the variation in the drive current Ioled can be suppressed by reducing the variation in the capacitance C1 of the first capacitor 91 and the capacitance C2 of the second capacitor 92. By suppressing the variation in the drive current Ioled, the luminance unevenness of the display device 10 can be suppressed.

  Variations in the thickness and dielectric constant of the first insulating layer 43 in each subpixel 99 can be reduced by forming the first insulating layer 43 using, for example, CVD (Chemical Vapor Deposition). Further, the variation in the area of the first metal plate 351 and the variation in the area of the second metal plate 352 in each sub-pixel 99 are created simultaneously by the photolithography method using the first metal plate 351 and the second metal plate 352. Can be reduced. Details of the method for manufacturing the display device 10 according to the present embodiment will be described later.

  The capacitance C1 and the second capacitance of the first capacitor 91 of each subpixel 99 are reduced by reducing the variation in the area and ratio of the area of the first metal plate 351 and the second metal plate 352 in each subpixel 99. The variation in the capacitance C2 of 92 can be reduced. The reason will be described below.

  FIG. 10 is an explanatory diagram showing a method for forming the insulating film 74. The insulating film 74 is used as the first insulating layer 43, for example. The mounting table 71 is a table on which the substrate 72 is mounted. The substrate fixing unit 73 fixes the substrate 72 to the mounting table 71. The substrate 72 is also called a mother substrate 72, and the substrate fixing portion 73 is also called a substrate presser 73.

  Hereinafter, for example, the case where the insulating film 74 having a uniform thickness is formed on the flat substrate 72 will be described.

  The manufacturing apparatus supplies a gas source and deposits an insulating film 74 on one surface of the substrate 72. A symbol C in FIG. 10 indicates the center of the insulating film 74. Further, reference numerals E1 and E2 in FIG. 10 indicate ends of a range where the insulating film 74 is formed. The substrate 72 is a flat plate having a size that can be divided into a plurality of first substrates 11 by cutting. The insulating film 74 outside the first end E1 and the second end E2 is not used. In the following description, an insulating film 74 having a size corresponding to one first substrate 11 is referred to as a unit insulating film 75. This one 1st board | substrate 11 is one display panel mounted in the one display apparatus 10 (refer FIG. 1), for example. The unit insulating film on the second end E2 side is referred to as a unit insulating film 76.

  FIG. 11 is a graph for explaining unevenness of the thickness of the insulating film 74. Note that the graph of FIG. 11 is an example. The horizontal axis in FIG. 11 indicates the distance from the center C of the insulating film 74. The vertical axis in FIG. 11 indicates the thickness of the insulating film 74. A thin solid line indicates an ideal thickness of the insulating film 74. A thick curve indicates the thickness of the insulating film 74 actually produced.

  As shown by the thin solid line in FIG. 11, it is ideal that the insulating film 74 has the same thickness from the center C to the first end E1 and the second end E2. However, in practice, the insulating film 74 becomes thinner as it approaches the first end E1 and the second end E2 from the center C.

  Note that the graph shown in FIG. 11 is a conceptual diagram for explaining uneven thickness of the insulating film 74. The shape of the graph shown in FIG. 11 differs depending on the model and setting of the manufacturing apparatus. In general, the film thickness of the insulating film 74 may deviate from the ideal film thickness as the distance from the center C of the substrate 72 increases. That is, the film thickness of the insulating film 74 may be slightly different from the ideal film thickness.

  FIG. 12 is a plan view of the unit insulating film 75. FIG. 13 is a cross-sectional view of the unit insulating film 75. 12 and 13, the left side of the drawing shows the direction of the center C, and the right side of the drawing shows the direction of the second end E2.

  It is assumed that the unit insulating film 75 in the first region 751 has a film thickness d1. Further, the unit insulating film 75 in the second region 752 has a film thickness d2. A case where the film thickness d1 is an ideal film thickness of the unit insulating film 75 will be described as an example. For the sake of explanation, the first region 751 and the second region 752 are largely shown in FIG. The areas of the first region 751 and the second region 752 are the pixel areas of a large number of subpixels 99 (for example, 100 vertical pixels and 100 horizontal pixels). The unit insulating film 75 has a constant film thickness inside the first region 751 and inside the second region 752.

Ｃ１は、第１容量９１の容量である。
Ｃ２は、第２容量９２の容量である。
Ａ１は、第１金属板３５１の面積である。
Ａ２は、第２金属板３５２の面積である。
εは、単位絶縁膜７５の比誘電率である。
ｄ１は、第１領域７５１内の単位絶縁膜７５の膜厚である。 The case where the unit insulating film 75 is used for the first insulating layer 43 (see FIG. 4) will be described as an example. In the calculation formula (see formula (1)) of the drive current of one sub-pixel 99 in the first region 751, C2 / (C2 + C1) of this calculation formula can be expressed by formula (3).

C1 is the capacity of the first capacitor 91.
C2 is the capacity of the second capacitor 92.
A1 is the area of the first metal plate 351.
A <b> 2 is the area of the second metal plate 352.
ε is the relative dielectric constant of the unit insulating film 75.
d1 is the thickness of the unit insulating film 75 in the first region 751.

  As apparent from the equation (3), the film thickness d1 of the unit insulating film 75 in the first region 751 is canceled, and C2 / (C2 + C1) is equal to A2 / (A2 + A1).

ｄ２は、第２領域７５２内の単位絶縁膜７５の膜厚である。 On the other hand, in the calculation formula of the drive current of one subpixel 99 in the second region 752 (see formula (1)), C2 / (C2 + C1) of this calculation formula can be expressed by formula (4).

d2 is the thickness of the unit insulating film 75 in the second region 752.

  As apparent from the equation (4), the film thickness d2 of the unit insulating film 75 in the second region 752 is canceled, and C2 / (C2 + C1) is equal to A2 / (A2 + A1).

  As described above, in the second region 752, the thickness d2 of the unit insulating film 75 is different from the ideal thickness d1. However, the same relational expression as that of the first region 751 is established among the capacitor C1, the capacitor C2, the area A1, and the area A2.

  Therefore, by reducing the variation in the area A1 of the first metal plate 351 and the area A2 of the second metal plate 352 and the variation in the ratio of the areas, the variation in C2 / (C2 + C1) of each subpixel 99 can be reduced. it can.

  In other words, according to the present embodiment, equation (3) and equation (4) are the same, and the variation in film thickness can be canceled. Then, if the area A1 of the first metal plate 351 and the area A2 of the second metal plate 352 are accurately defined and the data voltage Vdata and the reference voltage Vref are the same, the driving in each subpixel 99 of the first region 751 is performed. The current and the drive current in each subpixel 99 in the second region 752 are substantially the same. As a result, variation in emission luminance can be suppressed. For example, when the emission luminance of each sub-pixel 99 in the first area 751 and the emission luminance of each sub-pixel 99 in the second area 752 are controlled to be the same, variation in the emission luminance can be further suppressed, resulting in uneven luminance. It becomes difficult.

A comparative example will be described. In the comparative example, a capacitor corresponding to the first capacitor 91 in FIG. 3 is a first capacitor X, and a capacitor corresponding to the second capacitor 92 in FIG. In the comparative example, it is assumed that the insulating layer of the first capacitor X and the insulating layer of the second capacitor Y are formed in different steps in different processes. In the comparative example, for example, the insulating layer of the first capacitor X is formed in a layer including a TFT such as a driving TFT, and the insulating layer of the second capacitor Y is formed in the OLED layer.
The case where the material of the insulating layer of the first capacitor X and the insulating layer of the second capacitor Y are the same and the dielectric constant ε is equal will be described as an example.

  The insulating layer of the first capacitor X has an ideal film thickness d1 in the first region 751 and a film thickness d2 different from d1 in the second region 752 as in FIG. An example in which the insulating layer of the second capacitor Y has an ideal film thickness d1 in the first region 751 but has a film thickness d2 'different from d1 in the second region 752 will be described. It is assumed that d2 and d2 'are different.

In the subpixel in the first region 751 of the comparative example, since the thicknesses of the insulating films forming the two capacitors are both d1, the relationship of Expression (3) is established. On the other hand, the capacitance C1 of the first capacitance X and the capacitance C2 of the second capacitance X of the sub-pixel in the second region 752 of the comparative example can be expressed by Expression (5).

  As described above, in the comparative example in which the insulating layer of the first capacitor X and the insulating layer of the second capacitor Y are formed in different steps, the value of C2 / (C2 + C1) of each subpixel is set in each subpixel 99. In order to control only by the area A1 of the first metal plate 351 and the area A2 of the second metal plate 352, d2 and d2 ′ are made the same, that is, the insulating layer of the first capacitor X and the second capacitor Y The difficulty of manufacturing the insulating layer with the same film thickness distribution must be overcome.

  In other words, if Equation (3) and Equation (5) are not the same, even if the data voltage Vdata and the reference voltage Vref are the same, the driving current in each subpixel of the first region 751 of the comparative example and the comparative example The drive current in each subpixel of the second region 752 is different. As a result, even if the emission luminance of each subpixel in the first region 751 of the comparative example and the emission luminance of each subpixel of the second region 752 of the comparative example are controlled to be the same, the emission luminance may vary.

  In the above description, the unit insulating film 75 has been described, but the same description applies to other unit insulating films (for example, the unit insulating film 76).

  In summary, in the present embodiment, the first capacitance of each subpixel 99 can be reduced by reducing the variation in the area and ratio of the area of the first metal plate 351 and the second metal plate 352 in each subpixel 99. The variation in the capacitance C1 of 91 and the capacitance C2 of the second capacitance 92 can be reduced. In other words, in this embodiment, even if a variation in the thickness of the insulating layer occurs, this variation in the thickness can be canceled. On the other hand, the same effect is not obtained in the comparative example.

  As described above, according to the configuration of the present embodiment, the variation of C2 / (C2 + C1) of each subpixel 99 can be reduced. Therefore, according to the configuration of the present embodiment, it is possible to provide the display device 10 with reduced luminance unevenness.

  The technical significance of this embodiment will be described.

  In order to suppress the luminance unevenness of the display device 10, it is necessary to accurately control the drive current Ioled of the organic light emitting element 97. As described above, the drive transistor 98 controls the drive current Ioled. However, the characteristics of the drive transistor 98 tend to vary. Therefore, for example, even when a plurality of subpixels 99 are illuminated with the same luminance, the drive current Ioled varies among the subpixels 99. Due to this variation, luminance unevenness occurs.

  Patent Document 1 proposes a pixel circuit including a plurality of capacitors in order to prevent luminance unevenness due to the characteristics of the driving transistor 98, in particular, threshold voltage variations. In this pixel circuit, when there are variations in capacitance values, the variations cause uneven brightness.

  When two capacitors are formed in different layers, it is necessary to manufacture a plurality of capacitors in different manufacturing processes.

  The accuracy of the capacitance when the two capacitors are formed in different layers will be described in more detail. A capacitor is a circuit component that includes three components: two conductor plates facing each other and an insulator disposed therebetween. Capacitance characteristics are determined by the area of the portion where the two conductive plates face each other, the thickness of the insulator, and the dielectric constant of the insulator.

  The description will be continued with reference to FIG. First, one capacitor formed in the layer where the TFT circuit is formed will be described. For example, it can be used for two conductor plates that face the gate 32 and the semiconductor portion 31. In this case, the third insulating layer 42 serves as an insulator. A capacitor formed by the anode electrode and the intermediate metal for forming the capacitor can be formed by the first metal plate 351, the first insulating layer 43, and the first electrode 18 as in the present embodiment.

  For example, the first capacitor insulator is the insulating layer X, and the second capacitor insulator is the insulating layer Y. For example, a phenomenon in which the insulating layer X is finished thicker and the insulating layer Y is finished thinner can occur due to variations in the manufacturing process. When such a phenomenon occurs, the first capacity becomes a smaller capacity and the second capacity becomes a larger capacity. Since the two capacitance changes work in opposite directions, the fluctuation of the drive current Ioled increases. As a result, luminance unevenness increases. In order to prevent such a phenomenon, it is necessary to set the accuracy of each manufacturing process to a high level.

  Further, as described using the comparative example, the expressions (3) and (5) are not equal. Therefore, if the film thickness d1 of the insulating film (insulator) in the first region 751 and the film thickness d2 of the insulating film in the second region 752 in the display panel are different, C2 / (C2 + C1) of each subpixel 99 is obtained. It is difficult to reduce variation.

  For this reason, when two capacitors are formed in different layers, it is difficult to suppress variations in these capacitors, and luminance unevenness still occurs.

  On the other hand, in the display device 10 of the present disclosure, as described using the expressions (1), (3), and (4), the film thickness d1 of the insulating film (insulator) 74 in the first region 751 and the first Even if the film thickness d2 of the insulating film 74 in the two regions 752 is different, the variation in the drive current Ioled flowing through the organic light emitting element 97 of each subpixel 99 can be reduced. As a result, the luminance unevenness of the display device 10 can be reduced.

  Further, in the display device 10, the insulating layer that forms the capacitor is not disposed in the second stacked body 62 in which the TFT circuit is formed. For this reason, the first insulating layer 43 can be used exclusively for the capacitor insulator, so that there is no need to consider the withstand voltage performance of the TFT. That is, for the first insulating layer 43, a layer having an optimal thickness and material for obtaining a desired capacity can be used.

Therefore, the first insulating layer 43 can be made thinner than the third insulating layer 42 of the TFT circuit. For example, the relationship between the capacitances of the first capacitor 91 and the second capacitor 92 and the parasitic capacitance of the TFT circuit can be expressed by equation (6).
C1, C2 >> parasitic capacitance (6)
C1 is the capacity of the first capacitor 91.
C2 is the capacity of the second capacitor 92.
The parasitic capacitance is, for example, the capacitance between the gate source or gate drain terminals of the drive transistor 98 or the switch transistor 96.

  By setting the capacitor C1 of the first capacitor 91 and the capacitor C2 of the second capacitor 92 so as to satisfy the formula (6), it is possible to suppress the luminance unevenness caused by the influence of the parasitic capacitance.

  Moreover, according to the display device 10 of the present disclosure, various effects described below can be obtained.

  If the first metal plate 351 is made too small, that is, if the capacitance C1 is made too small, the influence of the parasitic capacitance of the TFT circuit becomes significant. Furthermore, the GS (Gate-Source) voltage of the drive transistor 98 may decrease due to leakage current during the light emission period of the organic light emitting element 97. When the voltage between the GS of the driving transistor 98 decreases, the driving current Ioled decreases, and the luminance of the organic light emitting element 97 decreases. Accordingly, the first metal plate 351 needs to have a certain area or more.

  That is, by securing the necessary capacitance C1, it is possible to prevent a decrease in the voltage between the GS of the drive transistor 98 and to prevent a decrease in luminance of the organic light emitting element 97.

  Furthermore, it is desirable to make the second metal plate 352 as large as possible after securing the above-described area in the first metal plate 351. That is, it is desirable to make C2 as large as possible while securing the necessary capacity C1. By doing so, the voltage applied to the drive transistor 98 when data is input from the input line Vinput can be lowered. Therefore, loss of data voltage input from the input line Vinput can be suppressed.

  Further, by using the first electrode 18 of the organic light emitting element 97 as a terminal of the first capacitor 91 and the second capacitor 92, a dedicated wiring for connecting the first capacitor 91 and the second capacitor 92 in series is unnecessary. can do.

  Further, since no capacitor is arranged in the second stacked body 62 in which the TFT circuit is formed, the area of the TFT circuit can be reduced. Therefore, the high-definition display device 10 can be provided by downsizing the sub-pixel 99.

  FIG. 14 is a flowchart showing the flow of manufacturing the display panel. 15 to 33 are explanatory views showing the manufacturing process of the display panel. The outline of the manufacturing method of the display panel used for the display apparatus 10 of this Embodiment is demonstrated using FIGS. In addition, manufacturing of coating devices such as vapor deposition devices, sputtering devices, slit coaters, etc. used for manufacturing display panels, exposure devices, developing devices, etching devices, sealing devices, cutting devices, and transport devices that connect these devices. The device is not shown. These devices operate according to a predetermined program.

  In the following description, the schematic cross-sectional view will be described by taking one subpixel 99 as an example. The manufacturing apparatus of the display device 10 forms the pixel circuit and the drive circuit 20 using a semiconductor process on the front side of the first substrate 11 that is a light-transmitting substrate such as a glass substrate (step S501).

  An overview of the step S501 will be described. First, it demonstrates using FIG. FIG. 15 is a schematic cross-sectional view of the display device 10 during the manufacturing process. The manufacturing apparatus forms a gate 32 having a predetermined shape on one surface of the first substrate 11 by sputtering or photolithography.

  As shown in the cross-sectional view of FIG. 16, the manufacturing apparatus forms the third insulating layer 42 having a uniform thickness by a CVD method or the like.

  As shown in the cross-sectional view of FIG. 17, the manufacturing apparatus forms a semiconductor portion 31 having a predetermined shape by a sputtering method, a photolithography method, or the like.

  As shown in the cross-sectional view of FIG. 18, the manufacturing apparatus forms an etching stop portion 34 having a predetermined shape by a CVD method, a photolithography method, or the like.

  As shown in the cross-sectional view of FIG. 19, the manufacturing apparatus forms the first hole 651 reaching the gate 32 from the surface of the third insulating layer 42 by a dry etching method or the like.

  As shown in the cross-sectional view of FIG. 20, the manufacturing apparatus forms a source / drain 33 having a predetermined shape by sputtering, photolithography, or the like. As described above, the material of the source / drain 33 is a conductor. The conductor that is the material of the source / drain 33 also covers the inner surface of the first hole 651 and forms the first conductive portion 65 that connects the source / drain 33 and the gate 32.

  FIG. 21 is a schematic plan view of the display device 10 at the stage shown in FIG. FIG. 21 shows the same part as FIG. FIG. 21 also shows the second conductive portion 66 and the third conductive portion 67 that are created in the subsequent steps.

  The gate 32, the semiconductor part 31, the etching stop part 34, and the source / drain 33 are formed by the steps described with reference to FIGS. The gate 32 has an L-shaped part and a rectangular part. The rectangular portion is continuous with a belt-like portion extending in the left-right direction. The semiconductor portion 31 is a rectangle that is long in the left-right direction. The semiconductor part 31 overlaps the gate 32. The etching stop part 34 is also rectangular. The etching stop part 34 covers the central part of the semiconductor part 31 in the left-right direction. The source / drain 33 has a shape in which rectangular portions covering both ends of the semiconductor portion 31 in the left-right direction are connected by a band-shaped portion.

  As shown in the sectional view of FIG. 22, the manufacturing apparatus forms an inorganic insulating layer (not shown) having a uniform thickness by a CVD method or the like. The coating apparatus creates the planarization layer 45 by a slit coat method or the like (step S503).

  As shown in the sectional view of FIG. 23, the manufacturing apparatus creates a second hole 661 that penetrates from the surface of the planarization layer 45 to the source / drain 33 by a dry etching method or the like.

  As shown in the cross-sectional view of FIG. 24, the manufacturing apparatus forms a metal plate layer 35 having a predetermined shape by a sputtering method, a photolithography method, or the like (step S504). FIG. 25 is a schematic plan view of the display device 10 at the stage shown in FIG. FIG. 25 shows the same part as FIG. The metal plate layer 35 includes a first metal plate 351 and a second metal plate 352. As described above, the metal plate layer 35 is a conductor.

  The second hole 661 in FIG. 23 is filled with the same conductor as that of the metal plate layer 35 to form a second conductive portion 66 that connects the metal plate layer 35 and the source / drain 33. In the present embodiment, the manufacturing apparatus employs manufacturing conditions such that the upper surface of the second conductive portion 66 is flat.

  As shown in the cross-sectional view of FIG. 26, the manufacturing apparatus forms the first insulating layer 43 by a CVD method or the like (step S505). In the present embodiment, the manufacturing apparatus employs manufacturing conditions such that the upper surface of the first insulating layer 43 is flat, including the portion between the first metal plate 351 and the second metal plate 352.

  As shown in the cross-sectional view of FIG. 27, the manufacturing apparatus creates a third hole 671 that penetrates from the surface of the first insulating layer 43 to above the second conductive portion 66 on the right side by a dry etching method or the like.

  As shown in the cross-sectional view of FIG. 28, the manufacturing apparatus forms the first electrode 18 having a predetermined shape by a sputtering method, a photolithography method, or the like (step S506). FIG. 29 is a schematic plan view of the display device 10 at the stage shown in FIG. FIG. 29 shows the same part as FIG. The material of the first electrode 18 is a conductor.

  The inside of the third hole 671 in FIG. 27 is filled with a conductor. The conductor filling the inside of the third hole 671 is connected to the lower second conductive portion 66 to form the third conductive portion 67 that connects the first electrode 18 and the source / drain 33. In the present embodiment, the manufacturing apparatus employs manufacturing conditions such that the upper surface of the third conductive portion 67 is flat.

  The description will be continued using the flowcharts shown in FIG. 30, FIG. 31, and FIG. FIG. 30 is a schematic view of the display device 10 during the manufacturing process.

  As shown in the cross-sectional view of FIG. 30, the manufacturing apparatus forms the second insulating layer 46 having a predetermined shape by a CVD method, a dry etching method, or the like (step S507). FIG. 31 is a schematic plan view of the display device 10 at the stage shown in FIG. FIG. 31 shows the same part as FIG. As described above, the second insulating layer 46 includes the opening 461 and the non-opening 462. The opening 461 covers the central portion of the first electrode 18. The non-opening 462 covers the boundary between the sub-pixels 99 and the edge of the first electrode 18.

  As shown in the cross-sectional view of FIG. 32, the manufacturing apparatus forms the organic light emitting layer 47 by a vapor deposition method or a coating method (step S508). The organic light emitting layer 47 covers the opening 461.

  As shown in the cross-sectional view of FIG. 33, the manufacturing apparatus forms the second electrode 19 by vapor deposition or sputtering (step S509).

  As described above, the manufacturing apparatus arranges the transistor 37 having the source electrode, the drain electrode, and the gate electrode on one surface of the first substrate 11. In the manufacturing apparatus, the third insulating layer 42 that covers the transistor 37 is disposed above the transistor 37. The manufacturing apparatus converts the first metal plate 351 connected to the gate electrode through the first conductive portion 65 penetrating the third insulating layer 42 and the second metal plate 352 insulated from the first metal plate 351 into the third metal plate 351. The insulating layer 42 is disposed on the same layer above the insulating layer 42. The manufacturing apparatus arranges the first insulating layer 43 above the layers of the first metal plate 351 and the second metal plate 352. The manufacturing apparatus arranges the first electrode 18 connected to the source electrode via the second conductive portion 66 penetrating the first insulating layer 43 and the third insulating layer 42 above the first insulating layer 43. The manufacturing apparatus arranges the organic light emitting layer 47 on the upper side of the first electrode 18. The manufacturing apparatus arranges the second electrode 19 on the upper side of the organic light emitting layer 47.

  FIG. 34 is a hardware configuration diagram of the display device 10. The display device 10 includes an FPC 14, a driver IC 13, and a display substrate 16. The display substrate 16 includes a drive circuit 20 and an image display unit 15. The drive circuit 20 includes, for example, a scan driver 21, a data voltage driver 22, an emission control driver 23, and a protection circuit 24.

  The driver IC 13 processes the image signal acquired via the FPC 14 and outputs it to the drive circuit 20 of the display substrate 16. The drive circuit 20 controls the image display unit 15.

  The emission control driver 23 and the scanning driver 21 control the luminance of the organic light emitting element 97 (see FIG. 3) of each subpixel 99. The image display unit 15 displays an image by this control.

  A voltage corresponding to the image signal is input from the data voltage driver 22 to the input line Vinput. When the scanning driver 21 selects a scanning line, that is, when the switch transistor 96 is in a conductive state, a voltage corresponding to a voltage input from the input line Vinput is a gate electrode of the driving transistor 98 via the switch transistor 96. To join.

  An output current IMD flows between the source electrode and the drain electrode of the drive transistor 98 in accordance with the voltage Vgs between the gate electrode and the source electrode of the drive transistor 98. A drive current Ioled equal to the output current IMD flows between the anode electrode and the cathode electrode of the organic light emitting element 97. The organic light emitting element 97 emits light with a luminance corresponding to the drive current Ioled. That is, the organic light emitting element 97 emits light with luminance according to the image signal.

  Note that the pixel circuit illustrated in FIG. 3 is an example. The pixel circuit may have a configuration in which a larger number of TFTs and capacitors are combined. For example, the pixel circuit may include a second switch transistor between the anode electrode of the organic light emitting element 97 and the control signal line. Further, the pixel circuit may include a third switch transistor between the drive transistor 98 and the high power supply line ELVDD. The operation of the first capacitor 91 and the second capacitor 92 will be described using the second embodiment.

  The shapes of the semiconductor portion 31, the gate 32, the source / drain 33, the first metal plate 351, the second metal plate 352, the first electrode 18 and the like described above are exemplifications and are simplified schematic diagrams for explanation. It is. Moreover, the manufacturing apparatus used in the manufacturing process and each process is also an example.

  In the present embodiment, the structure, operation, and manufacturing method have been described by taking the display device 10 using a top emission type OLED panel that emits light to the surface on the second substrate 12 side as an example. A bottom-emission type OLED panel that emits light toward the first substrate 11 may be used for the display device 10.

  In this embodiment, the case where the transistor 37 is an oxide TFT bottom-gate TFT has been described as an example. The transistor 37 may be a TFT using amorphous silicon or polysilicon. The transistor 37 may be a top gate type TFT.

  In the present embodiment, the case where the driving transistor 98 is an N-type transistor has been described as an example. In this case, the first electrode 18 is an anode electrode of the organic light emitting element 97. The second electrode 19 is a cathode electrode of the organic light emitting element 97. As described above, the drive transistor 98 is an N-type transistor, the first electrode 18 is an anode electrode, and the second electrode 19 is a cathode electrode.

[Embodiment 2]
The present embodiment relates to the display device 10 in which the fixed potential line VFIX (see FIG. 3) connected to the second capacitor 92 is shared with the low power supply line ELVSS. Description of portions common to the first embodiment is omitted.

  FIG. 35 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element 97 of the second embodiment to emit light. The circuit shown in FIG. 35 is a part of a pixel circuit included in the subpixel 99. In FIG. 35, the switch transistor 96 (see FIG. 3) is omitted.

  The circuit shown in FIG. 35 includes an organic light emitting element 97, a first capacitor 91, a second capacitor 92, and a drive transistor 98. A high power supply line ELVDD, a low power supply line ELVSS, and an input line Vinput are connected to the circuit shown in FIG. The input line Vinput is connected to the data voltage driver 22. The voltage of the input line Vinput alternately changes between the reference voltage Vref and the data voltage Vdata which is a voltage indicating the light emission luminance when the organic light emitting element 97 emits light.

  The input line Vinput is connected to the gate electrode of the driving transistor 98 and the first terminal of the first capacitor 91. The high power line ELVDD is connected to the drain electrode of the drive transistor 98. The low power line ELVSS is connected to the cathode electrode of the organic light emitting element 97 and the first terminal of the second capacitor 92. The low power line ELVSS is an example of a first voltage wiring. The source electrode of the driving transistor 98 is connected to the second terminal of the first capacitor 91, the second terminal of the second capacitor 92, and the anode electrode of the organic light emitting element 97.

  The organic light emitting element 97 emits light based on a signal input from the input line Vinput.

  According to this embodiment, since the fixed potential line VFIX and the low power supply line ELVSS can be made common, the display device 10 in which the layout of the pixel circuit is easy can be provided.

  In the present embodiment, the second capacitor 92 can be formed by the first electrode 18, the first insulating layer 43, and the second metal plate 352. In this case, the second metal plate 352 is connected to the low power line ELVSS. Therefore, the second metal plate 352 is connected to the cathode electrode of the organic light emitting element 97. The second electrode 19 is a cathode electrode of the organic light emitting element 97, for example. As described above, the second metal plate 352 is connected to the second electrode 19.

  FIG. 36 is a time chart showing the input voltage Vinput according to the second embodiment. The horizontal axis in FIG. 36 is time. The vertical axis in FIG. 36 is the voltage of the input voltage Vinput. In the threshold compensation period T1, the input voltage Vinput is the reference voltage Vref. In the data voltage writing period T2, the input voltage Vinput is the data voltage Vdata. The data voltage Vdata is a voltage indicating the light emission luminance of the organic light emitting element 97.

  The operation of the subpixel 99 and the method for deriving the equation (1) will be described with reference to FIGS. 35 and 36.

  In the following description, a portion where the gate electrode of the driving transistor 98, the first terminal of the first capacitor 91, and the input line Vinput are connected is referred to as a point G. Further, a portion where the source electrode of the driving transistor 98, the space between the first capacitor 91 and the second capacitor 92, and the anode electrode of the organic light emitting element 97 are connected is described as an S point. Further, the potential at the S point is described as VS, and the potential at the G point is described as VG.

The threshold compensation period T1 will be described. In the threshold compensation period T1, the reference voltage Vref is input to Vinput. A current flows from the high power supply line ELVDD to the S point via the drive transistor 98. The potential and charge at the point S converge while satisfying the expressions (7) to (9).
VG = Vref (7)
VS = VG-Vth
= Vref-Vth (8)
Q1 = (VS−VG) × C1 + (VS−ELVSS) × C2
= −Vth × C1 + (Vref−Vth−ELVSS) × C2 (9)
VG is the potential at point G.
Vref is a reference voltage.
VS is the potential at point S.
Vth is a threshold voltage of the driving transistor 98.
Q1 is the charge at point S at the time of convergence.
C1 is the capacity of the first capacitor 91.
C2 is the capacity of the second capacitor 92.
ELVSS is the potential of the cathode electrode of the organic light emitting device 97.

  The data voltage writing period T2 will be described. In the data voltage writing period, the data voltage Vdata is input to Vinput. That is, VG = Vdata. VS becomes a potential obtained by distributing (Vdata-ELVSS) by the first capacitor 91 and the second capacitor 92 connected in series.

The charge at point S is in a state satisfying equation (10). Note that the same symbols as those in the above-described formula represent the same meaning, and thus the description thereof is omitted.
Q2 = (VS−VG) × C1 + (VS−ELVSS) × C2
= (VS-Vdata) * C1 + (VS-ELVSS) * C2 (10)
Q2 is the charge at point S during the data voltage writing period T2.
Vdata is a data voltage input from the input line Vinput during the data voltage writing period T2.

Due to the charge conservation law, the charge at point S does not change during the threshold compensation period T1 and the data voltage writing period T2. That is, Q1 = Q2 is established. From Expression (9) and Expression (10), Expression (11) is established.
−Vth × C1 + (Vref−Vth−ELVSS) × C2
= (VS-Vdata) * C1 + (VS-ELVSS) * C2 (11)

Therefore, Expression (12) and Expression (13) are established.
VS = C1 / (C1 + C2) × Vdata + C2 / (C1 + C2) × Vref−Vth
(12) VGS = VG-VS
= C2 / (C1 + C2) × (Vdata−Vref) + Vth (13)
VGS is a potential difference between the G point and the S point. That is, the GS potential of the drive transistor 98.

  The light emission period T3 will be described. In the light emission period T3, the GS potential VGS of the drive transistor 98 maintains the state shown by the equation (13) by the function of the first capacitor 91 holding the charge. VGS is a potential corresponding to the luminance of the organic light emitting element 97. That is, the first capacitor 91 holds at least a charge corresponding to the luminance of the organic light emitting element 97.

An output current IMD flowing between the source electrode and the drain electrode of the drive transistor 98 flows to the organic light emitting element 97 as it is. At this time, the driving transistor 98 operates in a saturation region. Here, since the output current IMD and the drive current Ioled of the organic light emitting element 97 are the same, Expression (14) is established.

  Thus, the above-described formula (1) is established.

[Embodiment 3]
The present embodiment relates to a display device 10 in which the fixed potential line VFIX (see FIG. 3) connected to the second capacitor 92 is shared with the high power supply line ELVDD. A description of portions common to the second embodiment will be omitted.

  FIG. 37 is an equivalent circuit diagram showing a circuit for causing one organic light-emitting element 97 of Embodiment 3 to emit light. The circuit shown in FIG. 37 is a part of a pixel circuit included in the sub-pixel 99.

  The circuit shown in FIG. 37 includes an organic light emitting element 97, a first capacitor 91, a second capacitor 92, and a drive transistor 98. A high power supply line ELVDD, a low power supply line ELVSS, and an input line Vinput are connected to the circuit shown in FIG. The input line Vinput is connected to the data voltage driver 22. The voltage of the input line Vinput alternately changes between the reference voltage Vref and the data voltage Vdata which is a voltage indicating the light emission luminance when the organic light emitting element 97 emits light.

  The input line Vinput is connected to the gate electrode of the driving transistor 98 and the first terminal of the first capacitor 91. The high power supply line ELVDD is connected to the drain electrode of the drive transistor 98 and the first terminal of the second capacitor 92. The low power line ELVSS is connected to the cathode electrode of the organic light emitting element 97. The low power line ELVSS is an example of a first voltage wiring. The source electrode of the driving transistor 98 is connected to the second terminal of the first capacitor 91, the second terminal of the second capacitor 92, and the anode electrode of the organic light emitting element 97.

  The organic light emitting element 97 emits light based on a signal input from the input line Vinput.

  Also in the present embodiment, the second capacitor 92 is formed by the first electrode 18, the first insulating layer 43, and the second metal plate 352. The second metal plate 352 is connected to the high power line ELVDD. The high power line ELVDD is connected to the drain electrode of the drive transistor 98. As described above, the second metal plate 352 is connected to the drain electrode of the drive transistor 98.

  According to the present embodiment, since the fixed potential line VFIX and the high power supply line ELVDD can be made common, the display device 10 in which the layout of the pixel circuit is easy can be provided.

[Embodiment 4]
The present embodiment relates to a display device 10 using a P-type transistor as a drive transistor 98. A description of portions common to the second embodiment will be omitted.

  FIG. 38 is an equivalent circuit diagram showing a circuit for causing one organic light-emitting element 97 of Embodiment 4 to emit light. The circuit shown in FIG. 38 is a part of a pixel circuit included in the subpixel 99.

  The circuit shown in FIG. 38 includes an organic light emitting element 97, a first capacitor 91, a second capacitor 92, and a drive transistor 98. A high power supply line ELVDD, a low power supply line ELVSS, and an input line Vinput are connected to the circuit shown in FIG. The input line Vinput is connected to the data voltage driver 22. The voltage of the input line Vinput alternately changes between the reference voltage Vref and the data voltage Vdata which is a voltage indicating the light emission luminance when the organic light emitting element 97 emits light.

  The input line Vinput is connected to the gate electrode of the driving transistor 98 and the first terminal of the first capacitor 91. The high power supply line ELVDD is connected to the anode electrode of the organic light emitting element 97 and the first terminal of the second capacitor 92. The low power line ELVSS is connected to the drain electrode of the drive transistor 98. The source electrode of the drive transistor 98 is connected to the second terminal of the first capacitor 91, the second terminal of the second capacitor 92, and the cathode electrode of the organic light emitting element 97. Based on a signal input from the input line Vinput, the organic light emitting element 97 emits light.

  According to the present embodiment, it is possible to provide the display device 10 using a P-type semiconductor for the pixel circuit.

  As described above, the drive transistor 98 of the present embodiment is a P-type transistor. In this case, the first electrode 18 is a cathode electrode of the organic light emitting element 97. The second electrode 19 is an anode electrode of the organic light emitting element 97.

[Embodiment 5]
In a certain layer (hereinafter referred to as layer A), when there is a dent, gap or hole, if another layer (hereinafter referred to as layer B) is formed on layer A, this dent, gap or hole Along with this, a layer B is formed.

  For example, there is a gap between the first metal plate 351 and the second metal plate 352 (see FIG. 4, FIG. 24, etc.). If a layer is further formed on the gap portion, this layer may be formed along the gap. In the case of the above example, the first insulating layer 43 and a part of the first electrode 18 located above the gap may be recessed. The flatness of the first electrode 18 is lost due to the depression of the first electrode 18. If the organic light emitting layer 47 is formed in the portion where the flatness is lost, and this portion is used as the opening 461 (also referred to as a light emitting region), the image quality may deteriorate. Therefore, in the present embodiment, a configuration in which the dent portion is covered with the non-opening portion 462 will be described. Note that description of portions common to the first embodiment is omitted.

  FIG. 39 is a schematic cross-sectional view of the display device 10 according to the fifth embodiment. FIG. 39 is an enlarged view of a portion corresponding to one organic light emitting element 97. In FIG. 39, the second substrate 12, the space 27, and the second electrode 19 are not shown. In FIG. 39, the first insulating layer 43 and a part of the first electrode 18 located in the upper layer of the gap portion between the first metal plate 351 and the second metal plate 352 are recessed.

Due to such a dent, the flatness of the first electrode 18 is lost. If a portion where flatness is lost is used as a light emitting region, the image quality may deteriorate. Therefore, in this embodiment, such a dent is not used as a light emitting region.
Specifically, the opening 461 of the second insulating layer 46 is located only above the second metal plate 352. That is, the upper side of the first metal plate 351 is located below the non-opening 462 of the second insulating layer 46. The first metal plate 351 is connected to the source / drain 33 by the second conductive portion 66 located below the non-opening portion 462. The source / drain 33 is connected to the gate 32 via the first conductive portion 65.

  Therefore, the first metal plate 351 is connected to the gate electrode via the second conductive portion 66, the source / drain 33 and the first conductive portion 65. As described above, the first metal plate 351 is connected to the gate electrode at the portion covered by the non-opening 462.

  In the second conductive portion 66 and the third conductive portion 67, the material of the first insulating layer 43, the material of the first electrode 18, and the material of the second insulating layer 46 overlap each other inside the material of the metal plate layer 35. . This is because, as described above, when there is any dent or the like, the upper layer is formed along the dent or the like.

  FIG. 40 is a schematic plan view of the pixel 90 of the fifth embodiment. FIG. 40 shows the same range as FIG. The light emitting unit 17 is located above the subpixel 99.

  FIG. 41 is a schematic plan view of the second insulating layer 46 of the fifth embodiment. The second insulating layer 46 includes an opening 461 and a non-opening 462. The opening 461 is rectangular. The opening 461 of the present embodiment is a half portion on the upper side of the opening 461 (see FIG. 6) of the first embodiment. As described above, the positions and shapes of the opening 461 and the light emitting unit 17 are the same.

  As described above, in the display device 10 according to the present embodiment, the entire region of the opening 461 faces the second metal plate 352 with the first electrode 18 interposed therebetween.

  In the present embodiment, the entire light emitting unit 17 is located above the second metal plate 352. That is, there is no gap between the first metal plate 351 and the second metal plate 352 below the light emitting unit 17. Further, the second conductive portion 66 is not positioned below the light emitting portion 17. Therefore, each layer, such as the 1st electrode 18 of the light emission part 17, and the organic light emitting layer 47, maintains a flat state.

  As described above, the display device 10 includes the planar second insulating layer 46 including the opening 461 that emits the light emitted from the organic light emitting element 97 to the outside and the non-opening 462 that is not open. The second insulating layer 46 is disposed in a layer different from the layer in which the first metal plate 351 and the second metal plate 352 are disposed. The non-opening 462 covers the interval between the first metal plate 351 and the second metal plate 352.

  According to the present embodiment, it is possible to provide the display device 10 in which the luminance of the light emitting unit 17 in one organic light emitting element 97 is uniform. Thereby, the display apparatus 10 which suppressed the brightness nonuniformity can be provided.

  In the present embodiment, since the first insulating layer 43 in the light emitting unit 17 is flat, an effect of preventing the occurrence of a short circuit between the first electrode 18 and the second electrode 19 can also be realized.

  The manufacturing flow of the display device 10 of the present embodiment is the same as the manufacturing flow of the display device 10 of the first embodiment described with reference to FIG. 42 to 48 are explanatory views showing manufacturing steps of the display panel of the fifth embodiment. The outline of the manufacturing method of the display panel used for the display apparatus 10 of this Embodiment is demonstrated using FIG. 14 and FIG. 48-FIG.

  Steps up to step S503 are the same as those in the first embodiment, and thus description thereof is omitted.

  As shown in the cross-sectional view of FIG. 42, the manufacturing apparatus forms a metal plate layer 35 having a predetermined shape by sputtering, photolithography, or the like (step S504). The metal plate layer 35 includes a first metal plate 351 and a second metal plate 352. As described above, the metal plate layer 35 is a conductor.

  In the present embodiment, as described above, when there is a dent or the like, the case where a layer is formed along the dent or the like is illustrated. Therefore, a conductor layer is formed on the inner surface of the second hole 661. The conductor layer forms a second conductive portion 66 that connects the metal plate layer 35 and the source / drain 33. A hole remains in the central portion of the second conductive portion 66.

  As shown in the cross-sectional view of FIG. 43, the manufacturing apparatus forms the first insulating layer 43 by a CVD method or the like (step S505).

  In the present embodiment, a conductor layer is formed on the inner surface of the hole at the center of the second conductive portion 66. A hole shallower than the hole shown in FIG. 43 remains in the center of the second conductive portion 66. Further, the first insulating layer 43 has a groove-like dent between the first metal plate 351 and the second metal plate 352.

  As shown in the cross-sectional view of FIG. 44, the manufacturing apparatus creates a third hole 671 that penetrates from the surface of the first insulating layer 43 to above the right second conductive portion 66 by a dry etching method or the like. The conductor which is the material of the metal plate layer 35 is exposed on the inner surface of the third hole 671.

  As shown in the cross-sectional view of FIG. 45, the manufacturing apparatus forms the first electrode 18 having a predetermined shape by sputtering, photolithography, or the like (step S506).

  In the present embodiment, a conductor layer is formed on the inner surface of the central hole of the third hole 671. The conductor layer is connected to the lower second conductive portion 66 to form a third conductive portion 67 that connects the first electrode 18 and the source / drain 33.

  As shown in the cross-sectional view of FIG. 46, the manufacturing apparatus forms the second insulating layer 46 having a predetermined shape by a CVD method, a dry etching method, or the like (step S507). 47 is a schematic plan view of the display device 10 at the stage shown in FIG. 47 shows the same part as FIG. As described above, the second insulating layer 46 includes the opening 461 and the non-opening 462. The opening 461 covers the central portion of the upper half of the first electrode 18. The non-opening 462 covers the boundary between the sub-pixels 99, the lower half of the first electrode 18, and the edge of the first electrode 18.

  As shown in the cross-sectional view of FIG. 48, the manufacturing apparatus forms the organic light emitting layer 47 by a vapor deposition method or the like (step S508). The organic light emitting layer 47 covers the opening 461.

  Since step S509 and subsequent steps are the same as the manufacturing flow described in the first embodiment, description thereof is omitted.

  As described above, in the present embodiment, the case where the layer having the recessed upper surface is formed on the recessed portion is described as an example. According to the present embodiment, it is possible to suppress deterioration in image quality even in such a case.

[Embodiment 6]
The present embodiment relates to the display device 10 in which the entire region of the opening 461 faces the first metal plate 351. A description of portions common to the fifth embodiment is omitted.

  FIG. 49 is a schematic cross-sectional view of the display device 10 according to the sixth embodiment. FIG. 49 shows an enlarged view of a portion corresponding to one organic light emitting element 97. In FIG. 49, the second substrate 12, the space 27, and the second electrode 19 are not shown.

  The opening 461 of the second insulating layer 46 is located only above the first metal plate 351. That is, the upper side of the second metal plate 352 is located below the non-opening 462 of the second insulating layer 46.

  FIG. 50 is a schematic plan view of the pixel 90 according to the sixth embodiment. FIG. 50 shows the same range as FIG. The light emitting unit 17 is located below the subpixel 99.

As described above, in the display device 10 according to the present embodiment, the entire region of the opening 461 faces the first metal plate 351 with the first electrode 18 interposed therebetween.

  In the present embodiment, the entire light emitting unit 17 is located above the first metal plate 351. That is, there is no gap between the first metal plate 351 and the second metal plate 352 below the light emitting unit 17. Further, the second conductive portion 66 is not positioned below the light emitting portion 17. Therefore, each layer, such as the 1st electrode 18 of the light emission part 17, and the organic light emitting layer 47, maintains a flat state.

  According to the present embodiment, it is possible to provide the display device 10 in which the luminance of the light emitting unit 17 in one organic light emitting element 97 is uniform. Thereby, the display apparatus 10 which suppressed the brightness nonuniformity can be provided.

  In the present embodiment, since the first insulating layer 43 in the light emitting unit 17 is flat, an effect of preventing the occurrence of a short circuit between the first electrode 18 and the second electrode 19 can also be realized.

[Embodiment 7]
The present embodiment relates to the display device 10 in which the opening 461 has a region facing the first metal plate 351 and a region facing the second metal plate 352. A description of portions common to the fifth embodiment is omitted.

  FIG. 51 is a schematic cross-sectional view of the display device 10 according to the seventh embodiment. FIG. 51 shows an enlarged view of a portion corresponding to one organic light emitting element 97. In FIG. 49, the second substrate 12, the space 27, and the second electrode 19 are not shown.

  The opening 461 of the second insulating layer 46 has a first opening 4611 and a second opening 4612. The first opening 4611 is located only above the first metal plate 351. The second opening 4612 is located only above the second metal plate 352. The organic light emitting layer 47 covers both the first opening 4611 and the second opening 4612.

  FIG. 52 is a schematic plan view of the pixel 90 of the seventh embodiment. FIG. 52 shows the same range as FIG. One sub-pixel 99 has one first light emitting unit 171 and one second light emitting unit 172. The first light emitting unit 171 is located above the subpixel 99. The second light emitting unit 172 is located below the subpixel 99.

  The first opening 4611 is an example of a first region of the opening 461 in this embodiment. The second opening 4612 is an example of a second region of the opening 461 in this embodiment. The first opening 4611 and the second opening 4612 do not overlap each other.

  As described above, the opening 461 in this embodiment has the first region and the second region that do not overlap with each other. In the display device 10 of the present embodiment, the first region faces the first metal plate 351 with the first electrode 18 interposed therebetween, and the second region has the second electrode sandwiched with the first electrode 18. Facing the metal plate 352.

  In the present embodiment, the entire light emitting unit 17 is located above the first metal plate 351 or the second metal plate 352. That is, there is no gap between the first metal plate 351 and the second metal plate 352 below the light emitting unit 17. Further, the second conductive portion 66 is not positioned below the light emitting portion 17. Therefore, each layer, such as the 1st electrode 18 of the light emission part 17, and the organic light emitting layer 47, maintains a flat state.

  In addition, the area of the light emitting unit 17 according to the present embodiment occupies a larger ratio with respect to the area of the sub-pixel 99 than the light emitting unit 17 according to the fifth and sixth embodiments. Accordingly, it is possible to realize the sub-pixel 99 having high emission luminance.

  According to the present embodiment, it is possible to provide the display device 10 in which the luminance of the light emitting unit 17 in one organic light emitting element 97 is uniform and the light emission luminance is high. Accordingly, it is possible to provide the display device 10 that displays a bright image with little luminance unevenness.

  In the present embodiment, since the first insulating layer 43 in the light emitting unit 17 is flat, an effect of preventing the occurrence of a short circuit between the first electrode 18 and the second electrode 19 can also be realized.

[Embodiment 8]
The present embodiment relates to the display device 10 in which the second conductive portion 66 is disposed outside the first electrode 18. Description of portions common to the first embodiment is omitted. FIG. 53 is a schematic cross-sectional view of the display device 10 according to the eighth embodiment. FIG. 54 is a schematic cross-sectional view of a display device 10 of a comparative example of the eighth embodiment. 53 and 54 are enlarged views showing the vicinity of the metal plate layer 35 of one organic light emitting element 97. FIG.

  In the comparative example shown in FIG. 54, the first electrode 18 extends above the second conductive portion 66. Inside the second conductive portion 66 of the comparative example, the distance between the metal plate layer 35 and the first electrode 18, that is, the thickness t of the first insulating layer 43 is the original thickness T of the first insulating layer 43. It is thinner than.

  On the other hand, in the present embodiment, as shown in FIG. 53, the second conductive portion 66 is provided outside the first electrode 18. That is, the first electrode 18 does not cover the upper side of the second conductive portion 66. By doing in this way, it can prevent that the metal plate layer 35 and the 1st electrode 18 short-circuit.

  Here, the second conductive portion 66 connects the metal plate layer 35 and the source / drain 33 (see FIG. 4). The second conductive portion 66 shown on the left side of FIG. 53 is connected to a source electrode that is a part of the source / drain 33, for example.

  As described above, the first metal plate 351 is connected to the source electrode at a portion not covered by the first electrode 18.

[Embodiment 9]
The present embodiment relates to a display device 10 that uses five transistors and shares a fixed potential line VFIX (see FIG. 3) connected to a second capacitor 92 with a low power supply line ELVSS. Description of portions common to the first embodiment is omitted.

  FIG. 55 is an equivalent circuit diagram showing a circuit for causing one organic light emitting element of Embodiment 9 to emit light. The circuit shown in FIG. 55 is a part of a pixel circuit included in the subpixel 99.

  The circuit shown in FIG. 55 includes an organic light emitting element 97, a first capacitor 91, a second capacitor 92, switch transistors 96a, 96b, 96c, and 96d, and a drive transistor 98. The circuit shown in FIG. 55 is connected to a high power supply line ELVDD, a low power supply line ELVSS, an input line Vinput, an initialization power supply line Vini, and a setting power supply line V1. Note that the drive transistor 98a and the switch transistors 96a, 96b, 96c, and 96d of the present embodiment are N-type TFTs.

  The initialization power line Vini is connected to the drain electrode of the switch transistor 96a. The switch line S11 is connected to the gate electrode of the switch transistor 96a. The voltage of Vini (an example of the second voltage) is lower than the sum of the voltage Vth-oled (threshold voltage of the organic light emitting element 97) corresponding to the light emission threshold of the organic light emitting element 97 and ELVSS (that is, Vini− ELVSS <Vth-oled). Thereby, unnecessary light emission of the organic light emitting element 97 can be prevented in the initialization period.

  The input line Vinput is connected to the data voltage driver 22. The input line Vinput is connected to the drain electrode of the switch transistor 96b. The switch line S12 is connected to the gate electrode of the switch transistor 96b. The voltage of the input line Vinput alternately changes between a reference voltage Vref, which is an example of a third voltage, and a data voltage Vdata, which is a voltage indicating light emission luminance when the organic light emitting element 97 emits light. Here, Vref is a voltage having a value larger than the sum of Vth (threshold voltage of the driving transistor 98) and Vini (that is, Vref> Vth + Vini). This is because the driving transistor 98 is turned on to advance to the Vth compensation period T1.

  The high power supply line ELVDD is connected to the drain electrode of the switch transistor 96d. The gate electrode of the switch transistor 96d is connected to the switch line EM. The switch line EM is connected to the emission control driver 23. A signal is input from the emission control driver 23 to the gate electrode of the switch transistor 96d via the switch line EM. The light emission time of the organic light emitting element 97 is controlled by this signal. The drain electrode of the drive transistor 98 is connected to the source electrode of the switch transistor 96c and the source electrode of the switch transistor 96d.

  The setting power supply line V1 is connected to the drain electrode of the switch transistor 96c. The gate electrode of the switch transistor 96c is connected to the switch line S3. The voltage V1 (an example of the fourth voltage) is a voltage equal to or higher than the voltage obtained by subtracting Vth (the threshold voltage of the driving transistor 98) from Vref (that is, V1 ≧ Vref−Vth).

  The low power line ELVSS is connected to the cathode electrode of the organic light emitting element 97 and the first terminal of the second capacitor 92.

  The source electrode of the switch transistor 96 b is connected to the first terminal of the first capacitor 91 and the gate electrode of the drive transistor 98. The first terminal of the first capacitor 91 is connected to the gate electrode of the drive transistor 98. The source electrode of the drive transistor 98 is connected to the second terminal of the first capacitor 91, the second terminal of the second capacitor 92, the source electrode of the switching transistor 96 a, and the anode electrode of the organic light emitting element 97.

  The organic light emitting element 97 emits light based on signals input from the switch lines S1, S2, S3, EM and the input line Vinput.

  Details of the operations of the switch transistors 96a, 96b, 96c, 96d and the drive transistor 98 will be described. Here, in the following description, a portion where the gate electrode of the drive transistor 98, the first terminal of the first capacitor 91, and the source electrode of the switch transistor 96b are connected is described as a point G. Further, a portion where the source electrode of the driving transistor 98, the first capacitor 91 and the second capacitor 92, the anode electrode of the organic light emitting element 97, and the source electrode of the switch transistor 96a are connected is described as an S point. Further, a portion where the drain electrode of the drive transistor 98, the source electrode of the switch transistor 96c, and the source electrode of the switch transistor 96d are connected is described as a point D. The potential at point S is denoted as VS, the potential at point G as VG, and the potential at point D as VD.

  FIG. 56 is a time chart relating to driving of the circuit of the ninth embodiment. FIG. 57 is a graph showing changes in VD and VS in the circuit of the ninth embodiment. In the present embodiment, in the light emission operation of the organic light emitting element 97, the initialization period T0, the threshold voltage Vth compensation period T1, the data writing period T2, and the light emission period T3 elapse in order.

  As shown in FIG. 56, in the initialization period T0, the signals input to the switch lines S11 and S12 are at the high level, the signals input to the switch lines S13 and EM are at the low level, and the Vinput voltage is Vref. . In the initialization period T0, the switch transistors 96a and 96b are turned on, and the switch transistors 96c and 96d and the drive transistor 98 are turned off. At this time, VG = Vref. As shown in FIG. 57, VS = Vini and VD = VS. Further, as described above, since Vini-ELVSS <Vth-oled, leakage light emission of the organic light emitting element 97 is prevented. In the initialization period T0, the potentials of the gate electrode and the source electrode of the drive transistor 98 are initialized.

  In the Vth compensation period T1, the signals input to the switch lines S12 and S13 are at a high level, the signals input to the switch lines S11 and EM are at a low level, and the Vinput voltage is Vref. In the Vth compensation period T1, the switch transistors 96b and 96c and the drive transistor 98 are turned on, and the switch transistors 96a and 96d are turned off. When the driving transistor 98 is turned on and becomes conductive, the potential at the point S rises, and the potential difference between the point G and the point S converges at the threshold value Vth. Therefore, VG = Vref, and VS = Vref−Vth as shown in FIG. Further, VD = V1.

  In the data writing period T2, the signal input to the switch line S12 is at a high level, the signals input to the switch lines S11, S13, and EM are at a low level, and the Vinput voltage is Vdata. In the data writing period T2, the switch transistor 96b is turned on, and the switch transistors 96a, 96c, 96d and the drive transistor 98 are turned off. As a result, the data voltage Vdata is written between the gate electrode and the source electrode of the driving transistor 98 by the divided voltage of the first capacitor 91 and the second capacitor 92 in series. Therefore, VS = C1 / (C1 + C2) × Vdata + C2 / (C1 + C2) × Vref−Vth (formula (12)), and VG = Vdata. Further, VD = V1. Here, since VS is obtained by calculation based on the charge conservation law at point S during the periods T1 and T2 as in the second embodiment, description of the calculation procedure is omitted.

  In the light emission period T3, the signal input to the switch line EM is at a high level, the signals input to the switch lines S11, S12, and S13 are at a low level, and the Vinput voltage is Vref. In the light emission period T3, the switch transistor 96d and the drive transistor 98 are turned on, and the switch transistors 96a, 96b, and 96c are turned off. When the switch transistor 96 d and the drive transistor 98 are turned on, a current Ioled flows through the organic light emitting element 97. Here, VD = ELVDD. Ioled is the same as that in the second embodiment, and a detailed description thereof is omitted.

  Here, normally, in the Vth compensation period, when the gate-source voltage is in the vicinity of the threshold (Vth + 1 to 2 V), and the drain-source voltage increases at the same time, the kink effect is likely to occur. On the other hand, by increasing the channel length, it is possible to suppress the kink effect by weakening the electric field between the drain and the source, but in this case, it is disadvantageous for high definition.

  In the present embodiment, in the initialization period T0 and the Vth compensation period T1, the drain side voltage VD of the drive transistor 98 can be freely set by the voltage of the set power supply line V1 (where V1 ≧ Vref−Vth). ). Therefore, the bias stress on the driving transistor 98 can be alleviated by lowering the drain-source voltage (V1-Vini). As a result, the kink effect can be suppressed, and fluctuations in the threshold value Vth of the drive transistor 98 can be suppressed.

  Furthermore, in this embodiment, since the kink effect is suppressed by lowering the drain-source voltage, the channel length can be shortened, which is advantageous in high definition.

  Note that in the initialization period, a signal input to the switch line S3 may be at a high level. That is, the switch transistor 96c may be turned on in the initialization period. When the switch transistor 96c becomes conductive during the initialization period, the current from the set power supply line V1 flows to the initialization power supply line Vini via the switch transistors 96c and 96d and the drive transistor 98. The voltage of the power supply line Vini is lower than the sum of the voltage Vth corresponding to the light emission threshold of the organic light emitting element 97 and the voltage of the low power supply ELVSS (that is, Vini <Vth + ELVSS). Does not flow, and the organic light emitting element 97 does not emit light.

  In the above description of Embodiments 1 to 9, the organic light emitting element 97 having the organic light emitting layer is illustrated as an example of the light emitting element. However, the light emitting element may be, for example, an inorganic light emitting element having an inorganic light emitting layer. The inorganic light emitting element is, for example, a so-called quantum dot type light emitting element. A quantum dot type light emitting element has a quantum dot which is arranged between a first electrode and a second electrode and is a material made of a semiconductor microcrystal. Like the organic light emitting device, the quantum dot emits light by a current flowing between the first electrode and the second electrode.

The technical features (components) described in each embodiment can be combined with each other, and new technical features can be formed by combining them.
The embodiments disclosed herein are illustrative in all respects and should not be considered as restrictive. The scope of the present invention is defined not by the above-described meaning but by the scope of the claims, and is intended to include all modifications within the meaning and scope equivalent to the scope of the claims.

DESCRIPTION OF SYMBOLS 10 Display apparatus 11 1st board | substrate 12 2nd board | substrate 13 Driver IC
14 FPC
DESCRIPTION OF SYMBOLS 15 Image display part 16 Display board 17 Light emission part 171 1st light emission part 172 2nd light emission part 18 1st electrode (1st electrode)
DESCRIPTION OF SYMBOLS 19 2nd electrode 20 Drive circuit 21 Scan driver 22 Data voltage driver 23 Emission control driver 24 Protection circuit 25 Sealing part 27 Space 31 Semiconductor part 32 Gate 33 Source drain 34 Etching stop part 35 Metal plate layer 351 1st metal plate ( First metal plate)
352 Second metal plate (second metal plate)
37 transistor 371 first transistor 372 second transistor 42 third insulating layer 43 first insulating layer 45 planarizing layer 46 second insulating layer 461 opening 4611 first opening 4612 second opening 462 non-opening 47 organic light emitting layer 61 1st laminated body 62 2nd laminated body 65 1st electroconductive part 651 1st hole 66 2nd electroconductive part 661 2nd hole 67 3rd electroconductive part 671 3rd hole 71 mounting base 72 board | substrate (mother board | substrate)
73 Substrate fixing part (substrate holder)
74 Insulating film 75 Unit insulating film 751 First region 752 Second region 76 Unit insulating film 90 Pixel 91 First capacitor 92 Second capacitor 96, 96a, 96b, 96c, 96d Switch transistor 97 Organic light emitting device 98 Drive transistor 99 Subpixel

Claims (20)

A light emitting device in which a first electrode, a light emitting layer, and a second electrode are laminated;
A pixel circuit having a source electrode connected to the first electrode and controlling a current supplied to the light emitting element, the pixel circuit being disposed below the light emitting element;
A first metal plate and a second metal plate disposed to face the light emitting layer with the first electrode interposed therebetween;
A first insulating layer disposed between the first metal plate and the second metal plate and the first electrode;
The first metal plate is connected to a gate electrode of the driving transistor;
The second metal plate is connected to a wiring of a first voltage;
A display device in which the first metal plate and the second metal plate are arranged on the same surface. A first capacitor is formed by the first electrode, the first insulating layer, and the first metal plate,
A second capacitor is formed by the first electrode, the first insulating layer, and the second metal plate,
The display device according to claim 1, wherein the first capacitor and the second capacitor are connected in series, and a connection point between the first capacitor and the second capacitor is connected to the source electrode. The display device according to claim 1, wherein the first capacitor holds a charge corresponding to at least luminance of the light emitting element. The driving transistor is an N-type transistor,
The first electrode is an anode electrode;
The display device according to claim 1, wherein the second electrode is a cathode electrode. The drive transistor is a P-type transistor,
The first electrode is a cathode electrode;
The display device according to claim 1, wherein the second electrode is an anode electrode. The first electrode is planar,
6. The same first insulating layer is provided between the first metal plate and the first electrode and between the second metal plate and the first electrode. The display device described. The distance between the first metal plate and the first electrode and the distance between the second metal plate and the first electrode are equal to each other. Display device. A planar second insulating layer including an opening that emits light emitted from the light-emitting element to the outside and a non-opening that is not open;
The second insulating layer is disposed in a layer different from the layer in which the first metal plate and the second metal plate are disposed,
The display device according to claim 1, wherein the non-opening portion covers an interval between the first metal plate and the second metal plate.   The display device according to claim 8, wherein the first metal plate is connected to the gate electrode at a portion covered by the non-opening.   The display device according to claim 1, wherein the first metal plate is connected to the source electrode at a portion not covered with the first electrode.   The display device according to claim 8, wherein the first electrode is connected to the source electrode at a portion covered with the non-opening.   The display device according to claim 8, wherein the entire region of the opening faces the first metal plate across the first electrode.   The display device according to any one of claims 8 to 11, wherein the entire region of the opening faces the second metal plate with the first electrode interposed therebetween. The opening has a first region and a second region that do not overlap each other;
The first region faces the first metal plate across the first electrode;
The display device according to claim 8, wherein the second region faces the second metal plate with the first electrode interposed therebetween.   The display device according to claim 1, wherein the second metal plate is connected to the second electrode.   The display device according to claim 1, wherein the second metal plate is connected to the drain electrode.   The pixel circuit applies a second voltage lower than a sum of a voltage corresponding to a light emission threshold of the light emitting element and the first voltage to the first electrode, and a threshold voltage of the driving transistor to the gate electrode. The display device according to claim 2, wherein a third voltage equal to or greater than a sum of the second voltage and the second voltage is applied.   The display device according to claim 17, wherein the pixel circuit conducts the driving transistor and applies a fourth voltage equal to or higher than a voltage obtained by subtracting the threshold voltage from the third voltage to a drain electrode of the driving transistor.   The display device according to claim 18, wherein the pixel circuit stops applying the fourth voltage to the drain electrode and applies a voltage corresponding to light emission luminance of the light emitting element to the gate electrode. A transistor having a source electrode, a drain electrode and a gate electrode is disposed on one surface of the substrate;
A third insulating layer covering the transistor is disposed on the transistor;
A first metal plate connected to the gate electrode through a first conductive portion penetrating the third insulating layer and a second metal plate insulated from the first metal plate are disposed above the third insulating layer. On the same layer,
A first insulating layer is disposed above the layers of the first metal plate and the second metal plate;
A first electrode connected to the source electrode via a second conductive portion penetrating the first insulating layer and the third insulating layer is disposed on the upper side of the first insulating layer;
A light emitting layer is disposed above the first electrode;
A method for manufacturing a display device, wherein the second electrode is disposed on the light emitting layer.

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