JP6727482B2 - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
- Publication number
- JP6727482B2 JP6727482B2 JP2017020523A JP2017020523A JP6727482B2 JP 6727482 B2 JP6727482 B2 JP 6727482B2 JP 2017020523 A JP2017020523 A JP 2017020523A JP 2017020523 A JP2017020523 A JP 2017020523A JP 6727482 B2 JP6727482 B2 JP 6727482B2
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- JP
- Japan
- Prior art keywords
- signal terminal
- semiconductor chip
- signal
- semiconductor device
- electrode pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/49105—Connecting at different heights
- H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4911—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain
- H01L2224/49111—Disposition the connectors being bonded to at least one common bonding area, e.g. daisy chain the connectors connecting two common bonding areas, e.g. Litz or braid wires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49175—Parallel arrangements
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- Wire Bonding (AREA)
Description
本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成するものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。
12a:第1側面
12b:第2側面
12c:上面
16:第1電極パッド
18:第2電極パッド
26:第1信号端子
28:第2信号端子
32、34:ワイヤ
Claims (3)
- 上面と、第1側面と、前記第1側面に隣接する第2側面を有し、前記上面に、複数の第1電極パッドと、第2電極パッドが設けられた半導体チップを有し、
前記半導体チップを上から見たときに、前記第1側面に沿う方向を第1方向とし、前記第2側面に沿う方向を第2方向とし、
前記半導体チップの前記第2側面側に配置されており、前記第1方向に沿って伸びており、前記第2方向に沿って間隔を空けて配列されており、対応する第1電極パッドにワイヤを介して接続されている複数の第1信号端子と、
前記半導体チップの前記第2側面側に配置されており、前記第1方向に沿って伸びており、前記第2電極パッドに複数のワイヤを介して接続されており、前記第1信号端子よりも前記第2方向における幅が広い第2信号端子を有しており、
前記第2信号端子と前記第1信号端子は、前記第2方向に沿う直線上で見たときに、前記半導体チップの厚み方向において異なる位置に配置されている、
半導体装置。 - 前記厚み方向における前記第1信号端子と前記第2信号端子の間の距離をL1、前記第2方向における前記第1信号端子と前記第2信号端子の間の距離をL3、としたときに、前記第1信号端子と前記第2信号端子の間の最短距離が、(L1 2 +L3 2 ) 1/2 である、請求項1に記載の半導体装置。
- 上側から前記第2信号端子を平面視したときに、前記第2信号端子が、前記複数の第1信号端子の少なくとも1つと部分的に重複するように配置されている、請求項1又は2に記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017020523A JP6727482B2 (ja) | 2017-02-07 | 2017-02-07 | 半導体装置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017020523A JP6727482B2 (ja) | 2017-02-07 | 2017-02-07 | 半導体装置 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2018129366A JP2018129366A (ja) | 2018-08-16 |
JP6727482B2 true JP6727482B2 (ja) | 2020-07-22 |
Family
ID=63173101
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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JP2017020523A Active JP6727482B2 (ja) | 2017-02-07 | 2017-02-07 | 半導体装置 |
Country Status (1)
Country | Link |
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JP (1) | JP6727482B2 (ja) |
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2017
- 2017-02-07 JP JP2017020523A patent/JP6727482B2/ja active Active
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Publication number | Publication date |
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JP2018129366A (ja) | 2018-08-16 |
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