JP6707706B2 - 異なるクロックドメイン間のクロック信号の周波数変更の管理 - Google Patents

異なるクロックドメイン間のクロック信号の周波数変更の管理 Download PDF

Info

Publication number
JP6707706B2
JP6707706B2 JP2019501659A JP2019501659A JP6707706B2 JP 6707706 B2 JP6707706 B2 JP 6707706B2 JP 2019501659 A JP2019501659 A JP 2019501659A JP 2019501659 A JP2019501659 A JP 2019501659A JP 6707706 B2 JP6707706 B2 JP 6707706B2
Authority
JP
Japan
Prior art keywords
clock signal
clock
edge
read
fifo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2019501659A
Other languages
English (en)
Japanese (ja)
Other versions
JP2019522858A5 (cg-RX-API-DMAC7.html
JP2019522858A (ja
Inventor
コムルシュ スティーヴン
コムルシュ スティーヴン
メーラ アミタブ
メーラ アミタブ
マーティン ボーン リチャード
マーティン ボーン リチャード
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of JP2019522858A publication Critical patent/JP2019522858A/ja
Publication of JP2019522858A5 publication Critical patent/JP2019522858A5/ja
Application granted granted Critical
Publication of JP6707706B2 publication Critical patent/JP6707706B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Sources (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
JP2019501659A 2016-07-13 2016-09-15 異なるクロックドメイン間のクロック信号の周波数変更の管理 Active JP6707706B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/209,521 US10168731B2 (en) 2016-07-13 2016-07-13 Managing frequency changes of clock signals across different clock domains
US15/209,521 2016-07-13
PCT/US2016/051813 WO2018013155A1 (en) 2016-07-13 2016-09-15 Managing frequency changes of clock signals across different clock domains

Publications (3)

Publication Number Publication Date
JP2019522858A JP2019522858A (ja) 2019-08-15
JP2019522858A5 JP2019522858A5 (cg-RX-API-DMAC7.html) 2019-10-31
JP6707706B2 true JP6707706B2 (ja) 2020-06-10

Family

ID=60941023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2019501659A Active JP6707706B2 (ja) 2016-07-13 2016-09-15 異なるクロックドメイン間のクロック信号の周波数変更の管理

Country Status (6)

Country Link
US (1) US10168731B2 (cg-RX-API-DMAC7.html)
EP (1) EP3485341B1 (cg-RX-API-DMAC7.html)
JP (1) JP6707706B2 (cg-RX-API-DMAC7.html)
KR (1) KR102427773B1 (cg-RX-API-DMAC7.html)
CN (1) CN109478081A (cg-RX-API-DMAC7.html)
WO (1) WO2018013155A1 (cg-RX-API-DMAC7.html)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11525113B2 (en) 2016-10-31 2022-12-13 Global Life Sciences Solutions Usa Llc Bioreactor assembly
EP3871062B1 (en) * 2018-10-24 2025-11-26 Magic Leap, Inc. Asynchronous asic
WO2020242991A1 (en) 2019-05-24 2020-12-03 Intel Corporation Device, method and system for transparently changing a frequency of an interconnect fabric
TWI755830B (zh) * 2020-08-28 2022-02-21 力晶積成電子製造股份有限公司 記憶體的讀取方法
US11967960B2 (en) * 2021-07-30 2024-04-23 Advanced Micro Devices, Inc. Methods and apparatus for synchronizing data transfers across clock domains using heads-up indications
CN114461012B (zh) * 2022-01-19 2024-05-10 许昌许继软件技术有限公司 一种嵌入式系统不同时钟域运行时戳获取方法及装置

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07200095A (ja) * 1993-12-28 1995-08-04 Victor Co Of Japan Ltd データ転送回路
JP3417476B2 (ja) * 2000-09-06 2003-06-16 日本電気株式会社 多入力データ同期回路
US7194500B2 (en) * 2003-07-11 2007-03-20 Sony Corporation Scalable gray code counter
US7315600B2 (en) * 2004-03-30 2008-01-01 Arm Limited Asynchronous FIFO apparatus and method for passing data between a first clock domain and a second clock domain and a second clock domain of a data processing apparatus
US7519788B2 (en) 2004-06-04 2009-04-14 Micron Technology, Inc. System and method for an asynchronous data buffer having buffer write and read pointers
US7574635B1 (en) * 2004-12-23 2009-08-11 Xilinx, Inc. Circuit for and method of testing a memory device
US7234017B2 (en) * 2005-02-24 2007-06-19 International Business Machines Corporation Computer system architecture for a processor connected to a high speed bus transceiver
US8260982B2 (en) 2005-06-07 2012-09-04 Lsi Corporation Method for reducing latency
TW200717519A (en) * 2005-10-28 2007-05-01 Univ Nat Chiao Tung Asynchronous first-in-first-out cell
WO2008129364A1 (en) 2007-04-23 2008-10-30 Nokia Corporation Transferring data between asynchronous clock domains
US7934113B2 (en) * 2007-05-21 2011-04-26 Texas Instruments Incorporated Self-clearing asynchronous interrupt edge detect latching register
TWI385924B (zh) * 2009-09-24 2013-02-11 Richwave Technology Corp 非同步先進先出介面、介面操作方法和整合式接收器
US8433875B2 (en) 2010-02-24 2013-04-30 Esilicon Corporation Asynchronous scheme for clock domain crossing
GB2482303A (en) * 2010-07-28 2012-02-01 Gnodal Ltd Modifying read patterns for a FIFO between clock domains
CN102647374B (zh) * 2011-02-18 2015-01-28 瑞昱半导体股份有限公司 跨时钟域的干扰消除装置及方法
US8918666B2 (en) * 2011-05-23 2014-12-23 Intel Mobile Communications GmbH Apparatus for synchronizing a data handover between a first and second clock domain through FIFO buffering
US10025343B2 (en) 2011-12-28 2018-07-17 Intel Corporation Data transfer between asynchronous clock domains
WO2013147839A1 (en) * 2012-03-30 2013-10-03 Intel Corporation On-die all-digital delay measurement circuit
DE102013221678B4 (de) * 2012-11-12 2024-08-01 Nvidia Corp. System und Verfahren zum Bestimmen einer Zeit zum sicheren Abtasten eines Signals einer Takt-Domäne
US9367286B2 (en) * 2013-08-28 2016-06-14 Imagination Technologies Limited Crossing pipelined data between circuitry in different clock domains
US9449127B1 (en) * 2015-04-01 2016-09-20 Freescale Semiconductor, Inc. System for verifying timing constraints of IC design

Also Published As

Publication number Publication date
US20180017988A1 (en) 2018-01-18
JP2019522858A (ja) 2019-08-15
EP3485341B1 (en) 2022-09-07
WO2018013155A1 (en) 2018-01-18
EP3485341A4 (en) 2020-03-18
EP3485341A1 (en) 2019-05-22
US10168731B2 (en) 2019-01-01
KR102427773B1 (ko) 2022-08-01
CN109478081A (zh) 2019-03-15
KR20190018742A (ko) 2019-02-25

Similar Documents

Publication Publication Date Title
JP6707706B2 (ja) 異なるクロックドメイン間のクロック信号の周波数変更の管理
KR101297481B1 (ko) 프로세싱 코어들의 독립 전력 제어
TWI460583B (zh) 使用粗調時脈閘之動態頻率控制
US9304579B2 (en) Fast-wake memory control
KR102340679B1 (ko) 전압 드룹을 위한 클록 조정
JP5684918B2 (ja) 周波数変化中の効率的なｄｌｌトレーニングプロトコルのためのメカニズム
US8195849B2 (en) Device and method for transferring data between devices
KR20130088885A (ko) 동적 전압 펄스 스킴에 의한 개선된 전력 전송 성능을 위한 장치, 방법 및 시스템
JP7617026B2 (ja) 安定したクロッキングを維持するための装置および方法
KR20070035943A (ko) 반도체 메모리 장치
JP7299890B2 (ja) ポインタオフセットを用いた非同期バッファ
US7042263B1 (en) Memory clock slowdown synthesis circuit
US7187220B1 (en) Memory clock slowdown
US11967960B2 (en) Methods and apparatus for synchronizing data transfers across clock domains using heads-up indications
US8976619B2 (en) Semiconductor apparatus
TWI794949B (zh) 用於組態及狀態暫存器之獨立時脈之單晶片系統及方法

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190411

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190912

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20190912

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20190912

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20191030

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20191119

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20200207

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200422

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200520

R150 Certificate of patent or registration of utility model

Ref document number: 6707706

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250