KR102427773B1 - 상이한 클록 도메인에 걸친 클록 신호의 주파수 변화 관리 - Google Patents

상이한 클록 도메인에 걸친 클록 신호의 주파수 변화 관리 Download PDF

Info

Publication number
KR102427773B1
KR102427773B1 KR1020197003897A KR20197003897A KR102427773B1 KR 102427773 B1 KR102427773 B1 KR 102427773B1 KR 1020197003897 A KR1020197003897 A KR 1020197003897A KR 20197003897 A KR20197003897 A KR 20197003897A KR 102427773 B1 KR102427773 B1 KR 102427773B1
Authority
KR
South Korea
Prior art keywords
clock
clock signal
edge
read
fifo
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
KR1020197003897A
Other languages
English (en)
Korean (ko)
Other versions
KR20190018742A (ko
Inventor
스티븐 쿰므루쉬
아미타브 메흐라
리차드 마틴 본
Original Assignee
어드밴스드 마이크로 디바이시즈, 인코포레이티드
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 어드밴스드 마이크로 디바이시즈, 인코포레이티드 filed Critical 어드밴스드 마이크로 디바이시즈, 인코포레이티드
Publication of KR20190018742A publication Critical patent/KR20190018742A/ko
Application granted granted Critical
Publication of KR102427773B1 publication Critical patent/KR102427773B1/ko
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08—Clock generators with changeable or programmable clock frequency
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10—Distribution of clock signals, e.g. skew
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4027—Coupling between buses using bus bridges
    • G06F13/405—Coupling between buses using bus bridges where the bridge performs a synchronising function
    • G06F13/4059—Coupling between buses using bus bridges where the bridge performs a synchronising function where the synchronisation uses buffers, e.g. for speed matching between buses
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Sources (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Information Transfer Systems (AREA)
KR1020197003897A 2016-07-13 2016-09-15 상이한 클록 도메인에 걸친 클록 신호의 주파수 변화 관리 Active KR102427773B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/209,521 US10168731B2 (en) 2016-07-13 2016-07-13 Managing frequency changes of clock signals across different clock domains
US15/209,521 2016-07-13
PCT/US2016/051813 WO2018013155A1 (en) 2016-07-13 2016-09-15 Managing frequency changes of clock signals across different clock domains

Publications (2)

Publication Number Publication Date
KR20190018742A KR20190018742A (ko) 2019-02-25
KR102427773B1 true KR102427773B1 (ko) 2022-08-01

Family

ID=60941023

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020197003897A Active KR102427773B1 (ko) 2016-07-13 2016-09-15 상이한 클록 도메인에 걸친 클록 신호의 주파수 변화 관리

Country Status (6)

Country Link
US (1) US10168731B2 (cg-RX-API-DMAC7.html)
EP (1) EP3485341B1 (cg-RX-API-DMAC7.html)
JP (1) JP6707706B2 (cg-RX-API-DMAC7.html)
KR (1) KR102427773B1 (cg-RX-API-DMAC7.html)
CN (1) CN109478081A (cg-RX-API-DMAC7.html)
WO (1) WO2018013155A1 (cg-RX-API-DMAC7.html)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11525113B2 (en) 2016-10-31 2022-12-13 Global Life Sciences Solutions Usa Llc Bioreactor assembly
EP3871062B1 (en) * 2018-10-24 2025-11-26 Magic Leap, Inc. Asynchronous asic
WO2020242991A1 (en) 2019-05-24 2020-12-03 Intel Corporation Device, method and system for transparently changing a frequency of an interconnect fabric
TWI755830B (zh) * 2020-08-28 2022-02-21 力晶積成電子製造股份有限公司 記憶體的讀取方法
US11967960B2 (en) * 2021-07-30 2024-04-23 Advanced Micro Devices, Inc. Methods and apparatus for synchronizing data transfers across clock domains using heads-up indications
CN114461012B (zh) * 2022-01-19 2024-05-10 许昌许继软件技术有限公司 一种嵌入式系统不同时钟域运行时戳获取方法及装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090319745A1 (en) 2004-06-04 2009-12-24 Laberge Paul A System and method for an asynchronous data buffer having buffer write and read pointers
US20100111117A1 (en) 2007-04-23 2010-05-06 Pasi Kolinummi Transferring data between asynchronous clock domains
WO2012160108A1 (en) * 2011-05-23 2012-11-29 Intel Mobile Communications GmbH Apparatus for synchronizing a data handover between a first clock domain and a second clock domain
US20130254583A1 (en) 2011-12-28 2013-09-26 Michael C. Rifani Data transfer between asynchronous clock domains

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07200095A (ja) * 1993-12-28 1995-08-04 Victor Co Of Japan Ltd データ転送回路
JP3417476B2 (ja) * 2000-09-06 2003-06-16 日本電気株式会社 多入力データ同期回路
US7194500B2 (en) * 2003-07-11 2007-03-20 Sony Corporation Scalable gray code counter
US7315600B2 (en) * 2004-03-30 2008-01-01 Arm Limited Asynchronous FIFO apparatus and method for passing data between a first clock domain and a second clock domain and a second clock domain of a data processing apparatus
US7574635B1 (en) * 2004-12-23 2009-08-11 Xilinx, Inc. Circuit for and method of testing a memory device
US7234017B2 (en) * 2005-02-24 2007-06-19 International Business Machines Corporation Computer system architecture for a processor connected to a high speed bus transceiver
US8260982B2 (en) 2005-06-07 2012-09-04 Lsi Corporation Method for reducing latency
TW200717519A (en) * 2005-10-28 2007-05-01 Univ Nat Chiao Tung Asynchronous first-in-first-out cell
US7934113B2 (en) * 2007-05-21 2011-04-26 Texas Instruments Incorporated Self-clearing asynchronous interrupt edge detect latching register
TWI385924B (zh) * 2009-09-24 2013-02-11 Richwave Technology Corp 非同步先進先出介面、介面操作方法和整合式接收器
US8433875B2 (en) 2010-02-24 2013-04-30 Esilicon Corporation Asynchronous scheme for clock domain crossing
GB2482303A (en) * 2010-07-28 2012-02-01 Gnodal Ltd Modifying read patterns for a FIFO between clock domains
CN102647374B (zh) * 2011-02-18 2015-01-28 瑞昱半导体股份有限公司 跨时钟域的干扰消除装置及方法
WO2013147839A1 (en) * 2012-03-30 2013-10-03 Intel Corporation On-die all-digital delay measurement circuit
DE102013221678B4 (de) * 2012-11-12 2024-08-01 Nvidia Corp. System und Verfahren zum Bestimmen einer Zeit zum sicheren Abtasten eines Signals einer Takt-Domäne
US9367286B2 (en) * 2013-08-28 2016-06-14 Imagination Technologies Limited Crossing pipelined data between circuitry in different clock domains
US9449127B1 (en) * 2015-04-01 2016-09-20 Freescale Semiconductor, Inc. System for verifying timing constraints of IC design

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090319745A1 (en) 2004-06-04 2009-12-24 Laberge Paul A System and method for an asynchronous data buffer having buffer write and read pointers
US20100111117A1 (en) 2007-04-23 2010-05-06 Pasi Kolinummi Transferring data between asynchronous clock domains
WO2012160108A1 (en) * 2011-05-23 2012-11-29 Intel Mobile Communications GmbH Apparatus for synchronizing a data handover between a first clock domain and a second clock domain
US20130254583A1 (en) 2011-12-28 2013-09-26 Michael C. Rifani Data transfer between asynchronous clock domains

Also Published As

Publication number Publication date
US20180017988A1 (en) 2018-01-18
JP2019522858A (ja) 2019-08-15
EP3485341B1 (en) 2022-09-07
WO2018013155A1 (en) 2018-01-18
EP3485341A4 (en) 2020-03-18
EP3485341A1 (en) 2019-05-22
US10168731B2 (en) 2019-01-01
JP6707706B2 (ja) 2020-06-10
CN109478081A (zh) 2019-03-15
KR20190018742A (ko) 2019-02-25

Similar Documents

Publication Publication Date Title
KR102427773B1 (ko) 상이한 클록 도메인에 걸친 클록 신호의 주파수 변화 관리
JP6305661B1 (ja) グリッチフリークロック切替えのための装置、方法、およびシステム
US5506809A (en) Predictive status flag generation in a first-in first-out (FIFO) memory device method and apparatus
JP4249701B2 (ja) 一体化されたグラフィック装置の電力管理
CN108369434B (zh) 时基同步
US11256287B2 (en) Apparatus and method to maintain stable clocking
US11683149B2 (en) Precise time management using local time base
US8195849B2 (en) Device and method for transferring data between devices
CN100437436C (zh) 在节能模式下运行时减少cpu和总线功率
US8707081B2 (en) Memory clock slowdown
US7646838B2 (en) Providing accurate time-based counters for scaling operating frequencies of microprocessors
KR20130010446A (ko) 코어스 클럭 게이팅을 사용하는 동적 프리퀀시 제어
US11973504B2 (en) Multi-reset and multi-clock synchronizer, and synchronous multi-cycle reset synchronization circuit
JP2021506027A (ja) ポインタオフセットを用いた非同期バッファ
BR102013000054A2 (pt) Gerador de clock e método para gerar o sinal de clock
US7042263B1 (en) Memory clock slowdown synthesis circuit
US11967960B2 (en) Methods and apparatus for synchronizing data transfers across clock domains using heads-up indications
US20230396249A1 (en) Device, system and method to provide adaptive clock modulation with delay line circuits
US11687115B2 (en) Precise time management for peripheral device using local time base
Keller Energy-efficient system design through adaptive voltage scaling
GB2519414A (en) Crossing pipelined data between circuitry in different clock domains

Legal Events

Date Code Title Description
PA0105 International application

St.27 status event code: A-0-1-A10-A15-nap-PA0105

E13-X000 Pre-grant limitation requested

St.27 status event code: A-2-3-E10-E13-lim-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PG1501 Laying open of application

St.27 status event code: A-1-1-Q10-Q12-nap-PG1501

A201 Request for examination
A302 Request for accelerated examination
P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

PA0201 Request for examination

St.27 status event code: A-1-2-D10-D11-exm-PA0201

PA0302 Request for accelerated examination

St.27 status event code: A-1-2-D10-D17-exm-PA0302

St.27 status event code: A-1-2-D10-D16-exm-PA0302

E902 Notification of reason for refusal
PE0902 Notice of grounds for rejection

St.27 status event code: A-1-2-D10-D21-exm-PE0902

T11-X000 Administrative time limit extension requested

St.27 status event code: U-3-3-T10-T11-oth-X000

P11-X000 Amendment of application requested

St.27 status event code: A-2-2-P10-P11-nap-X000

P13-X000 Application amended

St.27 status event code: A-2-2-P10-P13-nap-X000

E701 Decision to grant or registration of patent right
PE0701 Decision of registration

St.27 status event code: A-1-2-D10-D22-exm-PE0701

GRNT Written decision to grant
PR0701 Registration of establishment

St.27 status event code: A-2-4-F10-F11-exm-PR0701

PR1002 Payment of registration fee

St.27 status event code: A-2-2-U10-U12-oth-PR1002

Fee payment year number: 1

PG1601 Publication of registration

St.27 status event code: A-4-4-Q10-Q13-nap-PG1601

PR1001 Payment of annual fee

St.27 status event code: A-4-4-U10-U11-oth-PR1001

Fee payment year number: 4

U11 Full renewal or maintenance fee paid

Free format text: ST27 STATUS EVENT CODE: A-4-4-U10-U11-OTH-PR1001 (AS PROVIDED BY THE NATIONAL OFFICE)

Year of fee payment: 4