JP2019522858A5 - - Google Patents
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- JP2019522858A5 JP2019522858A5 JP2019501659A JP2019501659A JP2019522858A5 JP 2019522858 A5 JP2019522858 A5 JP 2019522858A5 JP 2019501659 A JP2019501659 A JP 2019501659A JP 2019501659 A JP2019501659 A JP 2019501659A JP 2019522858 A5 JP2019522858 A5 JP 2019522858A5
- Authority
- JP
- Japan
- Prior art keywords
- edge
- clock signal
- selecting
- response
- processor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/209,521 US10168731B2 (en) | 2016-07-13 | 2016-07-13 | Managing frequency changes of clock signals across different clock domains |
| US15/209,521 | 2016-07-13 | ||
| PCT/US2016/051813 WO2018013155A1 (en) | 2016-07-13 | 2016-09-15 | Managing frequency changes of clock signals across different clock domains |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2019522858A JP2019522858A (ja) | 2019-08-15 |
| JP2019522858A5 true JP2019522858A5 (cg-RX-API-DMAC7.html) | 2019-10-31 |
| JP6707706B2 JP6707706B2 (ja) | 2020-06-10 |
Family
ID=60941023
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2019501659A Active JP6707706B2 (ja) | 2016-07-13 | 2016-09-15 | 異なるクロックドメイン間のクロック信号の周波数変更の管理 |
Country Status (6)
| Country | Link |
|---|---|
| US (1) | US10168731B2 (cg-RX-API-DMAC7.html) |
| EP (1) | EP3485341B1 (cg-RX-API-DMAC7.html) |
| JP (1) | JP6707706B2 (cg-RX-API-DMAC7.html) |
| KR (1) | KR102427773B1 (cg-RX-API-DMAC7.html) |
| CN (1) | CN109478081A (cg-RX-API-DMAC7.html) |
| WO (1) | WO2018013155A1 (cg-RX-API-DMAC7.html) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11525113B2 (en) | 2016-10-31 | 2022-12-13 | Global Life Sciences Solutions Usa Llc | Bioreactor assembly |
| EP3871062B1 (en) * | 2018-10-24 | 2025-11-26 | Magic Leap, Inc. | Asynchronous asic |
| WO2020242991A1 (en) | 2019-05-24 | 2020-12-03 | Intel Corporation | Device, method and system for transparently changing a frequency of an interconnect fabric |
| TWI755830B (zh) * | 2020-08-28 | 2022-02-21 | 力晶積成電子製造股份有限公司 | 記憶體的讀取方法 |
| US11967960B2 (en) * | 2021-07-30 | 2024-04-23 | Advanced Micro Devices, Inc. | Methods and apparatus for synchronizing data transfers across clock domains using heads-up indications |
| CN114461012B (zh) * | 2022-01-19 | 2024-05-10 | 许昌许继软件技术有限公司 | 一种嵌入式系统不同时钟域运行时戳获取方法及装置 |
Family Cites Families (21)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07200095A (ja) * | 1993-12-28 | 1995-08-04 | Victor Co Of Japan Ltd | データ転送回路 |
| JP3417476B2 (ja) * | 2000-09-06 | 2003-06-16 | 日本電気株式会社 | 多入力データ同期回路 |
| US7194500B2 (en) * | 2003-07-11 | 2007-03-20 | Sony Corporation | Scalable gray code counter |
| US7315600B2 (en) * | 2004-03-30 | 2008-01-01 | Arm Limited | Asynchronous FIFO apparatus and method for passing data between a first clock domain and a second clock domain and a second clock domain of a data processing apparatus |
| US7519788B2 (en) | 2004-06-04 | 2009-04-14 | Micron Technology, Inc. | System and method for an asynchronous data buffer having buffer write and read pointers |
| US7574635B1 (en) * | 2004-12-23 | 2009-08-11 | Xilinx, Inc. | Circuit for and method of testing a memory device |
| US7234017B2 (en) * | 2005-02-24 | 2007-06-19 | International Business Machines Corporation | Computer system architecture for a processor connected to a high speed bus transceiver |
| US8260982B2 (en) | 2005-06-07 | 2012-09-04 | Lsi Corporation | Method for reducing latency |
| TW200717519A (en) * | 2005-10-28 | 2007-05-01 | Univ Nat Chiao Tung | Asynchronous first-in-first-out cell |
| WO2008129364A1 (en) | 2007-04-23 | 2008-10-30 | Nokia Corporation | Transferring data between asynchronous clock domains |
| US7934113B2 (en) * | 2007-05-21 | 2011-04-26 | Texas Instruments Incorporated | Self-clearing asynchronous interrupt edge detect latching register |
| TWI385924B (zh) * | 2009-09-24 | 2013-02-11 | Richwave Technology Corp | 非同步先進先出介面、介面操作方法和整合式接收器 |
| US8433875B2 (en) | 2010-02-24 | 2013-04-30 | Esilicon Corporation | Asynchronous scheme for clock domain crossing |
| GB2482303A (en) * | 2010-07-28 | 2012-02-01 | Gnodal Ltd | Modifying read patterns for a FIFO between clock domains |
| CN102647374B (zh) * | 2011-02-18 | 2015-01-28 | 瑞昱半导体股份有限公司 | 跨时钟域的干扰消除装置及方法 |
| US8918666B2 (en) * | 2011-05-23 | 2014-12-23 | Intel Mobile Communications GmbH | Apparatus for synchronizing a data handover between a first and second clock domain through FIFO buffering |
| US10025343B2 (en) | 2011-12-28 | 2018-07-17 | Intel Corporation | Data transfer between asynchronous clock domains |
| WO2013147839A1 (en) * | 2012-03-30 | 2013-10-03 | Intel Corporation | On-die all-digital delay measurement circuit |
| DE102013221678B4 (de) * | 2012-11-12 | 2024-08-01 | Nvidia Corp. | System und Verfahren zum Bestimmen einer Zeit zum sicheren Abtasten eines Signals einer Takt-Domäne |
| US9367286B2 (en) * | 2013-08-28 | 2016-06-14 | Imagination Technologies Limited | Crossing pipelined data between circuitry in different clock domains |
| US9449127B1 (en) * | 2015-04-01 | 2016-09-20 | Freescale Semiconductor, Inc. | System for verifying timing constraints of IC design |
-
2016
- 2016-07-13 US US15/209,521 patent/US10168731B2/en active Active
- 2016-09-15 CN CN201680087626.8A patent/CN109478081A/zh active Pending
- 2016-09-15 KR KR1020197003897A patent/KR102427773B1/ko active Active
- 2016-09-15 JP JP2019501659A patent/JP6707706B2/ja active Active
- 2016-09-15 EP EP16909046.1A patent/EP3485341B1/en active Active
- 2016-09-15 WO PCT/US2016/051813 patent/WO2018013155A1/en not_active Ceased
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