JP6676052B2 - 不均一メモリアーキテクチャにおける改善されたレイテンシを可能にするためのシステムおよび方法 - Google Patents

不均一メモリアーキテクチャにおける改善されたレイテンシを可能にするためのシステムおよび方法 Download PDF

Info

Publication number
JP6676052B2
JP6676052B2 JP2017529057A JP2017529057A JP6676052B2 JP 6676052 B2 JP6676052 B2 JP 6676052B2 JP 2017529057 A JP2017529057 A JP 2017529057A JP 2017529057 A JP2017529057 A JP 2017529057A JP 6676052 B2 JP6676052 B2 JP 6676052B2
Authority
JP
Japan
Prior art keywords
address
page
soc
physical
volatile memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2017529057A
Other languages
English (en)
Japanese (ja)
Other versions
JP2018502379A (ja
JP2018502379A5 (enExample
Inventor
スティーヴン・アーサー・モロイ
デクスター・タミオ・チュン
Original Assignee
クアルコム，インコーポレイテッド
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by クアルコム，インコーポレイテッド filed Critical クアルコム，インコーポレイテッド
Publication of JP2018502379A publication Critical patent/JP2018502379A/ja
Publication of JP2018502379A5 publication Critical patent/JP2018502379A5/ja
Application granted granted Critical
Publication of JP6676052B2 publication Critical patent/JP6676052B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1072—Decentralised address translation, e.g. in distributed shared memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/254—Distributed memory
    • G06F2212/2542—Non-uniform memory access [NUMA] architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP2017529057A 2014-12-04 2015-11-20 不均一メモリアーキテクチャにおける改善されたレイテンシを可能にするためのシステムおよび方法 Active JP6676052B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/560,450 2014-12-04
US14/560,450 US9542333B2 (en) 2014-12-04 2014-12-04 Systems and methods for providing improved latency in a non-uniform memory architecture
PCT/US2015/061989 WO2016089632A1 (en) 2014-12-04 2015-11-20 Systems and methods for providing improved latency in a non-uniform memory architecture

Publications (3)

Publication Number Publication Date
JP2018502379A JP2018502379A (ja) 2018-01-25
JP2018502379A5 JP2018502379A5 (enExample) 2018-12-13
JP6676052B2 true JP6676052B2 (ja) 2020-04-08

Family

ID=54834930

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017529057A Active JP6676052B2 (ja) 2014-12-04 2015-11-20 不均一メモリアーキテクチャにおける改善されたレイテンシを可能にするためのシステムおよび方法

Country Status (9)

Country Link
US (1) US9542333B2 (enExample)
EP (1) EP3227787B1 (enExample)
JP (1) JP6676052B2 (enExample)
KR (1) KR20170091102A (enExample)
CN (1) CN107111560B (enExample)
BR (1) BR112017011765A2 (enExample)
CA (1) CA2964303A1 (enExample)
TW (1) TW201633151A (enExample)
WO (1) WO2016089632A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9575881B2 (en) 2014-12-04 2017-02-21 Qualcomm Incorporated Systems and methods for providing improved latency in a non-uniform memory architecture
US11157416B2 (en) * 2020-02-27 2021-10-26 Micron Technology, Inc. Firmware loading for a memory controller
CN111782411A (zh) * 2020-07-02 2020-10-16 江苏华创微系统有限公司 在numa系统中提升抢锁操作公平性的方法

Family Cites Families (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07182298A (ja) * 1993-12-22 1995-07-21 Canon Inc 情報処理方法及び装置
US5897664A (en) 1996-07-01 1999-04-27 Sun Microsystems, Inc. Multiprocessor system having mapping table in each node to map global physical addresses to local physical addresses of page copies
JPH10312338A (ja) * 1997-05-13 1998-11-24 Toshiba Corp メモリ制御装置、及びメモリ制御方法
US6049853A (en) 1997-08-29 2000-04-11 Sequent Computer Systems, Inc. Data replication across nodes of a multiprocessor computer system
US6167437A (en) 1997-09-02 2000-12-26 Silicon Graphics, Inc. Method, system, and computer program product for page replication in a non-uniform memory access system
WO1999012103A2 (en) 1997-09-05 1999-03-11 Sun Microsystems, Inc. Scalable shared memory multiprocessor system
US6785783B2 (en) 2000-11-30 2004-08-31 International Business Machines Corporation NUMA system with redundant main memory architecture
US6871219B2 (en) 2001-03-07 2005-03-22 Sun Microsystems, Inc. Dynamic memory placement policies for NUMA architecture
EP1611513B1 (en) 2003-04-04 2010-12-15 Oracle America, Inc. Multi-node system in which global address generated by processing subsystem includes global to local translation information
US7765381B2 (en) 2003-04-04 2010-07-27 Oracle America, Inc. Multi-node system in which home memory subsystem stores global to local address translation information for replicating nodes
US8417913B2 (en) * 2003-11-13 2013-04-09 International Business Machines Corporation Superpage coalescing which supports read/write access to a new virtual superpage mapping during copying of physical pages
US7921261B2 (en) 2007-12-18 2011-04-05 International Business Machines Corporation Reserving a global address space
CN102317938B (zh) * 2008-12-22 2014-07-30 谷歌公司 用于复制内容可寻址存储集群的异步分布式去重
US8451281B2 (en) 2009-06-23 2013-05-28 Intel Corporation Shared virtual memory between a host and discrete graphics device in a computing system
US8392736B2 (en) * 2009-07-31 2013-03-05 Hewlett-Packard Development Company, L.P. Managing memory power usage
US8924685B2 (en) * 2010-05-11 2014-12-30 Qualcomm Incorporated Configuring surrogate memory accessing agents using non-priviledged processes
JP5664347B2 (ja) * 2011-03-04 2015-02-04 ソニー株式会社 仮想メモリシステム、仮想メモリの制御方法、およびプログラム
US8560757B2 (en) 2011-10-25 2013-10-15 Cavium, Inc. System and method to reduce memory access latencies using selective replication across multiple memory ports
CN103257929B (zh) * 2013-04-18 2016-03-16 中国科学院计算技术研究所 一种虚拟机内存映射方法及系统
US9361233B2 (en) * 2013-12-20 2016-06-07 Intel Corporation Method and apparatus for shared line unified cache
US9558041B2 (en) * 2014-09-05 2017-01-31 Telefonaktiebolaget L M Ericsson (Publ) Transparent non-uniform memory access (NUMA) awareness
US9575881B2 (en) 2014-12-04 2017-02-21 Qualcomm Incorporated Systems and methods for providing improved latency in a non-uniform memory architecture

Also Published As

Publication number Publication date
US9542333B2 (en) 2017-01-10
CA2964303A1 (en) 2016-06-09
CN107111560B (zh) 2021-01-08
WO2016089632A1 (en) 2016-06-09
JP2018502379A (ja) 2018-01-25
TW201633151A (zh) 2016-09-16
KR20170091102A (ko) 2017-08-08
EP3227787B1 (en) 2020-03-04
CN107111560A (zh) 2017-08-29
BR112017011765A2 (pt) 2018-02-20
EP3227787A1 (en) 2017-10-11
US20160162415A1 (en) 2016-06-09

Similar Documents

Publication Publication Date Title
US10769073B2 (en) Bandwidth-based selective memory channel connectivity on a system on chip
US10628308B2 (en) Dynamic adjustment of memory channel interleave granularity
US20170177497A1 (en) Compressed caching of a logical-to-physical address table for nand-type flash memory
KR102051698B1 (ko) 단일 페이지 테이블 엔트리 내의 속성 필드들의 다중 세트들
JP6674460B2 (ja) 不均一メモリアーキテクチャにおける改善されたレイテンシのためのシステムおよび方法
US20150293845A1 (en) Multi-level memory hierarchy
US20210373790A1 (en) Inference in memory
JP2017528813A (ja) システムオンチップ用のメモリを拡張するためのシステムおよび方法
JP6676052B2 (ja) 不均一メモリアーキテクチャにおける改善されたレイテンシを可能にするためのシステムおよび方法
JP2016522915A (ja) 共有メモリシステム
EP3959611B1 (en) Intra-device notational data movement system
CN108959105A (zh) 一种实现地址映射的方法及装置
CN116795739B (zh) 一种内存访问方法及装置
WO2017084415A1 (zh) 一种存储器切换方法、装置及计算机存储介质
CN107632944A (zh) 一种读取数据的方法及装置
US12067237B2 (en) Flexible memory system
HK40024837B (zh) 内存管理方法、装置、设备及存储介质

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20181105

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20181105

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20190902

A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20190830

A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20190927

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200217

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200311

R150 Certificate of patent or registration of utility model

Ref document number: 6676052

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250