CN107111560B - 用于在非统一存储器架构中提供改进的延迟的系统和方法 - Google Patents

用于在非统一存储器架构中提供改进的延迟的系统和方法 Download PDF

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CN107111560B
CN107111560B CN201580062124.5A CN201580062124A CN107111560B CN 107111560 B CN107111560 B CN 107111560B CN 201580062124 A CN201580062124 A CN 201580062124A CN 107111560 B CN107111560 B CN 107111560B
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volatile memory
memory device
local volatile
physical address
address
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CN201580062124.5A
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Chinese (zh)
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CN107111560A (zh
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S·A·莫洛伊
D·T·全
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Qualcomm Inc
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Qualcomm Inc
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1072—Decentralised address translation, e.g. in distributed shared memory systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/10—Address translation
    • G06F12/1009—Address translation using page tables, e.g. page table structures
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1016—Performance improvement
    • G06F2212/1024—Latency reduction
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/25—Using a specific main memory architecture
    • G06F2212/254—Distributed memory
    • G06F2212/2542—Non-uniform memory access [NUMA] architecture
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/65—Details of virtual memory and virtual address translation
    • G06F2212/657—Virtual address space management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
CN201580062124.5A 2014-12-04 2015-11-20 用于在非统一存储器架构中提供改进的延迟的系统和方法 Active CN107111560B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/560,450 2014-12-04
US14/560,450 US9542333B2 (en) 2014-12-04 2014-12-04 Systems and methods for providing improved latency in a non-uniform memory architecture
PCT/US2015/061989 WO2016089632A1 (en) 2014-12-04 2015-11-20 Systems and methods for providing improved latency in a non-uniform memory architecture

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CN107111560A CN107111560A (zh) 2017-08-29
CN107111560B true CN107111560B (zh) 2021-01-08

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US (1) US9542333B2 (enExample)
EP (1) EP3227787B1 (enExample)
JP (1) JP6676052B2 (enExample)
KR (1) KR20170091102A (enExample)
CN (1) CN107111560B (enExample)
BR (1) BR112017011765A2 (enExample)
CA (1) CA2964303A1 (enExample)
TW (1) TW201633151A (enExample)
WO (1) WO2016089632A1 (enExample)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9575881B2 (en) 2014-12-04 2017-02-21 Qualcomm Incorporated Systems and methods for providing improved latency in a non-uniform memory architecture
US11157416B2 (en) * 2020-02-27 2021-10-26 Micron Technology, Inc. Firmware loading for a memory controller
CN111782411A (zh) * 2020-07-02 2020-10-16 江苏华创微系统有限公司 在numa系统中提升抢锁操作公平性的方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120226850A1 (en) * 2011-03-04 2012-09-06 Sony Corporation Virtual memory system, virtual memory controlling method, and program
CN102884506A (zh) * 2010-05-11 2013-01-16 高通股份有限公司 使用用于转换并存储数据值的指令来配置替代存储器存取代理
CN103257929A (zh) * 2013-04-18 2013-08-21 中国科学院计算技术研究所 一种虚拟机内存映射方法及系统

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07182298A (ja) * 1993-12-22 1995-07-21 Canon Inc 情報処理方法及び装置
US5897664A (en) 1996-07-01 1999-04-27 Sun Microsystems, Inc. Multiprocessor system having mapping table in each node to map global physical addresses to local physical addresses of page copies
JPH10312338A (ja) * 1997-05-13 1998-11-24 Toshiba Corp メモリ制御装置、及びメモリ制御方法
US6049853A (en) 1997-08-29 2000-04-11 Sequent Computer Systems, Inc. Data replication across nodes of a multiprocessor computer system
US6167437A (en) 1997-09-02 2000-12-26 Silicon Graphics, Inc. Method, system, and computer program product for page replication in a non-uniform memory access system
US20010042176A1 (en) 1997-09-05 2001-11-15 Erik E. Hagersten Skewed finite hashing function
US6785783B2 (en) 2000-11-30 2004-08-31 International Business Machines Corporation NUMA system with redundant main memory architecture
US6871219B2 (en) 2001-03-07 2005-03-22 Sun Microsystems, Inc. Dynamic memory placement policies for NUMA architecture
ATE491991T1 (de) 2003-04-04 2011-01-15 Oracle America Inc Mehrknoten system, bei dem die globale adresse, die durch ein verarbeitungsuntersystem erzeugt wird, globale-zu-lokale übersetzungsinformationen miteinschliesst
US7765381B2 (en) 2003-04-04 2010-07-27 Oracle America, Inc. Multi-node system in which home memory subsystem stores global to local address translation information for replicating nodes
US8417913B2 (en) * 2003-11-13 2013-04-09 International Business Machines Corporation Superpage coalescing which supports read/write access to a new virtual superpage mapping during copying of physical pages
US7921261B2 (en) 2007-12-18 2011-04-05 International Business Machines Corporation Reserving a global address space
JP5579195B2 (ja) * 2008-12-22 2014-08-27 グーグル インコーポレイテッド 複製されたコンテンツアドレス可能ストレージクラスタのための非同期分散型重複排除
US8451281B2 (en) 2009-06-23 2013-05-28 Intel Corporation Shared virtual memory between a host and discrete graphics device in a computing system
US8392736B2 (en) * 2009-07-31 2013-03-05 Hewlett-Packard Development Company, L.P. Managing memory power usage
US8560757B2 (en) 2011-10-25 2013-10-15 Cavium, Inc. System and method to reduce memory access latencies using selective replication across multiple memory ports
US9361233B2 (en) * 2013-12-20 2016-06-07 Intel Corporation Method and apparatus for shared line unified cache
US9558041B2 (en) * 2014-09-05 2017-01-31 Telefonaktiebolaget L M Ericsson (Publ) Transparent non-uniform memory access (NUMA) awareness
US9575881B2 (en) 2014-12-04 2017-02-21 Qualcomm Incorporated Systems and methods for providing improved latency in a non-uniform memory architecture

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102884506A (zh) * 2010-05-11 2013-01-16 高通股份有限公司 使用用于转换并存储数据值的指令来配置替代存储器存取代理
US20120226850A1 (en) * 2011-03-04 2012-09-06 Sony Corporation Virtual memory system, virtual memory controlling method, and program
CN103257929A (zh) * 2013-04-18 2013-08-21 中国科学院计算技术研究所 一种虚拟机内存映射方法及系统

Also Published As

Publication number Publication date
CN107111560A (zh) 2017-08-29
EP3227787B1 (en) 2020-03-04
WO2016089632A1 (en) 2016-06-09
KR20170091102A (ko) 2017-08-08
US20160162415A1 (en) 2016-06-09
US9542333B2 (en) 2017-01-10
JP6676052B2 (ja) 2020-04-08
TW201633151A (zh) 2016-09-16
EP3227787A1 (en) 2017-10-11
BR112017011765A2 (pt) 2018-02-20
CA2964303A1 (en) 2016-06-09
JP2018502379A (ja) 2018-01-25

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