JP6672285B2 - 高密度ファンアウトパッケージ構造 - Google Patents
高密度ファンアウトパッケージ構造 Download PDFInfo
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- JP6672285B2 JP6672285B2 JP2017521532A JP2017521532A JP6672285B2 JP 6672285 B2 JP6672285 B2 JP 6672285B2 JP 2017521532 A JP2017521532 A JP 2017521532A JP 2017521532 A JP2017521532 A JP 2017521532A JP 6672285 B2 JP6672285 B2 JP 6672285B2
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- conductive
- layer
- package structure
- conductive interconnect
- interconnect
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01073—Tantalum [Ta]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15313—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a land array, e.g. LGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
- H01L2924/15321—Connection portion the connection portion being formed on the die mounting surface of the substrate being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Geometry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Wire Bonding (AREA)
- Packages (AREA)
- Linear Motors (AREA)
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201462073804P | 2014-10-31 | 2014-10-31 | |
| US62/073,804 | 2014-10-31 | ||
| US14/693,820 | 2015-04-22 | ||
| US14/693,820 US10157823B2 (en) | 2014-10-31 | 2015-04-22 | High density fan out package structure |
| PCT/US2015/048514 WO2016069112A1 (en) | 2014-10-31 | 2015-09-04 | High density fan out package structure |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2017534177A JP2017534177A (ja) | 2017-11-16 |
| JP2017534177A5 JP2017534177A5 (enExample) | 2018-09-27 |
| JP6672285B2 true JP6672285B2 (ja) | 2020-03-25 |
Family
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2017521532A Active JP6672285B2 (ja) | 2014-10-31 | 2015-09-04 | 高密度ファンアウトパッケージ構造 |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US10157823B2 (enExample) |
| EP (1) | EP3213345B1 (enExample) |
| JP (1) | JP6672285B2 (enExample) |
| KR (1) | KR102440270B1 (enExample) |
| CN (1) | CN107078119B (enExample) |
| BR (1) | BR112017008727B1 (enExample) |
| SG (1) | SG11201701990SA (enExample) |
| WO (1) | WO2016069112A1 (enExample) |
Families Citing this family (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9728507B2 (en) * | 2011-07-19 | 2017-08-08 | Pfg Ip Llc | Cap chip and reroute layer for stacked microelectronic module |
| US20170047276A1 (en) * | 2015-08-13 | 2017-02-16 | Advanced Semiconductor Engineering, Inc. | Semiconductor device package and method of manufacturing the same |
| US9761509B2 (en) | 2015-12-29 | 2017-09-12 | United Microelectronics Corp. | Semiconductor device with throgh-substrate via and method for fabrication the semiconductor device |
| US10141198B2 (en) * | 2016-07-08 | 2018-11-27 | Dyi-chung Hu | Electronic package and manufacturing method thereof |
| CN110024111B (zh) | 2016-12-30 | 2024-03-19 | 英特尔公司 | 带有具有用于扇出缩放的柱和过孔连接的高密度互连层的封装衬底 |
| US10050021B1 (en) * | 2017-02-16 | 2018-08-14 | Nanya Technology Corporation | Die device, semiconductor device and method for making the same |
| US11699651B2 (en) | 2017-10-23 | 2023-07-11 | Applied Materials, Inc. | Fan-out interconnect integration processes and structures |
| DE102018127448B4 (de) | 2017-11-30 | 2023-06-22 | Taiwan Semiconductor Manufacturing Co. Ltd. | Metallschienenleiter für nicht-planare Halbleiter-Bauelemente |
| US10700207B2 (en) | 2017-11-30 | 2020-06-30 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device integrating backside power grid and related integrated circuit and fabrication method |
| US10804254B2 (en) | 2018-06-29 | 2020-10-13 | Taiwan Semiconductor Manufacturing Company, Ltd. | Fan-out package with cavity substrate |
| US20200212536A1 (en) * | 2018-12-31 | 2020-07-02 | Texas Instruments Incorporated | Wireless communication device with antenna on package |
| JP7335036B2 (ja) * | 2019-03-29 | 2023-08-29 | ラピスセミコンダクタ株式会社 | 半導体パッケージの製造方法 |
| KR102615198B1 (ko) | 2019-10-15 | 2023-12-18 | 삼성전자주식회사 | 반도체 패키지 |
| KR102765303B1 (ko) | 2019-12-31 | 2025-02-07 | 삼성전자주식회사 | 반도체 패키지 |
| US12166003B2 (en) * | 2020-04-03 | 2024-12-10 | Macom Technology Solutions Holdings, Inc. | RF amplifier devices including top side contacts and methods of manufacturing |
| US11356070B2 (en) | 2020-06-01 | 2022-06-07 | Wolfspeed, Inc. | RF amplifiers having shielded transmission line structures |
| US11302662B2 (en) * | 2020-05-01 | 2022-04-12 | Nanya Technology Corporation | Semiconductor package with air gap and manufacturing method thereof |
| CN114743942A (zh) * | 2021-01-07 | 2022-07-12 | 联华电子股份有限公司 | 混合式接合结构及其制作方法 |
| US11682607B2 (en) * | 2021-02-01 | 2023-06-20 | Qualcomm Incorporated | Package having a substrate comprising surface interconnects aligned with a surface of the substrate |
| KR20220126850A (ko) | 2021-03-09 | 2022-09-19 | 삼성전자주식회사 | 반도체 패키지 |
| CN117546291A (zh) * | 2021-06-11 | 2024-02-09 | 株式会社村田制作所 | 半导体装置 |
| TWI884561B (zh) * | 2023-02-13 | 2025-05-21 | 胡迪群 | 半導體基板及其製造方法 |
| US12148688B2 (en) | 2023-02-13 | 2024-11-19 | Dyi-chung Hu | Semiconductor substrate and manufacturing method thereof |
Family Cites Families (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3817463B2 (ja) * | 2001-11-12 | 2006-09-06 | 新光電気工業株式会社 | 多層配線基板の製造方法 |
| US6706625B1 (en) * | 2002-12-06 | 2004-03-16 | Chartered Semiconductor Manufacturing Ltd. | Copper recess formation using chemical process for fabricating barrier cap for lines and vias |
| US6927159B2 (en) * | 2003-05-27 | 2005-08-09 | Texas Instruments Incorporated | Methods for providing improved layer adhesion in a semiconductor device |
| TWI286372B (en) | 2003-08-13 | 2007-09-01 | Phoenix Prec Technology Corp | Semiconductor package substrate with protective metal layer on pads formed thereon and method for fabricating the same |
| US9460951B2 (en) * | 2007-12-03 | 2016-10-04 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of wafer level package integration |
| US8513119B2 (en) * | 2008-12-10 | 2013-08-20 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method of forming bump structure having tapered sidewalls for stacked dies |
| US8441124B2 (en) | 2010-04-29 | 2013-05-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Cu pillar bump with non-metal sidewall protection structure |
| US9048233B2 (en) * | 2010-05-26 | 2015-06-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package systems having interposers |
| US8330274B2 (en) * | 2010-09-29 | 2012-12-11 | Infineon Technologies Ag | Semiconductor structure and method for making same |
| US20120282767A1 (en) | 2011-05-05 | 2012-11-08 | Stmicroelectronics Pte Ltd. | Method for producing a two-sided fan-out wafer level package with electrically conductive interconnects, and a corresponding semiconductor package |
| KR101828490B1 (ko) | 2011-08-30 | 2018-02-12 | 삼성전자주식회사 | 관통전극을 갖는 반도체 소자 및 그 제조방법 |
| US8552556B1 (en) | 2011-11-22 | 2013-10-08 | Amkor Technology, Inc. | Wafer level fan out package |
| US8716859B2 (en) * | 2012-01-10 | 2014-05-06 | Intel Mobile Communications GmbH | Enhanced flip chip package |
| US8779559B2 (en) * | 2012-02-27 | 2014-07-15 | Qualcomm Incorporated | Structure and method for strain-relieved TSV |
| US9385006B2 (en) * | 2012-06-21 | 2016-07-05 | STATS ChipPAC Pte. Ltd. | Semiconductor device and method of forming an embedded SOP fan-out package |
| KR20140024674A (ko) * | 2012-08-20 | 2014-03-03 | 삼성전자주식회사 | 관통 비아 구조체 및 재배선 구조체를 갖는 반도체 소자 |
| US9006101B2 (en) | 2012-08-31 | 2015-04-14 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method |
| US8993380B2 (en) | 2013-03-08 | 2015-03-31 | Taiwan Semiconductor Manufacturing Company, Ltd. | Structure and method for 3D IC package |
-
2015
- 2015-04-22 US US14/693,820 patent/US10157823B2/en active Active
- 2015-09-04 BR BR112017008727-8A patent/BR112017008727B1/pt active IP Right Grant
- 2015-09-04 SG SG11201701990SA patent/SG11201701990SA/en unknown
- 2015-09-04 CN CN201580058661.2A patent/CN107078119B/zh active Active
- 2015-09-04 EP EP15767632.1A patent/EP3213345B1/en active Active
- 2015-09-04 JP JP2017521532A patent/JP6672285B2/ja active Active
- 2015-09-04 KR KR1020177011236A patent/KR102440270B1/ko active Active
- 2015-09-04 WO PCT/US2015/048514 patent/WO2016069112A1/en not_active Ceased
Also Published As
| Publication number | Publication date |
|---|---|
| US10157823B2 (en) | 2018-12-18 |
| US20160126173A1 (en) | 2016-05-05 |
| BR112017008727A2 (pt) | 2017-12-19 |
| WO2016069112A1 (en) | 2016-05-06 |
| JP2017534177A (ja) | 2017-11-16 |
| EP3213345B1 (en) | 2021-01-13 |
| KR20170077133A (ko) | 2017-07-05 |
| SG11201701990SA (en) | 2017-05-30 |
| CN107078119A (zh) | 2017-08-18 |
| EP3213345A1 (en) | 2017-09-06 |
| CN107078119B (zh) | 2021-05-14 |
| KR102440270B1 (ko) | 2022-09-02 |
| BR112017008727B1 (pt) | 2022-06-28 |
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