JP6672285B2 - 高密度ファンアウトパッケージ構造 - Google Patents

高密度ファンアウトパッケージ構造 Download PDF

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JP6672285B2
JP6672285B2 JP2017521532A JP2017521532A JP6672285B2 JP 6672285 B2 JP6672285 B2 JP 6672285B2 JP 2017521532 A JP2017521532 A JP 2017521532A JP 2017521532 A JP2017521532 A JP 2017521532A JP 6672285 B2 JP6672285 B2 JP 6672285B2
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conductive
layer
package structure
conductive interconnect
interconnect
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JP2017534177A5 (enExample
JP2017534177A (ja
Inventor
ドン・ウク・キム
ホン・ボク・ウィ
ジェ・シク・イ
シーチュン・グ
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クアルコム，インコーポレイテッド
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/099—Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/7424—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self-supporting substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/70—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping
    • H10P72/74—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support
    • H10P72/743—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07202—Connecting or disconnecting of bump connectors using auxiliary members
    • H10W72/07204—Connecting or disconnecting of bump connectors using auxiliary members using temporary auxiliary members, e.g. sacrificial coatings
    • H10W72/07207—Temporary substrates, e.g. removable substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07302—Connecting or disconnecting of die-attach connectors using an auxiliary member
    • H10W72/07304—Connecting or disconnecting of die-attach connectors using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating
    • H10W72/07307—Connecting or disconnecting of die-attach connectors using an auxiliary member the auxiliary member being temporary, e.g. a sacrificial coating the auxiliary member being a temporary substrate, e.g. a removable substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/29—Bond pads specially adapted therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/791—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads
    • H10W90/794—Package configurations characterised by the relative positions of pads or connectors relative to package parts of direct-bonded pads between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Wire Bonding (AREA)
  • Packages (AREA)
  • Linear Motors (AREA)
JP2017521532A 2014-10-31 2015-09-04 高密度ファンアウトパッケージ構造 Active JP6672285B2 (ja)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US201462073804P 2014-10-31 2014-10-31
US62/073,804 2014-10-31
US14/693,820 2015-04-22
US14/693,820 US10157823B2 (en) 2014-10-31 2015-04-22 High density fan out package structure
PCT/US2015/048514 WO2016069112A1 (en) 2014-10-31 2015-09-04 High density fan out package structure

Publications (3)

Publication Number Publication Date
JP2017534177A JP2017534177A (ja) 2017-11-16
JP2017534177A5 JP2017534177A5 (enExample) 2018-09-27
JP6672285B2 true JP6672285B2 (ja) 2020-03-25

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
JP2017521532A Active JP6672285B2 (ja) 2014-10-31 2015-09-04 高密度ファンアウトパッケージ構造

Country Status (8)

Country Link
US (1) US10157823B2 (enExample)
EP (1) EP3213345B1 (enExample)
JP (1) JP6672285B2 (enExample)
KR (1) KR102440270B1 (enExample)
CN (1) CN107078119B (enExample)
BR (1) BR112017008727B1 (enExample)
SG (1) SG11201701990SA (enExample)
WO (1) WO2016069112A1 (enExample)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9728507B2 (en) * 2011-07-19 2017-08-08 Pfg Ip Llc Cap chip and reroute layer for stacked microelectronic module
US20170047276A1 (en) * 2015-08-13 2017-02-16 Advanced Semiconductor Engineering, Inc. Semiconductor device package and method of manufacturing the same
US9761509B2 (en) 2015-12-29 2017-09-12 United Microelectronics Corp. Semiconductor device with throgh-substrate via and method for fabrication the semiconductor device
US10141198B2 (en) * 2016-07-08 2018-11-27 Dyi-chung Hu Electronic package and manufacturing method thereof
DE112016007567T5 (de) * 2016-12-30 2019-11-21 Intel Corporation Gehäusesubstrat mit hochdichte-zwischenverbindungsschicht mit säulen- und via-verbindungen zur fan-out-skalierung
US10050021B1 (en) * 2017-02-16 2018-08-14 Nanya Technology Corporation Die device, semiconductor device and method for making the same
US11699651B2 (en) * 2017-10-23 2023-07-11 Applied Materials, Inc. Fan-out interconnect integration processes and structures
US10700207B2 (en) 2017-11-30 2020-06-30 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device integrating backside power grid and related integrated circuit and fabrication method
DE102018127448B4 (de) 2017-11-30 2023-06-22 Taiwan Semiconductor Manufacturing Co. Ltd. Metallschienenleiter für nicht-planare Halbleiter-Bauelemente
US10804254B2 (en) 2018-06-29 2020-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. Fan-out package with cavity substrate
US20200212536A1 (en) * 2018-12-31 2020-07-02 Texas Instruments Incorporated Wireless communication device with antenna on package
JP7335036B2 (ja) * 2019-03-29 2023-08-29 ラピスセミコンダクタ株式会社 半導体パッケージの製造方法
KR102615198B1 (ko) 2019-10-15 2023-12-18 삼성전자주식회사 반도체 패키지
KR102765303B1 (ko) 2019-12-31 2025-02-07 삼성전자주식회사 반도체 패키지
US12500562B2 (en) 2020-04-03 2025-12-16 Macom Technology Solutions Holdings, Inc. RF amplifier devices and methods of manufacturing including modularized designs with flip chip interconnections
US11356070B2 (en) 2020-06-01 2022-06-07 Wolfspeed, Inc. RF amplifiers having shielded transmission line structures
US12647083B2 (en) 2020-04-03 2026-06-02 Wolfspeed, Inc. RF amplifier devices and methods of manufacturing including modularized designs with flip chip interconnections and integration into packaging
US12166003B2 (en) 2020-04-03 2024-12-10 Macom Technology Solutions Holdings, Inc. RF amplifier devices including top side contacts and methods of manufacturing
US11302662B2 (en) * 2020-05-01 2022-04-12 Nanya Technology Corporation Semiconductor package with air gap and manufacturing method thereof
CN114743942B (zh) * 2021-01-07 2026-02-10 联华电子股份有限公司 混合式接合结构及其制作方法
US11682607B2 (en) * 2021-02-01 2023-06-20 Qualcomm Incorporated Package having a substrate comprising surface interconnects aligned with a surface of the substrate
KR102932521B1 (ko) 2021-03-09 2026-03-04 삼성전자주식회사 반도체 패키지
WO2022259923A1 (ja) * 2021-06-11 2022-12-15 株式会社村田製作所 半導体装置
US12593737B2 (en) 2021-07-30 2026-03-31 Samsung Electronics Co., Ltd. Semiconductor package
US12620530B2 (en) 2022-09-23 2026-05-05 Wolfspeed, Inc. Device and process for implementing silicon carbide (SiC) surface mount devices
TWI884561B (zh) * 2023-02-13 2025-05-21 胡迪群 半導體基板及其製造方法
US12148688B2 (en) 2023-02-13 2024-11-19 Dyi-chung Hu Semiconductor substrate and manufacturing method thereof

Family Cites Families (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3817463B2 (ja) * 2001-11-12 2006-09-06 新光電気工業株式会社 多層配線基板の製造方法
US6706625B1 (en) * 2002-12-06 2004-03-16 Chartered Semiconductor Manufacturing Ltd. Copper recess formation using chemical process for fabricating barrier cap for lines and vias
US6927159B2 (en) * 2003-05-27 2005-08-09 Texas Instruments Incorporated Methods for providing improved layer adhesion in a semiconductor device
TWI286372B (en) 2003-08-13 2007-09-01 Phoenix Prec Technology Corp Semiconductor package substrate with protective metal layer on pads formed thereon and method for fabricating the same
US9460951B2 (en) * 2007-12-03 2016-10-04 STATS ChipPAC Pte. Ltd. Semiconductor device and method of wafer level package integration
US8513119B2 (en) * 2008-12-10 2013-08-20 Taiwan Semiconductor Manufacturing Company, Ltd. Method of forming bump structure having tapered sidewalls for stacked dies
US8441124B2 (en) * 2010-04-29 2013-05-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cu pillar bump with non-metal sidewall protection structure
US9048233B2 (en) * 2010-05-26 2015-06-02 Taiwan Semiconductor Manufacturing Company, Ltd. Package systems having interposers
US8330274B2 (en) * 2010-09-29 2012-12-11 Infineon Technologies Ag Semiconductor structure and method for making same
US20120282767A1 (en) 2011-05-05 2012-11-08 Stmicroelectronics Pte Ltd. Method for producing a two-sided fan-out wafer level package with electrically conductive interconnects, and a corresponding semiconductor package
KR101828490B1 (ko) 2011-08-30 2018-02-12 삼성전자주식회사 관통전극을 갖는 반도체 소자 및 그 제조방법
US8552556B1 (en) 2011-11-22 2013-10-08 Amkor Technology, Inc. Wafer level fan out package
US8716859B2 (en) * 2012-01-10 2014-05-06 Intel Mobile Communications GmbH Enhanced flip chip package
US8779559B2 (en) * 2012-02-27 2014-07-15 Qualcomm Incorporated Structure and method for strain-relieved TSV
US9385006B2 (en) * 2012-06-21 2016-07-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming an embedded SOP fan-out package
KR20140024674A (ko) * 2012-08-20 2014-03-03 삼성전자주식회사 관통 비아 구조체 및 재배선 구조체를 갖는 반도체 소자
US9006101B2 (en) 2012-08-31 2015-04-14 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method
US8993380B2 (en) 2013-03-08 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method for 3D IC package

Also Published As

Publication number Publication date
EP3213345A1 (en) 2017-09-06
BR112017008727B1 (pt) 2022-06-28
KR20170077133A (ko) 2017-07-05
CN107078119B (zh) 2021-05-14
BR112017008727A2 (pt) 2017-12-19
WO2016069112A1 (en) 2016-05-06
KR102440270B1 (ko) 2022-09-02
JP2017534177A (ja) 2017-11-16
US10157823B2 (en) 2018-12-18
EP3213345B1 (en) 2021-01-13
US20160126173A1 (en) 2016-05-05
SG11201701990SA (en) 2017-05-30
CN107078119A (zh) 2017-08-18

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