JP6668337B2 - レジスタファイル回路および最小動作供給電圧を改善するための方法 - Google Patents

レジスタファイル回路および最小動作供給電圧を改善するための方法 Download PDF

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JP6668337B2
JP6668337B2 JP2017515931A JP2017515931A JP6668337B2 JP 6668337 B2 JP6668337 B2 JP 6668337B2 JP 2017515931 A JP2017515931 A JP 2017515931A JP 2017515931 A JP2017515931 A JP 2017515931A JP 6668337 B2 JP6668337 B2 JP 6668337B2
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nfet
header
gate
pfet
coupled
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JP2017529644A (ja
JP2017529644A5 (enExample
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フランソワ・イブラヒム・アタラー
ジフン・ジョン
キース・アラン・ボウマン
アメイ・スドィール・クルカルニ
ジェイソン・フィリップ・マルツロフ
ジョシュア・ランス・パケット
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クアルコム，インコーポレイテッド
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/007—Register arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Power Engineering (AREA)
JP2017515931A 2014-09-26 2015-08-04 レジスタファイル回路および最小動作供給電圧を改善するための方法 Active JP6668337B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US14/499,052 2014-09-26
US14/499,052 US9251875B1 (en) 2014-09-26 2014-09-26 Register file circuit and method for improving the minimum operating supply voltage
PCT/US2015/043602 WO2016048455A1 (en) 2014-09-26 2015-08-04 Register file circuit and method for improving the minimum operating supply voltage

Publications (3)

Publication Number Publication Date
JP2017529644A JP2017529644A (ja) 2017-10-05
JP2017529644A5 JP2017529644A5 (enExample) 2018-08-23
JP6668337B2 true JP6668337B2 (ja) 2020-03-18

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JP2017515931A Active JP6668337B2 (ja) 2014-09-26 2015-08-04 レジスタファイル回路および最小動作供給電圧を改善するための方法

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Country Link
US (1) US9251875B1 (enExample)
EP (1) EP3198608B1 (enExample)
JP (1) JP6668337B2 (enExample)
KR (1) KR102133758B1 (enExample)
CN (1) CN106716541B (enExample)
WO (1) WO2016048455A1 (enExample)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5317900B2 (ja) 2009-09-14 2013-10-16 ルネサスエレクトロニクス株式会社 半導体集積回路およびその動作方法
US10163524B2 (en) 2016-06-22 2018-12-25 Darryl G. Walker Testing a semiconductor device including a voltage detection circuit and temperature detection circuit that can be used to generate read assist and/or write assist in an SRAM circuit portion and method therefor
US9940999B2 (en) 2016-06-22 2018-04-10 Darryl G. Walker Semiconductor devices, circuits and methods for read and/or write assist of an SRAM circuit portion based on voltage detection and/or temperature detection circuits
US11417370B2 (en) 2020-08-12 2022-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Memory device
RU2771447C1 (ru) * 2021-08-03 2022-05-04 Владимир Владимирович Шубин Элемент входного регистра
US11955171B2 (en) 2021-09-15 2024-04-09 Mavagail Technology, LLC Integrated circuit device including an SRAM portion having end power select circuits

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US20070047364A1 (en) * 2005-08-31 2007-03-01 International Business Machines Corporation Methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices
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JP4865360B2 (ja) * 2006-03-01 2012-02-01 パナソニック株式会社 半導体記憶装置
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US7542329B2 (en) * 2006-07-19 2009-06-02 International Business Machines Corporation Virtual power rails for integrated circuits
US7692130B2 (en) * 2006-11-01 2010-04-06 International Business Machines Corporation CMOS imaging sensor having a third FET device with a gate terminal coupled to a second diffusion region of a first FET device and a first terminal coupled to a row select signal
US7414878B1 (en) * 2007-05-04 2008-08-19 International Business Machines Corporation Method for implementing domino SRAM leakage current reduction
JP2009076164A (ja) * 2007-09-21 2009-04-09 Fujitsu Microelectronics Ltd 半導体記憶装置
US7551508B2 (en) * 2007-11-16 2009-06-23 International Business Machines Corporation Energy efficient storage device using per-element selectable power supply voltages
US8099688B2 (en) * 2007-11-19 2012-01-17 International Business Machines Corporation Circuit design
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US8493124B2 (en) 2010-07-26 2013-07-23 Taiwan Semiconductor Manufacturing Company, Ltd. Low minimum power supply voltage level shifter
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Also Published As

Publication number Publication date
EP3198608B1 (en) 2019-11-06
EP3198608A1 (en) 2017-08-02
WO2016048455A1 (en) 2016-03-31
CN106716541B (zh) 2021-06-04
JP2017529644A (ja) 2017-10-05
CN106716541A (zh) 2017-05-24
US9251875B1 (en) 2016-02-02
KR102133758B1 (ko) 2020-07-14
KR20170063609A (ko) 2017-06-08

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