JP6657063B2 - ３トランジスタ２接合ｍｒａｍビットセル - Google Patents

３トランジスタ２接合ｍｒａｍビットセル Download PDF

Info

Publication number
JP6657063B2
JP6657063B2 JP2016238559A JP2016238559A JP6657063B2 JP 6657063 B2 JP6657063 B2 JP 6657063B2 JP 2016238559 A JP2016238559 A JP 2016238559A JP 2016238559 A JP2016238559 A JP 2016238559A JP 6657063 B2 JP6657063 B2 JP 6657063B2
Authority
JP
Japan
Prior art keywords
mtj
transistor
terminal
bit line
current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
JP2016238559A
Other languages
English (en)
Japanese (ja)
Other versions
JP2017152071A (ja
JP2017152071A5 (https=
Inventor
ラフ・アッペルタンス
プラヴィーン・ラガヴァン
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Katholieke Universiteit Leuven
Interuniversitair Microelektronica Centrum vzw IMEC
Original Assignee
Katholieke Universiteit Leuven
Interuniversitair Microelektronica Centrum vzw IMEC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Katholieke Universiteit Leuven, Interuniversitair Microelektronica Centrum vzw IMEC filed Critical Katholieke Universiteit Leuven
Publication of JP2017152071A publication Critical patent/JP2017152071A/ja
Publication of JP2017152071A5 publication Critical patent/JP2017152071A5/ja
Application granted granted Critical
Publication of JP6657063B2 publication Critical patent/JP6657063B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1675—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1653—Address circuits or decoders
    • G11C11/1657—Word-line or row circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1659—Cell access
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
    • G11C11/16—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using elements in which the storage effect is based on magnetic spin effect
    • G11C11/165—Auxiliary circuits
    • G11C11/1673—Reading or sensing circuits or methods

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Mram Or Spin Memory Techniques (AREA)
  • Hall/Mr Elements (AREA)
JP2016238559A 2015-12-09 2016-12-08 ３トランジスタ２接合ｍｒａｍビットセル Active JP6657063B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP15198573 2015-12-09
EP15198573.6 2015-12-09

Publications (3)

Publication Number Publication Date
JP2017152071A JP2017152071A (ja) 2017-08-31
JP2017152071A5 JP2017152071A5 (https=) 2019-12-12
JP6657063B2 true JP6657063B2 (ja) 2020-03-04

Family

ID=54838247

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2016238559A Active JP6657063B2 (ja) 2015-12-09 2016-12-08 ３トランジスタ２接合ｍｒａｍビットセル

Country Status (2)

Country Link
US (1) US10127961B2 (https=)
JP (1) JP6657063B2 (https=)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP6421309B2 (ja) * 2013-09-30 2018-11-14 テンパール工業株式会社 端子台
EP3435413A1 (en) * 2017-07-28 2019-01-30 IMEC vzw A semiconductor device and a method for forming a semiconductor device
US11290110B2 (en) * 2017-10-26 2022-03-29 Samsung Electronics Co., Ltd. Method and system for providing a variation resistant magnetic junction-based XNOR cell usable in neuromorphic computing
US10461751B2 (en) 2018-03-08 2019-10-29 Samsung Electronics Co., Ltd. FE-FET-based XNOR cell usable in neuromorphic computing
US10726896B1 (en) 2019-01-30 2020-07-28 Globalfoundries Inc. Resistive nonvolatile memory structure employing a statistical sensing scheme and method
CN112542189B (zh) * 2019-09-20 2024-07-16 中芯国际集成电路制造(上海)有限公司 磁性存储器及其编程控制方法、读取方法、磁性存储装置
US11101320B2 (en) 2019-10-22 2021-08-24 Samsung Electronics Co., Ltd System and method for efficient enhancement of an on/off ratio of a bitcell based on 3T2R binary weight cell with spin orbit torque MJTs (SOT-MTJs)
TWI852976B (zh) * 2020-01-07 2024-08-21 聯華電子股份有限公司 記憶體
CN112382319B (zh) * 2020-10-10 2023-01-17 中国科学院微电子研究所 一种自参考存储结构和存算一体电路
TW202547280A (zh) * 2024-05-15 2025-12-01 聯華電子股份有限公司 磁阻式隨機存取記憶體電路與佈局結構

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7272034B1 (en) * 2005-08-31 2007-09-18 Grandis, Inc. Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells
US7742329B2 (en) * 2007-03-06 2010-06-22 Qualcomm Incorporated Word line transistor strength control for read and write in spin transfer torque magnetoresistive random access memory
US8995180B2 (en) * 2012-11-29 2015-03-31 Taiwan Semiconductor Manufacturing Company, Ltd. Magnetoresistive random access memory (MRAM) differential bit cell and method of use
US9218877B2 (en) * 2013-06-19 2015-12-22 Broadcom Corporation Differential bit cell

Also Published As

Publication number Publication date
JP2017152071A (ja) 2017-08-31
US20170169873A1 (en) 2017-06-15
US10127961B2 (en) 2018-11-13

Similar Documents

Publication Publication Date Title
JP6657063B2 (ja) ３トランジスタ２接合ｍｒａｍビットセル
US11004490B2 (en) Spin orbit torque magnetoresistive random access memory device
TWI503820B (zh) 數位記憶體裝置以及磁阻式隨機存取記憶體之配置方法
US9508923B2 (en) Magnetic memory using spin orbit interaction
TWI550925B (zh) 數位記憶體、改良磁阻隨機存取記憶體配置以及配置自旋轉移力矩磁阻隨機存取記憶體的方法
CN110827879B (zh) 磁阻存储器中的冗余磁性隧道结
US7894248B2 (en) Programmable and redundant circuitry based on magnetic tunnel junction (MTJ)
US20190334080A1 (en) Memory cell, memory array, method of forming and operating memory cell
EP2320425B1 (en) Selection device for a spin transfer torque magnetoresistive random access memory
JP2005116162A (ja) 直列に接続されたメモリ素子のグループを含む磁気メモリデバイス
US20180061887A1 (en) Magnetoresistive random access memory (mram) with an interconnect that generates a spin current and a magnetic field effect
US11527709B2 (en) SOT multibit memory cell
JP2007518216A (ja) 磁気トンネル接合用の分離書込みおよび読出しアクセスアーキテクチャ
EP3945521A1 (en) Magnetic random access memory cell and method for reading said cell
US7457149B2 (en) Methods and apparatus for thermally assisted programming of a magnetic memory device
Durlam et al. 90nm toggle MRAM array with 0.29/spl mu/m/sup 2/cells
US7986548B2 (en) Current re-routing scheme for serial-programmed MRAM
US20250322861A1 (en) Configuration bit with spin orbit torque
JP5147972B2 (ja) 薄膜磁性体記憶装置

Legal Events

Date Code Title Description
A521 Request for written amendment filed

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20191030

A621 Written request for application examination

Free format text: JAPANESE INTERMEDIATE CODE: A621

Effective date: 20191030

A871 Explanation of circumstances concerning accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A871

Effective date: 20191030

A975 Report on accelerated examination

Free format text: JAPANESE INTERMEDIATE CODE: A971005

Effective date: 20191031

TRDD Decision of grant or rejection written
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 20200107

A61 First payment of annual fees (during grant procedure)

Free format text: JAPANESE INTERMEDIATE CODE: A61

Effective date: 20200205

R150 Certificate of patent or registration of utility model

Ref document number: 6657063

Country of ref document: JP

Free format text: JAPANESE INTERMEDIATE CODE: R150

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250

R250 Receipt of annual fees

Free format text: JAPANESE INTERMEDIATE CODE: R250