JP6649765B2 - Thin film transistor and method of manufacturing thin film transistor - Google Patents

Description

  The present invention relates to a thin film transistor and a method for manufacturing the thin film transistor.

  Conventionally, as a semiconductor material used for a field effect transistor, an inorganic material such as amorphous silicon or polysilicon formed on a silicon single crystal or a glass substrate is generally used. On the other hand, a field-effect transistor using an organic semiconductor as described in Patent Document 1, for example, is easier to form at a lower temperature and has a larger area than those using an inorganic semiconductor as described above. However, the cost can be reduced because of the simplicity. Moreover, since it has the property of being rich in flexibility unique to organic substances, it is considered to be applied to flexible substrates such as plastics, and development has been particularly advanced recently.

However, in an organic thin film transistor using an active layer composed of an organic semiconductor film of this type, the mobility of electrons and holes in the active layer is generally smaller than that of an inorganic semiconductor, and therefore, compared to an inorganic semiconductor field-effect transistor. There is a problem that the current that can be controlled is small.
For this purpose, search and structural studies of organic semiconductor materials having a large mobility so that a larger amount of current can flow are being advanced, but at present, they have not achieved sufficient results.

Patent Documents 2 and 3 disclose a double gate structure in which gate electrodes are arranged above and below a semiconductor layer, but do not disclose a method of electrically connecting the gate electrodes above and below the semiconductor layer.
Patent Documents 4 and 5 disclose a double gate structure in which gate electrodes are arranged above and below a semiconductor layer, similarly to Patent Documents 2 and 3. In a contact plug for electrically connecting upper and lower gate electrodes, a contact hole is formed by etching a gate insulating film on the lower gate electrode, and a contact plug is formed in the contact hole.

JP-A-02-074075 JP 2000-323715 A JP 2005-79549 A JP 2011-233889 A JP 2003-338628 A

An object of the present invention is to provide a thin film transistor in which the upper and lower gate electrodes of a thin film transistor having two or more gate electrodes are electrically connected so that more current can be controlled and passed. is there.
SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a thin film transistor in which the upper and lower gate electrodes of a thin film transistor having two or more gate electrodes can be easily connected between layers.

To manufacture a thin film transistor having two or more gate electrodes, a contact hole is formed by etching a gate insulating film on a lower gate electrode to form a contact plug for electrically connecting the two gate electrodes. In such a case, the number of steps of forming a contact plug therein is required, and there has been a problem of lowering the yield.
The present inventors have found that the above problem can be solved by forming a convex-shaped conductor by printing and baking a composition containing metal particles on a lower gate electrode by various printing methods such as ink-jet printing and baking. .

1.2. A thin film transistor having at least two gate electrodes, wherein two of the two or more gate electrodes are electrically connected by a convex conductor containing metal particles.
2. 2. The thin film transistor according to claim 1, wherein the conductor includes a liquid repellent material.
3. 3. The thin film transistor according to claim 2, wherein the liquid repellent material is exposed on the surface of the conductor.
4. 4. The thin film transistor according to 2 or 3, wherein the liquid repellent material is a fluorine-containing compound.
5. The thin film transistor according to any one of claims 2 to 4, wherein the liquid repellent material is a fluorine-containing thiol compound.
6. The thin film transistor according to any one of claims 1 to 5, wherein the conductor has a surface energy of 10 mN / m to 80 mN / m.
7. An insulating layer between two gate electrodes electrically connected by the conductor;
The conductor is formed on one gate electrode through the insulating layer,
The thin film transistor according to any one of claims 1 to 6, wherein a height of the conductor is 0.5 to 10 times the thickness of the insulating layer in the one gate electrode.
8. The thin film transistor according to any one of claims 1 to 7, wherein the diameter of the conductor is 10 µm or more and 100 µm or less.
9. The thin film transistor according to any one of 1 to 8, which has two gate electrodes.
10. 10. The thin film transistor according to any one of 1 to 9, wherein the semiconductor layer of the thin film transistor is a semiconductor layer made of an organic semiconductor material.
11. A convex conductor is formed by printing and firing a composition containing metal particles on a gate electrode, and the convex conductor electrically connects the gate electrode to another gate electrode. A method for manufacturing a thin film transistor having two or more gate electrodes.
12. 12. The method for manufacturing a thin film transistor according to 11, wherein the composition includes a liquid repellent material.
13. 13. The method for manufacturing a thin film transistor according to 12, wherein the liquid repellent material is a fluorine-containing compound.
14． 14. The method for manufacturing a thin film transistor according to 12 or 13, wherein the liquid repellent material is a fluorine-containing thiol compound.
15. 15. The method of manufacturing a thin film transistor according to any one of items 11 to 14, wherein the printing is performed by an inkjet process.
16. An electronic apparatus, comprising: the thin film transistor according to any one of 1 to 10.

According to the present invention, it is possible to provide a thin film transistor in which upper and lower gate electrodes of a thin film transistor having two or more gate electrodes are electrically connected so that more current can be controlled and flow.
According to the present invention, it is possible to provide a method of manufacturing a thin film transistor in which the upper and lower gate electrodes of a thin film transistor having two or more gate electrodes can be easily connected between layers.

FIG. 3 is a diagram illustrating a method for manufacturing a thin film transistor according to one embodiment of the present invention. FIG. 3 is a diagram illustrating a method for manufacturing a thin film transistor according to one embodiment of the present invention. FIG. 3 is a diagram illustrating a method for manufacturing a thin film transistor according to one embodiment of the present invention. FIG. 3 is a diagram illustrating a method for manufacturing a thin film transistor according to one embodiment of the present invention. FIG. 3 is a diagram illustrating a method for manufacturing a thin film transistor according to one embodiment of the present invention. FIG. 3 is a diagram illustrating a method for manufacturing a thin film transistor according to one embodiment of the present invention. FIG. 3 is a diagram illustrating a method for manufacturing a thin film transistor according to one embodiment of the present invention. FIG. 2 is a diagram illustrating a structure of a thin film transistor according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a structure of a thin film transistor according to an embodiment of the present invention. FIG. 2 is a diagram illustrating a structure of a thin film transistor according to an embodiment of the present invention. FIG. 4 is a view illustrating a structure of a thin film transistor according to another embodiment of the present invention. FIG. 4 is a view illustrating a structure of a thin film transistor according to another embodiment of the present invention. FIG. 4 is a diagram illustrating a method for manufacturing a thin film transistor according to a comparative example of the invention. FIG. 4 is a diagram illustrating a method for manufacturing a thin film transistor according to a comparative example of the invention. FIG. 4 is a diagram illustrating a method for manufacturing a thin film transistor according to a comparative example of the invention. FIG. 4 is a diagram illustrating a method for manufacturing a thin film transistor according to a comparative example of the invention. FIG. 4 is a diagram illustrating a method for manufacturing a thin film transistor according to a comparative example of the invention. FIG. 4 is a diagram illustrating a method for manufacturing a thin film transistor according to a comparative example of the invention. FIG. 4 is a diagram illustrating a method for manufacturing a thin film transistor according to a comparative example of the invention. FIG. 4 is a diagram illustrating a method for manufacturing a thin film transistor according to a comparative example of the invention. FIG. 3 is a diagram illustrating a thin film transistor structure according to a comparative example of the present invention. FIG. 3 is a diagram illustrating a thin film transistor structure according to a comparative example of the present invention. FIG. 3 is a diagram illustrating a thin film transistor structure according to a comparative example of the present invention. It is a figure which shows the longitudinal cross-sectional shape of a convex via post. It is a figure explaining the diameter of a convex via post. It is a figure explaining height of a convex via post.

<Method of manufacturing thin film transistor>
In the method for manufacturing a thin film transistor according to the present invention, a convex-shaped conductor is formed by printing and baking a composition containing metal particles (hereinafter, sometimes referred to as a conductive composition ink) on a gate electrode. Electrically connects the gate electrode to another gate electrode. Thus, a thin film transistor having two or more gate electrodes is manufactured.

The metal particles contained in the conductor composition ink are the origin of the conductivity of the convex conductor.
Examples of the metal species of the metal particles include silver, copper, mercury, tin, indium, nickel, palladium, platinum, and gold. These may be used alone or in combination of two or more. Among these, silver is particularly preferable from the viewpoint of affinity with a liquid repellent material described later.
The metal particles preferably have an average particle size of 1 nm or more and 1000 nm or less. Further, metal nanowires having a diameter of 50 nm or less may be included. The average particle size of the metal particles can be measured by observation with a transmission electron microscope (TEM). Specifically, in a field of view containing about 50 particles, there is a method of measuring the projected area circle equivalent diameters of all the particles and calculating the average thereof.

  The content of the metal particles is preferably from 15% by mass to 75% by mass, and more preferably from 20% by mass to 50% by mass, based on the total amount of the conductive composition ink. When the content of the metal particles is within the above range, a convex conductor can be formed more efficiently.

The conductor composition ink preferably includes a lyophobic material.
The liquid-repellent material imparts liquid-repellency to the convex conductor.
The liquid-repellent material is, for example, a fluorine-containing compound, and preferably a fluorine-containing thiol compound. The fluorine-containing thiol compound can provide the metal particles with liquid repellency while securing the conductivity of the metal particles. Therefore, the convex conductor can achieve both conductivity and liquid repellency.

  The fluorine-containing compound that is a liquid-repellent material is selected from the group consisting of, for example, a fluorine-containing disulfide compound, a fluorine-containing amine compound, a fluorine-containing carboxylic acid compound, a fluorine-containing nitrile compound, a fluorine-containing tellurium compound, and a fluorine-containing selenium compound. It is preferable that at least one kind is used. Among these, a fluorine-containing thiol compound, a fluorine-containing disulfide compound, a fluorine-containing amine compound, and a fluorine-containing carboxylic acid compound are particularly preferable.

  Examples of the fluorine-containing thiol compound include a fluorine-containing thiol compound having an aromatic ring and a thiol compound having a carbon chain having a fluorinated moiety. Among them, at least one compound selected from the group consisting of fluorine-containing thiols having 6 to 20 carbon atoms and having an aromatic ring (preferably a benzene ring) is preferable from the viewpoint of surface modification properties of the metal particles.

  As the fluorine-containing thiol having 6 to 20 carbon atoms having an aromatic ring, specifically, trifluoromethylbenzenethiol (for example, 4-trifluoromethylbenzenethiol, 3-trifluoromethylbenzenethiol), pentafluorobenzenethiol 2,3,5,6-tetrafluorobenzenethiol, 2,3,5,6-tetrafluoro-4- (trifluoromethyl) benzenethiol, 2,3,5,6-tetrafluoro-4-mercaptobenzoic Acid methyl ester, 3,5-bistrifluoromethylbenzenethiol, 4-fluorobenzenethiol and 11- (2,3,4,5,6-pentafluorobenzyloxy) -1-undecanethiol. Among these, trifluoromethylbenzenethiol and 2,3,5,6-tetrafluoro-4- (trifluoromethyl) benzenethiol are particularly preferred from the viewpoint of liquid repellency.

  The content of the liquid repellent material is preferably 10% by mass or less, more preferably 5% by mass or less, based on the total amount of the conductive composition ink. When the content of the liquid repellent material is equal to or less than the upper limit, the dispersibility of the metal particles in the conductive composition ink is not hindered. Further, the lower limit of the content of the liquid repellent material is preferably 0.1% by mass or more from the viewpoint of the liquid repellency of the convex conductor obtained from the conductor composition ink.

The conductor composition ink may include a solvent, which disperses or dissolves the metal particles and the liquid repellent material.
Examples of the solvent include water, alcohol solvents (monoalcohol solvents, diol solvents, polyhydric alcohol solvents, etc.), hydrocarbon solvents, ketone solvents, ester solvents, ether solvents, glyme solvents, halogen solvents. And the like. These solvents may be used alone or as a mixture of two or more. Of these, alcohol solvents are preferred from the viewpoint of printability.

The solvent preferably has a surface tension of 40 mN / m to 65 mN / m at 25 ° C. When the surface tension of the solvent is within the above range, the conductive composition ink can be sufficiently adhered to the base. The surface tension can be measured by a pendant drop method.
Examples of the alcohol solvent having a surface tension of 40 mN / m to 65 mN / m at 25 ° C include ethylene glycol, glycerin, and 1,3-propanediol. Among these, 1,3 propanediol is particularly preferred.

  The content of the solvent is preferably from 25% by mass to 85% by mass, more preferably from 50% by mass to 80% by mass, based on the total amount of the conductive composition ink. When the content of the solvent is within the above range, the conductive composition ink can be appropriately applied.

The conductor composition ink may include an optional component in addition to the components described above.
Various optional components include dispersants and the like.
These optional components are preferably 10% by mass or less based on the total amount of the conductive composition ink.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
The embodiments described below can be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. The embodiments of the present invention are provided to more completely explain the present invention to those having ordinary skill in the art. In the drawings, the thickness of layer regions may be exaggerated relative to actual thickness for clarity. Also, if a layer is referred to as being on another layer or substrate, it can be formed directly on the other layer or substrate, or with a third layer interposed between them. Can also. Like reference numerals throughout the embodiments denote like components.

FIGS. 1A to 1G are views for explaining an embodiment of a method for manufacturing a thin film transistor according to the present invention.
FIG. 1A is a plan view of an intermediate product according to the present embodiment in which a gate line is formed. In addition, FIGS. 1B to 1G show a cross section in a first direction (II ′) and a cross section in a second direction (II-II ′) of FIG. 1A for convenience of description.
Here, the gate line is for transmitting a gate signal, and is provided in a line shape extended in a first direction II ′ of FIG. 2A, and the data line is for transmitting a data signal. And provided in the form of a line extending in the second direction II-II ′.

Referring to FIG. 1B, a buffer film 110 is formed on a substrate 100.
The substrate 100 may be, for example, a glass substrate or a plastic substrate. The buffer film 110 is for preventing diffusion of moisture or impurities generated from the substrate 100, and is, for example, a single layer of an organic polymer insulating film, a silicon oxide film, a silicon nitride film, or an aluminum oxide film. It may be formed or may be formed of multiple layers in which these are laminated.

Next, lower gate electrodes 120A and 120B of the double gate transistor are formed on the buffer film 110. As shown in FIG. 1A, the lower gate electrode 120A corresponds to the line portion of the T-shaped gate line 120, and the lower gate electrode 120B corresponds to the protrusion of the T-shaped gate line 120.
Hereinafter, for convenience of description, a protruding portion of the gate line 120 is denoted by reference numeral '120B', and a line portion adjacent to the protruding portion is denoted by reference numeral '120A'. In FIG. 1B, the lower gate electrodes 120A and 120B are illustrated as being divided into two regions, but this is one pattern.

The lower gate electrodes 120A and 120B are made of, for example, various print forming films such as a film obtained by firing a conductive paste printed by a reverse printing method, or an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd). It may be formed as a single layer, or may be formed as a multilayer in which a molybdenum (Mo) alloy and an aluminum alloy are stacked.
When the lower gate electrodes 120A and 120B are transparent, the lower gate electrodes 120A and 120B may be formed of a single layer of ITO (Indium Tin Oxide), or may be formed of multiple layers of a silver alloy and an ITO layer. .

  Next, the conductive vial 160 is formed by printing the above-described conductive composition ink by various printing methods such as ink-jet printing and baking on the structure of the resultant product having the lower gate electrode 120A formed thereon. The via post preferably corresponds to a convex-shaped conductor and preferably has liquid repellency.

The printing method of the conductor composition ink is not particularly limited as long as it can be printed in a predetermined pattern. For example, an ink jet method, a dispenser method, a screen printing method, a gravure printing method, a gravure offset printing method, a reverse offset printing method And a letterpress printing method. In the present embodiment, it is preferable to use an inkjet method.
The method for firing the coating film made of the conductor composition ink is not particularly limited as long as the solvent contained in the conductor composition ink can be removed and the conductor composition ink can be solidified, and a general firing method can be used. it can. Specifically, baking can be performed using a hot plate or the like.
Before or during baking, a treatment for stimulating the transfer of the liquid-repellent material by irradiating ultrasonic waves or the like may be performed.

The sintering temperature and the sintering time of the coating film made of the conductor composition ink are appropriately adjusted according to the type of the solvent, the liquid repellent material, etc. contained in the conductor composition ink.
The firing temperature is not particularly limited as long as the solvent contained in the conductor composition ink can be removed, but is preferably 100 ° C to 220 ° C, and is preferably 120 ° C to 200 ° C. Is more preferred. If the firing temperature is too high, the metal particles may be deteriorated and it may be difficult to exhibit the desired conductivity. If the firing temperature is too low, the solvent may remain in the convex via posts, and impurities may be mixed into the insulating layer in the insulating layer forming step described later.

The baking time is not particularly limited as long as the solvent contained in the conductive composition ink can be removed, but is preferably from 10 minutes to 60 minutes, and preferably from 15 minutes to 60 minutes. Is more preferable, and it is particularly preferable that it is 30 minutes or more and 60 minutes or less.
If the firing time is too short, when the conductive composition ink contains a liquid-repellent material, it is difficult to sufficiently transfer the liquid-repellent material, so that the liquid repellency of the convex via post is improved. This can be difficult. On the other hand, if the firing time is too long, the metal particles and the like may be deteriorated, making it difficult to exhibit the desired conductivity, and the productivity may be reduced.

Next, a first gate insulating layer 130 is formed on the entire structure of the resultant structure in which the lower gate electrodes 120A and 120B and the via posts 160 are formed. Here, the first gate insulating film 130 is, for example, an organic polymer insulating film formed by a coating process. The organic polymer insulating film is preferably formed as a single layer or as a multi-layer in which these layers are stacked.
In the above coating process, the via post 160 repels the insulating film solution, and the via post 160 can protrude from the first gate insulating film 130.

As shown in FIG. 1C, a source electrode 162 and a drain electrode 164 are formed on the first gate insulating layer 130. Here, the source electrode 162 and the drain electrode 164 are made of, for example, various print forming films such as a film obtained by firing a conductive paste printed by a reverse printing method, or aluminum (Al) or aluminum-neodymium (Al-Nd). It is preferable to form a single aluminum alloy layer or multiple layers in which a molybdenum (Mo) alloy and an aluminum alloy are stacked.
In the case where the source electrode 162 and the drain electrode 164 are formed of transparent electrodes, it is preferable that the source electrode 162 and the drain electrode 164 be formed of a single layer of an ITO film or a multilayer in which a silver alloy and an ITO film are stacked.

  As shown in FIG. 1D, a channel film (semiconductor layer) 140 is formed on the first gate insulating film 130 between the source electrode 162 and the drain electrode 164. In order to electrically connect the channel layer 140 to the source electrode 162 and the drain electrode 164, it is preferable to pattern the sidewalls and a part of the upper portion of the source electrode 162 and the drain electrode 164. A protection film 150 may be formed as shown in FIG. The channel film 140 and the protection film 150 are formed on a part of the lower gate electrode 120B corresponding to the protrusion of the lower gate electrode.

  The channel film 140 can be formed using, for example, an organic semiconductor, but is not limited thereto, and may be formed using an oxide semiconductor, a silicon semiconductor, or the like.

  The protective film 150 may be a fluorine-based organic polymer insulating film, but is not limited thereto. The protective film 150 may be formed as a single layer of a silicon oxide film, a silicon nitride film, or an aluminum oxide film, or may be formed by laminating them. It can be formed of multiple layers.

As shown in FIG. 1E, the protrusions formed by printing and firing a conductive composition ink on the via posts 160 and the drain electrodes 164 protruding from the first gate insulating film 130 by various printing methods such as inkjet, and the like. Form via posts 161 and 200 are formed. This via post preferably has liquid repellency. The convex via posts 161 and 200 can be formed in the same manner as the via posts 160, respectively.
The via post 161 on the via post 160 may not be formed if the via post 160 has a sufficient height.

Next, a second gate insulating film 170 is formed on the entire structure of the resultant structure in which the via posts 161 and 200, the channel film 140, the protective film 150, the source electrode 162, and the drain electrode 164 are formed.
Here, the second gate insulating film 170 is, for example, an organic polymer insulating film formed by a coating process. The organic polymer insulating film is preferably formed as a single layer or as a multi-layer in which these layers are stacked.
In the above coating process, the insulating film solution is repelled from above the via posts 161 and 200, and the via posts 161 and 200 can be made to protrude from the second gate insulating film 170.

As shown in FIG. 1F, an upper gate electrode 180 is formed on the second gate insulating film 170.
The upper gate electrode 180 is made of, for example, various print forming films such as a film obtained by firing a conductive paste printed by a reverse printing method, or a single layer of an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd). It may be formed, or may be formed as a multilayer in which a molybdenum (Mo) alloy and an aluminum alloy are laminated.
When the upper gate electrode 180 is transparent, the upper gate electrode 180 may be formed of a single layer of an ITO film, or may be formed of multiple layers of a silver alloy and an ITO film.

  The upper gate electrode 180 is electrically connected to the lower gate electrode 120A through the via posts 160 and 161. Thus, a double gate transistor including the lower gate electrode 120A and the upper gate electrode 180 connected by the via posts 160 and 161 is formed.

Next, on the via post 200 protruding from the second gate insulating film 170, a conductive vial 201 is formed by printing and firing a conductive composition ink by various printing methods such as inkjet. This via post preferably has liquid repellency.
Note that the via posts 201 on the via posts 200 need not be formed if the via posts 200 have a sufficient height.

Next, an interlayer insulating film 190 is formed on the entire structure of the resultant structure on which the second gate insulating film 170 and the via posts 201 are formed. An example of the interlayer insulating film 190 is an organic polymer insulating film formed by a coating process. The organic polymer insulating film is preferably formed as a single layer or as a multi-layer in which these layers are stacked.
In the above coating process, the interlayer insulating film solution is repelled from above the via posts 201, and the via posts 201 can be made to protrude from the interlayer insulating film 190.

As shown in FIG. 1g, a first functional electrode 182 is formed on the via post 201.
The upper gate electrode 180 and the first functional electrode 182 are electrically insulated from each other by the interlayer insulating film 190.

The first functional electrode 182 may be a pixel electrode of a display device such as an organic light emitting display or a liquid crystal display, and is electrically connected to the source electrode 162 or the drain electrode 164. In this drawing, as an example, a case where the first functional electrode 182 and the drain electrode 164 are connected is shown.
Thus, a thin film transistor according to one embodiment of the present invention is formed.

<Thin film transistor>
The thin film transistor of the present invention is a thin film transistor having two or more layers of gate electrodes, wherein two of the two or more gate electrodes are electrically connected by a convex conductor containing metal particles. The thin film transistor of the present invention is a transistor obtained by the above-described method for manufacturing a thin film transistor of the present invention.
The "thin film transistor having two or more layers of gate electrodes" is a thin film transistor having a structure called a double gate structure, a dual gate structure, a bottom-top gate structure, a double gate structure, a multi-gate structure, or the like.

2A to 2C are views illustrating a structure of a thin film transistor according to an exemplary embodiment of the present invention.
FIG. 2A is a plan view of an intermediate product in which one double gate transistor and one first functional electrode are formed, FIG. 2B is a cross-sectional view in a first direction (II ′) of FIG. 2A, FIG. 2C is a cross-sectional view in the second direction (II-II ′) of FIG. 2A.

As shown in FIG. 2B, the thin film transistor according to an embodiment of the present invention includes a lower gate electrode 120, an upper gate electrode 180 formed on the lower gate electrode 120, and a lower gate electrode 120 and an upper gate electrode 180. And a via post 160 and a via post 161 which are connected to each other.
In the present embodiment, the via posts 160 and the via posts 161 correspond to convex conductors including metal particles, respectively. In FIG. 2, the lower gate electrode and the upper gate electrode are electrically connected by two convex via posts. However, if the height is sufficient, the lower gate electrode and the upper gate electrode are electrically connected by one convex via post. Is also good.

  The metal particles included in the via post and the lyophobic material optionally included are the same as the metal particles and the lyophobic material included in the conductive composition ink described in the method for manufacturing a thin film transistor of the present invention.

When the convex via post includes a liquid repellent material, the convex via post exhibits liquid repellency. Here, “the convex via post has liquid repellency” means that, for example, in FIG. 2B, the contact angle between the surface of the convex via post 160 and water is the contact angle between the surface of the lower gate electrode 120 and water. And a contact angle between the surface of the buffer film 110 and water.
For example, the contact angle between the surface of the convex via post 160 and water is preferably 5 ° or more, more preferably 20 ° or more, between the contact angle of the surface of the lower gate electrode 120 and water. If the difference between the two contact angles is small, it may be difficult to flip the resin composition by utilizing the difference in wettability when the resin composition is applied on the lower gate electrode on which the via posts are formed. is there.
The upper limit of the difference between the contact angles is appropriately determined according to the material of the via post, the material of the gate electrode, and the like, and is not particularly limited, but is, for example, about 100 °.

Further, for example, the difference between the contact angle between the surface of the via post 160 and water and the contact angle between the surface of the buffer film 110 and water is preferably 5 ° or more, and more preferably 20 ° or more. If the difference between the two contact angles is small, it may be difficult to flip the resin composition by utilizing the difference in wettability when the resin composition is applied to the lower electrode on which the via posts are formed. .
The upper limit of the contact angle difference is appropriately determined according to the material of the via post, the material of the buffer film, and the like, and is not particularly limited, but is, for example, about 100 °.

  The plan view shape of the convex via post is not particularly limited as long as the via post can be formed, and examples thereof include a circular shape, an elliptical shape, a square shape, and a polygonal shape. Especially, it is preferable that the planar view shape of the convex via post is circular or elliptical.

FIG. 6 is an explanatory diagram illustrating a vertical cross-sectional shape of the convex via post in the present embodiment. The vertical cross-sectional shape of the convex via post refers to the cross-sectional shape of the convex via post perpendicular to the lower gate electrode.
Specific vertical cross-sectional shapes of the convex via posts include a semicircular shape as shown in FIG. 6A, a semi-elliptical shape as shown in FIG. 6B, a trapezoidal shape (not shown), and a square shape. And the like. In addition, these shapes may have a flat portion or a depression in the center. FIG. 6C shows a semi-elliptical shape having a flat portion at the center.

The diameter of the convex via post is not particularly limited as long as the lower gate electrode and the upper gate electrode can be electrically connected via the convex via post, but is preferably, for example, 1 μm or more and 5000 μm or less. The thickness is more preferably 5 μm or more and 1000 μm or less, particularly preferably 10 μm or more and 100 μm or less.
If the convex via posts are too large, it may be difficult to achieve high definition and high integration of the thin film transistor. If the convex via posts are too small, it may be difficult to make the lower gate electrode and the upper gate electrode conductive well.
The "diameter of the convex via post" refers to the size of the planar view of the convex via post. For example, when the planar view is circular, it refers to the diameter, and the planar view is square. In the case of, it means the width of one side. When the shape in plan view is a shape having a short side and a long side such as a rectangle and an ellipse, the width of the short side is referred to. When the shape in a plan view is a polygonal shape, it refers to the diameter of an inscribed circle.
Specifically, the size of the convex via post refers to a distance indicated by u in FIG.

It is preferable that the height of the via posts be 0.5 to 10 times the thickness of the insulating layer on the gate electrode.
A specific numerical value of the height of the convex via post is preferably, for example, 10 nm or more and 15000 nm or less, and more preferably 100 nm or more and 10000 nm or less. If the height of the convex via post is too high, it may be difficult to improve the flatness of the upper gate electrode side surface. If it is too low, it may be difficult for the convex via post to exhibit desired conductivity.
The “height of the convex via post” refers to a value of a portion where the vertical distance of the insulating film is maximum in the vertical cross-sectional shape of the convex via post, and is a distance indicated by x in FIG. Say. y is the thickness of the insulating film on the gate electrode, and x is preferably 0.5 to 10 times y.

The aspect ratio (height / diameter) of the convex via post is not particularly limited, but is preferably 0.001 or more and 1 or less, more preferably 0.01 or more and 0.8 or less, and 0 or less. It is particularly preferred that the ratio be from 0.01 to 0.5.
When the aspect ratio of the convex via post is too large, it may be difficult to form the convex via post itself, or the convex via post may be easily damaged. Further, when the aspect ratio of the convex via post is too small, it may be difficult for the convex via post to exhibit sufficient conductivity and liquid repellency.

The convex via post preferably has a surface energy of 10 mN / m or more and 80 mN / m or less.
The surface energy of the convex via post is adjusted by, for example, the content of the liquid repellent material. If the surface energy is smaller than the lower limit, metal particles in the convex via posts may be agglomerated. On the other hand, if the surface energy is larger than the upper limit, the liquid repellency may be reduced, and the gate insulating layer may not be able to be opened.
The surface energy in the present embodiment is, for example, that 1 microliter of a liquid is dropped on a measurement target, the shape of the dropped droplet is observed from a side surface, and the angle between the droplet and the measurement target is measured. By the geometric averaging method based on the extended Fowkes equation of Kitazaki and Hata from the values of the contact angles measured in each solvent (Yoshiaki Kitazaki, Toshio Hata et al., Journal of the Adhesion Society of Japan, Vol. 8) (3) Pages 131-141 (1972)).
The contact angle in the present embodiment can be measured using, for example, a contact angle measuring device manufactured by Imoto Seisakusho or a contact angle meter DM-901 manufactured by Kyowa Interface Science.

  2A to 2C, the lower gate electrode 120 and the upper gate electrode 180 are electrically connected by the convex via posts 160 and 161 so that the lower gate electrode 120 and the upper gate electrode 180 are simultaneously driven. Become. The conventional double-gate transistor is generally driven by independently applying a voltage to the lower gate electrode and the upper gate electrode, whereas the double-gate transistor according to the present embodiment is driven by the lower gate electrode and the upper gate electrode. The electrodes are driven simultaneously.

3A and 3B are views illustrating another embodiment of the thin film transistor of the present invention.
In FIG. 2B, the lower gate electrode and the upper gate electrode are connected by each transistor, but in the other embodiment, as shown in FIGS. 3A and 3B, an electrode extraction portion of the lower gate electrode and the upper gate electrode. By forming a via post (III-III 'portion in FIG. 3B), only one via post is formed, and the lower and upper gate electrodes are electrically connected.
Note that II-II ′ in FIG. 3A has the same form as FIG. 2C.

The thin film transistor of the present invention can be used for various uses such as a display device and a sensor.
For example, in the case of an organic electroluminescent display device in which a thin film transistor is a display device to which an organic light emitting element is applied, the first functional electrode 182 may be used as a pixel electrode. In addition, the light emitting device further includes an organic light emitting layer formed on the first functional electrode 182 and a common electrode.

  As another example, when the thin film transistor is a display device to which a liquid crystal display element is applied, the first functional electrode 182 is used as a pixel electrode. In addition, the liquid crystal display further includes an alignment film, a short portion, a sealant, and a spacer formed on the first functional electrode 182, and further includes a color filter substrate including a common electrode, a color filter, and a liquid crystal.

As another example, when the thin film transistor is a sensor, the first functional electrode 182 is used as a lower electrode of the sensor. In addition, it further includes a spacer formed on the first functional electrode 182 and an upper electrode of the sensor.
The thin film transistor of the present invention can be applied to not only a contact type and a capacitance type sensor but also an optical sensor.

  By applying the double gate transistor having such a high on-state current to a display device and a sensor, a display device with high image quality and a large area can be provided, and the performance of the sensor can be improved.

A conventional single gate transistor has a low field-effect mobility of 0.01 to ¹ cm ² / Vs in the case of an organic thin film transistor using an organic semiconductor, and thus realizes a display device and a sensor with a large area and high image quality. There is a limit to doing. On the other hand, the thin film transistor of the present invention uses a double gate transistor having a field effect mobility that is at least twice as high as that of a single gate transistor.

  A conventional single-gate transistor has a structure of a channel film, a gate insulating film, and a gate electrode. When an electric field is applied to the gate electrode, charges are accumulated in the channel film near the interface with the gate insulating film. On the other hand, since the double gate transistor has a structure of a lower gate electrode, a first gate insulating film, a channel film, a second gate insulating film, and an upper gate electrode, a lower interface of the channel film in contact with the first gate insulating film and Electric charges are accumulated at the upper interface of the channel film in contact with the second gate insulating film. Therefore, in the double-gate thin-film transistor, the area in which charges can move is twice as large as that of a single-gate thin-film transistor, so that the channel resistance of the element is halved and the on-current is doubled.

<Comparison form>
FIGS. 4A to 4H show a comparative example of the method for manufacturing a thin film transistor of the present invention.
4A to 4H are views showing a comparative example of a method of manufacturing a thin film transistor using a process of partially removing an insulating film by etching, exposing a lower electrode, and forming a contact hole.
FIG. 4A is a plan view illustrating an intermediate product according to a comparative example in which a gate line is formed. 4B to 4H show a cross section in the third direction (IV-IV ') and a cross section in the fourth direction (VV') of FIG. 4A together for convenience of description.

As shown in FIG. 4B, a buffer film 110 is formed on the substrate 100.
Next, after forming a conductive film for a lower gate electrode on the buffer film 110, the conductive film is patterned to form lower gate electrodes 120A and 120B of the double gate transistor. At this time, as shown in FIG. 4A, the lower gate electrodes 120A and 120B are formed in a form having a line portion and a protrusion protruding from the line portion, that is, a T-shaped gate line 120. As in FIG. 1, for convenience of description, the protruding portion of the gate line 120 is denoted by reference numeral '120B', and the line portion adjacent to the protruding portion is denoted by reference numeral '120A'. That is, in FIG. 4B, although the lower gate electrodes 120A and 120B are illustrated as being divided into two regions, this is one pattern.

  Next, a first gate insulating layer 130 is formed on the entire structure of the resultant structure on which the lower gate electrodes 120A and 120B are formed.

Referring to FIG. 4C, the first gate insulating layer 130 is etched to expose the surface of the lower gate electrode 120A, thereby forming a first contact hole C1. At this time, the first contact hole C1 is formed such that the surface of the lower gate electrode 120A corresponding to the line portion region of the lower gate electrode that contacts the protrusion is exposed.
In this drawing, the first gate insulating film etched in the process of forming the first contact hole C1 is denoted by reference numeral '130A'.

Next, a conductive film for contact is formed on the first gate insulating film 130A in which the first contact hole C1 is formed. At this time, a conductive film for contact is buried in the first contact hole C1.
After the conductive film for contact is etched, a contact plug 260 connected to the lower gate electrode 120A is formed, and at the same time, a source electrode 162 and a drain electrode 164 are formed at positions separated from the contact plug 260. The formation of the contact plug 260, the source electrode 162, and the drain electrode 164 can be performed simultaneously through one deposition process and one mask process, thereby forming the contact plug 260, the source electrode 162, and the drain electrode 164 made of the same material. it can.

  Referring to FIG. 4D, a channel layer 140 is formed on the first gate insulating layer 130 between the source electrode 162 and the drain electrode 164. In order to electrically connect the channel layer 140 to the source electrode 162 and the drain electrode 164, it is preferable to pattern the sidewalls and a part of the upper portion of the source electrode 162 and the drain electrode 164. In some cases, a protective film 150 may be formed. The channel film 140 and the protection film 150 are formed on a part of the lower gate electrode 120B corresponding to the protrusion of the lower gate electrode.

Next, a second gate insulating film 170 is formed on the entire structure of the resultant structure in which the contact plug 260, the channel film 140, the protective film 150, the source electrode 162, and the drain electrode 164 are formed.
Here, it is preferable that the capacitance per unit area of the second gate insulating film 170 and the protection film 150 has a value similar to the capacitance per unit area of the first gate insulating film 130A.

  As shown in FIG. 4E, the second gate insulating film 170 is etched to form a second contact hole C2 for exposing the surface of the contact plug 260, and at the same time, a third for exposing the surface of the source electrode 162 or the drain electrode 164. A contact hole C3 is formed.

  FIG. 4E illustrates a case where the surface of the drain electrode 164 is exposed as an example of the third contact hole C3. The second gate insulating layer etched in the process of forming the second contact hole C2 and the third contact hole C3 is illustrated by reference numeral '170A'.

As shown in FIG. 4F, a conductive film for an electrode is formed on the second gate insulating film 170A in which the second contact hole C2 and the third contact hole C3 are formed. Next, the electrode conductive film is etched to form an upper gate electrode 180 located at a part of the upper part of the lower gate electrode 120A and an intermediate electrode 181 located at a distance from the upper gate electrode 180.
The upper gate electrode 180 and the intermediate electrode 181 can be formed simultaneously using one deposition process and one mask process. By forming them simultaneously, the upper gate electrode 180 and the intermediate electrode 181 are formed at substantially the same height. Also, an upper gate electrode 180 and an intermediate electrode 181 made of the same material are formed.

The upper gate electrode 180 is electrically connected to the lower gate electrode 120A through the contact plug 260. Thus, a double gate transistor including the lower gate electrode 120A and the upper gate electrode 180 connected by the contact plug 260 is formed.
Although the upper gate electrode 180 is illustrated as being divided into two regions according to the position of the cross section, it can be seen from FIG. 4A that the upper gate electrode 180 has a single pattern.

  Next, an interlayer insulating film 190 is formed on the entire structure of the resultant structure on which the upper gate electrode 180 and the intermediate electrode 181 are formed. The upper gate electrode 180 and the intermediate electrode 181 are electrically insulated from each other by the interlayer insulating film 190.

  As shown in FIG. 4G, the interlayer insulating film 190 is etched to form an opening C4 exposing the surface of the intermediate electrode 181. The interlayer insulating film etched at the time of forming the opening C4 is shown by reference numeral "190A".

  As shown in FIG. 4H, a first functional electrode 182 is formed on the intermediate electrode 181 exposed through the opening C4. The first functional electrode 182 may be a pixel electrode of a display device such as an organic light emitting display or a liquid crystal display, and is electrically connected to the source electrode 162 or the drain electrode 164. FIG. 4H illustrates a case where the first functional electrode 182 and the drain electrode 164 are connected as an example.

  Thus, a thin film transistor according to the comparative example is formed. Although the thin film transistor of FIG. 4h and the thin film transistor of FIG. 1g have the same configuration, in the comparative embodiment, a contact hole is formed by etching a gate insulating film or an interlayer insulating film as compared with the embodiment of the present invention. It can be confirmed that a multi-stage process is required more than the present invention.

5A to 5C are a schematic plan view and a cross-sectional view of a thin film transistor obtained by the manufacturing method according to the comparative embodiment.
FIG. 5A is a plan view of an intermediate product in which one double gate transistor and one first functional electrode are formed, FIG. 5B is a cross-sectional view in a first direction (IV-IV ′) of FIG. FIG. 5C illustrates a cross-sectional view in the second direction (VV ′) of FIG. 5A.
The thin film transistor according to the comparative example includes a lower gate electrode 120, an upper gate electrode 180 formed on the lower gate electrode 120, and a contact plug 260 connecting the lower gate electrode 120 and the upper gate electrode 180 (FIG. 5B).

  Although the embodiment of the present invention has been described above, the present invention is not limited to the above-described embodiment, and includes modifications and improvements as long as the object of the present invention can be achieved.

  Next, an embodiment of the present invention will be described in detail with one specific example simply manufactured, but the present invention is not limited to these examples.

Example 1
Glass (Eagle XG manufactured by Corning, size: 40 mm × 40 mm, thickness: 0.7 mm) was prepared as a substrate. Chromium was deposited to a thickness of 50 nm on the surface of the base material by a sputtering method to form a gate electrode. Next, the substrate was ultrasonically cleaned with isopropyl alcohol for 10 minutes, and then dried by blowing dry N2 gas.
On the lower gate electrode, a conductive composition ink (silver nanocolloid (average particle diameter: 40 nm), 2,3,5,6-tetrafluoro-4- (trifluoromethyl) benzenethiol, and a solvent (water and 1,3 -A mixed solvent of propanediol and glycerin in a mass ratio of 39.4: 1.5: 59.1) was inkjetted and baked at 150 ° C for 30 minutes to form via posts.
Poly (methyl methacrylate) (PMMA, Sigma-Aldrich 445746) was dissolved at 5% by mass in 1-Methoxy-2-propyl acetate (Kanto Chemical) to prepare a resin composition. After applying the above-mentioned resin composition to the surface of the above-mentioned base material by a spin coat method, it was dried on a hot plate (As One EC-1200NP) at 130 ° C. for 5 minutes to form a first gate insulating film by PMMA. When the surface of the first gate insulating film was observed with a microscope (MX61, manufactured by Olympus Corporation), the first gate insulating film on the via post showed an opening.

Next, a conductive paste was printed by a reverse printing method and baked at 180 ° C. to form a source electrode and a drain electrode. Next, on the first gate insulating film between the source electrode and the drain electrode, Deposit Hydronaphthalene (P3HT, Sigma-Aldrich 6988989) was deposited on the first gate insulating film by inkjet printing. An organic semiconductor ink dissolved at 1 wt% was applied to (Yakuhin Kogyo) and dried on a hot plate at 150 ° C. for 10 minutes to form a channel film.
The conductive composition ink was again ink-jetted on the via posts protruding from the first gate insulating film and on the drain electrodes, and baked at 150 ° C. for 30 minutes to form via posts.

Next, the above resin composition is applied by a spin coating method on the entire structure of the resultant structure in which the via post, the channel film, the source electrode, and the drain electrode are formed, and then dried on a hot plate at 130 ° C. for 5 minutes. And a second gate insulating film made of PMMA. When the surface of the second gate insulating film was observed with a microscope, the second gate insulating film on the via post described above showed an opening.
Then, a conductive paste was printed by an inversion printing method, baked at 180 ° C. to form an upper gate electrode, and electrically connected to the lower gate electrode through a via post to obtain a double gate transistor.

  About the obtained transistor, the probe for a measurement was made to contact the lead wire connected to the source electrode and the drain electrode, respectively, and the transistor characteristic was measured using the semiconductor parameter analyzer (Agilent B1500A). As a result, the current value of the manufactured double gate transistor increased in accordance with the potential difference between the source electrode and the drain electrode, and the gate voltage exhibited a normal operation capable of controlling the current value. In addition, about twice the ON current was obtained as compared with a single-gate transistor having a similar structure.

REFERENCE SIGNS LIST 100 substrate 110 buffer film 120 lower gate electrode 130 first gate insulating film 140 channel film 150 protective film 160, 161, 200, 201 convex via post 162 source electrode 164 drain electrode 170 second gate insulating film 180 upper gate electrode 181 Intermediate electrode 182 First functional electrode 190 Interlayer insulating film 260 Contact plug

Claims (9)

In a thin film transistor including two or more gate electrodes, two of the two or more gate electrodes are electrically connected to each other by a convex conductor including metal particles, and the conductor includes a fluorine-containing thiol compound. a thin film transistor wherein the. The thin film transistor according to claim 1 , wherein a surface energy of the conductor is 10 mN / m or more and 80 mN / m or less. An insulating layer between two gate electrodes electrically connected by the conductor;
The conductor is formed on one gate electrode through the insulating layer,
The height of the conductor, a thin film transistor according to claim 1 or 2, wherein the at 10 times or less 0.5 times the thickness of one said insulating layer in the gate electrode of. The diameter of the conductor, a thin film transistor according to any one of claims 1 to 3, characterized in that at 10μm or 100μm or less. The thin film transistor according to any one of claims 1 to 4 having two gate electrodes. The thin film transistor according to any one of claims 1 to 5 , wherein the semiconductor layer of the thin film transistor is a semiconductor layer made of an organic semiconductor material. Forming a conductive convex by on the gate electrode to print by firing a composition comprising metal particles, conductor of said convex is electrically connected to the gate electrode and another gate electrode, said composition A method for manufacturing a thin film transistor having two or more gate electrodes, wherein the product contains a fluorine-containing thiol compound . The method according to claim 7 , wherein the printing is performed by an inkjet process. An electronic apparatus comprising: a thin film transistor according to any one of claims 1-6.

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