JP2017108040A - Thin film transistor and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor in which upper and lower gate electrodes of the thin film transistor having two or more gate electrodes are electrically connected so that more current can flow.SOLUTION: In the thin film transistor having two or more gate electrodes, two of the two or more gate electrodes are electrically connected with a convex electric conductor containing metal particles.SELECTED DRAWING: Figure 1g

Description

  The present invention relates to a thin film transistor and a method for manufacturing the thin film transistor.

  Conventionally, as a semiconductor material used for a field effect transistor, an inorganic material such as a silicon single crystal, amorphous silicon formed on a glass substrate, or polysilicon is generally used. On the other hand, for example, a field effect transistor using an organic semiconductor as described in Patent Document 1 is easier to manufacture at a low temperature and having a larger area than those using an inorganic semiconductor as described above. However, it is possible to reduce the cost. In addition, since it has properties that are rich in flexibility unique to organic substances, it is also considered to be applied to flexible substrates such as plastics, and recently, development has been particularly advanced.

However, in an organic thin film transistor using an active layer made of this kind of organic semiconductor film, the mobility of electrons and holes in the active layer is generally smaller than that of an inorganic semiconductor, so that it is smaller than that of an inorganic semiconductor field effect transistor. The current that can be controlled is small.
For this reason, investigations and structural studies of organic semiconductor materials having a large mobility capable of flowing a larger amount of current are underway, but at present, sufficient results have not been achieved.

Patent Documents 2 and 3 disclose a double gate structure in which gate electrodes are arranged above and below a semiconductor layer, but there is no disclosure regarding a method for electrically connecting the upper and lower gate electrodes.
Patent Documents 4 and 5 disclose a double gate structure in which gate electrodes are arranged above and below a semiconductor layer, similarly to Patent Documents 2 and 3. The contact plug for electrically connecting the upper and lower gate electrodes forms a contact hole by etching the gate insulating film on the lower gate electrode, and the contact plug is formed in the contact hole.

Japanese Patent Laid-Open No. 02-077405 JP 2000-323715 A JP 2005-79549 A JP 2011-233889 A JP 2003-338628 A

An object of the present invention is to provide a thin film transistor in which upper and lower gate electrodes of a thin film transistor having two or more gate electrodes are electrically connected so that more current can be controlled to flow. is there.
An object of the present invention is to provide a method of manufacturing a thin film transistor that can easily connect the upper and lower gate electrodes of a thin film transistor having two or more gate electrodes.

In manufacturing a thin film transistor having two or more gate electrodes, a contact hole is formed by etching the gate insulating film on the lower gate electrode in order to form a contact plug for electrically connecting the two gate electrodes. This requires the number of steps of forming contact plugs therein, resulting in a problem of yield reduction.
The present inventors have found that the above problem can be solved by forming a convex conductor by printing and baking a composition containing metal particles on the lower gate electrode by various printing methods such as inkjet. .

A thin film transistor having a gate electrode of 1.2 or more, wherein two of the two or more gate electrodes are electrically connected by a convex conductor containing metal particles.
2. 2. The thin film transistor according to 1, wherein the conductor includes a liquid repellent material.
3. 3. The thin film transistor according to 2, wherein the liquid repellent material is exposed on a surface of the conductor.
4). 4. The thin film transistor according to 2 or 3, wherein the liquid repellent material is a fluorine-containing compound.
5). 5. The thin film transistor according to any one of 2 to 4, wherein the liquid repellent material is a fluorine-containing thiol compound.
6). The thin film transistor according to any one of 1 to 5, wherein the surface energy of the conductor is 10 mN / m or more and 80 mN / m or less.
7). Including an insulating layer between two gate electrodes electrically connected by the conductor;
The conductor is formed on one gate electrode through the insulating layer;
The thin film transistor according to any one of claims 1 to 6, wherein a height of the conductor is 0.5 to 10 times a thickness of the insulating layer in the one gate electrode.
8). The thin film transistor according to any one of 1 to 7, wherein the conductor has a diameter of 10 μm to 100 μm.
9. The thin film transistor according to any one of 1 to 8 having two gate electrodes.
10. The thin film transistor according to any one of 1 to 9, wherein the semiconductor layer of the thin film transistor is a semiconductor layer made of an organic semiconductor material.
11. A convex conductor is formed by printing and baking a composition containing metal particles on a gate electrode, and the convex conductor electrically connects the gate electrode to another gate electrode. A method for manufacturing a thin film transistor having two or more gate electrodes.
12 12. The method for producing a thin film transistor according to 11, wherein the composition contains a liquid repellent material.
13. 13. The method for producing a thin film transistor according to 12, wherein the liquid repellent material is a fluorine-containing compound.
14 The method for producing a thin film transistor according to 12 or 13, wherein the liquid repellent material is a fluorine-containing thiol compound.
15. The method of manufacturing a thin film transistor according to any one of 11 to 14, wherein the printing is performed by an ink jet process.
16. An electronic apparatus comprising the thin film transistor according to any one of 16.1 to 10.

According to the present invention, it is possible to provide a thin film transistor in which the upper and lower gate electrodes of a thin film transistor having two or more gate electrodes are electrically connected so that more current can be controlled to flow.
ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the thin-film transistor which can carry out interlayer connection simply between the upper and lower gate electrodes of the thin-film transistor which has two or more gate electrodes can be provided.

It is a figure explaining the manufacturing method of the thin-film transistor which concerns on one Embodiment of this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on one Embodiment of this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on one Embodiment of this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on one Embodiment of this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on one Embodiment of this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on one Embodiment of this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on one Embodiment of this invention. It is a figure which shows the structure of the thin-film transistor which concerns on one Embodiment of this invention. It is a figure which shows the structure of the thin-film transistor which concerns on one Embodiment of this invention. It is a figure which shows the structure of the thin-film transistor which concerns on one Embodiment of this invention. It is a figure which shows the thin-film transistor structure concerning other embodiment of this invention. It is a figure which shows the thin-film transistor structure concerning other embodiment of this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on the comparison form with respect to this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on the comparison form with respect to this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on the comparison form with respect to this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on the comparison form with respect to this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on the comparison form with respect to this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on the comparison form with respect to this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on the comparison form with respect to this invention. It is a figure explaining the manufacturing method of the thin-film transistor which concerns on the comparison form with respect to this invention. It is a figure which shows the thin-film transistor structure which concerns on the comparison form with respect to this invention. It is a figure which shows the thin-film transistor structure which concerns on the comparison form with respect to this invention. It is a figure which shows the thin-film transistor structure which concerns on the comparison form with respect to this invention. It is a figure which shows the longitudinal cross-sectional shape of a convex via post. It is a figure explaining the diameter of a convex via post. It is a figure explaining the height of a convex via post.

<Method for Manufacturing Thin Film Transistor>
In the method for manufacturing a thin film transistor of the present invention, a convex conductor is formed by printing and baking a composition containing metal particles (hereinafter sometimes referred to as a conductor composition ink) on a gate electrode, The conductor electrically connects the gate electrode to another gate electrode. Thus, a thin film transistor having two or more gate electrodes is manufactured.

The metal particles contained in the conductor composition ink are the origin of the electrical conductivity of the convex conductor.
Examples of the metal species of the metal particles include silver, copper, mercury, tin, indium, nickel, palladium, platinum, and gold. These may be used alone or in combination of two or more. Among these, silver is particularly preferable from the viewpoint of affinity with the liquid repellent material described later.
The metal particles preferably have an average particle size of 1 nm to 1000 nm. Moreover, you may include metal nanowire with a diameter of 50 nm or less. The average particle diameter of the metal particles can be measured by observation with a transmission electron microscope (TEM). Specifically, in a visual field including about 50 particles, there is a method of measuring the projected area equivalent circle diameter of all the particles and calculating the average.

  The content of the metal particles is preferably 15% by mass or more and 75% by mass or less, and more preferably 20% by mass or more and 50% by mass or less based on the total amount of the conductor composition ink. If the content of the metal particles is within the above range, a convex conductor can be formed more efficiently.

The conductor composition ink preferably includes a liquid repellent material.
The liquid repellent material imparts liquid repellency to the convex conductor.
The liquid repellent material is, for example, a fluorine-containing compound, preferably a fluorine-containing thiol compound. The fluorine-containing thiol compound can provide liquid repellency to the metal particles while ensuring the conductivity of the metal particles. Therefore, the convex conductor can achieve both conductivity and liquid repellency.

  The fluorine-containing compound as the liquid repellent material is selected from the group consisting of, for example, fluorine-containing disulfide compounds, fluorine-containing amine compounds, fluorine-containing carboxylic acid compounds, fluorine-containing nitrile compounds, fluorine-containing tellurium compounds, and fluorine-containing selenium compounds. One or more are preferable. Of these, fluorine-containing thiol compounds, fluorine-containing disulfide compounds, fluorine-containing amine compounds, and fluorine-containing carboxylic acid compounds are particularly preferred.

  Examples of the fluorine-containing thiol compound include a fluorine-containing thiol compound having an aromatic ring and a thiol compound having a carbon chain having a fluorinated portion. Among these, at least one compound selected from the group consisting of a fluorine-containing thiol having 6 to 20 carbon atoms having an aromatic ring (preferably a benzene ring) is preferable from the surface modification property of the metal particles.

  Specific examples of the fluorine-containing thiol having 6 to 20 carbon atoms having an aromatic ring include trifluoromethylbenzenethiol (for example, 4-trifluoromethylbenzenethiol and 3-trifluoromethylbenzenethiol), pentafluorobenzenethiol. 2,3,5,6-tetrafluorobenzenethiol, 2,3,5,6-tetrafluoro-4- (trifluoromethyl) benzenethiol, 2,3,5,6-tetrafluoro-4-mercaptobenzoic acid Examples include acid methyl ester, 3,5-bistrifluoromethylbenzenethiol, 4-fluorobenzenethiol and 11- (2,3,4,5,6-pentafluorobenzyloxy) -1-undecanethiol. Among these, trifluoromethylbenzenethiol and 2,3,5,6-tetrafluoro-4- (trifluoromethyl) benzenethiol are particularly preferable from the viewpoint of liquid repellency.

  The content of the liquid repellent material is preferably 10% by mass or less, and more preferably 5% by mass or less, based on the total amount of the conductor composition ink. If content of a liquid repellent material is below the said upper limit, the dispersibility of the metal particle in conductor composition ink will not be inhibited. Further, the lower limit of the content of the liquid repellent material is preferably 0.1% by mass or more from the viewpoint of the liquid repellency of the convex conductor obtained with the conductor composition ink.

The conductor composition ink may contain a solvent, which disperses or dissolves the metal particles and the liquid repellent material.
Solvents include water, alcohol solvents (monoalcohol solvents, diol solvents, polyhydric alcohol solvents, etc.), hydrocarbon solvents, ketone solvents, ester solvents, ether solvents, glyme solvents, halogen solvents. A solvent etc. are mentioned. These solvents may be used alone or in a combination of two or more. Among these, alcohol-based solvents are preferable from the viewpoint of printability.

The surface tension of the solvent is preferably 40 mN / m or more and 65 mN / m or less at 25 ° C. When the surface tension of the solvent is within the above range, the conductor composition ink can be sufficiently adhered to the ground. The surface tension can be measured by a pendant drop method.
Examples of the alcohol solvent having a surface tension of 40 mN / m or more and 65 mN / m or less at 25 ° C. include ethylene glycol, glycerin, and 1,3-propanediol. Among these, 1,3-propanediol is particularly preferable.

  The content of the solvent is preferably 25% by mass or more and 85% by mass or less, and more preferably 50% by mass or more and 80% by mass or less with respect to the total amount of the conductor composition ink. When the content of the solvent is within the above range, the conductor composition ink can be appropriately applied.

The conductor composition ink may contain an arbitrary component in addition to the components described above.
Examples of various optional components include dispersants.
These optional components are preferably 10% by mass or less based on the total amount of the conductor composition ink.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.
The embodiments described below can be modified in various other forms, and the scope of the present invention is not limited to the embodiments described below. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art. In the drawings, the thickness of the layer region can be exaggerated relative to the actual thickness for clarity. Also, if a layer is referred to as being on another layer or substrate, this can be formed directly on the other layer or substrate, or intervening a third layer therebetween. You can also. Like reference numerals refer to like elements throughout the embodiments.

FIG. 1A to FIG. 1G are diagrams for explaining an embodiment of a method for manufacturing a thin film transistor of the present invention.
FIG. 1a shows a plan view of an intermediate product according to the present embodiment in which a gate line is formed. FIGS. 1b to 1g also show the first direction (II ′) section and the second direction (II-II ′) section of FIG. 1a together for convenience of explanation.
Here, the gate line is for transmitting a gate signal, and is provided in a line form extended in the first direction II ′ of FIG. 2A, and the data line is for transmitting a data signal. Provided in the form of a line extending in the second direction II-II ′.

As shown in FIG. 1 b, a buffer film 110 is formed on the substrate 100.
For example, the substrate 100 may be a glass substrate or a plastic substrate. The buffer film 110 is for preventing diffusion of moisture or impurities generated from the substrate 100. As an example, the buffer film 110 is a single layer of an organic polymer insulating film, a silicon oxide film, a silicon nitride film, or an aluminum oxide film. It can be formed, or it can be formed of multiple layers in which these are stacked.

Next, lower gate electrodes 120 </ b> A and 120 </ b> B of double gate transistors are formed on the buffer film 110. As shown in FIG. 1 a, the lower gate electrode 120 </ b> A corresponds to the line portion of the T-shaped gate line 120, and the lower gate electrode 120 </ b> B corresponds to the protruding portion of the T-shaped gate line 120.
Hereinafter, for the convenience of description, the protruding part of the gate line 120 is indicated by reference numeral '120B', and the line part adjacent to the protruding part is indicated by reference numeral '120A'. In FIG. 1b, the lower gate electrodes 120A and 120B are divided into two regions and are shown as one pattern.

The lower gate electrodes 120A and 120B are formed of various print-formed films such as a film obtained by firing a conductive paste printed by a reverse printing method, or an aluminum alloy such as aluminum (Al) or aluminum-neodymium (Al-Nd). It can be formed of a single layer or a multilayer of molybdenum (Mo) alloy and aluminum alloy.
In addition, when the lower gate electrodes 120A and 120B are transparent, the lower gate electrodes 120A and 120B may be formed of a single layer of an ITO (Indium Tin Oxide) film or a multilayer of a silver alloy and an ITO film. .

  Next, a convex via post 160 is formed on the resulting structure on which the lower gate electrode 120A is formed by printing and baking the above-described conductive composition ink by various printing methods such as inkjet. This via post corresponds to a convex conductor and preferably has liquid repellency.

The method for printing the conductor composition ink is not particularly limited as long as it can be printed in a predetermined pattern. For example, the inkjet method, the dispenser method, the screen printing method, the gravure printing method, the gravure offset printing method, the reverse offset printing. And letterpress printing. In the present embodiment, it is preferable to use an inkjet method.
The method for firing the coating film made of the conductor composition ink is not particularly limited as long as the solvent contained in the conductor composition ink can be removed and the conductor composition ink can be solidified, and a general firing method can be used. it can. Specifically, it can be fired using a hot plate or the like.
Before firing or during firing, treatment for accelerating the migration of the liquid repellent material by irradiating ultrasonic waves or the like may be performed.

The firing temperature and firing time of the coating film made of the conductor composition ink are appropriately adjusted according to the type of solvent, liquid repellent material, etc. contained in the conductor composition ink.
The firing temperature is not particularly limited as long as it can remove the solvent contained in the conductor composition ink, but it is preferably 100 ° C. or higher and 220 ° C. or lower, and 120 ° C. or higher and 200 ° C. or lower. Is more preferable. If the firing temperature is too high, the metal particles may be deteriorated, making it difficult to exhibit desired conductivity. If the firing temperature is too low, the solvent remains in the convex via post, which may cause impurities to be mixed into the insulating layer in the insulating layer forming step described later.

The firing time is not particularly limited as long as it can remove the solvent contained in the conductor composition ink, but it is preferably 10 minutes or more and 60 minutes or less, and preferably 15 minutes or more and 60 minutes or less. Is more preferable, and it is particularly preferably 30 minutes or longer and 60 minutes or shorter.
If the firing time is too short, it is difficult for the liquid repellent material to be sufficiently transferred when the conductor composition ink contains the liquid repellent material, so that the liquid repellency of the convex via post is improved. May be difficult. Moreover, when baking time is too long, metal particles etc. may deteriorate and it may become difficult to show desired electroconductivity, and productivity may fall.

Next, a first gate insulating film 130 is formed on the entire structure of the resultant structure in which the lower gate electrodes 120A and 120B and the via posts 160 are formed. Here, the first gate insulating film 130 is, for example, an organic polymer insulating film formed by a coating process. The organic polymer insulating film is preferably formed of a single layer or a multilayer formed by laminating them.
In the coating process, the via post 160 can repel the insulating film solution, and the via post 160 can protrude from the first gate insulating film 130.

As shown in FIG. 1C, a source electrode 162 and a drain electrode 164 are formed on the first gate insulating film 130. Here, the source electrode 162 and the drain electrode 164 are, for example, various print formation films such as a film obtained by baking a conductive paste printed by a reverse printing method, aluminum (Al), or aluminum-neodymium (Al-Nd). It is preferable to form a single aluminum alloy layer or a multilayer in which a molybdenum (Mo) alloy and an aluminum alloy are laminated.
In the case where the source electrode 162 and the drain electrode 164 are formed of transparent electrodes, it is preferable that the source electrode 162 and the drain electrode 164 be formed of a single layer of ITO film or a multi-layer in which a silver alloy and an ITO film are laminated.

  As shown in FIG. 1 d, a channel film (semiconductor layer) 140 is formed on the first gate insulating film 130 between the source electrode 162 and the drain electrode 164. It is preferable that the channel film 140 is patterned so as to cover the side walls and part of the upper portion of the source electrode 162 and the drain electrode 164 so that the channel film 140 is electrically connected to the source electrode 162 and the drain electrode 164. A protective film 150 may be formed as shown in FIG. The channel film 140 and the protective film 150 are formed on a part of the upper part of the lower gate electrode 120B corresponding to the protruding part of the lower gate electrode.

  For example, an organic semiconductor can be used for the channel film 140, but the present invention is not limited thereto, and an oxide semiconductor, a silicon semiconductor, or the like may be used.

  The protective film 150 may be a fluorine-based organic polymer insulating film, but is not limited thereto, and may be formed of a single layer of a silicon oxide film, a silicon nitride film, or an aluminum oxide film, or a multi-layer formed by laminating these layers. It can be formed with multiple layers.

As shown in FIG. 1e, a protrusion formed by printing and baking conductor composition ink on the via post 160 and the drain electrode 164 protruding from the first gate insulating film 130 by various printing methods such as inkjet. Mold via posts 161 and 200 are formed. The via post preferably has liquid repellency. The convex via posts 161 and 200 can be formed by the same method as the via post 160, respectively.
The via post 161 on the via post 160 may not be formed when the via post 160 has a sufficient height.

Next, a second gate insulating film 170 is formed on the overall structure of the resultant structure in which the via posts 161 and 200, the channel film 140, the protective film 150, the source electrode 162, and the drain electrode 164 are formed.
Here, examples of the second gate insulating film 170 include an organic polymer insulating film formed by a coating process. The organic polymer insulating film is preferably formed of a single layer or a multilayer formed by laminating them.
In the coating process, the insulating film solution is repelled from the via posts 161 and 200, and the via posts 161 and 200 can protrude from the second gate insulating film 170.

As shown in FIG. 1 f, the upper gate electrode 180 is formed on the second gate insulating film 170.
The upper gate electrode 180 is, for example, various print formation films such as a film obtained by baking a conductive paste printed by a reverse printing method, or an aluminum alloy single layer such as aluminum (Al) or aluminum-neodymium (Al-Nd). It can be formed, or can be formed of multiple layers in which a molybdenum (Mo) alloy and an aluminum alloy are laminated.
When the upper gate electrode 180 is transparent, the upper gate electrode 180 may be formed of a single layer of an ITO film, or may be formed of multiple layers in which a silver alloy and an ITO film are stacked.

  The upper gate electrode 180 is electrically connected to the lower gate electrode 120A through the via posts 160 and 161. Thus, a double gate transistor including the lower gate electrode 120A and the upper gate electrode 180 connected by the via posts 160 and 161 is formed.

Next, a convex via post 201 is formed on the via post 200 protruding from the second gate insulating film 170 by further printing and baking the conductive composition ink by various printing methods such as inkjet. The via post preferably has liquid repellency.
Note that the via post 201 on the via post 200 may not be formed if the via post 200 has a sufficient height.

Next, an interlayer insulating film 190 is formed on the entire structure of the resultant structure on which the second gate insulating film 170 and the via post 201 are formed. An example of the interlayer insulating film 190 is an organic polymer insulating film formed by a coating process. The organic polymer insulating film is preferably formed of a single layer or a multilayer formed by laminating them.
In the coating process, the interlayer insulating film solution is repelled from the via post 201, and the via post 201 can protrude from the interlayer insulating film 190.

As shown in FIG. 1 g, the first functional electrode 182 is formed on the via post 201.
The upper gate electrode 180 and the first functional electrode 182 are electrically insulated from each other by the interlayer insulating film 190.

The first functional electrode 182 may be a pixel electrode of a display device such as an organic light emitting display device or a liquid crystal display device, and is electrically connected to the source electrode 162 or the drain electrode 164. In this drawing, the case where the 1st functional electrode 182 and the drain electrode 164 are connected is shown as an example.
Thereby, the thin film transistor according to the embodiment of the present invention is formed.

<Thin film transistor>
The thin film transistor of the present invention is a thin film transistor having two or more layers of gate electrodes, and two of the two or more gate electrodes are electrically connected by a convex conductor including metal particles. The thin film transistor of the present invention is a transistor obtained by the above-described method for producing a thin film transistor of the present invention.
The “thin film transistor having two or more layers of gate electrodes” is a thin film transistor having a structure called a double gate structure, a dual gate structure, a bottom-top gate structure, a double gate structure, a multi-gate structure, or the like.

2a to 2c are views showing a structure of a thin film transistor according to an embodiment of the present invention.
2a shows a plan view of an intermediate result in which one double gate transistor and one first functional electrode are formed, FIG. 2b shows a cross-sectional view in the first direction (II ′) of FIG. 2a, 2c shows a cross-sectional view in the second direction (II-II ′) of FIG. 2a.

Referring to FIG. 2 b, the thin film transistor according to an embodiment of the present invention electrically connects the lower gate electrode 120, the upper gate electrode 180 formed on the lower gate electrode 120, and the lower gate electrode 120 and the upper gate electrode 180. A convex via post 160 and a via post 161 connected to each other.
In the present embodiment, the via post 160 and the via post 161 correspond to convex conductors each including metal particles. In FIG. 2, the lower gate electrode and the upper gate electrode are electrically connected by two convex via posts. However, if the height is sufficient, the lower gate electrode and the upper gate electrode are electrically connected by one convex via post. Also good.

  The metal particles included in the via post and the liquid repellent material optionally included are the same as the metal particles and the liquid repellent material included in the conductive composition ink described in the thin film transistor manufacturing method of the present invention.

When the convex via post includes a liquid repellent material, the convex via post exhibits liquid repellency. Here, “the convex via post has liquid repellency” means that, for example, in FIG. 2 b, the contact angle between the surface of the convex via post 160 and water is the contact angle between the surface of the lower gate electrode 120 and water. It means that the contact angle between the surface of the buffer film 110 and water is larger.
For example, the contact angle between the surface of the convex via post 160 and water is such that the difference between the contact angle between the surface of the lower gate electrode 120 and water is 5 ° or more, and preferably 20 ° or more. If the difference between the contact angles is small, it may be difficult to repel the resin composition using the difference in wettability when the resin composition is applied on the lower gate electrode on which the via post is formed. is there.
The upper limit value of the contact angle difference is appropriately determined according to the material of the via post, the material of the gate electrode, and the like, and is not particularly limited, but is about 100 °, for example.

In addition, for example, the contact angle between the surface of the via post 160 and water is preferably 5 ° or more, and preferably 20 ° or more, between the surface of the buffer film 110 and water. If the difference between the contact angles is small, it may be difficult to repel the resin composition using the difference in wettability when the resin composition is applied onto the lower electrode on which the via post is formed. .
The upper limit of the contact angle difference is appropriately determined according to the material of the via post, the material of the buffer film, and the like, and is not particularly limited, but is about 100 °, for example.

  The plan view shape of the convex via post is not particularly limited as long as the via post can be formed, and examples thereof include a circular shape, an elliptical shape, a quadrangular shape, and a polygonal shape. Especially, it is preferable that the planar view shape of the convex via post is a circular shape or an elliptical shape.

FIG. 6 is an explanatory view for explaining the vertical cross-sectional shape of the convex via post in the present embodiment. The vertical cross-sectional shape of the convex via post refers to the cross-sectional shape of the convex via post perpendicular to the lower gate electrode.
Specifically, the vertical cross-sectional shape of the convex via post includes a semicircular shape as shown in FIG. 6A, a semi-elliptical shape as shown in FIG. 6B, a trapezoidal shape, and a rectangular shape although not shown. Etc. Moreover, these shapes may have a flat part or a hollow in the center. FIG. 6C shows a shape having a flat portion at the center of the semi-elliptical shape.

The diameter of the convex via post is not particularly limited as long as the lower gate electrode and the upper gate electrode can be conducted through the convex via post, but is preferably 1 μm or more and 5000 μm or less, for example. It is more preferably 5 μm or more and 1000 μm or less, and particularly preferably 10 μm or more and 100 μm or less.
If the convex via post is too large, it may be difficult to achieve high definition and high integration of the thin film transistor. If the convex via post is too small, it may be difficult to make the lower gate electrode and the upper gate electrode conductive.
The “diameter of the convex via post” refers to the size of the convex via post in a plan view shape. For example, when the planar view shape is a circular shape, the diameter is the square shape, and the planar view shape is a square shape. In the case of, it means the width of one side. In addition, when the shape in plan view is a shape having a short side and a long side, such as a rectangle or an ellipse, the width of the short side is meant. Moreover, when the planar view shape is a polygonal shape, it refers to the diameter of the inscribed circle.
Specifically, the size of the convex via post refers to the distance indicated by u in FIG.

The height of the convex via post is preferably 0.5 to 10 times the thickness of the insulating layer on the gate electrode.
The specific numerical value of the height of the convex via post is, for example, preferably from 10 nm to 15000 nm, and more preferably from 100 nm to 10,000 nm. If the height of the convex via post is too high, it may be difficult to improve the flatness of the surface on the upper gate electrode side. If it is too low, it may be difficult for the convex via post to exhibit the desired conductivity.
The “height of the convex via post” refers to the value of the portion where the vertical distance of the insulating film is maximum in the longitudinal sectional shape of the convex via post, and the distance indicated by x in FIG. Say. y is the thickness of the insulating film on the gate electrode, and x is preferably 0.5 times or more and 10 times or less of y.

The aspect ratio (height / diameter) of the convex via post is not particularly limited, but is preferably 0.001 or more and 1 or less, more preferably 0.01 or more and 0.8 or less. It is particularly preferable that the ratio is 0.01 or more and 0.5 or less.
If the aspect ratio of the convex via post is too large, it may be difficult to form the convex via post itself, or the convex via post may be easily damaged. Moreover, when the aspect ratio of the convex via post is too small, it may be difficult for the convex via post to exhibit sufficient conductivity and liquid repellency.

The convex via post preferably has a surface energy of 10 mN / m or more and 80 mN / m or less.
The surface energy of the convex via post is adjusted by, for example, the content of the liquid repellent material. If the surface energy is smaller than the lower limit, the metal particles in the convex via post may be aggregated. On the other hand, when the surface energy is larger than the upper limit value, the liquid repellency is lowered, and there is a possibility that the gate insulating layer cannot be opened.
The surface energy in this embodiment is, for example, that 1 microliter of liquid is dropped on the measurement target, the shape of the dropped liquid droplet is observed from the side surface, and the angle between the droplet and the measurement target is measured. The contact angle was measured by the above, and the analysis by the geometric mean method based on the extended Fowkes equation of Kitazaki and Hata from the contact angle value measured with each solvent (Natsuaki Kitasaki, Toshio Hata et al., Journal of Japan Adhesion Association, Vol. 8) (3) This refers to the value obtained on pages 131-141 (1972)).
The contact angle in this embodiment can be measured using, for example, a contact angle measuring device manufactured by Imoto Seisakusho or a contact angle meter DM-901 manufactured by Kyowa Interface Science.

  In the thin film transistor of FIGS. 2a to 2c, the lower gate electrode 120 and the upper gate electrode 180 are electrically connected by convex via posts 160 and 161 so that the lower gate electrode 120 and the upper gate electrode 180 are driven simultaneously. Become. The conventional double gate transistor is generally driven by applying a voltage independently to the lower gate electrode and the upper gate electrode, whereas the double gate transistor according to the present embodiment has the lower gate electrode and the upper gate electrode. The electrodes are driven simultaneously.

3a and 3b are diagrams showing another embodiment of the thin film transistor of the present invention.
In FIG. 2b, the lower gate electrode and the upper gate electrode are connected by each transistor. However, in the other embodiment, as shown in FIGS. 3a and 3b, electrode extraction portions of the lower gate electrode and the upper gate electrode By forming a via post (III-III ′ portion in FIG. 3b), the lower and upper gate electrodes are electrically connected by forming only one via post.
In addition, II-II 'in FIG. 3a becomes a form similar to FIG. 2c.

The thin film transistor of the present invention can be used in various applications such as a display device and a sensor.
As an example, in the case of an organic light emitting display device in which a thin film transistor is a display device to which an organic light emitting element is applied, the first functional electrode 182 may be used as a pixel electrode. In addition, an organic light emitting layer and a common electrode formed on the first functional electrode 182 are further included.

  As another example, in the case of a display device using a liquid crystal display element as a thin film transistor, the first functional electrode 182 is used as a pixel electrode. Further, it further includes an alignment film, a short portion, a sealant, and a spacer formed on the first functional electrode 182, and further includes a color filter substrate including a common electrode, a color filter, and the like, and a liquid crystal.

As yet another example, when the thin film transistor is a sensor, the first functional electrode 182 is used as a lower electrode of the sensor. Further, a spacer formed on the first functional electrode 182 and an upper electrode of the sensor are further included.
The thin film transistor of the present invention can be applied not only to a contact type and capacitance type sensor but also to an optical sensor.

  By applying such a double gate transistor having a high on-state current to a display device and a sensor, a display device with a high image quality and a large area can be provided, and the performance of the sensor can be improved.

In the case of an organic thin film transistor using an organic semiconductor, a conventional single gate transistor has a low field-effect mobility of 0.01 to ¹ cm ² / Vs, thus realizing a display device and a sensor with a large area and high image quality. There is a limit to doing it. On the other hand, the thin film transistor of the present invention uses a double gate transistor having a field effect mobility that is at least twice as high as that of a single gate transistor.

  A conventional single gate transistor has a structure of a channel film, a gate insulating film, and a gate electrode. When an electric field is applied to the gate electrode, charges are accumulated in the channel film near the interface with the gate insulating film. On the other hand, the double gate transistor has a structure of a lower gate electrode, a first gate insulating film, a channel film, a second gate insulating film, and an upper gate electrode, so that the lower interface of the channel film in contact with the first gate insulating film and Charges are accumulated at the upper interface of the channel film in contact with the second gate insulating film. Therefore, the double-gate thin film transistor has twice as many regions where charges can move as compared with a single gate transistor, so that the channel resistance of the element is halved and the on-current is doubled.

<Comparison form>
4a to 4h are shown as a comparison with respect to the method for manufacturing the thin film transistor of the present invention.
4A to 4H are diagrams showing a comparative example of a method of manufacturing a thin film transistor using a process of partially removing an insulating film by etching and exposing a lower electrode to form a contact hole.
FIG. 4a shows a plan view of an intermediate result according to a comparative embodiment in which gate lines are formed. 4b to 4h show the third direction (IV-IV ′) cross section and the fourth direction (VV ′) cross section of FIG. 4a together for convenience of explanation.

As shown in FIG. 4B, a buffer film 110 is formed on the substrate 100.
Next, after forming a conductive film for a lower gate electrode on the buffer film 110, this is patterned to form lower gate electrodes 120A and 120B of a double gate transistor. At this time, as shown in FIG. 4A, the lower gate electrodes 120A and 120B are formed in a form having a line part and a protruding part protruding from the line part, that is, a T-shaped gate line 120. As in FIG. 1, for convenience of explanation, the protruding portion of the gate line 120 is indicated by the reference symbol “120B”, and the line portion adjacent to the protruding portion is indicated by the reference symbol “120A”. That is, in FIG. 4B, the lower gate electrodes 120A and 120B are illustrated as being divided into two regions, but this is one pattern.

  Next, a first gate insulating film 130 is formed on the entire structure of the resultant structure where the lower gate electrodes 120A and 120B are formed.

As shown in FIG. 4c, the first gate insulating film 130 is etched to expose the surface of the lower gate electrode 120A, thereby forming a first contact hole C1. At this time, the first contact hole C1 is formed so that the surface of the lower gate electrode 120A corresponding to the line portion region in contact with the protruding portion of the lower gate electrode is exposed.
In the drawing, the first gate insulating film etched in the process of forming the first contact hole C1 is denoted by reference numeral '130A'.

Next, a contact conductive film is formed on the first gate insulating film 130A in which the first contact hole C1 is formed. At this time, a contact conductive film is buried in the first contact hole C1.
After the contact conductive film is etched, a contact plug 260 connected to the lower gate electrode 120A is formed, and at the same time, a source electrode 162 and a drain electrode 164 are formed at positions separated from the contact plug 260. The contact plug 260, the source electrode 162, and the drain electrode 164 can be formed simultaneously through one deposition process and one mask process, whereby the contact plug 260, the source electrode 162, and the drain electrode 164 made of the same material are formed. it can.

  As shown in FIG. 4 d, the channel film 140 is formed on the first gate insulating film 130 between the source electrode 162 and the drain electrode 164. It is preferable that the channel film 140 is patterned so as to cover the side walls and part of the upper portion of the source electrode 162 and the drain electrode 164 so that the channel film 140 is electrically connected to the source electrode 162 and the drain electrode 164. In some cases, the protective film 150 may be formed. The channel film 140 and the protective film 150 are formed on a part of the upper part of the lower gate electrode 120B corresponding to the protruding part of the lower gate electrode.

Next, a second gate insulating film 170 is formed on the entire structure of the resultant structure in which the contact plug 260, the channel film 140, the protective film 150, the source electrode 162, and the drain electrode 164 are formed.
Here, it is preferable that the capacitance per unit area of the second gate insulating film 170 and the protective film 150 has a value similar to the capacitance per unit area of the first gate insulating film 130A.

  As shown in FIG. 4e, the second gate insulating film 170 is etched to form a second contact hole C2 that exposes the surface of the contact plug 260, and at the same time, a third that exposes the surface of the source electrode 162 or the drain electrode 164. A contact hole C3 is formed.

  FIG. 4e illustrates a case where the surface of the drain electrode 164 is exposed as an example of the third contact hole C3. The second gate insulating film etched in the formation process of the second contact hole C2 and the third contact hole C3 is denoted by reference numeral '170A'.

As shown in FIG. 4f, an electrode conductive film is formed on the second gate insulating film 170A in which the second contact hole C2 and the third contact hole C3 are formed. Next, the electrode conductive film is etched to form an upper gate electrode 180 located at a part of the upper portion of the lower gate electrode 120A and an intermediate electrode 181 located away from the upper gate electrode 180.
The upper gate electrode 180 and the intermediate electrode 181 can be formed simultaneously using one deposition process and one mask process. By forming them simultaneously, the upper gate electrode 180 and the intermediate electrode 181 are formed at substantially the same height. In addition, the upper gate electrode 180 and the intermediate electrode 181 made of the same material are formed.

Upper gate electrode 180 is electrically connected to lower gate electrode 120 </ b> A through contact plug 260. Thus, a double gate transistor including the lower gate electrode 120A and the upper gate electrode 180 connected by the contact plug 260 is formed.
Although the upper gate electrode 180 is divided into two regions according to the position of the cross section, it can be seen from FIG. 4A that the upper gate electrode 180 has one pattern.

  Next, an interlayer insulating film 190 is formed on the entire structure of the resultant structure on which the upper gate electrode 180 and the intermediate electrode 181 are formed. The upper gate electrode 180 and the intermediate electrode 181 are electrically insulated from each other by the interlayer insulating film 190.

  As shown in FIG. 4g, the interlayer insulating film 190 is etched to form an opening C4 that exposes the surface of the intermediate electrode 181. The interlayer insulating film etched when the opening C4 is formed is indicated by reference numeral '190A'.

  As shown in FIG. 4h, the first functional electrode 182 is formed on the intermediate electrode 181 exposed through the opening C4. The first functional electrode 182 may be a pixel electrode of a display device such as an organic light emitting display device or a liquid crystal display device, and is electrically connected to the source electrode 162 or the drain electrode 164. FIG. 4h illustrates a case where the first functional electrode 182 and the drain electrode 164 are connected as an example.

  Thereby, the thin film transistor according to the comparative form is formed. The thin film transistor of FIG. 4h and the thin film transistor of FIG. 1g are thin film transistors having the same configuration, but in the comparative embodiment, a contact hole is formed by etching the gate insulating film and the interlayer insulating film as compared with the embodiment of the present invention. It can be confirmed that a multi-step process is necessary as compared with the present invention.

5a to 5c are a schematic plan view and a cross-sectional view of a thin film transistor obtained by the manufacturing method according to the comparative embodiment.
FIG. 5a shows a plan view of an intermediate result in which one double gate transistor and one first functional electrode are formed, FIG. 5b shows a cross-sectional view in the first direction (IV-IV ′) of FIG. FIG. 5c shows a cross-sectional view in the second direction (VV ′) of FIG. 5a.
The thin film transistor according to the comparative example includes a lower gate electrode 120, an upper gate electrode 180 formed on the lower gate electrode 120, and a contact plug 260 connecting the lower gate electrode 120 and the upper gate electrode 180 (FIG. 5b).

  Although the embodiments of the present invention have been described above, the present invention is not limited to the above-described embodiments, and modifications, improvements, and the like within the scope that can achieve the object of the present invention are included in the present invention.

  Next, an embodiment of the present invention will be described in detail using one specific example that is simply manufactured. However, the present invention is not limited to these examples.

Example 1
As a base material, glass (Corning Eagle XG, size: 40 mm × 40 mm, thickness: 0.7 mm) was prepared. A chromium electrode was formed to a thickness of 50 nm on the surface of the base material by sputtering to produce a gate electrode. Next, this substrate was ultrasonically cleaned with isopropyl alcohol for 10 minutes, and then dried by blowing dry N 2 gas.
On the lower gate electrode, a conductor composition ink (silver nanocolloid (average particle size: 40 nm), 2,3,5,6-tetrafluoro-4- (trifluoromethyl) benzenethiol and solvent (water and 1,3 A mixed solvent of propanediol and glycerin) mixed at a mass ratio of 39.4: 1.5: 59.1) was ink-jetted and baked at 150 ° C. for 30 minutes to form via posts.
Poly (methyl methacrylate) (PMMA, Sigma-Aldrich 445746) was dissolved in 1-methoxy-2-propyl acetate (Kanto Chemical Co., Ltd.) at 5 mass% to prepare a resin composition. The above-mentioned resin composition was applied to the surface of the base material by a spin coating method, and then dried on a hot plate (ASONE EC-1200NP) at 130 ° C. for 5 minutes to form a first gate insulating film made of PMMA. When the surface of the first gate insulating film was observed with a microscope (Olympus MX61), the first gate insulating film on the via post showed an opening.

Next, a conductive paste was printed by a reverse printing method and baked at 180 ° C. to form a source electrode and a drain electrode. Next, on the first gate insulating film between the source electrode and the drain electrode, a Regularregular poly (3-hexyl thiophene-2,5-diyl) (P3HT, Sigma-Aldrich 69889) is applied to the Decahydronaphthalene (Wako Pure). The organic semiconductor ink dissolved at 1 wt% was applied to Yakuhin Kogyo) and dried on a hot plate at 150 ° C. for 10 minutes to form a channel film.
On the via post protruding from the first gate insulating film and the drain electrode, the above-mentioned conductor composition ink was again ink-jetted and baked at 150 ° C. for 30 minutes to form a via post.

Next, the resin composition is applied on the entire structure of the resultant structure on which the via post, the channel film, the source electrode and the drain electrode have been formed, and then dried on a hot plate at 130 ° C. for 5 minutes. A second gate insulating film was formed by PMMA. When the surface of the second gate insulating film was observed with a microscope, the second gate insulating film on the via post described above showed an opening.
Then, a conductive paste was printed by a reverse printing method, fired at 180 ° C. to form an upper gate electrode, and electrically connected to the lower gate electrode through a via post to obtain a double gate transistor.

  About the obtained transistor, the probe for a measurement was made to contact with the lead wire connected to the source electrode and the drain electrode, respectively, and the transistor characteristic was measured using the semiconductor parameter analyzer (Agilent B1500A). As a result, the fabricated double gate transistor showed a normal operation in which the current value increased according to the potential difference between the source electrode and the drain electrode, and the gate voltage could control it. In addition, about twice as much on-current was obtained as compared with a single gate transistor having a similar structure.

DESCRIPTION OF SYMBOLS 100 Substrate 110 Buffer film 120 Lower gate electrode 130 First gate insulating film 140 Channel film 150 Protective film 160, 161, 200, 201 Convex-type via post 162 Source electrode 164 Drain electrode 170 Second gate insulating film 180 Upper gate electrode 181 Intermediate electrode 182 First functional electrode 190 Interlayer insulating film 260 Contact plug

Claims (16)

  A thin film transistor having two or more gate electrodes, wherein two of the two or more gate electrodes are electrically connected by a convex conductor containing metal particles.   The thin film transistor according to claim 1, wherein the conductor includes a liquid repellent material.   The thin film transistor according to claim 2, wherein the liquid repellent material is exposed on a surface of the conductor.   4. The thin film transistor according to claim 2, wherein the liquid repellent material is a fluorine-containing compound.   The thin film transistor according to claim 2, wherein the liquid repellent material is a fluorine-containing thiol compound.   The thin film transistor according to any one of claims 1 to 5, wherein the conductor has a surface energy of 10 mN / m or more and 80 mN / m or less. Including an insulating layer between two gate electrodes electrically connected by the conductor;
The conductor is formed on one gate electrode through the insulating layer;
The height of the conductor is 0.5 to 10 times the thickness of the insulating layer in the one gate electrode, according to any one of claims 1 to 6. Thin film transistor.   The thin film transistor according to claim 1, wherein the conductor has a diameter of 10 μm to 100 μm.   The thin-film transistor as described in any one of Claims 1-8 which has two gate electrodes.   The thin film transistor according to claim 1, wherein the semiconductor layer of the thin film transistor is a semiconductor layer made of an organic semiconductor material.   A convex conductor is formed by printing and baking a composition containing metal particles on a gate electrode, and the convex conductor electrically connects the gate electrode to another gate electrode. A method for manufacturing a thin film transistor having two or more gate electrodes.   The method of manufacturing a thin film transistor according to claim 11, wherein the composition contains a liquid repellent material.   13. The method of manufacturing a thin film transistor according to claim 12, wherein the liquid repellent material is a fluorine-containing compound.   The method for producing a thin film transistor according to claim 12 or 13, wherein the liquid repellent material is a fluorine-containing thiol compound.   The method of manufacturing a thin film transistor according to claim 11, wherein the printing is performed by an inkjet process.   An electronic apparatus comprising the thin film transistor according to claim 1.

Images