JP4984416B2

JP4984416B2 - Thin film transistor manufacturing method

Info

Publication number: JP4984416B2
Application number: JP2005101404A
Authority: JP
Inventors: 隆一中村; 修喜納; 透大久保; 亮平松原; 守石崎
Original assignee: 凸版印刷株式会社
Priority date: 2005-03-31
Filing date: 2005-03-31
Publication date: 2012-07-25
Anticipated expiration: 2025-03-31
Also published as: JP2006286719A

Description

The present invention relates to a method for manufacturing a thin film transistor.

A thin film transistor (TFT) in which amorphous silicon, polysilicon, or the like is formed on a glass substrate is manufactured based on a technology such as a transistor or an integrated circuit using a semiconductor itself as a substrate, and is applied to a liquid crystal display or an electronic book. In such a thin film transistor, amorphous glass or the like can be formed at a relatively low film formation temperature of about 400 to 500 degrees, so that an inexpensive glass having a melting point lower than that of quartz is used as a substrate.
In addition, in order to support electronic paper, RFID tags, etc., development of devices using organic semiconductors that form thin film transistors that form electronic circuits on flexible substrates from the viewpoint of flexibility, cost reduction, and weight reduction. Has been done.
In this thin film transistor using an organic semiconductor or an oxide semiconductor, the film forming temperature can be reduced from room temperature to about 200 ° C., so that a thin film transistor using a plastic substrate can be manufactured, and a light and flexible logic circuit is expected to be manufactured. Has been.

In general, when an organic semiconductor is used as a device configuration, a liquid process is possible, so that a large area, application of a printing method, and use of a plastic substrate are possible, and flexibility, cost reduction, and weight reduction are achieved. There exists an advantage which can achieve an objective (for example, nonpatent literature 1). In order to realize cost reduction and flexibility, it is desirable that not only a semiconductor but also a gate electrode, a source electrode, a drain electrode, and a gate insulating film are formed by a printing method or the like.
In addition, in the formation of electrodes using a printing method, development related to the formation of electrode patterns using a conductive polymer, a metal colloid solution, or the like has also been performed (Non-Patent Document 2).

For example, as shown in FIG. 9, a rectangular gate electrode 2 is formed on the upper surface of a substrate 1 made of plastic, and a source electrode 4 and a drain electrode 5 are formed thereon with a gate insulating film 3 interposed therebetween. A thin film transistor 40 having an organic semiconductor 6 formed thereon is known. In such a thin film transistor 40, the source electrode 4 and the drain electrode 5 are formed by screen printing. In general, in screen printing, in consideration of poor alignment accuracy of the source electrode 4, the drain electrode 5, and the gate electrode 2, the electrode overlap is designed to be large. Therefore, there is a possibility that the capacitance between the electrodes is large and the response speed of the thin film transistor is deteriorated.

As a method for solving such a problem, a gate electrode is formed on a transparent insulating substrate, a gate insulating film is formed thereon, a photoresist is further applied thereon, and then the gate electrode is self-exposed by back exposure. After leaving the matched resist pattern and depositing it so as to cover the position where the source electrode and drain electrode are formed and the resist pattern, the resist pattern is lifted off together with the deposited material to form the source electrode and drain electrode, and the gate There is a method for improving the alignment accuracy of the source electrode and the drain electrode with respect to the electrode (Non-Patent Document 3).
However, in such a method, there is a problem that a vacuum process called vapor deposition is necessary and production cost increases. If the resist pattern is not formed in a reverse taper shape, there is a problem that the film to be the source electrode and the drain electrode is connected to the film to be removed, which makes it difficult to lift off.
Science vo 1.265, 1684 (1994) Thin Solid Films Vol. 438, 279 (2003) Japan Journal of Applied Physics Vol. 43, no. 4B, 2323 (2004)

The present invention has been made in view of the above circumstances, and improves the alignment accuracy of the gate electrode, the source electrode, and the drain electrode without using an expensive process such as vapor deposition or lift-off, and the source electrode with respect to the gate electrode. And it aims at making overlap of a drain electrode small.

In order to achieve the above object, the present invention employs the following configuration.
The thin film transistor manufacturing method of the present invention includes a step of forming a gate electrode on a transparent insulating substrate, a step of forming a gate insulating film so as to cover the transparent insulating substrate and the gate electrode, and a step of forming a semiconductor layer. A method of manufacturing a thin film transistor comprising at least a step of applying a resist, a step of forming a resist pattern self-aligned with the gate electrode by back exposure, a step of forming a source electrode and a drain electrode, and a step of removing the resist a is, the step of forming the source electrode and the drain electrode, viewed contains the step of applying a liquid containing metal nanoparticles to form a resist pattern in the boundary portion between the source electrode formation portion and the drain electrode forming portion, A liquid containing the metal nanoparticles is applied thereon so as to include the source electrode forming part and the drain electrode forming part. And, and forming the resist pattern source and drain electrodes of the liquid by utilizing the force play the liquid is divided into the drain electrode formation portion and the source electrode formation portions of the.

According to this method, since the gate electrode acts as a light-shielding portion when the back exposure is performed, the resist in the portion shielded by the gate electrode has the same shape as the gate electrode in plan view, and the exposed portion By removing the resist, a resist accurately aligned with the gate electrode is formed. By applying a liquid containing metal nanoparticles to the resist, the liquid flows out onto the gate insulating film, and a source electrode and a drain electrode with one end face of the resist are formed on the gate insulating film. As a result, the one end surfaces of the source electrode and the drain electrode are accurately formed at the same position as the end surface of the gate electrode.
Furthermore, according to such a method, the liquid containing the metal nanoparticles applied on the resist pattern can flow out more reliably to the source electrode formation portion and the drain electrode formation portion, thereby forming the source electrode and the drain electrode.

In the method for manufacturing a thin film transistor of the present invention, it is preferable that the step of forming the source electrode and the drain electrode includes a step of flexographic printing.
The manufacturing method of a thin film transistor of the present invention includes the steps forming the source electrode and the drain electrode, to create with the drain electrode formation portion and the source electrode forming portions by the table pattern exposure and the back exposure, the And a step of applying a liquid containing the metal nanoparticles to the source electrode forming portion and the drain electrode forming portion in this order.
According to this method, the source electrode forming portion and the drain electrode forming portion can be manufactured by only the back exposure without using the front exposure.

In the method for producing a thin film transistor of the present invention, the step of applying the liquid containing the metal nanoparticles is preferably a dispensing step or an inkjet step.
In addition, the thin film transistor manufacturing method of the present invention is characterized in that the main component of the liquid solvent containing the metal nanoparticles is water.
According to this method, the liquid containing the metal nanoparticles applied on the resist flows out more reliably onto the gate insulating film. In this case, it is preferable to use a hydrophobic resist.

As described above, according to the method of manufacturing a thin film transistor of the present invention, the gate electrode acts as a light-shielding portion when the back exposure is performed. By removing the exposed portion of the resist that has substantially the same shape, a resist that is accurately aligned with the gate electrode is formed. By applying a liquid containing metal nanoparticles onto the resist-containing sample, this liquid flows out onto the gate insulating film, and a source electrode and a drain electrode with one end face of the resist formed on the gate insulating film. Is done. Thereby, the one end surfaces of the source electrode and the drain electrode can be accurately formed at the same position as the end surface of the gate electrode.
Further, a source electrode and a drain electrode that are self-aligned with the gate can be formed without using a high-cost process such as vapor deposition and without forming the resist in a reverse taper shape, similarly to vapor deposition lift-off.

Hereinafter, although embodiment of this invention is described with reference to FIGS. 1-8, this invention is not limited to these. In the drawings used below, the scale is different from the actual one for easy understanding of the description.

(First embodiment)
A first embodiment of the present invention for manufacturing the thin film transistor of FIG. 1 will be described below.
In the thin film transistor 30 of FIG. 1, a rectangular gate electrode 2 is formed on the upper surface of the transparent insulating substrate 1, and the insulating substrate 1 and the gate electrode 2 are covered with a gate insulating film 3. A rectangular source electrode 4 and drain electrode 5 are formed on the upper surface of the gate insulating film 3, and a gap between the source electrode 4 and the drain electrode 5 is covered with a semiconductor layer 6.

As shown in FIG. 2, in the manufacturing method of the first embodiment, a rectangular gate electrode 2 is formed on the upper surface of the transparent insulating substrate 1 (FIG. 2A), and the transparent insulating substrate 1 and the gate electrode 2 are formed. A gate insulating film 3 is formed so as to cover it, and a positive resist 20 is formed on the upper surface of the gate insulating film 3 (FIG. 2B). Here, a resist pattern 21 self-aligned with the gate electrode 2 is left by exposure (back exposure) from the back side of the transparent insulating substrate 1 (FIG. 2C) and development (FIG. 2D).
Next, when the liquid containing the metal nanoparticles is flexographically printed using a pattern including the source electrode forming portion 4a, the channel portion 8, and the drain electrode forming portion 5a, the liquid is repelled by the resist pattern 21 and the gate insulating layer. It flows out upward (FIG. 2 (e)). Here, the source electrode 4 and the drain electrode 5 are provisionally formed by temporary baking at a low temperature (about 100 ° C.), and then the resist pattern 21 is removed by dipping in a stripping solution (FIG. 2F). Thereafter, the main electrode is fired at about 150 ° C. to reduce the resistance of the source electrode 4 and the drain electrode 5. Finally, the semiconductor layer 6 is formed (FIG. 2G).

Note that the shape (forward taper or reverse taper) and width of the resist pattern 21 can be controlled by exposure conditions and development conditions.
In the manufacturing method of the present invention, the source electrode and the drain electrode can be formed even if the resist pattern 21 is forward tapered.
The source electrode formation portion is a region where the source electrode is formed, and the drain electrode formation portion is a region where the drain electrode is formed. The channel portion is a region between the source electrode 4 and the drain electrode 5 in a plan view arrangement, and is a region where a semiconductor layer is formed.

(Second Embodiment)
A second embodiment of the present invention for manufacturing the thin film transistor of FIG. 1 will be described below.
As shown in FIG. 3, in the manufacturing method of the second embodiment, a rectangular gate electrode 2 is formed on the upper surface of the transparent insulating substrate 1 (FIG. 3A), and the transparent insulating substrate 1 and the gate electrode 2 are formed. A gate insulating film 3 is formed so as to cover it, and a positive resist 20 is formed on the upper surface of the gate insulating film 3 (FIG. 3B). Here, the resist pattern 21 self-aligned with the gate electrode 2 and the source electrode forming portion 4a and the drain electrode by front pattern exposure using the mask 10, back pattern exposure using the mask 11 (FIG. 3C) and development. Resist patterns 22 and 23 surrounding the forming portion 5a are left (FIG. 3D).

In order to perform the exposure as described above, as the back exposure, the gate electrode 2 is exposed as a light shielding portion. Thus, a resist pattern 21 having the same shape as that of the gate electrode 2 is formed in a planar view. Further, a mask 11 having a light shielding part 14 slightly larger than the light shielding part 13 of the mask 10 for surface exposure is used so as not to hinder the formation of the resist patterns 22 and 23 by surface exposure. For surface exposure, the light shielding portion 13 is formed on the mask 10 so as to form resist patterns 22 and 23 surrounding the source electrode forming portion 4a and the drain electrode forming portion 5a. Further, a mask 10 that surrounds the gate electrode 2 and has a light shielding portion 13 slightly larger than the gate electrode 2 is used so as not to hinder the formation of the resist pattern 21 by back exposure.

Subsequently, a liquid containing metal nanoparticles is applied to the source electrode forming portion 4a and the drain electrode forming portion 5a by a dispenser or the like. At this time, even if the liquid is applied onto the resist pattern 21, it is repelled by the resist pattern 21 and separated into the source electrode forming portion 4a and the drain electrode forming portion 5a (FIG. 3E). Here, the liquid containing metal nanoparticles is temporarily fired at a low temperature (about 100 ° C.) to temporarily form the source electrode 4 and the drain electrode 5, and then immersed in a stripping solution to remove the resist patterns 21 to 23 (FIG. 3). (F)). Thereafter, the main electrode is fired at about 150 ° C. to reduce the resistance of the source electrode 4 and the drain electrode 5. Finally, the semiconductor layer 6 is formed (FIG. 3G).

Note that the shape (forward taper or reverse taper) and width of the resist pattern 21 can be controlled by exposure conditions and development conditions.
In addition, the resist patterns 22 and 23 can be formed with higher accuracy if they are formed by the front exposure pattern, but may be formed only by the light-shielding portion for the back exposure.

(Third embodiment)
A third embodiment of the present invention for manufacturing the thin film transistor of FIG. 4 will be described below.
In the thin film transistor 31 of FIG. 4, the gate electrode 2 and the gate wiring 7 are formed on the upper surface of the transparent insulating substrate 1, and the transparent insulating substrate 1, the gate electrode 2, and the gate wiring 7 are covered with the gate insulating film 3. A semiconductor layer 6 is formed on the upper surface of the gate insulating film 3, and a source electrode 4 and a drain electrode 5 are formed on the upper surface of the semiconductor layer 6. The source electrode 4 is formed in a circular shape, and the drain electrode 5 is formed in a shape in which a rectangular center is cut out into a circular shape. The gate electrode 2 is formed in a uniform width ring shape, and a gate wiring 7 is connected to a part of the outer circumference circle. In the plan view arrangement, the gate electrode 2 is formed between the source electrode 4 and the drain electrode 5, and the center positions of the electrodes are formed so as to substantially coincide with each other.

As shown in FIG. 5, in the manufacturing method of the third embodiment, a uniform-width ring-shaped gate electrode 2 and a gate wiring 7 are formed on the upper surface of a transparent insulating substrate 1 (FIG. 5A), and transparent insulation is performed. A gate insulating film 3 is formed so as to cover the substrate 1, the gate electrode 2, and the gate wiring 7. Further, the semiconductor layer 6 and the positive resist 20 are sequentially formed on the upper surface of the gate insulating film 3 (FIG. 5B). Next, the positive resist on the gate wiring is removed by front pattern exposure and back exposure using the mask 10 (FIG. 5C) and development, leaving only the resist pattern 21 self-aligned with the gate electrode 2 (FIG. 5). 5 (d)).

In order to perform the exposure as described above, as the back exposure, the gate electrode 2 is exposed as a light shielding portion. Thus, a resist pattern 21 having the same shape as that of the gate electrode 2 is formed in a planar view. As the front exposure, a mask 10 that surrounds the gate electrode 2 and has a light shielding portion 13 slightly larger than the gate electrode 2 is used so as not to hinder the formation of the resist pattern 21 by the back exposure.

Next, when the liquid containing the metal nanoparticles is flexographically printed using a pattern including the source electrode forming portion 4a, the channel portion 8, and the drain electrode forming portion 5a, the liquid is repelled by the resist pattern 21 to form the source electrode. The portion 4a and the drain electrode forming portion 5a are separated (FIG. 5E). Here, the source electrode 4 and the drain electrode 5 are temporarily formed by calcination at a low temperature (about 100 ° C.), and then the resist pattern 21 is removed by dipping in a stripping solution (FIG. 5F). Thereafter, the main electrode is fired at about 150 ° C. to reduce the resistance of the source electrode 4 and the drain electrode 5.
Note that the shape (forward taper or reverse taper) and width of the resist pattern 21 can be controlled by exposure conditions and development conditions.

(Fourth embodiment)
A fourth embodiment of the present invention for manufacturing the thin film transistor of FIG. 4 will be described below.
As shown in FIG. 6, a uniform-width ring-shaped gate electrode 2 and a gate wiring 7 are formed on the upper surface of the transparent insulating substrate 1 (FIG. 6A), on which a gate insulating film 3, a semiconductor layer 6 and Positive resists 20 are sequentially formed (FIG. 6B). Here, the front pattern exposure using the mask 10 and the back pattern exposure using the mask 11 (FIG. 6C) and development leave the resist pattern 21 and the resist pattern 23 self-aligned with the gate electrode 2 (FIG. 6). (D)).

In order to perform the exposure as described above, as the back exposure, the gate electrode 2 is exposed as a light shielding portion. Thus, a resist pattern 21 having the same shape as that of the gate electrode 2 is formed in a planar view. Further, a mask 11 that surrounds the resist pattern 23 to be formed and has a light shielding portion 14 slightly larger than the resist pattern 23 is used so as not to hinder the formation of the resist pattern 23 by surface exposure. For the surface exposure, the mask 10 is formed so as to form resist patterns 21 and 23 surrounding the source electrode forming portion 4a and the drain electrode forming portion 5a. Further, a mask 10 that surrounds the gate electrode 2 and has a light shielding portion 13 slightly larger than the gate electrode 2 is used so as not to hinder the formation of the resist pattern 21 by back exposure.

Next, a liquid containing metal nanoparticles is applied to the source electrode forming portion 4a and the drain electrode forming portion 5a by a dispenser or the like. At this time, even if the liquid is applied onto the resist pattern 21, it is repelled by the resist pattern 21 and separated into the source electrode forming portion 4a and the drain electrode forming portion 5a (FIG. 6E). Here, the source electrode 4 and the drain electrode 5 are temporarily formed at a low temperature (about 100 ° C.) and then immersed in a stripping solution to remove the resist patterns 21 and 23 (FIG. 6F). Thereafter, the main electrode is fired at about 150 ° C. to reduce the resistance of the source electrode 4 and the drain electrode 5.
Note that the shape (forward taper or reverse taper) and width of the resist pattern 21 can be controlled by exposure conditions and development conditions.

(Fifth embodiment)
A fifth embodiment of the present invention for manufacturing the thin film transistor of FIG. 7 will be described below.
In the thin film transistor 32 of FIG. 7, the gate electrode 2 and the gate wiring 7 are formed on the upper surface of the transparent insulating substrate 1, and the insulating substrate 1, the gate electrode 2, and the gate wiring 7 are covered with the gate insulating film 3. A source electrode 4, a drain electrode 5, and a semiconductor layer 6 are formed on the upper surface of the gate insulating film 3. The source electrode 4 is formed in a circular shape, and the drain electrode 5 is formed in a shape in which a rectangular center is cut out into a circular shape. The gate electrode 2 is formed in a uniform width ring shape, and a gate wiring 7 is connected to a part of the outer circumference circle. A semiconductor layer 6 is formed between the source electrode 4 and the drain electrode 5. The semiconductor layer 6 is disposed so as to overlap the gate electrode 2. That is, in the plan view arrangement, the gate electrode 2 is formed between the source electrode 4 and the drain electrode 5, and the center positions of the electrodes are formed so as to substantially coincide with each other.

As shown in FIG. 8, in the manufacturing method of the fifth embodiment, a uniform-width ring-shaped gate electrode 2 and a gate wiring 7 are formed on the upper surface of the transparent insulating substrate 1 (FIG. 8A), and then Then, the gate insulating film 3, the semiconductor layer 6 and the positive resist 20 are sequentially formed (FIG. 8B). Here, only the resist pattern 21 self-aligned with the gate electrode 2 is left by the front pattern exposure and back exposure using the mask 10 (FIG. 8C) and development (FIG. 8D).

In order to perform the exposure as described above, as the back exposure, the gate electrode 2 is exposed as a light shielding portion. Thus, a resist pattern 21 having the same shape as that of the gate electrode 2 is formed in a planar view. As the front exposure, a mask 10 that surrounds the gate electrode 2 and has a light shielding portion 13 slightly larger than the gate electrode 2 is used so as not to hinder the formation of the resist pattern 21 by back exposure.

Next, the semiconductor layer 6 is etched to leave the semiconductor layer 6 that becomes the channel portion 8 only under the resist pattern 21 (FIG. 8E). On top of that, when a liquid containing metal nanoparticles is flexographically printed using a pattern including the source electrode forming portion 4a, the channel portion 8 and the drain electrode forming portion 5a, the liquid is repelled by the resist pattern 21 and the source electrode Separated into a formation portion 4a and a drain electrode formation portion 5a (FIG. 8F). Here, the source electrode 4 and the drain electrode 5 are temporarily formed at a low temperature (about 100 ° C.) and then immersed in a stripping solution to remove the resist pattern 21 (FIG. 8G). Thereafter, the main electrode is fired at about 150 ° C. to reduce the resistance of the source electrode 4 and the drain electrode 5.
Note that the shape (forward taper or reverse taper) and width of the resist pattern 21 can be controlled by exposure conditions and development conditions.

As described above, in the present invention, a step of forming a gate electrode on a transparent insulating substrate, a step of forming a gate insulating film so as to cover the transparent insulating substrate and the gate electrode, and a step of forming a semiconductor layer A method of manufacturing a thin film transistor comprising at least a step of applying a resist, a step of forming a resist pattern self-aligned with the gate electrode by back exposure, a step of forming a source electrode and a drain electrode, and a step of removing the resist And the process of forming the said source electrode and a drain electrode includes the process of apply | coating the liquid containing a metal nanoparticle, It is characterized by the above-mentioned. However, the formation of the semiconductor layer may be a step subsequent to the formation of the gate insulating film, or may be a step after the source electrode 4 and the drain electrode 5 are formed. When the semiconductor layer 6 is an oxide, the former can be suitably used, and when the semiconductor layer 6 is an organic substance, the latter can be preferably used, but is not limited thereto. The gate electrode 2 has a rectangular shape and a ring shape, but is not limited thereto.

In the step of applying the liquid, flexographic printing is performed using a pattern including the source electrode 4, the channel portion 8, and the drain electrode 5, and the liquid in the channel portion 8 is repelled by the resist pattern and the source electrode 4 and the drain electrode 5. It is preferable that it is the process of isolate | separating into.
The resist preferably has hydrophobicity, and the larger the contact angle with water, the better. However, a resist of 30 ° or more can be used. For example, a novolac positive resist has a contact angle with water of about 40 ° to 80 ° and can be used sufficiently. It is more desirable to mix a water repellent (for example, silicone or fluorine) to make the contact angle 90 ° or more. Further, it is necessary that the contact angle of the underlayer with water is smaller than the contact angle of the resist 20 with water.

The above back exposure is pattern exposure using a mask having a light shielding portion in addition to the gate electrode, and the resist patterns 22 and 23 for forming the source electrode forming portion and the drain electrode forming portion together with the resist pattern 21 of the channel portion 8 are also included. You may leave and apply | coat a liquid with a dispenser etc. In this case, the exposure of the two types of resist patterns may be performed simultaneously at the same time or separately.

Metal nanoparticles are metal particles having a particle size of less than 1 μm. The main component of the liquid containing the metal nanoparticles is preferably water. Here, the main component is water means that 50 wt% or more of the solvent (that is, the metal nanoparticles are not included) is water. As the metal nanoparticles, Ag, Ni, Au, Pt, Pd, or the like can be used. Since the main component of the liquid is water, it is repelled by the resist 21 without dissolving the resists 21 to 23, and a good coating shape is obtained. On the other hand, when the organic solvent is the main component, the resist 21 is dissolved, and good coating is difficult.

As the semiconductor, an oxide semiconductor or an organic semiconductor can be used. As the oxide semiconductor, InGaZnO-based, InZnO-based, ZnGaO-based, InGaO-based, ZnO-based, SnO-based, or a mixture thereof is preferably used, and as the organic semiconductor, polythiophene derivatives, polyphenylene vinylene derivatives, polythienylenes are used. Vinylene derivatives, polyallylamine derivatives, polyacetylene derivatives, acene derivatives, oligothiophene derivatives and the like are preferably used.

In the case where a semiconductor layer is formed using an oxide semiconductor, film formation by sputtering or laser ablation can be preferably used. Also, metal organic chemical vapor deposition and coating / firing of raw materials can be used. In the case of forming a semiconductor layer using an organic semiconductor, coating and baking of raw materials can be preferably used.

Since oxide semiconductors and organic semiconductors can be formed at room temperature or at a low temperature of 200 ° C. or lower, a plastic material (polyethylene terephthalate (PET) or the like) can be used as the transparent insulating substrate 1.

As the gate electrode 2, metals such as Al, Cr, Au, Ag, Cu, Ti, and Ni can be used. As the gate insulating layer 3, inorganic materials such as SiO ₂ , Al ₂ O ₃ , SiN, Ta ₂ O ₅ , Y ₂ O ₃ , and organic materials such as epoxy can be used.

Example 1
A first embodiment of the present invention will be described with reference to FIG. Polyethylene terephthalate (PET) having a thickness of 100 μm was prepared as the substrate 1, and a rectangular gate electrode 2 was produced by sputtering Al, photolithography and etching (FIG. 2A). The thickness was 100 nm, the gate length was 300 μm, and the width was 5 μm. Next, the gate insulating film 3 and the positive resist 20 made of epoxy were formed by spin coating and baking (FIG. 2B). The thickness of the gate insulating film 3 was 500 nm, and the thickness of the positive resist 20 was 5 μm.

Next, a resist pattern 21 self-aligned with the gate electrode 2 was left by back exposure (FIG. 2C) and development (FIG. 2D). Then, the source electrode 4 and the drain electrode 5 were formed by the flexographic printing of the liquid containing Ag nanoparticle (FIG.2 (e)). After temporary baking at 100 ° C., the resist pattern 21 was removed with a stripping solution (FIG. 2F), and the source electrode 4 and the drain electrode 5 having a thickness of 300 nm were formed by main baking at 150 ° C. Finally, the semiconductor layer 6 was formed by dispensing and baking the polythiophene derivative solution (FIG. 2 (g)).

(Example 2)
A second embodiment of the present invention will be described with reference to FIG. Polyethylene terephthalate (PET) having a thickness of 100 μm was prepared as the substrate 1, and a rectangular gate electrode 2 was produced by sputtering Al, photolithography and etching (FIG. 3A). The thickness was 100 nm, the gate length was 300 μm, and the width was 5 μm. Next, the gate insulating film 3 and the positive resist 20 made of epoxy were formed by spin coating and baking (FIG. 3B). The thickness of the gate insulating film 3 was 500 nm, and the thickness of the positive resist 20 was 5 μm.

Next, a resist pattern 22 that forms a resist pattern 21 that is self-aligned with the gate electrode 2 and a source electrode forming portion 4a and a drain electrode forming portion 5a by front pattern exposure, back pattern exposure (FIG. 3C), and development, 23 was left (FIG. 3D). Then, the source electrode 4 and the drain electrode 5 were formed by the dispensing of the liquid containing Ag nanoparticle (FIG.3 (e)). After temporary baking at 100 ° C., the resist patterns 21 to 23 were removed with a stripping solution (FIG. 3 (f)), and a source electrode 4 and a drain electrode 5 having a thickness of 300 nm were formed by main baking at 150 ° C. Finally, the semiconductor layer 6 was formed by dispensing and baking the polythiophene derivative solution (FIG. 3G).

(Example 3)
A third embodiment of the present invention will be described with reference to FIG. As the substrate 1, polyethylene terephthalate (PET) having a thickness of 100 μm was prepared, and the ring-shaped gate electrode 2 and the gate wiring 7 were prepared by sputtering Al, photolithography and etching (FIG. 5A). The thickness of the gate electrode was 100 nm, the outer diameter was 300 μm, and the inner diameter was 290 μm. Next, SiO ₂ was formed as the gate insulating film 3 by sputtering, InGaZnO ₄ was formed as the semiconductor layer 6, and a positive resist 20 was formed by spin coating (FIG. 5B). The thickness of the gate insulating film 3 was 500 nm, the thickness of the semiconductor layer 6 was 200 nm, and the thickness of the resist 20 was 5 μm.

Next, a resist pattern 21 self-aligned with the gate electrode 2 was left by front surface exposure, back exposure (FIG. 5C), and development (FIG. 5D). And the source electrode 4 and the drain electrode 5 were formed by the flexographic printing of the liquid containing Ag nanoparticle (FIG.5 (e)). After temporary baking at 100 ° C., the resist pattern 21 was removed with a stripping solution (FIG. 5F), and a source electrode 4 and a drain electrode 5 having a thickness of 300 nm were formed by main baking at 150 ° C.

(Example 4)
A fourth embodiment of the present invention will be described with reference to FIG. Polyethylene terephthalate (PET) having a thickness of 100 μm was prepared as the substrate 1, and a ring-shaped gate electrode 2 was produced by sputtering Al, photolithography and etching (FIG. 7A). The thickness of the gate electrode was 100 nm, the outer diameter was 300 μm, and the inner diameter was 290 μm.
Next, SiO ₂ was formed as the gate insulating film 3 by sputtering, InGaZnO ₄ was formed as the semiconductor layer 6, and a positive resist 20 was formed by spin coating (FIG. 7B). The thickness of the gate insulating film 3 was 500 nm, the thickness of the semiconductor layer 6 was 200 nm, and the thickness of the resist 20 was 5 μm.

Next, a resist pattern 21 self-aligned with the gate electrode 2 and a resist pattern 23 for forming a drain electrode forming portion are left by front pattern exposure, back pattern exposure (FIG. 7C) and development (FIG. 7D). )). Then, the source electrode 4 and the drain electrode 5 were formed by dispensing a liquid containing Ag nanoparticles (FIG. 7E). After temporary baking at 100 ° C., the resist patterns 21 and 23 were removed with a stripping solution (FIG. 7F), and a source electrode 4 and a drain electrode 5 having a thickness of 300 nm were formed by main baking at 150 ° C.

(Example 5)
A fifth embodiment of the present invention will be described with reference to FIG. Polyethylene terephthalate (PET) having a thickness of 100 μm was prepared as the substrate 1, and the ring-shaped gate electrode 2 and gate wiring 7 were prepared by sputtering Al, photolithography and etching (FIG. 8A). The gate electrode has a thickness of 100 nm, an outer diameter of 300 μm, and an inner diameter of 290 μm.

Next, SiO ₂ was formed as the gate insulating film 3 by sputtering, InGaZnO ₄ was formed as the semiconductor layer 6, and a resist 20 was formed by spin coating (FIG. 8B). The thickness of the gate insulating film 3 was 500 nm, the thickness of the semiconductor layer 6 was 200 nm, and the thickness of the positive resist 20 was 5 μm. Next, a resist pattern 21 self-aligned with the gate electrode 2 was left by front pattern exposure, back exposure (FIG. 8C), and development (FIG. 8D). Here, the semiconductor layer 6 was etched by wet etching (FIG. 8E). And the source electrode 4 and the drain electrode 5 were formed by the flexographic printing of the liquid containing Ag nanoparticle (FIG.8 (f)). After temporary baking at 100 ° C., the resist pattern 21 was removed with a stripping solution (FIG. 8G), and a source electrode 4 and a drain electrode 5 having a thickness of 300 nm were formed by main baking at 150 ° C.

In the thin film transistors manufactured by the manufacturing methods of Examples 1 to 5, the overlapping width in the planar arrangement of the gate electrode, the source electrode, and the drain electrode was measured and found to be 1 μm or less in any of the examples. Further, even when the gate electrode and the source electrode and the drain electrode do not overlap and are separated from each other, the separation distance is 1 μm or less.

It is a figure which shows a thin-film transistor, (a) is a top view, (b) is sectional drawing. It is a figure which shows the manufacturing method of the thin-film transistor which concerns on the 1st Embodiment of this invention. It is a figure which shows the manufacturing method of the thin-film transistor which concerns on the 2nd Embodiment of this invention. It is a figure which shows a thin-film transistor, (a) is a top view, (b) is sectional drawing. It is a figure which shows the manufacturing method of the thin-film transistor which concerns on the 3rd Embodiment of this invention. It is a figure which shows the manufacturing method of the thin-film transistor which concerns on the 4th Embodiment of this invention. It is a figure which shows a thin-film transistor, (a) is a top view, (b) is sectional drawing. It is a figure which shows the manufacturing method of the thin-film transistor which concerns on the 5th Embodiment of this invention. It is a figure which shows the conventional thin-film transistor, (a) is a top view, (b) is sectional drawing.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Transparent insulating substrate, 2 ... Gate electrode, 3 ... Gate insulating film, 4 ... Source electrode, 4a ... Source electrode formation part, 5 ... Drain electrode, 5a ... Drain electrode formation part, 6 ... semiconductor layer, 7 ... gate wiring, 8 ... channel part, 10, 11 ... photomask, 12 ... ultraviolet light, 13, 14 ... light shielding part, 20: Positive resist, 21-23: Resist pattern, 30, 31, 32, 40: Thin film transistor

Claims

Forming a gate electrode on the transparent insulating substrate; forming a gate insulating film so as to cover the transparent insulating substrate and the gate electrode; forming a semiconductor layer; applying a resist ; A method of manufacturing a thin film transistor comprising at least a step of forming a resist pattern self-aligned with the gate electrode by exposure, a step of forming a source electrode and a drain electrode, and a step of removing the resist,
The step of forming the source electrode and the drain electrode, viewed contains the step of applying a liquid containing metal nanoparticles,
A resist pattern is formed at a boundary portion between the source electrode formation portion and the drain electrode formation portion, and a liquid containing the metal nanoparticles is applied thereon so as to include the source electrode formation portion and the drain electrode formation portion, A manufacturing method of a thin film transistor, wherein a source electrode and a drain electrode are formed by dividing the liquid into the source electrode forming portion and the drain electrode forming portion using a force of repelling the liquid of a resist pattern. Method.
2. The method of manufacturing a thin film transistor according to claim 1, wherein the step of forming the source electrode and the drain electrode includes a step of flexographic printing.
The step of forming the source electrode and the drain electrode, a step of creating said drain electrode forming portion and the source electrode forming portions by the table pattern exposure and the back exposure, the drain electrode formation portion and the source electrode forming portion The method for producing a thin film transistor according to claim 1, further comprising a step of applying a liquid containing the metal nanoparticles in this order.
The method of manufacturing a thin film transistor according to claim 3, wherein the step of applying the liquid containing the metal nanoparticles is a dispensing step or an inkjet step.
5. The method of manufacturing a thin film transistor according to claim 1, wherein a main component of the liquid solvent containing the metal nanoparticles is water.