JP2012119531A - Semiconductor device, manufacturing method of semiconductor device, electric apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, a manufacturing method of the semiconductor device, and an electric apparatus.SOLUTION: A semiconductor device of this invention includes: a first substrate 34 having a source electrode 41c and a drain electrode 41d on one surface; a second substrate 39 having a gate electrode 41e, a gate insulation film 41b, and a semiconductor layer 41a; and a thin film transistor TR formed between the first substrate 34 and the second substrate 39 by bonding the first substrate 34 to the second substrate 39 with the one surface of the first substrate 34 and the one surface of the second substrate 39 facing each other.

Description

  The present invention relates to a semiconductor device, a semiconductor device manufacturing method, and an electric device.

  Conventionally, a method of forming a thin film transistor by sequentially forming and processing a plurality of thin films on a substrate is known (Patent Document 1). Also disclosed is a method of connecting a pixel electrode and a thin film transistor by forming a pixel electrode on a substrate different from the substrate on which the thin film transistor is formed and bonding the substrates together through an anisotropic conductive film. (Patent Documents 2 and 3).

JP 2010-135584 A JP 2005-114916 A JP 2004-272162 A

  However, in the case of Patent Document 1, since the thin film transistor is present on the surface of the substrate, the material constituting the thin film transistor is easily broken during the subsequent process or in actual use due to peeling off from the substrate. This is a particular problem when a thin film transistor is formed on a flexible substrate and the substrate is used in a curved state, for example. In addition, since a plurality of thin films are continuously formed on the substrate and the processing is repeated for each thin film, defects are likely to occur and the yield is reduced.

  Further, when forming a source electrode, a drain electrode, and the like constituting the thin film transistor, patterning of the metal film is performed using a photoetching method. Since the underlying semiconductor layer and gate insulating film are exposed to the etching solution and stripping solution used at this time, the semiconductor layer and the gate insulating film suffer from problems such as deterioration, resulting in deterioration of the characteristics and reliability of the thin film transistor produced. It is easy to deteriorate. Even if an attempt is made to create a thin film transistor by a printing method without using a photo-etching method, the pattern rule becomes large (photo-etching method: L / S = 3/3 μm, printing method: L / S = about 20/20 μm), which is necessary The definition cannot be obtained.

  In addition, in the case of Patent Documents 2 and 3, since an anisotropic conductive film is required, realization of a thin flat panel display is hindered. Moreover, the subject of the position accuracy which provides it arises.

  The present invention has been made in view of the above-described problems of the prior art, and an object of the present invention is to provide a thin and light semiconductor device, a semiconductor device manufacturing method, and an electric device.

  The semiconductor device of the present invention includes a first substrate having a source electrode and a drain electrode on one surface, a second substrate having a gate electrode, a gate insulating film, and a semiconductor layer on one surface, the first substrate, and the second substrate. Includes a thin film transistor formed between the first substrate and the second substrate by being bonded to each other with the one side facing each other.

  According to this, an anisotropic conductive film as conventionally used is not required at the bonding interface between the first substrate and the second substrate, so that a thin and light semiconductor device having a thin film transistor having a TGBC structure is formed. can do.

  The semiconductor device of the present invention includes a first substrate having a source electrode, a drain electrode, and a semiconductor layer on one surface, a second substrate having a gate electrode on one surface, the source electrode, the drain electrode, and the gate electrode. A gate insulating film that is disposed between and insulates between the first substrate and the second substrate, and the first substrate and the second substrate are bonded to each other with the one side facing each other. And the gate insulating film is provided on the first substrate or the second substrate.

  According to this, since the anisotropic conductive film used conventionally is unnecessary at the bonding interface between the first substrate and the second substrate, the BGTC structure, the BGBC structure, the TGBC structure, and the TGTC structure. A thin and light semiconductor device including a thin film transistor having any structure can be obtained.

  A semiconductor device according to the present invention includes a first substrate having a source electrode, a drain electrode, a gate electrode, and a gate insulating film disposed between the source electrode, the drain electrode, and the gate electrode on one surface. And a second substrate having a semiconductor layer on one side, and the first substrate and the second substrate are bonded together with the one side facing each other, so that the first substrate and the second substrate And a thin film transistor formed therebetween.

  This eliminates the need for an anisotropic conductive film as used in the past at the bonding interface between the first substrate and the second substrate. Therefore, a thin and light semiconductor having a thin film transistor having a TGTC structure or a BGBC structure. A device can be formed.

The semiconductor layer may be made of an organic semiconductor or an oxide semiconductor.
Here, the thin film transistor is configured by bonding the first substrate and the second substrate. At this time, conduction between the semiconductor layer, the drain electrode, and the source electrode is obtained by press bonding. For this reason, if the surface of the semiconductor layer is made of a material that forms a natural oxide film, such as silicon, conduction cannot be stably achieved. In the present invention, by using an organic semiconductor or an oxide semiconductor as a semiconductor layer of the thin film transistor, a change in contact resistance does not occur, and stable conduction with each of the electrodes can be achieved.

  In addition, the thin film transistor has an offset configuration in which the source electrode, the drain electrode, and the gate electrode do not overlap each other in plan view, and a first conductive portion connected to the source electrode, and the drain electrode At least a portion of the second conductive portion connected to the gate electrode overlaps the gate electrode in plan view, and the first conductive portion and the second conductive portion include the gate electrode, the drain electrode, and the It is good also as a structure formed using a softer material than a source electrode.

  Here, when an overlap region between electrodes made of a hard metal material is to be formed by bonding the substrates together, a short circuit occurs between these hard electrodes due to the pressure bonding when the substrates are bonded together. There are things to do. According to the configuration of the present invention, the overlap region is formed between the gate electrode and the first and second conductive portions that are connected to the drain electrode and the source electrode, respectively, and are made of a softer material than each electrode. Therefore, it is possible to prevent a short circuit between the gate electrode, the drain electrode, and the source electrode, which is caused by pressure bonding between the substrates.

Further, a protective layer may be provided at the interface between the semiconductor layer and the first substrate or the second substrate.
According to this, since it is possible to prevent impurities from entering the semiconductor layer, it is possible to prevent the electrical characteristics from changing greatly.

Further, a pixel electrode connected to the drain electrode may be provided on the surface of the first substrate or the second substrate.
According to this, the pixel electrode can be formed by a photoetching method. Compared with the case of forming by a coating method, the dimensional accuracy becomes high. In addition, since the thin film transistor connected to the pixel electrode is held between the substrates, a sufficient region for forming the pixel electrode can be secured. As a result, the arrangement and size of the electrodes can be changed as appropriate, and the degree of freedom in design is improved.

Further, a reflective film may be provided so as to cover at least the semiconductor layer.
According to this, since it is possible to prevent external light from entering the semiconductor layer, the thin film transistor is prevented from being damaged by the light leakage current. Further, a display device capable of displaying a bright image can be obtained by reflecting external light.

Further, the first substrate and the second substrate may be flexible or stretchable.
According to this, the entire semiconductor device including the thin film transistor has flexibility, and the semiconductor device can be used by being bent. Even in such a use state, since the thin film transistor is disposed between the first substrate and the second substrate, peeling of the thin film transistor and the like are prevented, and the thin film transistor is favorably held between these substrates. Thereby, a thin and light semiconductor device having flexibility can be obtained.

The method for manufacturing a semiconductor device of the present invention includes a step of forming a source electrode and a drain electrode on one surface of a first substrate, a step of forming a gate electrode, a gate insulating film and a semiconductor layer on one surface of the second substrate, A step of forming a thin film transistor between the first substrate and the second substrate by bonding the one surface side of the first substrate and the second substrate to each other.
According to this, since the anisotropic conductive film used conventionally is unnecessary, a thin and light semiconductor device having a thin film transistor having a TGBC structure can be formed.

  The method for manufacturing a semiconductor device according to the present invention includes a step of forming a source electrode and a drain electrode on one surface of a first substrate, a step of forming a semiconductor layer on the source electrode and the drain electrode, and a surface of the second substrate. Forming a gate electrode; forming a gate insulating film on the first substrate having the source electrode, the drain electrode, and the semiconductor layer; or forming a gate insulating film on the second substrate having the gate electrode. And a step of forming a thin film transistor between the first substrate and the second substrate by bonding the one side of the first substrate and the second substrate to each other. To do.

  According to this, since the conventionally used anisotropic conductive film becomes unnecessary, a semiconductor device having a thin and light thin film transistor can be obtained. Further, by changing the types of constituent elements of the thin film transistor formed separately on the first substrate and the second substrate, a semiconductor device having a thin film transistor of each structure of the BGTC structure, the BGBC structure, the TGBC structure, and the TGTC structure is formed. can do.

  The method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode on one surface of a first substrate, a step of forming a gate insulating film on the first substrate so as to cover the gate electrode, and the gate insulation A step of forming a source electrode and a drain electrode on the film; a step of forming a semiconductor layer on one surface of the second substrate; and bonding the one surface side of the first substrate and the second substrate to each other. Forming a thin film transistor between one substrate and the second substrate.

  According to this, since a conventionally used anisotropic conductive film is not necessary, a thin and light semiconductor device having a thin film transistor having a TGTC structure or a BGBC structure can be formed.

Alternatively, the semiconductor layer may be made of an organic semiconductor or an oxide semiconductor.
Here, the thin film transistor is configured by bonding the first substrate and the second substrate. At this time, conduction between the semiconductor layer, the drain electrode, and the source electrode is achieved by pressure bonding at the time of bonding the substrates. For this reason, if the surface of the semiconductor layer is made of a material that forms a natural oxide film, such as silicon, conduction cannot be stably achieved. In the present invention, by using an organic semiconductor or an oxide semiconductor as a semiconductor layer of the thin film transistor, a change in contact resistance does not occur, and stable conduction with each of the electrodes can be achieved.

In the step of forming the source electrode and the drain electrode, the source electrode and the drain electrode are formed at offset positions that do not overlap the gate electrode in plan view, and are connected to the source electrode. A step of forming a first conductive portion and a second conductive portion connected to the drain electrode, wherein in the step, at least a part of the first conductive portion and the second conductive portion in the plan view It may be formed so as to overlap with the gate electrode, and a material softer than the gate electrode, the drain electrode, and the source electrode may be used as a material for forming the first conductive portion and the second conductive portion.
According to this, it is possible to prevent a short circuit between the gate electrode, the drain electrode, and the source electrode, which is caused by pressure bonding when the first substrate and the second substrate are bonded to each other.

Further, a protective layer may be formed at the interface between the semiconductor layer and the first substrate or the second substrate.
According to this, since it is possible to prevent impurities from entering the semiconductor layer, it is possible to prevent the electrical characteristics from changing greatly.

Further, the method may include a step of forming a pixel electrode connected to the drain electrode on one of the first substrate and the second substrate.
According to this, the pixel electrode can be formed by a photoetching method. Compared with the case of forming by a coating method, the dimensional accuracy becomes high. In addition, since the thin film transistor connected to the pixel electrode is held between the substrates, a sufficient formation region of the pixel electrode can be secured on the surface of the substrate. The degree of freedom in design can be improved.

Moreover, it is good also as a method which has the process of forming the reflective film which covers at least the said semiconductor layer in any one of a said 1st board | substrate and a said 2nd board | substrate.
According to this, since it is possible to prevent external light from entering the semiconductor layer, the thin film transistor is prevented from being damaged by the light leakage current. Further, a display device capable of displaying a bright image can be obtained by reflecting external light.

In addition, an alignment mark is formed on each of the one surface of the first substrate and the second substrate, and a reading hole for reading the alignment mark on another substrate with respect to the first substrate and the second substrate When the substrates are bonded to each other, the alignment marks on one substrate are read through the reading holes on the other substrate, thereby bonding the first substrate and the second substrate to each other. It is good also as a method of determining a position.
According to this, since the alignment mark formed on each of the first substrate and the second substrate is read through the reading hole formed on the other substrate, the bonding position between the substrates is determined. The material for forming the alignment mark is not particularly limited.

In addition, when an alignment mark is formed on the one surface of the first substrate and the first substrate and the second substrate are bonded together, transmitted light that passes through the second substrate is used on the first substrate. It is good also as a method of determining the bonding position of the said 1st board | substrate and the said 2nd board | substrate by reading the said alignment mark.
This eliminates the need to form reading holes in the first substrate and the second substrate. When used in a display device, since one substrate side is the viewing side, there is no problem even if it is a transparent substrate.

The electrical device of the present invention includes an element substrate provided with a plurality of electrodes, a counter substrate disposed to face the element substrate, a functional element disposed between the element substrate and the counter substrate, The element substrate is made of the above semiconductor device, and the thin film transistor embedded in the element substrate is connected to the electrode.
According to this, since a semiconductor device in which the first substrate and the second substrate are bonded to each other without an anisotropic conductive film is used as the element substrate, a thin and light electric device can be obtained.

Further, the functional element may be a display element having a display portion in which a plurality of pixels are arranged, and the thin film transistor may function as a switching element for driving the pixels constituting the display portion.
According to this, since the thin film transistor as the switching element is held in the element substrate, a highly reliable, thin and light display device can be obtained.

Sectional drawing which shows schematic structure of the semiconductor device which incorporated the thin-film transistor of each structure in the board | substrate. Sectional drawing which shows schematic structure of the semiconductor device which incorporated the thin-film transistor and the reflective electrode. FIG. 6 is a cross-sectional view illustrating a schematic configuration of a semiconductor device that does not include a pixel electrode. 1 is a cross-sectional view illustrating a schematic configuration of a semiconductor device provided with a pixel electrode on a back surface side of a semiconductor substrate. FIG. 3 is a cross-sectional view illustrating a schematic configuration of a semiconductor device in which a plurality of island-shaped pixel electrodes are arranged in one pixel. Sectional drawing which shows the manufacturing process of the semiconductor device incorporating the thin-film transistor of a BGTC structure. The figure for demonstrating the bonding state of the 1st board | substrate and the 2nd board | substrate. Sectional drawing which shows the 2nd manufacturing process of the semiconductor device incorporating the thin-film transistor of a bottom gate top contact (BGTC) structure. Sectional drawing which shows the 3rd manufacturing process of the semiconductor device which incorporates the thin-film transistor of a bottom gate top contact (BGTC) structure. Sectional drawing which shows the 4th manufacturing process of the semiconductor device incorporating the thin-film transistor of a bottom gate top contact (BGTC) structure. 10 is a cross-sectional view illustrating a manufacturing process of a semiconductor device including a thin film transistor having a TGBC structure. FIG. Sectional drawing which shows the 2nd manufacturing process of the semiconductor device incorporating the thin-film transistor of a top gate bottom contact (TGBC) structure. Sectional drawing which shows the manufacturing process of the semiconductor device incorporating the thin-film transistor of a BGBC structure. Sectional drawing which shows the manufacturing process of the semiconductor device incorporating the thin-film transistor of a TGTC structure. Sectional drawing which shows the manufacturing process of the semiconductor device which incorporates the thin-film transistor provided with the protective layer. Sectional drawing which shows the manufacturing process of the semiconductor device provided with the reflective electrode and the thin-film transistor of BTBC structure. (A)-(e) is a top view which shows schematic structure of the active matrix substrate produced using the thin-film transistor of each above-mentioned structure. The equivalent circuit diagram in 1 pixel. Sectional drawing which follows the AA line of FIG.17 (c). Sectional drawing which follows the BB line of FIG.17 (e). Sectional drawing which shows schematic structure of an electrophoretic display apparatus. Sectional drawing which shows schematic structure of a liquid crystal device. The figure which shows schematic structure of the element substrate to which the moisture resistance with respect to the control transistor was provided. (A) is sectional drawing which shows TFT of an offset structure, (b) is sectional drawing which comprises the retention capacity of an offset structure. (A) is a figure which shows the structure before a countermeasure, (b) is a figure which shows the structure after a countermeasure. The figure which shows the example in which the pressure sensor was provided in the fingertip of the robot. Sectional drawing which shows the structure of a pressure-sensitive sensor. The figure which shows the factor which reduces manufacturing yield.

  Embodiments of the present invention will be described below with reference to the drawings. In each drawing used for the following description, the scale of each member is appropriately changed to make each member a recognizable size.

[Semiconductor Device of First Embodiment]
Hereinafter, the configuration of the semiconductor devices 100 (1) to 100 (4) including the thin film transistor TR having each structure will be described focusing on the configuration of the thin film transistor TR.
FIG. 1 is a cross-sectional view showing a schematic configuration of a semiconductor device in which a thin film transistor having each structure is built in a substrate, where (a) is a bottom gate top contact (BGTC) structure, and (b) is a top gate bottom contact. (TGBC) structure, (c) shows a bottom gate bottom contact (BGBC) structure, and (d) shows a top gate top contact (TGTC) thin film transistor.

(BGTC structure)
As shown in FIG. 1A, a thin film transistor TR (bgtc) having a BGTC structure includes a gate electrode 41e provided on the surface (one surface) 34a of the first substrate 34, and a surface 34a covering the gate electrode 41e. A gate insulating film 41b provided on the entire surface of the semiconductor layer 41, a semiconductor layer 41a provided on the gate insulating film 41b so as to overlap the gate electrode 41e, and a source formed so as to partially run on the peripheral edge of the semiconductor layer 41a It consists of an electrode 41c and a drain electrode 41d. On the first substrate 34, a second substrate 39 is provided on the entire surface 34a so as to cover the thin film transistor TR (bgtc). The pixel electrode 35 formed on the second substrate 39 is connected to the drain electrode 41 d through a contact hole H that penetrates the thickness direction of the second substrate 39.

(TGBC structure)
As shown in FIG. 1B, the thin film transistor TR (tgbc) having the TGBC structure is formed on the source electrode 41c and the drain electrode 41d provided on the surface 34a of the first substrate 34, and on the source electrode 41c and the drain electrode 41d. A semiconductor layer 41a formed so as to partially climb, a gate insulating film 41b formed over the entire surface 34a so as to cover the semiconductor layer 41a, and the semiconductor layer 41a and the source electrode 41c on the gate insulating film 41b. And a gate electrode 41e disposed at a position overlapping the drain electrode 41d. On the first substrate 34, a second substrate 39 is provided so as to cover the thin film transistor TR (tgbc). The pixel electrode 35 formed on the second substrate 39 is connected to the drain electrode 41d through a contact hole H penetrating the second substrate 39 and the gate insulating film 41b in the thickness direction.

(BGBC structure)
As shown in FIG. 1C, the thin film transistor TR (bgbc) having the BGBC structure has a gate electrode 41e provided on the surface 34a of the first substrate 34 and the entire surface 34a so as to cover the gate electrode 41e. The source electrode 41c and the drain electrode 41d provided on the gate insulating film 41b and on the gate insulating film 41b so as to overlap a part of the gate electrode 41e, and the source electrode 41c and the drain electrode 41d. The semiconductor layer 41a is provided so as to partially ride up. On the first substrate 34, a second substrate 39 is provided so as to cover the thin film transistor TR (bgbc). The pixel electrode 35 formed on the second substrate 39 is connected to the drain electrode 41d of the thin film transistor TR (tgbc) through a contact hole H penetrating the second substrate 39 in the thickness direction.

(TGTC structure)
As shown in FIG. 1D, the thin film transistor TR (tgtc) having a TGTC structure has a semiconductor layer 41a provided on the surface 34a of the first substrate 34 and a part of the semiconductor layer 41a on the peripheral edge thereof. On the gate insulating film 41b, the source electrode 41c and the drain electrode 41d provided, the gate insulating film 41b provided on the entire surface 34a so as to cover the semiconductor layer 41a, the source electrode 41c and the drain electrode 41d, The gate electrode 41e is provided so as to overlap with part of the semiconductor layer 41a, the source electrode 41c, and the drain electrode 41d. On the first substrate 34, a second substrate 39 is provided so as to cover the thin film transistor TR (tgtc). The pixel electrode 35 formed on the second substrate 39 is connected to the drain electrode 41d of the thin film transistor TR (tgtc) through a contact hole H penetrating the second substrate 39 and the thickness direction of the gate insulating film 41b. Has been.

  Here, the first substrate 34 is made of polyimide having a thickness of 50 μm, the gate electrode 41 e is made of Cu having a thickness of 0.5 μm, the gate insulating film 41 b is made of acrylic having a thickness of 0.5 μm, and the semiconductor layer 41 a is thick. It consists of pentacene with a thickness of 0.05 μm. The source electrode 41c and the drain electrode 41d are made of Cu having a thickness of 1 μm, and the second substrate 39 is made of polyimide having a thickness of 50 μm. The pixel electrode 35 is made of Cu having a thickness of 0.3 μm.

  In general, the second substrate 39 is made of an insulating material such as acrylic having a thickness of about 10 μm, and is used to serve both as a protection and an insulating function for the thin film transistor TR. For this reason, the thin film transistor TR has a structure covered with a thick insulating film as a result, and it is difficult for the constituent elements to be damaged when handled.

  Moreover, since both the 1st board | substrate 34 and the 2nd board | substrate 39 are comprised from the polyimide material, they have a flexibility. For this reason, as the first substrate 34 and the second substrate 39 are curved, the thin film transistor TR formed between the substrates 34 and 39 is also curved, and has flexibility. Since the thin film transistor TR is sandwiched between the two substrates 34 and 39, even if both the substrates 34 and 39 are curved, the constituent elements of the thin film transistor TR are not easily peeled off from the surfaces of the substrates. Peeling between elements is less likely to occur. For this reason, the characteristics of the thin film transistor are not deteriorated even when used in a curved state, and the highly reliable semiconductor device 100 having excellent robustness can be obtained.

  Here, the first substrate 34 and the second substrate 39 are preferably non-transparent substrates. In general, the semiconductor layer 41a easily absorbs light. When light is absorbed, light leakage occurs, and an effective ON / OFF ratio of the thin film transistor TR is reduced, or carriers induced by light move into the gate insulating film 41b and the threshold value Vth is shifted. is there. In order to avoid this, it is desirable that both the upper and lower substrates 34 and 39 sandwiching the thin film transistor TR are non-transparent.

In the above description, it has been described that both the first substrate 34 and the second substrate 39 are made of a polyimide material. However, the present invention is not limited to this. For example, polyester, other organic materials, or inorganic materials can be used to provide flexible substrates, such as phenol, paper epoxy, glass composite, glass epoxy, thin glass, Teflon (registered trademark), ceramics, their composite materials, and others. By using an organic material or an inorganic material, a rigid substrate that is not flexible is obtained. Here, stretchability can be imparted by using a stretchable substrate in which rubber, nonwoven fabric, or woven fabric is coated with an organic material.
In addition, the pixel electrode 35, the gate electrode 41e, the source electrode 41c, and the drain electrode 41d are made of other paste, metal, conductive material such as carbon nanotube, inorganic conductive material, organic conductive material, transparent electrode (ITO, etc.) or It is also possible to form using a conductive paste.

[Each semiconductor device of the second embodiment]
Next, each semiconductor device of the second embodiment will be described.
FIG. 2 is a cross-sectional view showing a schematic configuration of a semiconductor device incorporating a thin film transistor and a reflective electrode, and FIGS. 2A to 2D show the thin film transistor and the reflective electrode of each structure.
As illustrated in FIGS. 2A to 2D, the semiconductor devices 102 (1) to 102 (4) each include a thin film transistor TR having each structure between a first substrate 34 and a second substrate 39. A reflective electrode 45 having a predetermined size is provided on the surface 39 a of each second substrate 39. The reflective electrode 45 is made of Al or Au having a thickness of 0.5 μm and has a size that covers at least the channel region of the semiconductor layer 41a. The reflective electrode 45 has a configuration in which a potential can be input from the outside. For example, the same potential as that of the pixel electrode 35 may be input. On the 2nd board | substrate 39, the 3rd board | substrate 46 formed in the whole surface 39a so that the reflective electrode 45 may be covered is provided. The third substrate 46 is a transparent substrate.

Here, the reflective electrode 45 can also be configured using a metal, carbon nanotube, or the like other than those described above. The reflective electrode 45 is provided so as to cover the semiconductor layer 41a, and also serves as a light shielding layer. Further, instead of the reflective electrode 45 capable of inputting a potential, it may be provided as a light shielding layer. By doing so, the material is not limited to a conductive material, and other materials can be used as long as a light shielding function is obtained.
Note that the reflective electrode 45 may be connected to the pixel electrode 35.

  In the present embodiment, as described above, the configuration may be such that a potential can be input to the reflective electrode 45. In this case, the semiconductor device of this configuration is employed as the element substrate of the electrophoretic display device. In some cases, it can function as a control electrode for controlling the movement of the charged particles. Thereby, the movement of the charged particles becomes smooth and the display can be switched stably.

  The semiconductor devices 100 and 102 of the first and second embodiments described above are constituted by a semiconductor substrate 111 in which a thin film transistor TR is embedded, and a pixel electrode 35 provided on the surface 111a. Such a configuration (configuration of the thin film transistor TR and the pixel electrode 35) can be employed in the configuration of an element substrate (active matrix substrate) of an electro-optical device in which a part of a pixel circuit is embedded in the substrate. is there.

[Each Semiconductor Device of Third Embodiment]
Next, each semiconductor device of the third embodiment will be described.
FIG. 3 is a cross-sectional view showing a schematic configuration of a semiconductor device having no pixel electrode, and shows a case where thin film transistors having respective structures are provided in (a) to (d).
As shown in FIGS. 3A to 3D, the semiconductor devices 103 (1) to 103 (4) are each configured without the pixel electrode 35. The configuration of such a semiconductor device (only the thin film transistor) is not a pixel circuit constituted by each thin film transistor TR and the pixel electrode 35, but a built-in driver (scanning line drive driver, data line drive driver) for driving the pixel circuit. It is possible to employ in this configuration. Alternatively, when a circuit for obtaining other functions or an inspection circuit is configured, a configuration in which the thin film transistor TR is built in the substrate can be employed.

[Each Semiconductor Device of Fourth Embodiment]
Next, each semiconductor device of the fourth embodiment will be described.
FIG. 4 is a cross-sectional view showing a schematic configuration of a semiconductor device provided with a pixel electrode on the back surface side of a semiconductor substrate, and shows a case where a thin film transistor having each structure is provided in (a) to (d).
As shown in FIG. 4A, the pixel electrode 35 provided on the back surface 111b (the back surface 34b of the first substrate 34) side of the semiconductor substrate 111 is a contact hole H penetrating the first substrate 34 and the gate insulating film 41b. Is connected to the drain electrode 41d of the thin film transistor TR having the BGTC structure.
As shown in FIG. 4B, the pixel electrode 35 provided on the back surface 111 b (the back surface 34 b of the first substrate 34) side of the semiconductor substrate 111 is connected to the TGBC via a contact hole H penetrating the first substrate 34. It is connected to the drain electrode 41d of the thin film transistor TR having the structure.
As shown in FIG. 4C, the pixel electrode 35 provided on the back surface 111b (the back surface 34b of the first substrate 34) side of the semiconductor substrate 111 is a contact hole H penetrating the first substrate 34 and the gate insulating film 41b. Is connected to the drain electrode 41d of the thin film transistor TR having the BGBC structure.
As shown in FIG. 4D, the pixel electrode 35 provided on the back surface 111b (the back surface 34b of the first substrate 34) side of the semiconductor substrate 111 is connected to the TGTC through a contact hole H penetrating the first substrate 34. It is connected to the drain electrode 41d of the thin film transistor TR having the structure.

As described above, in the case where the pixel electrode 35 is provided on the back surface 111b side of the semiconductor substrate 111, the pixel electrode 35 can be formed by a photoetching method. It can be formed with higher accuracy than when formed by a coating method. For this reason, one pixel can be constituted by an assembly of a plurality of small island-like pixel electrodes 35.
Further, since the thin film transistor TR is held between the first substrate 34 and the second substrate 39, a sufficient formation region of the pixel electrode 35 can be secured on the back surface 34b of the substrate 34. Thereby, the arrangement and size of the pixel electrode 35 can be changed as appropriate, and the degree of freedom in design is improved.

[Each Semiconductor Device of Fifth Embodiment]
Next, each semiconductor device of the fifth embodiment will be described.
FIG. 5 is a cross-sectional view showing a schematic configuration of a semiconductor device in which a plurality of island-shaped pixel electrodes are arranged in one pixel, and shows a case where thin film transistors having respective structures are provided in (a) to (d). . In the figure, a part of one pixel is shown.
As shown in FIGS. 5A to 5D, each of the semiconductor devices 105 (1) to 105 (4) has a plurality of island-like pixel electrodes 35 in a predetermined region. It is connected to one thin film transistor TR. The semiconductor substrate 111 of the present embodiment includes a first substrate 34 and a second substrate 39, a thin film transistor TR disposed between the substrates 34 and 39, and a third substrate disposed on the back surface 34b side of the first substrate 34. 46. All of these pixel electrodes 35 are provided on the back surface 111 b of the semiconductor substrate 111 (the back surface 46 b of the third substrate 46). Then, by being connected to each other by the connection electrodes 44 formed on the back surface 34b of the first substrate 34, all the pixel electrodes 35 formed in the predetermined region are simultaneously supplied with the same potential from the corresponding thin film transistors TR. Is entered. Each pixel electrode 35 is connected to the connection electrode 44 through a contact hole H penetrating the third substrate 46. On the other hand, the connection electrode 44 is connected to the drain electrode 41d of the thin film transistor TR having each structure through a contact hole H1 penetrating the first substrate 34 and the gate insulating film 41b. The pixel electrode 35 has a circular shape in plan view and has a diameter of 10 to 20 μm.

[Method of Manufacturing Semiconductor Device]
Hereinafter, a method for manufacturing a semiconductor device will be described for each configuration of the thin film transistor.
First, a method for manufacturing a semiconductor device incorporating a thin film transistor having a bottom gate top contact (BGTC) structure will be described with reference to four examples.

(Method for Manufacturing Semiconductor Device “BGTC (1)” of First Embodiment)
FIG. 6 is a cross-sectional view showing a manufacturing process of a semiconductor device incorporating a thin film transistor having a BGTC structure. FIG. 7 is an explanatory view showing a bonded state of the first substrate and the second substrate.
First, as shown in FIG. 6A, a gate electrode 41e made of Cu having a thickness of 0.5 μm is formed on the surface (one surface) 34a of the first substrate 34 made of polyimide having a thickness of 50 μm. The Cu film was formed by using an electroless plating method, and then patterned by a photoetching method.

Next, as shown in FIG. 6B, a gate insulating film 41b having a thickness of 0.5 μm is formed on the entire surface 34a of the first substrate 34 so as to cover the gate electrode 41e. Here, the gate insulating film 41b is formed by applying an acrylic material to the entire surface 34a using a spin coating method and performing baking. Subsequently, a semiconductor layer 41a made of pentacene and having a thickness of 0.05 μm is formed at a position overlapping the gate electrode 41e on the gate insulating film 41b. Here, the ink jet method is used.
In this way, the first substrate 34 having the gate electrode 41e, the gate insulating film 41b, and the semiconductor layer 41a is prepared.

On the other hand, as shown in FIG. 6C, a source electrode 41c and a drain electrode 41d made of Cu having a thickness of 1 μm are formed on the rear surface (one surface) 39b side of the second substrate 39 made of polyimide having a thickness of 50 μm. Thereafter, a through-hole 13 that penetrates the thickness direction of the second substrate 39 is formed using a laser or photoetching at a position overlapping the drain electrode 41d in plan view, and the pixel electrode material enters the through-hole 13. Thus, a pixel electrode 35 made of Cu having a thickness of 0.3 μm is formed on the surface 34a. Thereby, a contact hole H is formed simultaneously with the pixel electrode 35, and the pixel electrode 35 is connected to the drain electrode 41d on the back surface 34b side through the contact hole H. Here, the Cu film was formed using an electroless plating method, and then patterned by a photoetching method, thereby forming the source electrode 41c, the drain electrode 41d, and the pixel electrode 35. The through hole 13 was also formed by using a photoetching method.
In this way, the second substrate 39 having the source electrode 41c, the drain electrode 41d, and the pixel electrode 35 is prepared.

  Next, as shown in FIG. 6D, the front surface (one surface) 34a side of the first substrate 34 and the back surface (one surface) 39b side of the second substrate 39 face each other, and the first substrate 34 and the second substrate The substrates 39 are bonded together so as to be pressure-bonded. The substrates 34 and 39 were bonded together under reduced pressure. Thereafter, baking was performed at the lowest melting point or lower than the melting point among the materials constituting the thin film transistor TR and the substrates 34 and 39. At this time, the pressure may be applied. For this reason, the diffusion and decomposition of the material at the interface of each layer does not occur, the cleanliness can be easily controlled, and a low interface state number can be realized with good reproducibility.

  When the first substrate 34 and the second substrate 39 are bonded to each other, the alignment marks 112 formed in advance on the bonding surface of the first substrate 34 or the second substrate 39 are used to connect the substrates 34 and 39 to each other. Perform positioning. Here, it is important to read the alignment marks 112 formed on the first substrate 34 and the second substrate 39. When the substrate to be bonded is a transparent substrate, it is possible to read the alignment mark 112 formed on each substrate using a CCD camera or the like, but the substrates 34 and 39 are non-transparent substrates. Therefore, the alignment mark 112 cannot be detected using a normal camera.

  Therefore, as shown in FIG. 7, the alignment mark 112 is formed on the front surface 34a of the first substrate 34 and the back surface 39b of the second substrate 39, respectively, and the reading hole 113 for reading the alignment mark 112 on the other substrate is formed. Form. Then, the alignment mark 112 on the other substrate 39 (34) is read by the CCD camera 93 through the reading hole 113 formed in one substrate 34 (39). The number of CCD cameras 93 is not particularly limited, and the positions, sizes, shapes, and the like of the alignment marks 112 and the reading holes 113 can be set freely.

  In this manner, a thin film transistor TR having a BGTC structure is formed between the substrates 34 and 39.

  In the manufacturing method of this embodiment, the gate electrode 41e, the source electrode 41c, the drain electrode 41d, and the pixel electrode 35 are all formed by a photoetching method. Thereby, pattern formation with high definition is possible. Then, patterning is not performed on the gate insulating film 41b and the semiconductor layer 41a by a photoetching method. For this reason, it is not exposed to chemicals such as an etching solution and a developing solution. Therefore, a thin film transistor with high reliability and excellent carrier mobility and ON / OFF ratio is formed.

  In each manufacturing process described above, as a method of forming the constituent material of each element on the substrate, other plating methods such as electroless plating, ink jet, spin coating, sputtering, or vacuum such as evaporation are used. Film formation or other printing methods may be used. Further, the firing temperature of each film forming material is not limited to the above, and firing is not necessarily performed. Further, the substrates 34 and 39 are not necessarily bonded to each other under reduced pressure, and it is not necessary to apply pressure at the time of bonding. In the present embodiment, the substrates 34 and 39 are bonded together by pressure bonding.

  In other words, since the source electrode 41c and the drain electrode 41d and the semiconductor layer 41a are electrically connected by pressure bonding, when the surface of the semiconductor layer 41a is a material that forms a natural oxide film such as silicon, the conduction should be stable. Is difficult. A material that does not cause a change in contact resistance due to a natural oxide film, such as an organic semiconductor or an oxide semiconductor, is preferable. In particular, since the semiconductor layer 41a formed using an organic semiconductor or an oxide semiconductor can be formed by a coating method, it is suitable for the manufacturing method of this embodiment.

  Thus, in this embodiment, since both the boards 34 and 39 are connected by pressure bonding, it is not necessary to interpose a special material such as an anisotropic conductive film at the bonding interface as in the prior art. As a result, a thin and light semiconductor device can be produced.

  It is also possible to read the alignment mark 112 using infrared light instead of visible light. This can be realized by forming the alignment mark 112 with a material that does not transmit or reflect infrared light on a substrate that is transparent to infrared light. As a material that does not transmit infrared light, Cu, other metals, transparent electrodes, and the like can be used. According to this method, it is not necessary to form the reading hole 113 for reading the alignment mark 112 in each of the substrates 34 and 39.

(Method for Manufacturing Semiconductor Device “BGTC (2)” of Second Embodiment)
FIG. 8 is a cross-sectional view showing a second manufacturing process of a semiconductor device incorporating a thin film transistor having a bottom gate top contact (BGTC) structure. In the following description, description of the same steps as those of the manufacturing method of the first embodiment is omitted.
In the manufacturing method of the first embodiment described above, the semiconductor layer 41a is formed on the first substrate 34 side. However, in the present embodiment, the semiconductor layer 41a is formed on the second substrate 39 side. Is different.

As shown in FIG. 8A, after forming the gate electrode 41e on the surface 34a of the first substrate 34, as shown in FIG. 8B, the gate electrode 41e is covered so as to cover the gate electrode 41e. A gate insulating film 41b is formed on the entire surface 34a.
In this way, the first substrate 34 having the gate electrode 41e and the gate insulating film 41b is prepared.

On the other hand, as shown in FIG. 8C, the source electrode 41c and the drain electrode 41d are formed on the back surface 39b side of the second substrate 39, and the pixel electrode 35 is formed on the front surface 39a side.
Next, as shown in FIG. 8D, the semiconductor layer 41a is formed so as to partially run on the source electrode 41c and the drain electrode 41d formed on the back surface 39b side.
In this way, the second substrate 39 having the source electrode 41c, the drain electrode 41d, the semiconductor layer 41a, and the pixel electrode 35 is prepared.

  Next, as shown in FIG. 8E, the front surface (one surface) 34a side of the first substrate 34 and the back surface (one surface) 39b side of the second substrate 39 face each other, and the first substrate 34 and the second substrate The substrates 39 are bonded together by pressure bonding. At this time, the substrates 34 and 39 are positioned using the alignment mark 112 described above. In this way, a thin film transistor TR having a BGTC structure is formed between the substrates 34 and 39.

In the manufacturing method of the present embodiment, the gate insulating film 41b and the semiconductor layer 41a are formed on the separate substrates 34 and 39. For this reason, it is important how to maintain the cleanliness of both interfaces (bonding interfaces of the substrates 34 and 39).
Therefore, both substrates 34 and 39 before bonding (first substrate 34 with gate electrode 41e and gate insulating film 41b, source electrode 41c, drain electrode 41d, semiconductor layer 41a and second substrate 39 with pixel electrode 35) are attached. Each is stored under reduced pressure, and these are bonded together under reduced pressure without being exposed to the atmosphere.
Thereby, a highly reliable thin film transistor TR (bgtc) is obtained.

(Method for Manufacturing Semiconductor Device “BGTC (3)” of Third Embodiment)
FIG. 9 is a cross-sectional view showing a third manufacturing process of a semiconductor device incorporating a thin film transistor having a bottom gate top contact (BGTC) structure. In the following description, the description of the same steps as those in the manufacturing methods of the previous embodiments will be omitted.
This embodiment is different from the previous embodiment in that only the gate electrode 41e is formed on the first substrate 34 side and other components are formed on the second substrate 39 side.

As shown in FIG. 9A, the gate electrode 41 e is formed on the surface 34 a of the first substrate 34.
On the other hand, as shown in FIG. 9B, the source electrode 41c and the drain electrode 41d are formed on the back surface 39b side of the second substrate 39, and the pixel electrode 35 is formed on the front surface 39a side.
Next, as shown in FIG. 9C, the semiconductor layer 41a is formed so as to partially run on the source electrode 41c and the drain electrode 41d formed on the back surface 39b side. Thereafter, a gate insulating film 41b is formed on the entire back surface 39b so as to cover the source electrode 41c, the drain electrode 41d and the semiconductor layer 41a.

  Then, as shown in FIG. 9 (d), the front surface (one surface) 34a side of the first substrate 34 and the back surface (one surface) 39b side of the second substrate 39 are opposed to each other using the alignment mark 112. 34 and 39 are positioned. Thereafter, the first substrate 34 and the second substrate 39 are bonded together while being bonded to each other, whereby a semiconductor device including a thin film transistor having a BGTC structure is obtained.

  In the manufacturing method of the present embodiment, the cleanliness at the interface between the gate insulating film 41b and the semiconductor layer 41a can be kept good, and the connection between the source electrode 41c and drain electrode 41d and the semiconductor layer 41a is good. Can be formed. Although the gate electrode 41e and the gate insulating film 41b come into contact with each other when the substrates 34 and 39 are bonded together, it is not necessary to pass a current between the gate electrode 41e and the gate insulating film 41b. Can be taken big. However, it is important that the gate electrode 41e and the gate insulating film 41b are bonded together so that no gap is formed (no bubbles are mixed in). If there is a gap (space), the gate voltage will drop at that portion, so bonding is done with care.

(Method for Manufacturing Semiconductor Device “BGTC (4)” of Fourth Embodiment)
FIG. 10 is a cross-sectional view showing a fourth manufacturing process of a semiconductor device incorporating a thin film transistor having a bottom gate top contact (BGTC) structure. In the following description, the description of the same steps as those in the manufacturing methods of the previous embodiments will be omitted.
This embodiment is different from the previous embodiment in that only the pixel electrode 35 is formed on the second substrate 39 side and other components are formed on the first substrate 34 side.

As shown in FIGS. 10A to 10C, a gate electrode 41e, a gate insulating film 41b, a semiconductor layer 41a, a source electrode 41c, and a drain electrode 41d are formed on the surface 34a of the first substrate 34, and the thin film transistor TR A substrate having the above is prepared.
On the other hand, as shown in FIG. 10D, only the pixel electrode 35 is formed on the surface 39 a side of the second substrate 39. The pixel electrode 35 is exposed to the back surface 39 b side through the through hole 13 that penetrates the thickness direction of the second substrate 39.
Then, as shown in FIG. 10E, the pixel electrodes 35 on the second substrate 39 side are connected to each other through the contact holes H formed in the second substrate 39 by bonding the substrates 34 and 39 together by pressure bonding. The thin film transistor TR is formed between the substrates 34 and 39, connected to the drain electrode 41d on the one substrate 34 side.

  In the present embodiment, the source electrode 41c and the drain electrode 41d are formed by directly applying a Cu paste onto the semiconductor layer 41a. According to this method, an overlap region between the gate electrode 41e, the source electrode 41c, and the drain electrode 41d can be directly formed. The parasitic capacitance (Cgs) of the thin film transistor TR is proportional to the area of the overlap region. The alignment position variation dimension at the time of bonding is a variation in the area of the overlap region. Therefore, a thin film transistor having a small variation in parasitic capacitance can be produced by the above method.

  Next, a method for manufacturing a semiconductor device incorporating a thin film transistor having a top gate bottom contact (TGBC) structure will be described with reference to two examples.

(Method for Manufacturing Semiconductor Device “TGBC (1)” of First Embodiment)
FIG. 11 is a cross-sectional view showing a manufacturing process of a semiconductor device incorporating a thin film transistor having a TGBC structure.
First, the source electrode 41c and the drain electrode 41d are formed on the surface 34a of the first substrate 34 (FIG. 11A), and the semiconductor layer 41a is formed so as to partially run over the source electrode 41c and the drain electrode 41d. . Thereafter, a gate insulating film 41b having a through hole 41B that covers the source electrode 41c, the drain electrode 41d, and the semiconductor layer 41a and exposes part of the drain electrode 41d is formed on the surface 34a of the first substrate 34 (see FIG. FIG. 11B).

On the other hand, a through-hole 13 is formed at a predetermined position of the second substrate 39, and a metal film made of Cu is formed on each of the front and back surfaces so as to grow inside the through-hole 13.
Next, both metal films provided on the front and back surfaces are appropriately patterned to form the pixel electrode 35 on the front surface 39a and the gate electrode 41e on the back surface 39b side (FIG. 11C). When forming the gate electrode 41e, by performing patterning so as to leave the metal film on the through-hole 13, a part of the pixel electrode 35 provided on the front surface 39a side protrudes to the back surface 39b side, and a protruding portion 35A is formed. It is formed. The protruding portion 35A has a shape corresponding to the through hole 41B of the gate insulating film 41b provided on the first substrate 34.

  Then, by bonding the substrates 34 and 39 together, a thin film transistor TR having a TGBC structure is formed between them. At this time, the projection 35A of the pixel electrode 35 on the second substrate 39 side is inserted into the through hole 41B of the gate insulating film 41b on the first substrate 34 side, whereby the pixel electrode 35 is connected to the drain electrode 41d. The

  According to the manufacturing method of this embodiment, since the semiconductor layer 41a and the gate insulating film 41b are formed continuously, these interfaces can be protected and the cleanliness can be maintained. In addition, since the semiconductor layer 41a and the gate insulating film 41b are not exposed to a chemical solution such as an etching solution, good TFT characteristics can be obtained. In addition, a fine pattern can be obtained by forming each electrode using a photoetching method. In the present embodiment, since the source electrode 41c and the drain electrode 41d and the semiconductor layer 41a are continuously formed, other semiconductor materials other than the organic TFT (materials for forming a natural oxide film such as silicon) ), It is possible to obtain good contact characteristics with the electrodes 41d and 41c.

(Method for Manufacturing Semiconductor Device “TGBC (2)” of Second Embodiment)
FIG. 12 is a cross-sectional view showing a second manufacturing process of a semiconductor device incorporating a thin film transistor having a top gate bottom contact (TGBC) structure. In the following description, the description of the same steps as those in the manufacturing methods of the previous embodiments will be omitted.
This embodiment is different from the previous embodiment in that only the pixel electrode 35 is formed on the second substrate 39 side and other components are formed on the first substrate 34 side.

As shown in FIGS. 12A to 12C, a gate electrode 41e, a gate insulating film 41b, a semiconductor layer 41a, a source electrode 41c, and a drain electrode 41d are formed on the surface 34a of the first substrate 34, and the thin film transistor TR A substrate having the above is prepared.
On the other hand, as shown in FIG. 12D, only the pixel electrode 35 is formed on the surface 39 a side of the second substrate 39.
Then, by bonding the two substrates 34 and 39, the drain electrode 41d of the thin film transistor TR (TGBC) and the pixel electrode 35 are connected.

Next, a method for manufacturing a semiconductor device incorporating a thin film transistor having a bottom gate bottom contact (BGBC) structure will be described.
FIG. 13 is a cross-sectional view showing a manufacturing process of a semiconductor device incorporating a thin film transistor having a BGBC structure.
First, the gate electrode 41e, the gate insulating film 41b, the source electrode 41c, and the drain electrode 41d are formed on the surface 34a of the first substrate 34 (FIGS. 13A and 13B).
On the other hand, the through hole 13 is formed at a predetermined position of the second substrate 39, and the pixel electrode 35 is formed on the surface 39a (FIG. 13C). At this time, a part of the pixel electrode 35 is formed so as to protrude toward the back surface 39b. Further, the semiconductor layer 41a is formed on the back surface 39b.

  Then, by bonding the substrates 34 and 39 together, a thin film transistor TR having a BGBC structure is formed between them. At this time, the substrates 34 and 39 are pressed from the outside so as to be bonded, so that the semiconductor layer 41a is joined so as to enter the gap between the source electrode 41c and the drain electrode 41d, and the pixel electrode 35 The protruding portion 35A is pressed (pressed) onto the drain electrode 41d. Since the protruding portion 35A of the pixel electrode 35 protrudes from the back surface 39b of the second substrate 39, the protruding portion 35A of the pixel electrode 35 is pressure-bonded (pressed) onto the drain electrode 41d by pressurization when the substrates are bonded together. Become. As a result, connection failure of both is prevented, and conduction can be ensured.

  In the present embodiment, the source electrode 41c and the drain electrode 41d are formed by using an inkjet printing method. The printing method has a lower patterning accuracy than the photoetching method. For this reason, the source electrode 41c and the drain electrode 41d may be formed by a photoetching method. However, since the gate insulating film 41b is exposed to an etching solution, a material having chemical resistance is preferable. The printing method is not limited to the inkjet method, and other printing methods may be used.

As another method for manufacturing a transistor having a BGBC structure, for example, a first substrate 34 in which a gate electrode 41e and a gate insulating film 41b are formed on the surface 34a side, and a pixel electrode 35 on the surface 39a side are provided. A thin film transistor having a BTBG structure is formed between the source electrode 41c and the drain electrode 41d formed on the back surface 39b side and the second substrate 39 on which the semiconductor layer 41a is formed by bonding them together. May be.
Further, a first substrate 34 having a gate electrode 41e formed on the front surface 34a, and a second substrate 39 having a semiconductor layer 41a, a source electrode 41c, a drain electrode 41d, and a gate insulating film 41b formed on the back surface 39b. A thin film transistor TR having a BGBC structure may be formed by bonding.

  As described above, also in each manufacturing method, the gate electrode 41e is formed on the first substrate 34, the pixel electrode 35 is formed on the second substrate 39 side, and the source is supplied to either the first substrate 34 or the second substrate 39. An electrode 41c and a drain electrode 41d are formed.

  Next, a method for manufacturing a semiconductor device incorporating a thin film transistor having a top gate top contact (TGTC) structure will be described.

FIG. 14 is a cross-sectional view showing a manufacturing process of a semiconductor device incorporating a thin film transistor having a TGTC structure.
A source electrode 41c and a drain electrode 41d are formed in this order on the surface 34a of the first substrate 34 so as to partially run over the semiconductor layer 41a and its peripheral edge (FIGS. 14A and 14B).
After the pixel electrode 35 is formed on the front surface 39a of the second substrate 39, a gate electrode 41e is formed on the back surface 39b side (FIG. 14C), and a gate insulating film is formed on the entire back surface 39b so as to cover it. 41b is formed (FIG. 14D).
Then, the first substrate 34 and the second substrate 39 are bonded together to form a thin film transistor TR having a TGTC structure between the substrates 34 and 39 (FIG. 14E).

  As another method for manufacturing a transistor having a TGTC structure, for example, a semiconductor layer 41a, a source electrode 41c, a drain electrode 41d, and a gate insulating film 41b are formed in this order on a first substrate 34, and a second substrate 39 is formed. The pixel electrode 35 may be formed on the front surface 39a, and the gate electrode 41e may be formed on the back surface 39b in this order, and the substrates 34 and 39 may be bonded together.

  Further, the semiconductor layer 41a, the source electrode 41c and the drain electrode 41d, the gate insulating film 41b and the gate electrode 41e are formed in this order on the first substrate 34, and the pixel electrode is formed on the surface 39a of the second substrate 39. 35 may be formed, and the two substrates 34 and 39 may be bonded together.

Next, a method for protecting the semiconductor layer will be described.
The semiconductor layer 41a is a region where current actually flows, and it is generally known that the electrical characteristics greatly change when impurities are mixed. Therefore, it is important to provide protective layers for preventing impurities from entering above and below the semiconductor layer 41a. In particular, it is known that a flexible substrate such as polyimide is generally an organic material, has many impurities, and allows water and oxygen to permeate well.

The structure of a thin film transistor provided with a protective layer is described below.
FIG. 15 is a cross-sectional view showing a manufacturing process of a semiconductor device incorporating a thin film transistor having a protective layer. Here, a structure of a thin film transistor having a BGTC structure is described, but the present invention can be applied to a thin film transistor having a structure other than this.
As shown in FIG. 15A, a gate electrode 41e is formed on the surface 34a of the first substrate 34, and as shown in FIG. 15B, a gate insulating film 41b is formed so as to cover the gate electrode 41e. At the same time, a semiconductor layer 41a is formed thereon.

On the other hand, as shown in FIG. 15C, the pixel electrode 35 is formed on the front surface 39a of the second substrate 39, and the source electrode 41c and the drain electrode 41d are formed on the back surface 39b side. Thereafter, the protective layer 38 is formed between the source electrode 41c and the drain electrode 41d so as to be thinner than the source electrode 41c and the drain electrode 41d. The protective layer 38 is formed using the same material as the gate insulating film 41b. In this case, an acrylic material is used. By forming the protective layer 38 using the same material as that for forming the gate insulating film 41b, the material cost can be reduced.
Then, as shown in FIG. 15E, the substrates 34 and 39 are bonded together to form a BGTC thin film transistor TR therebetween.

  Thus, the upper and lower sides of the semiconductor layer 41a are sandwiched between the gate insulating materials (the gate insulating film 41b and the protective layer 38), and the semiconductor layer 41a can be protected. Thereby, impurities can be prevented from entering the semiconductor layer 41a.

  Here, the protective layer 38 is provided at the boundary portion between the semiconductor layer 41a and the second substrate 39. However, when the semiconductor layer 41a and the first substrate 34 are in contact with each other, the boundary portion is protected. The layer 38 is provided to prevent impurities from entering the semiconductor layer 41a.

  As another configuration, in the case of the thin film transistor having the TGBC structure (FIG. 1B) and the TGTC structure (FIG. 1D) (FIG. 1B), the first substrate 34 and the semiconductor layer 41a are interposed between each other. In the case of a thin film transistor having a BGBC structure (FIG. 1C) provided with the protective layer 38, the semiconductor layer 41a can be protected by providing the protective layer 38 between the second substrate 39 and the semiconductor layer 41a. .

Next, a method for manufacturing a semiconductor device including a reflective electrode and a thin film transistor will be described.
FIG. 16 is a cross-sectional view showing a manufacturing process of a semiconductor device including a reflective electrode and a thin film transistor having a BTBC structure.
As shown in FIGS. 16A and 16B, a gate electrode 41e, a gate insulating film 41b, and a semiconductor layer 41a are formed in this order on the first substrate.
On the other hand, as shown in FIG. 16C, the second substrate 39 and the third substrate 46 are bonded together through the reflective electrode 45, and the source electrode 41c and the drain electrode 41d are formed on the back surface 39b of the second substrate 39. Then, the pixel electrode 35 is formed on the surface 46 a of the third substrate 46. Here, the pixel electrode 35 is connected to the drain electrode 41 d through a contact hole H penetrating the second substrate 39 and the third substrate 46.
Then, by bonding the front surface 34a side of the first substrate 34 and the back surface 39b side of the second substrate 39 to which the third substrate 46 is bonded, the BGTC whose upper part is covered with the reflective electrode 45 between them. A thin film transistor TR having a structure is formed.

  Note that although a thin film transistor having a BGTC structure is described here as an example, thin film transistors having other structures can be formed using the above-described manufacturing method.

(Active matrix substrate)
FIGS. 17A to 17E are plan views showing a schematic configuration of an active matrix substrate formed using a semiconductor device incorporating the above-described thin film transistors, and FIG. 18 is an equivalent circuit diagram of one pixel. It is.
An active matrix substrate (element substrate 300) shown in FIG. 17A is provided with a display section (display area) 5 in which a plurality of pixels 40 are arranged in a matrix. Each pixel 40 has a control transistor TRc (FIG. 18) having any one of the above-described structures, and is embedded in the first substrate 30 constituting the element substrate 300. The control transistor TRc is created using each of the manufacturing methods described above.

  On the element substrate (semiconductor device) 300, three scanning line driving circuits 61, two data line driving circuits 62, and three common power supply circuits 64 are mounted on the flexible substrates 201A to 201C, respectively, by COF (Chip On Film). (Or TAB (Tape Automated Bonding) implementation). External circuit boards 202A to 202C are connected to the flexible boards 201A to 201C, respectively. On the external circuit boards 202A to 202C, circuits such as a driver IC, a battery, and a memory for driving the scanning line driving circuit 61, the data line driving circuit 62, and the common power supply circuit 64 are mounted.

  In addition, a plurality of wirings (scanning lines 66 and data lines 68) drawn from the display unit 5 are extended to a region where the scanning line driving circuit 61, the data line driving circuit 62, and the common power supply circuit 64 are mounted. These are connected to connection terminals formed in each mounting area. And flexible board | substrate 201A-201C is mounted with respect to this connection terminal via ACP or ACF.

  An element substrate (semiconductor device) 301 shown in FIG. 17B includes a built-in driver (scanning line driving circuit 61, data line driving) configured to include a driving transistor TRs (FIG. 19) having any one of the structures described above. Circuit 62 and common power supply circuit 64), which are embedded in the first substrate 30 around the display unit 5. Connected to one side of the element substrate 301 via the flexible substrate 204 is a controller IC for driving the built-in driver, an external circuit substrate 205 on which circuits such as a battery and a memory are mounted.

  An element substrate (semiconductor device) 302 shown in FIG. 17C is a circuit such as a controller IC, battery, or memory for driving a built-in driver (scanning line driving circuit 61, data line driving circuit 62, common power supply circuit 64). Are embedded in the first substrate 30 as the electronic component 10.

  In an element substrate (semiconductor device) 303 shown in FIG. 17D, the built-in driver (the scanning line driving circuit 61, the data line driving circuit 62, and the common power supply circuit 64) does not include the thin film transistors having the structures described above. The driver ICs 51, 52, and 54, which are parts, are provided. The scanning line driving circuit 61 includes a plurality of driver ICs 51, the data line driving circuit 62 includes a plurality of driver ICs 52, and the common power supply circuit 64 includes a plurality of driver ICs 54. In FIG. 17D, the external circuit board 205 is connected to one side of the element board 303 via the flexible board 204. Instead, as shown in FIG. An element substrate (semiconductor device) 304 incorporated in one substrate 30 may be used.

  As shown in FIG. 18, the display unit 5 of each of the element substrates 300 to 304 includes a plurality of pixels 40 corresponding to the intersection positions of the plurality of scanning lines 66 and the plurality of data lines 68. . The pixel circuit in one pixel (pixel 40) includes an electro-optical element (functional element) 32 as a display element, and a control transistor TRc for performing a switching operation to apply a voltage to the electro-optical element 32. It is configured.

  The control transistor TRc in each pixel 40 has a gate connected to the scanning line 66, a source connected to the data line 68, and a drain connected to one electrode of the storage capacitor Cs and the pixel electrode 35 (electro-optical element 32). ing. The other electrode of the storage capacitor Cs is connected to a capacitor line (not shown).

  Although FIG. 18 shows a storage capacitor, an equivalent circuit without a storage capacitor may be used.

FIG. 19 is a cross-sectional view taken along the line AA in FIG.
The element substrate 302 is formed by bonding a plurality of base materials, and here, the three base materials 30A, 30B, and 30F are bonded. The driving transistor TRs of the scanning line driving circuit 61 (built-in driver) is connected to the output side of the electronic component 10 embedded in the base material 30A via the connection line 23 (contact hole H) made of Cu formed on the base material 30B. The gate electrode 41e is connected. The connection wiring 22 is used for connection between the electronic components 10. Between the base material 30B and the base material 30F, a control transistor TRc (only the scanning line driving circuit 61 is shown in FIG. 19) and a driving transistor TRs that form a pixel circuit, which are created by the above-described method, are included. Has been placed. Here, the base material 30A, the base material 30B, and the base material F are all made of non-transparent polyimide. Further, the base materials 30A, 30B, 30F have a thickness of 50 μm and have the same thickness.

  Note that the thin film transistor having the reflective electrode 45 above as shown in FIG. 2 can be used in place of the pixel TFT. The reflective electrodes 45 provided in each pixel are connected to each other by a connection wiring (not shown) and are connected to a power source outside the display area. Thereby, the same voltage can be simultaneously applied to the plurality of reflective electrodes 45.

  Here, the transistors TRc and TRs are preferably formed by repeating the coating method and baking. In general, plasma CVD or sputtering is used for production of silicon-based and oxide TFTs. In this method, plasma is generated and the substrate is strongly charged. In this embodiment, the drive circuit layer 24 including the control transistor TRc and the drive transistor TRs is formed after the electronic component 10 is embedded in the first substrate 30 formed by bonding the base material 30A and the base material 30B. .

  For this reason, the first substrate 30 in which the electronic component 10 has already been embedded is exposed to plasma when the TFT is formed. When the first substrate 30 is exposed to plasma, the electronic component 10 is electrostatically broken. In particular, since the connection line 23 connected to the external connection terminal 10a of the electronic component 10 is exposed on the surface 30a, static electricity enters the electronic component 10 from there and causes electrostatic breakdown. For this reason, it is preferable to form a thin film transistor by a process that does not use plasma.

  As one of the methods, there is a combination of printing and inkjet coating methods and baking, vapor deposition, sol-gel method, or the like. Organic TFTs and oxide TFTs that can be produced using such a method are suitable.

FIG. 20 is a cross-sectional view taken along the line BB in FIG.
The element substrate 304 is formed by bonding a plurality of base materials, and here, the six base materials 30A to 30F are bonded.
An element substrate 304 shown in FIG. 20 is configured around a first substrate 30 in which a plurality of base materials 30A to 30E made of non-transparent polyimide are laminated, and a drive circuit layer 24 formed on the surface 30a. ing.

  In the first substrate 30, driver ICs 51, 52 (FIG. 17 (e)), 54 (FIG. 17 (e)) for driving the drive circuit layer 24 constituted by the pixel circuit including the control transistor TRc, A plurality of electronic components 10 (controller 63) for controlling the driver ICs 51, 52, and 54 are held.

  Specifically, an electronic component (controller) 10 and a driver IC 51 are disposed between the base material 30A and the base material 30B, and these (external connection terminals 10a and 51a) are provided on the base material 30B. The connection wiring 22 is connected. The driver IC 51 is connected to the scanning line 66 on the surface 30a of the first substrate 30 (the surface 30a of the base material 30E) via the gate connection line 66A formed on the base material 30B. Here, the storage capacitor connection line 69A formed on the substrate 30C is connected to the storage capacitor line 69 on the surface 30a through a contact hole, a connection line, and the like (not shown).

The control transistor TRc is gate-insulated on the first substrate 30 in which an electronic component (controller) 10, a driver IC 51, etc. are embedded, and a scanning line 66, a gate electrode 41e, a storage capacitor line 69, etc. are provided on the surface 30a. By bonding the base material 30F provided with other components of the control transistor TRc through the film 41b, the first substrate 30 (base material 30E) and the base material 30F are formed. . The pixel electrode 35 provided on the base material 30F is connected to the drain electrode 41d of the control transistor TRc through the contact hole H.
The base material 30F is also made of non-transparent polyimide and functions as a protective layer for the control transistor TRc.

  The pixel circuit in the present embodiment is provided with a storage capacitor Cs having a pair of storage capacitor electrodes 1a and 1b arranged to face each other with a gate insulating film 41b interposed therebetween. One storage capacitor electrode 1 a constituting the storage capacitor Cs is connected to the drain electrode 41 d of the control transistor TRc, and the other storage capacitor electrode 1 b is connected to the storage capacitor line 69. The storage capacitor Cs is in the same layer as the control transistor TRc, and uses the gate insulating film 41b as a storage capacitor.

  Also in this embodiment, in order to prevent electrostatic breakdown of the electronic component 10 held in the first substrate 30, it is preferable to form a thin film transistor by a process that does not use plasma. Examples of the method include a combination of the above-described printing and ink jet coating methods and baking, vapor deposition, sol-gel method, and the like, and organic TFTs and oxide TFTs that can be created using such methods are suitable as before. is there.

19 and 20, the electronic component 10 is held between the base material 30 </ b> A and the base material 30 </ b> B, but may be configured between other base materials or in the base material. good. When the electronic component 10 is thicker than the thickness of each base material, the electronic component 10 is held over a plurality of base materials. Moreover, you may arrange | position so that several electronic components may overlap on both sides of a base material in a film thickness direction.
In FIG. 19 and FIG. 20, the electronic components are arranged around the display unit 5, but may be arranged in the display unit 5. Moreover, you may make it arrange | position to both the display part 5 and the circumference | surroundings (non-display area) of the display part 5. FIG. Accordingly, the frame of the electro-optical device configured using these element substrates 302 and 304 can be reduced.
Further, a connection terminal (not shown) to the outside of the electronic component 10 may be provided on the back surface of the drive circuit layer 24 of the first substrate. In this case, external connection electrodes are provided on the back surface of the first substrate 30 to perform input / output of signals between the electro-optical device and the outside, power supply, and the like. The electronic component 10 is not limited to the above, and components such as a battery, a memory, a communication function, a resistor, and a capacitor may be used.

Next, an electro-optical device configured using the element substrate having each configuration described above will be described.
FIG. 21 is a cross-sectional view illustrating a schematic configuration of the electrophoretic display device.
An element substrate 302 shown in FIG. 21 is the same as the element substrate shown in FIG.
In the electrophoretic display device (electric device) 120, an electrophoretic layer as the electro-optical element 32 is sandwiched between the element substrate 302 and the counter substrate 310 described above. The counter substrate 310 includes a substrate 31 and a counter electrode 37 formed on the entire surface of the substrate 31 (surface on the electro-optical element 32 side). The electrophoretic layer (electro-optical element 32) is formed by arranging a plurality of microcapsules 20. Then, white particles and black particles held in the microcapsule 20 and charged with different polarities move based on a voltage applied between the pixel electrode 35 and the counter electrode 37 to perform display. .
The configuration of the electrophoretic layer (electro-optical element 32) is not limited to using the microcapsule 20, but may be a method using other partitions such as a partition or a configuration without partitions.

  Moreover, it is possible to use an electrophoretic material using only black particles without using white particles. In this case, the reflective electrode 45 shown in FIG. 2 is used to realize white display. White light is displayed by reflecting external light by the reflective electrode 45.

FIG. 22 is a cross-sectional view illustrating a schematic configuration of the liquid crystal device.
An element substrate 302 shown in FIG. 22 is the same as the element substrate shown in FIG.
The liquid crystal device (electric device) 121 is obtained by sandwiching a liquid crystal layer as the electro-optical element 32 between the element substrate 302 described above and the counter substrate 310 having the counter electrode 37.
As the liquid crystal material, a material having less influence of the cell gap d such as guest-host liquid crystal, PDLC (polymer dispersed liquid crystal), and PNLC (polymer network type liquid crystal) was applied. In general, the liquid crystal is optically designed by the product Δn · d of the cell gap d and the refractive index anisotropy Δn. When a flexible substrate is employed, the cell gap changes when the liquid crystal display device is bent. Therefore, when the liquid crystal display device is rolled up into a cylindrical shape, the display color and contrast may shift. For this reason, it is desirable to use the liquid crystal material described above, but other liquid crystal materials may be used.

Here, when a liquid crystal material is used, it does not have a memory property itself, and thus it is desirable to provide a volatile memory such as an SRAM in each pixel.
In the case of a liquid crystal device, a polarizing plate is required. On the other hand, in the case of the above-described electrophoretic display device, since a polarizing plate is unnecessary, bright display is possible.

  Note that electroluminescence, electrochromic, electrowetting, or the like may be used instead of the liquid crystal material.

  As described above, in an electro-optical device including a liquid crystal device and an electrophoretic display device, a flexible polyimide material is used as a material of the element substrate 300. A material having flexibility is generally an organic material, and has a thermal expansion coefficient that is about one order of magnitude larger than a rigid inorganic material, and a thermal conductivity coefficient that is one order of magnitude smaller. For this reason, when the element substrate 300 generates heat, heat tends to accumulate, and the substrate extends. For this reason, warpage occurs in the electro-optical device. Further, when the electro-optical device is used in a curved state in this state, there is a possibility that a connection failure between the electronic component 10 and the connection wiring 22 or a disconnection of the wiring may occur. Conventionally, there has been an electro-optical device using electroluminescence that uses an inorganic substrate provided with a heat diffuser to prevent heat from being accumulated on the element substrate, but the structure is complicated.

  As described above, when the electro-optical device including the element substrate 300 (first substrate 30) made of a material mainly composed of flexibility or an organic material is used in a curved state, an electro-optical material (electro-optical element) is used. It is desirable to use a material that generates less heat. The material that generates less heat is a material that does not allow current or voltage to flow as much as possible during display. Most preferred is an electro-optic material having a memory property, which can hold a display even when no voltage is applied after a voltage is applied once. Specifically, it is an electrophoretic material or an electrochromic material. The next most suitable is a material that is driven by a voltage rather than a current, such as liquid crystal or electrowetting. The least preferred is electroluminescence driven by current.

  Note that examples of the material used for the first substrate 30, the second substrate 31, the first substrate 34, and the second substrate 39 of the element substrate 302 include flexible polyester, PET, other organic materials, and inorganic materials. Moreover, as long as it does not have flexibility, BT resin, allylated phenylene resin, liquid crystal polymer, PEEK, epoxy resin, paper phenol, paper epoxy, glass composite, glass epoxy, thin glass, Teflon (registered trademark), ceramics These composite materials and other organic and inorganic materials may be used. A substrate having elasticity such as rubber may be used.

  In addition, the pixel electrode 35, the counter electrode 37, the source electrode 41c, the drain electrode 41d, the gate electrode 41e, the storage capacitor electrodes 1a and 1b of the storage capacitor Cs, various wirings (scanning line 66, data line 68, storage capacitor line 69, etc.) As a material used for this, a metal paste other than Cu or Au, a metal, an organic conductive material, an inorganic conductive material, a conductive material such as a transparent electrode (ITO), a carbon nanotube, or the like may be used.

Further, the number and thickness of the base materials constituting the first substrate 30, the second substrate 31, the first substrate 34, and the second substrate 39 are not limited to the above. In addition, the first substrate 30 may be formed of a single layer substrate instead of the multilayer substrate, and the first substrate 30 is not limited to the multilayer substrate as long as the electronic components and the wiring and electrodes of the TFT can be embedded in the first substrate 30.
Further, the configuration of the pixel circuit may be a pre-stage gate capacitance system in which the capacitance is held in the holding capacitance Cs by the pre-stage scanning line 66.

Here, it is known that the characteristics of liquid crystal materials, electrophoretic materials, electroluminescent materials, electrochromic materials, and the like change depending on humidity. For example, if a material contains a lot of humidity, the leakage current increases and the power consumption increases. In order to prevent this, it is important to have a moisture resistant structure.
The structure of the element substrate having a moisture resistant structure will be described below.

23A and 23B show a schematic configuration of an element substrate provided with moisture resistance for the control transistor.
As shown in FIG. 23A, at least one of a plurality of base materials constituting the first substrate 30 may be replaced with a moisture resistant substrate 78. An example of the moisture resistant substrate 78 is a glass substrate. Here, a glass substrate thinned to a thickness of 20 μm is used. The base material 30 </ b> A provided in the lowermost layer of the first substrate 30 may be the moisture resistant substrate 78, and other base materials may be replaced with the moisture resistant substrate 78. Moreover, you may interpose between any base materials. In addition, a moisture-resistant substrate 78 may be separately provided on the back surface 30b side of the first substrate 30.

In FIG. 23B, a moisture resistant layer 79 is provided so as to cover the entire surface 30e of the substrate 30F. A pixel electrode 35 is formed on the surface of the moisture resistant layer 79. The moisture resistant layer 79 is made of silicon nitride and formed by applying and baking an organic material containing silicon. The moisture resistant layer 79 may be provided on either the front surface 30 a (FIG. 23C) or the back surface 30 b of the first substrate 30, and is disposed between a plurality of base materials constituting the first substrate 30. May be. The arrangement position of the moisture-resistant layer 79 is not particularly limited, and the moisture-resistant layer 79 is not limited to one layer and may be provided in plural.
Further, moisture resistance may be imparted to the material of the base material 30F that also functions as a protective layer of the control transistor TRc, or moisture resistance may be imparted to the material of the base material constituting the first substrate 30 itself. . Here, the material of the moisture resistant layer is not limited to silicon nitride.

  By the way, in each embodiment mentioned above, the component of TFT was divided and formed on a different base material, and TFT was created between the board | substrates bonded together by bonding these base materials. Here, there are several factors that reduce the manufacturing yield. First, when the substrates are bonded together, a short circuit occurs between the gate electrode 41e, the source electrode 41c and the drain electrode 41d, or between the pair of storage capacitor electrodes 1a and 1b in the storage capacitor. (FIGS. 28A and 28B). Since each electrode is made of a metal such as Cu and has rigidity and overlaps each other in the same area, when the substrates are bonded together, the gap between the gate electrode 41e, the source electrode 41c, and the drain electrode 41d To short.

  Secondly, since the bonding surfaces of the substrates are uneven, bubbles are mixed into the bonding interface after bonding (FIG. 28 (a), (B)). That is, since the conduction between the electrodes is achieved by pressing the substrates together, contact failure is likely to occur.

A countermeasure method for preventing manufacturing defects will be described below.
(Short defect countermeasures)
FIG. 24A is a sectional view showing a TFT having an offset structure, and FIG. 24B is a sectional view showing a storage capacitor having an offset structure.
In the TFT configuration described above, the source electrode 41c and the drain electrode 41d are arranged so as to partially overlap the peripheral edge of the gate electrode 41e in plan view.

In the thin film transistor TR shown in FIG. 24A, neither the source electrode 41c nor the drain electrode 41d overlaps the gate electrode 41e in plan view, and overlaps between the source electrode 41c, the drain electrode 41d, and the gate electrode 41e. The offset structure has no part (overlapping part in plan view).
The source electrode 41c and the drain electrode 41d are disposed at a position (offset position) separated from the gate electrode 41e by a predetermined distance in plan view. Conductive portions 114 and 115 are arranged in an offset portion between the gate electrode 41e and the source electrode 41c and the drain electrode 41d in the plane direction. The conductive portion (first conductive portion) 114 is formed such that one end side is connected to the source electrode 41c and the other end side overlaps with the gate electrode 41e in plan view. The conductive portion (second conductive portion) 115 is formed so that one end side is connected to the drain electrode 41d and the other end side overlaps with the gate electrode 41e in plan view. The semiconductor layer 41a is formed so as to partially run on the opposing ends of the conductive portions 114 and 115.

Further, in the configuration of the storage capacitor described above, the pair of storage capacitor electrodes 1a and 1b are disposed to face each other in plan view.
The storage capacitor Cs shown in FIG. 24B has a configuration in which the storage capacitor electrodes 1a and 1b do not overlap with each other in a plan view and there is no overlap portion between the storage capacitor electrodes 1a and 1b. A conductive portion 116 is disposed at an offset portion in the plane direction between the storage capacitor electrodes 1a and 1b. The conductive portion 116 is formed on the gate insulating film 41b so as to cover the storage capacitor electrode 1b, and one end thereof is connected to the storage capacitor electrode 1a (drain electrode 41d) arranged in an offset manner.

Here, since the gate electrode 41e, the drain electrode 41d, and the source electrode 41c are formed of a hard metal material such as Cu, an overlap region between the gate electrode 41e, the drain electrode 41d, and the source electrode 41c is formed between the substrates. In the case of forming and using by bonding, a short circuit may occur between these hard electrodes due to the pressure bonding between the substrates.
The conductive portions 114 to 116 used in the present embodiment are made of a soft material such as an organic material. For this reason, it becomes possible to contact each above-mentioned electrode favorably by the crimping | compression-bonding at the time of bonding of a board | substrate, and generation | occurrence | production of the short circuit between electrodes can be prevented. As the material of the conductive portions 114 to 116, a non-metallic material such as an organic conductive polymer, a carbon nanotube, other organic materials, or a mixed material of organic and inorganic materials can be used.

  The present invention can also be applied to a structure of a thin film transistor other than the structure shown in FIG. Further, the positions where the conductive portions 114 to 116 are disposed are not limited to the positions described above. Any position is acceptable as long as the semiconductor layer 41a can be connected to the source electrode 41c and the drain electrode 41d and can be connected to one storage capacitor electrode 1a constituting the storage capacitor Cs.

(Measures against poor contact)
The contact failure between the electrodes is that the electrodes (wirings) formed separately on each substrate cannot be sufficiently brought into contact with each other because the bonding surfaces of the substrates to be bonded are uneven. Responsible. In particular, each of the electrodes 41c, 41d, and 41e constituting the thin film transistor is formed in a specific area and has a large film thickness, so that contact failure is likely to occur.

FIG. 25A is a diagram showing a configuration before countermeasures, and FIG. 25B is a diagram showing a configuration after countermeasures.
Therefore, as shown in FIG. 25 (a), each electrode 41c, 41d, 41e and members such as wiring connected thereto are embedded in each of the base materials 30A to 30E. At this time, the surface of each electrode 41c, 41d, 41e and each wiring is exposed, and it is made to be on the same plane as the surface of the substrate or slightly protruded. Thereby, when a base material is bonded together, the contact failure of electrodes can be reduced.
The embedding of the metal film can also be applied to the pixel electrode 35, the reflective electrode 45, and the like.

Next, an example in which the electric device including the element substrate of each of the above embodiments is applied to another device will be described.
26 and 27 are examples in which a pressure sensor is used as the artificial skin of the robot, FIG. 26 is a diagram showing an example in which a pressure sensor is provided on the fingertip of the robot, and FIG. 27 is a configuration of the pressure sensor. FIG.
As shown in FIGS. 26 and 27, the pressure-sensitive sensor 70 (electric device) provided on the fingertip 74 of the robot includes a plurality of detection elements 71 (corresponding to pixels of the electro-optical device) 71. The detection element 71 can be configured using the element substrate of any of the above embodiments.
The detection element 71 includes an element substrate (semiconductor device) 92 having a first substrate 30 and a drive circuit layer 24 provided on the first substrate 30, and an opposing electrode having a counter electrode 37 on the second substrate 31. A substrate 310 and a piezoelectric element 77 disposed between the element substrate 92 and the counter substrate 310 are provided.

On the first substrate 30 in the detection area 96, a detection circuit 98 including a detection electrode 97 and a control transistor TRc and a drive circuit 99 connected to the detection circuit 98 are arranged. In addition, wiring for configuring the detection circuit 98 and the drive circuit 99 is embedded in the first substrate 30 in the detection area 96. In addition, a drive IC 76 connected to the detection circuit 98 and the drive circuit 99 via the wirings or the like is embedded in the first substrate 30 at the boundary between the detection area 96 and the non-detection area 95.
On the other hand, the counter substrate 310 includes a second substrate 31 and a counter electrode 37 made of carbon nanotubes provided on the inner surface (the surface facing the piezoelectric element 77) of the second substrate 31. Here, the second substrate 31 is made of PET having a thickness of 0.2 mm.

  A piezoelectric element 77 made of a copolymer of trifluoroethylene and vinylidene fluoride having a thickness of 1 μm is sandwiched between the element substrate 92 and the counter substrate 310. A copolymer of trifluoroethylene and vinylidene fluoride is an organic material and can be bent in the same manner as the element substrate 92. Further, between the peripheral portions of the element substrate 92 and the counter substrate 310, a sealing material 65 that is partitioned so as to surround the piezoelectric element 77 is disposed.

  In the pressure-sensitive sensor 70 having a large number of such detection elements 71, when a pressure is applied to each detection element 71, a voltage is induced between the counter electrode 37 and the pixel electrode 35, and this voltage change is detected. By detecting, it is determined whether or not the fingertip 74 of the robot has touched the object.

Here, any one of the above-described embodiments can be used as the element substrate 92.
As the piezoelectric material, other organic materials and inorganic materials that are not limited to the above can be used. If a pyroelectric material is used instead of the piezoelectric material, a two-dimensional temperature sensor can be configured, and if a photoelectric conversion material is used, a two-dimensional optical sensor, a terahertz wave sensor, or an X-ray sensor can be configured. Moreover, it is good also as a structure which detects the change of an electric current value. In addition, application to other electrical devices is possible.
When a material having elasticity such as rubber is used for the first substrate 30 and the second substrate 31, the electric device can have elasticity. This allows the electrical device to be placed on a complex surface such as a palm without any gaps.

  As described above, the preferred embodiments according to the present invention have been described with reference to the accompanying drawings, but the present invention is not limited to the examples. It is obvious for those skilled in the art that various changes or modifications can be conceived within the scope of the technical idea described in the claims. It is understood that it belongs to.

  In each of the embodiments described above, by embedding elements other than the drive circuit layer in the first substrate 30, it is possible to make all four sides of the element substrate, that is, all four sides of the electric device flexible. As a result, it is a thin, light and flexible electrical device such as paper, which achieves downsizing and weight reduction by reducing the overall thickness of the device, narrowing the frame, and achieving high robustness (high reliability). can do. Thereby, the versatility of an electric apparatus spreads.

In the above embodiment, the capsule type electrophoretic material is used, but the present invention is not limited to this. A partition such as a partition wall type may be present, or a partition may not be present. Further, a particle configuration other than black and white two particles charged to different polarities may be used.
Further, applicable electro-optic materials are not limited to electrophoretic materials. For example, liquid crystal, EL, electrowetting, MEMS, or the like can be used.
In addition, the electronic component may be installed outside the display area, or the frame may be made as small as possible by embedding it below the display area.

  5 ... Display unit, 30, 34 ... First substrate, 30a, 30e, 34a, 39a, 46a, 111a ... Surface, 31, 39 ... Second substrate, 32 ... Electro-optical element (functional element), 34a ... Surface (one surface) , 35... Pixel electrode, 38... Protective layer, 39 b .. back surface (one side), 40, TFT... Pixel, 41 a... Semiconductor layer, 41 b ... gate insulating film, 41 c. 71 ... detection element (electrical device), 92,300,301,302,303,304 ... element substrate, 92,300,301,302,303,304 ... element substrate (semiconductor device), TR, TRc ... thin film transistor, DESCRIPTION OF SYMBOLS 100,102,103,105 ... Semiconductor device, 112 ... Alignment mark, 113 ... Reading hole, 114, 116 ... Conductive part, 114 ... Conductive part (1st conductive part) 115 ... conductive portion (second conducting portion), 120 ... electrophoretic display device (an electric device), 121 ... liquid crystal device (electrical device), 310 ... counter substrate

Claims (21)

A first substrate having a source electrode and a drain electrode on one side;
A second substrate having a gate electrode, a gate insulating film and a semiconductor layer on one surface;
The first substrate and the second substrate are provided with a thin film transistor configured between the first substrate and the second substrate by bonding the first substrate and the first substrate facing each other. A featured semiconductor device. A first substrate having a source electrode, a drain electrode and a semiconductor layer on one side;
A second substrate having a gate electrode on one side;
A gate insulating film disposed between the source electrode and the drain electrode and the gate electrode to insulate them;
A thin film transistor configured between the first substrate and the second substrate by bonding the first substrate and the second substrate so that the one surface faces each other; and
The semiconductor device, wherein the gate insulating film is provided on the first substrate or the second substrate. A first substrate having a source electrode, a drain electrode, a gate electrode, and a gate insulating film disposed between the source electrode, the drain electrode, and the gate electrode on one surface;
A second substrate having a semiconductor layer on one surface;
A thin film transistor configured between the first substrate and the second substrate by bonding the first substrate and the second substrate with the one side facing each other. A featured semiconductor device. The semiconductor device according to claim 1, wherein the semiconductor layer is made of an organic semiconductor or an oxide semiconductor. The thin film transistor has an offset structure in which the source electrode, the drain electrode, and the gate electrode do not overlap each other in plan view,
At least a part of the first conductive part connected to the source electrode and the second conductive part connected to the drain electrode overlaps the gate electrode in plan view,
The said 1st electroconductive part and the said 2nd electroconductive part are formed using the material softer than the said gate electrode, the said drain electrode, and the said source electrode, The any one of Claims 1-4 characterized by the above-mentioned. The semiconductor device according to item. The semiconductor device according to claim 1, wherein a protective layer is provided at an interface between the semiconductor layer and the first substrate or the second substrate. The semiconductor device according to claim 1, wherein a pixel electrode connected to the drain electrode is provided on a surface of the first substrate or the second substrate. The semiconductor device according to claim 1, wherein a reflective film is provided so as to cover at least the semiconductor layer. The semiconductor device according to claim 1, wherein the first substrate and the second substrate have flexibility or stretchability. Forming a source electrode and a drain electrode on one surface of the first substrate;
Forming a gate electrode, a gate insulating film and a semiconductor layer on one surface of the second substrate;
A step of forming a thin film transistor between the first substrate and the second substrate by bonding the one substrate side of the first substrate and the second substrate to each other. Method. Forming a source electrode and a drain electrode on one surface of the first substrate;
Forming a semiconductor layer on the source electrode and the drain electrode;
Forming a gate electrode on one surface of the second substrate;
Forming a gate insulating film on the first substrate having the source electrode, the drain electrode and the semiconductor layer, or forming a gate insulating film on the second substrate having the gate electrode;
A step of forming a thin film transistor between the first substrate and the second substrate by bonding the one substrate side of the first substrate and the second substrate to each other. Method. Forming a gate electrode on one surface of the first substrate;
Forming a gate insulating film on the first substrate so as to cover the gate electrode;
Forming a source electrode and a drain electrode on the gate insulating film;
Forming a semiconductor layer on one surface of the second substrate;
A step of forming a thin film transistor between the first substrate and the second substrate by bonding the one substrate side of the first substrate and the second substrate to each other. Method. The method for manufacturing a semiconductor device according to claim 10, wherein the semiconductor layer is made of an organic semiconductor or an oxide semiconductor. In the step of forming the source electrode and the drain electrode,
Forming the source electrode and the drain electrode at offset positions that do not overlap the gate electrode in plan view,
The method further includes forming a first conductive portion connected to the source electrode and a second conductive portion connected to the drain electrode, and in the step, the first conductive portion and the second conductive portion are formed. At least a portion is formed so as to overlap with the gate electrode in plan view, and a material softer than the gate electrode, the drain electrode, and the source electrode is used as a material for forming the first conductive portion and the second conductive portion. The method for manufacturing a semiconductor device according to claim 10, wherein the method is used. The method for manufacturing a semiconductor device according to claim 10, wherein a protective layer is formed at an interface between the semiconductor layer and the first substrate or the second substrate. The semiconductor device according to claim 10, further comprising a step of forming a pixel electrode connected to the drain electrode on one of the first substrate and the second substrate. Production method. The semiconductor device according to claim 10, further comprising a step of forming a reflective film covering at least the semiconductor layer on one of the first substrate and the second substrate. Production method. An alignment mark is formed on each of the one surface of the first substrate and the second substrate, and a reading hole for reading the alignment mark on another substrate is formed on the first substrate and the second substrate. And
When the substrates are bonded to each other, the alignment mark on one substrate is read through the reading hole on the other substrate, thereby determining the bonding position between the first substrate and the second substrate. The method for manufacturing a semiconductor device according to claim 10, wherein: Forming an alignment mark on the one surface of the first substrate;
When the first substrate and the second substrate are bonded together, the alignment marks on the first substrate are read using transmitted light that passes through the second substrate, so that the first substrate and the second substrate are connected to each other. The method for manufacturing a semiconductor device according to claim 10, wherein a bonding position of the semiconductor device is determined. An element substrate provided with a plurality of electrodes;
A counter substrate disposed to face the element substrate;
A functional element disposed between the element substrate and the counter substrate;
An electric device, wherein the element substrate comprises the semiconductor device according to any one of claims 1 to 9, and the thin film transistor embedded in the element substrate is connected to the electrode. The functional element is a display element having a display unit in which a plurality of pixels are arranged,
21. The electric device according to claim 20, wherein the thin film transistor functions as a switching element for driving a pixel included in the display portion.

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