JP6628688B2 - Energization inspection device and energization inspection method - Google Patents

Description

  The technology disclosed in the specification of the present application relates to an energization inspection device and an energization inspection method.

  In a silicon carbide semiconductor, when electrons and holes generated when a forward current flows through a pn junction diode are recombined, stacking faults may grow from defects existing in the silicon carbide semiconductor.

  Since a current does not flow in a region where a stacking fault occurs, a metal-oxide-semiconductor field-effect transistor (ie, MOSFET) element or an insulated gate type which performs on / off control of the current is provided. In the case where a bipolar transistor (insulated gate bipolar transistor, that is, an IGBT) element or the like is formed using a silicon carbide semiconductor, there is a problem that on-resistance increases due to growth of stacking faults.

As a method for detecting the occurrence of stacking faults, for example, a forward current of 100 A / cm ² is applied to a pn junction diode for 1 hour as disclosed in Patent Document 1 (Japanese Patent Application Laid-Open No. 2005-167035). There is a method of detecting an increase in the forward voltage.

Further, for example, there is a detection method as disclosed in Patent Document 2 (WO 2014/148294). That is, the temperature of the semiconductor element is set to, for example, 150 ° C. or more and 230 ° C. or less, and the current density at the pn junction of the semiconductor element is set to, for example, 120 A / cm ² or more and 400 A / cm ² or less. A certain forward current is continuously supplied to the semiconductor element. Then, when the increase in the forward resistance becomes saturated, the degree of change in the forward resistance is calculated, and it is determined whether or not the calculated degree of change is less than a threshold value.

  The conduction inspection device disclosed in Patent Document 2 (WO 2014/148294) includes a cooling plate that contacts a back electrode of a silicon carbide semiconductor element chip and an electrode that contacts a front electrode of a silicon carbide semiconductor element chip. And Then, the conduction test device disclosed in Patent Document 2 applies pressure across the semiconductor element chip of silicon carbide between the electrode and the cooling plate, and causes a forward current of a pn junction to flow between the electrode and the cooling plate.

  When a forward current is applied, a stacking fault grows in a semiconductor element chip including a defect serving as a starting point of a stacking fault. Therefore, the on-resistance increases.

JP 2005-167035 A WO 2014/148294

  A silicon carbide semiconductor device includes an epitaxial layer on a silicon carbide semiconductor substrate having an off angle. The epitaxial layer is formed by epitaxially growing a silicon carbide film. When a silicon carbide film is epitaxially grown on a silicon carbide semiconductor substrate having an off-angle, step-flow growth is performed, and a high-quality epitaxial layer with few defects can be formed.

On the other hand, for example, as disclosed in Japanese Patent Application Laid-Open No. 2013-232574, stacking faults grow in a direction perpendicular to the direction of step flow growth. Therefore, when stacking faults grow to the end of the current-carrying region of the semiconductor element, the growth stops and the increase in on-resistance is saturated. For example, at a current of 400 A / cm ² or less, the growth rate of stacking faults can be increased as the current density is increased, so that the increase in on-resistance is saturated in a short time.

  In addition, as the temperature at the time of current application is higher, the increase in on-resistance is saturated in a shorter time. However, when the temperature is raised to, for example, 230 ° C. or higher, the Au surface is oxidized when, for example, a Ni / Au laminated film is used for the back electrode. Then, when joining with a solder when assembling a semiconductor element chip, there is a case where joining cannot be performed because the wettability of the solder is deteriorated. For this reason, there is a limit to increasing the temperature in order to shorten the energization time. Under such circumstances, the energization time until the stacking fault is saturated needs to be about several minutes, which is one of the causes of the energization time lengthening when conducting an energization inspection of a plurality of semiconductor element chips.

  The technique disclosed in the specification of the present application has been made in order to solve the problems described above, and shortens the energization time even when performing an energization test on a plurality of semiconductor element chips. It is about technology that can be.

According to a first aspect of the technology disclosed in the present specification, there is provided a semiconductor wafer including a silicon carbide substrate of a first conductivity type, a drift layer of a first conductivity type formed on an upper surface of the semiconductor wafer, and a drift layer. And a first conductivity type source layer formed on the surface of the well layer and a plurality of semiconductor element chips provided with a second conductivity type well layer formed on the surface of the well layer. Each of the semiconductor element chips includes a pn junction composed of the drift layer and the well layer; and a surface electrode connected to a first end of the pn junction. A first conductive material provided across the plurality of front electrodes, a second conductive material in contact with a back electrode provided on the lower surface of the semiconductor wafer, and a second conductive material; Sandwich the first cushioning material between A first energizing mechanism provided at a position, and a second energizing mechanism provided at a position sandwiching the second buffer material between the back electrode and the back electrode, wherein the back electrode of the semiconductor wafer includes the pn A first end of the joint is connected to a second end opposite to the first end, and the first energizing mechanism and the second energizing mechanism are arranged in the order of the pn junction. A current is caused to flow in the direction until the growth of stacking faults in the semiconductor element chip is saturated .
A second aspect of the technology disclosed in the specification of the present application is a conduction test apparatus that performs a conduction test on a plurality of semiconductor element chips, and each of the semiconductor element chips is provided on an upper surface of one semiconductor wafer. , A pn junction, and a surface electrode connected to a first end of the pn junction, wherein the conduction test device is provided with a first conductive buffer provided over a plurality of the surface electrodes. A second conductive material that contacts a back electrode provided on the lower surface of the semiconductor wafer, and a first energization provided at a position sandwiching the first buffer material between the material and the front surface electrode A second energizing mechanism provided at a position sandwiching the second buffer between the back electrode and the back electrode, wherein the back electrode of the semiconductor wafer is provided at the first end of the pn junction. Connected to the second end, which is the opposite end The first energizing mechanism and the second energizing mechanism flow a current in a forward direction of the pn junction, and a plurality of semiconductor wafers provided on an upper surface of the plurality of semiconductor wafers provided to overlap each other in plan view. An electric current inspection device that performs an electric current inspection of the semiconductor element chip, wherein the electric current inspection device further includes at least one conductive third buffer material provided between the adjacent semiconductor wafers, The third cushioning material is provided across the surface electrode of the semiconductor element chip in the first semiconductor wafer of the adjacent semiconductor wafers, and the first semiconductor of the semiconductor wafer is provided. The wafer contacts the back electrode of the second semiconductor wafer adjacent to the wafer.
A third aspect of the technology disclosed in the specification of the present application is a conduction test apparatus for conducting conduction of a plurality of semiconductor element chips, and each of the semiconductor element chips is provided on an upper surface of one semiconductor wafer. , A pn junction, and a surface electrode connected to a first end of the pn junction, wherein the conduction test device is provided with a first conductive buffer provided over a plurality of the surface electrodes. A second conductive material that contacts a back electrode provided on the lower surface of the semiconductor wafer, and a first energization provided at a position sandwiching the first buffer material between the material and the front surface electrode A second energizing mechanism provided at a position sandwiching the second buffer between the back electrode and the back electrode, wherein the back electrode of the semiconductor wafer is provided at the first end of the pn junction. Connected to the second end, which is the opposite end The first energizing mechanism and the second energizing mechanism allow a current to flow in a forward direction of the pn junction, and the first buffer is provided across a plurality of the surface electrodes. A conductive fourth buffer member, and a conductive fifth buffer member provided across the plurality of surface electrodes not provided with the fourth buffer member, wherein the first energizing mechanism is provided. A third energizing mechanism provided at a position sandwiching the fourth buffer between the surface electrode and a fourth energizing mechanism provided at a position sandwiching the fifth buffer between the surface electrode and the fourth electrode; And an energizing mechanism.

A fourth aspect of the technology disclosed in the specification of the present application is a conduction test method for conducting conduction of a plurality of semiconductor element chips, wherein each of the semiconductor element chips is provided on an upper surface of one semiconductor wafer. And each of the semiconductor element chips includes a surface electrode connected to a first end of the pn junction, and has a conductive first electrode extending over a plurality of the surface electrodes. And a conductive second cushioning material that straddles a second end of the plurality of semiconductor element chips, which is an end opposite to the first end of the pn junction. A first energizing mechanism is provided at a position sandwiching the first cushioning material with the front surface electrode, and the second cushioning material is provided between the second cushioning material and the second end of the pn junction. A second energizing mechanism is provided at a position between the first energizing mechanism and the second energizing mechanism. A current flowing in the forward direction of the pn junction by using an electrical mechanism, and flowing a current in the forward direction of the pn junction, at least the second buffer material and the second energizing mechanism A back electrode is provided which is removed and connected to the second end of the pn junction.

According to a first aspect of the technology disclosed in the present specification, there is provided a semiconductor wafer including a silicon carbide substrate of a first conductivity type, a drift layer of a first conductivity type formed on an upper surface of the semiconductor wafer, and a drift layer. And a first conductivity type source layer formed on the surface of the well layer and a plurality of semiconductor element chips provided with a second conductivity type well layer formed on the surface of the well layer. Each of the semiconductor element chips includes a pn junction composed of the drift layer and the well layer; and a surface electrode connected to a first end of the pn junction. A first conductive material provided across the plurality of front electrodes, a second conductive material in contact with a back electrode provided on the lower surface of the semiconductor wafer, and a second conductive material; Sandwich the first cushioning material between A first energizing mechanism provided at a position, and a second energizing mechanism provided at a position sandwiching the second buffer material between the back electrode and the back electrode, wherein the back electrode of the semiconductor wafer includes the pn A first end of the joint is connected to a second end opposite to the first end, and the first energizing mechanism and the second energizing mechanism are arranged in the order of the pn junction. A current is caused to flow in the direction until the growth of stacking faults in the semiconductor element chip is saturated . According to such a configuration, the energization time can be shortened even when the energization inspection of a plurality of semiconductor element chips is performed.
A second aspect of the technology disclosed in the specification of the present application is a conduction test apparatus that performs a conduction test on a plurality of semiconductor element chips, and each of the semiconductor element chips is provided on an upper surface of one semiconductor wafer. , A pn junction, and a surface electrode connected to a first end of the pn junction, wherein the conduction test device is provided with a first conductive buffer provided over a plurality of the surface electrodes. A second conductive material that contacts a back electrode provided on the lower surface of the semiconductor wafer, and a first energization provided at a position sandwiching the first buffer material between the material and the front surface electrode A second energizing mechanism provided at a position sandwiching the second buffer between the back electrode and the back electrode, wherein the back electrode of the semiconductor wafer is provided at the first end of the pn junction. Connected to the second end, which is the opposite end The first energizing mechanism and the second energizing mechanism flow a current in a forward direction of the pn junction, and a plurality of semiconductor wafers provided on an upper surface of the plurality of semiconductor wafers provided to overlap each other in plan view. An electric current inspection device that performs an electric current inspection of the semiconductor element chip, wherein the electric current inspection device further includes at least one conductive third buffer material provided between the adjacent semiconductor wafers, The third cushioning material is provided across the surface electrode of the semiconductor element chip in the first semiconductor wafer of the adjacent semiconductor wafers, and the first semiconductor of the semiconductor wafer is provided. The wafer contacts the back electrode of the second semiconductor wafer adjacent to the wafer. According to such a configuration, the energization time can be shortened even when the energization inspection of a plurality of semiconductor element chips is performed.
A third aspect of the technology disclosed in the specification of the present application is a conduction test apparatus that performs a conduction test on a plurality of semiconductor element chips, and each of the semiconductor element chips is provided on an upper surface of one semiconductor wafer. , A pn junction, and a surface electrode connected to a first end of the pn junction, wherein the conduction test device is provided with a first conductive buffer provided over a plurality of the surface electrodes. A second conductive material that contacts a back electrode provided on the lower surface of the semiconductor wafer, and a first energization provided at a position sandwiching the first buffer material between the material and the front surface electrode A second energizing mechanism provided at a position sandwiching the second buffer between the back electrode and the back electrode, wherein the back electrode of the semiconductor wafer is provided at the first end of the pn junction. Connected to the second end, which is the opposite end The first energizing mechanism and the second energizing mechanism allow a current to flow in a forward direction of the pn junction, and the first buffer is provided across a plurality of the surface electrodes. A conductive fourth buffer member, and a conductive fifth buffer member provided across the plurality of surface electrodes not provided with the fourth buffer member, wherein the first energizing mechanism is provided. A third energizing mechanism provided at a position sandwiching the fourth buffer between the surface electrode and a fourth energizing mechanism provided at a position sandwiching the fifth buffer between the surface electrode and the fourth electrode; And an energizing mechanism. According to such a configuration, the energization time can be shortened even when the energization inspection of a plurality of semiconductor element chips is performed.

A fourth aspect of the technology disclosed in the specification of the present application is a conduction test method for conducting conduction of a plurality of semiconductor element chips, wherein each of the semiconductor element chips is provided on an upper surface of one semiconductor wafer. And each of the semiconductor element chips includes a surface electrode connected to a first end of the pn junction, and has a conductive first electrode extending over a plurality of the surface electrodes. And a conductive second cushioning material that straddles a second end of the plurality of semiconductor element chips, which is an end opposite to the first end of the pn junction. A first energizing mechanism is provided at a position sandwiching the first cushioning material with the front surface electrode, and the second cushioning material is provided between the second cushioning material and the second end of the pn junction. A second energizing mechanism is provided at a position between the first energizing mechanism and the second energizing mechanism. A current flowing in the forward direction of the pn junction by using an electrical mechanism, and flowing a current in the forward direction of the pn junction, at least the second buffer material and the second energizing mechanism A back electrode is provided which is removed and connected to the second end of the pn junction. According to such a configuration, even in the case where the energization inspection of multiple semiconductor device chips, it is possible to shorten the energizing time.

  The objects, features, aspects, and advantages of the technology disclosed in this specification will become more apparent from the following detailed description and the accompanying drawings.

FIG. 1 is a plan view schematically illustrating a configuration for realizing a semiconductor element chip according to an embodiment. FIG. 2 is a cross-sectional view illustrating an AA cross section of the current conducting unit in FIG. FIG. 11 is a plan view schematically illustrating a configuration of a semiconductor element chip according to an embodiment when a forward current is continuously supplied. FIG. 1 is a cross-sectional view schematically illustrating a configuration for realizing a conduction inspection device according to an embodiment. 4 is a flowchart illustrating an operation of the conduction inspection apparatus according to the embodiment. 4 is a flowchart illustrating an operation of the conduction inspection apparatus according to the embodiment. FIG. 2 is a cross-sectional view schematically illustrating a configuration of an energization inspection device during energization screening according to the embodiment. FIG. 4 is a cross-sectional view schematically illustrating a configuration of a semiconductor element chip on which a back surface drain electrode is formed according to the embodiment. 4 is a flowchart illustrating an operation of the conduction inspection apparatus according to the embodiment. FIG. 5 is a cross sectional view schematically illustrating a configuration of a silicon carbide semiconductor device after a preliminary test according to the embodiment. FIG. 5 is a cross sectional view schematically illustrating a configuration of a silicon carbide semiconductor device after a preliminary test according to the embodiment. FIG. 1 is a cross-sectional view schematically illustrating a configuration for realizing a conduction inspection device according to an embodiment. FIG. 1 is a cross-sectional view schematically illustrating a configuration for realizing a conduction inspection device according to an embodiment. FIG. 1 is a cross-sectional view schematically illustrating a configuration for realizing a conduction inspection device according to an embodiment.

  Hereinafter, embodiments will be described with reference to the accompanying drawings.

  It should be noted that the drawings are schematically shown, and the correlation between the size and the position of the image shown in each of the different drawings is not necessarily accurately described and can be changed as appropriate.

  In the following description, similar components are denoted by the same reference numerals, and their names and functions are the same. Therefore, a detailed description of them may be omitted.

  Further, in the following description, terms that mean a specific position and direction such as “top”, “bottom”, “side”, “bottom”, “front” or “back” may be used. Even so, these terms are used for the sake of convenience to facilitate understanding of the contents of the embodiments, and are not related to the direction in which they are actually implemented.

<First embodiment>
Hereinafter, an energization inspection device and an energization inspection method according to the present embodiment will be described.

  Note that the following description is based on the assumption that the first conductivity type is an n-type and the second conductivity type is a p-type.

<About the configuration of the conduction inspection device>
FIG. 1 is a plan view schematically illustrating a configuration for realizing a semiconductor element chip according to the present embodiment.

  As illustrated in FIG. 1, a semiconductor element chip 1 of a MOSFET includes a current conducting part 2 of a MOSFET, a gate pad part 3, and a termination part 4.

  A semiconductor element chip 1 of a MOSFET is formed on an upper surface of a silicon carbide semiconductor substrate having an off angle. The gate pad section 3 applies an ON signal and an OFF signal. The terminal portion 4 is a region for ensuring a withstand voltage.

  Here, a defect 5 serving as a starting point of a stacking fault, and a stacking fault 6 and a stacking fault 7 are formed in the semiconductor element chip 1. Note that the direction of the arrow in FIG. 1 is the step flow direction.

  FIG. 2 is a cross-sectional view illustrating an AA cross section of the current passing unit 2 in FIG. As illustrated in FIG. 2, the semiconductor element chip includes a first conductivity type silicon carbide semiconductor substrate 11 having an off angle, and a drift layer 12 formed on the upper surface of silicon carbide semiconductor substrate 11.

  Drift layer 12 is a first conductivity type silicon carbide epitaxial film formed on the upper surface of silicon carbide semiconductor substrate 11 by step flow growth.

  The semiconductor element chip includes a well layer 13 of the second conductivity type formed on the surface layer of the drift layer 12, a source layer 14 of the first conductivity type formed on the surface layer of the well layer 13, and a well layer 13. And a high-concentration second-conduction-type contact injection layer 15 formed on the surface layer.

  The semiconductor element chip includes a gate insulating film 17 formed in contact with the well layer 13 interposed between the source layer 14 and the drift layer 12, and a gate electrode 16 formed in contact with the gate insulating film 17. And an interlayer insulating film 18 formed to cover the gate electrode 16.

  Gate electrode 16 includes, for example, a conductive polysilicon film. The gate electrode 16 is connected to the gate pad section 3 in FIG.

Gate insulating film 17 includes, for example, SiO ₂ . Interlayer insulating film 18 includes, for example, SiO ₂ .

  The semiconductor element chip includes a source electrode 19, a back contact electrode 20 formed on the lower surface of the silicon carbide semiconductor substrate 11, a back drain electrode 21 formed on the lower surface of the back contact electrode 20, and a back drain electrode 21. And a back surface drain electrode 22 formed on the lower surface.

  Source electrode 19 includes, for example, aluminum (Al) metal. Source electrode 19 is connected to contact injection layer 15 and source layer 14.

  Back contact electrode 20 includes, for example, nickel silicide. Further, the back surface drain electrode 21 and the back surface drain electrode 22 are laminated metal films. Back surface drain electrode 21 is, for example, nickel, and back surface drain electrode 22 is, for example, gold.

  FIG. 2 illustrates a stacking fault 6 corresponding to FIG.

  Next, an on / off operation of a semiconductor element chip, for example, an on / off operation of a MOSFET will be described. Hereinafter, a case where the first conductivity type is an n-type semiconductor and the second conductivity type is a p-type semiconductor will be described.

  When a positive ON voltage is applied to the gate electrode 16, an n-type inversion channel layer is formed on the surface layer of the well layer 13 in a region overlapping with the gate electrode 16 in plan view.

  Then, the source layer 14 and the drift layer 12 are connected via the n-type inversion channel layer. Therefore, a current flows between the source electrode 19 and the backside drain electrode 21 and the backside drain electrode 22.

  When an off-voltage is applied to the gate electrode 16, the n-type inversion channel layer is not formed, and no current flows between the source electrode 19 and the backside drain electrode 21 and the backside drain electrode 22.

  In an actual on / off operation when an inverter device is configured using a semiconductor element, a forward direction is applied to a body diode formed of a pn junction between a p-type well layer 13 and an n-type drift layer 12 at the time of off. There is a timing at which the current 8 flows.

  FIG. 2 discloses a pn junction 100 showing a pn junction between p-type well layer 13 and n-type drift layer 12. The source side of the pn junction 100 is connected to a source electrode 19 which is a surface electrode. The drain side of the pn junction 100 is connected to a back surface drain electrode 21 and a back surface drain electrode 22 which are back surface electrodes.

  When a forward current 8 flows through the pn junction 100 of the silicon carbide semiconductor, stacking faults 6 may grow due to energy generated when electrons and holes are recombined when current flows.

  As illustrated in FIG. 1, the stacking fault 6 is generated from the defect 5 serving as a starting point and grows in a direction orthogonal to the step flow growth direction of the drift layer 12 which is an epitaxial layer. Here, the growth in the step flow direction is limited by the thickness of the drift layer 12 which is an epitaxial layer.

  For example, when defect 5 serving as a starting point is present at the interface between silicon carbide semiconductor substrate 11 and drift layer 12, for example, when off angle is 4 ° and drift layer 12 has a thickness of 30 μm, In some cases, the width of the stacking fault 6 is

  Is limited to When the forward current 8 continues to flow through the pn junction 100, the stacking faults 6 grow in a direction orthogonal to the step flow growth direction. Then, the stacking fault 6 grows until it reaches the end of the current conducting portion 2 of the semiconductor element chip.

  In the case illustrated in FIG. 1, the stacking fault 7 has grown until it reaches the upper end of the current flow section 2. On the other hand, the stacking fault 6 has grown to the center of the current-carrying part 2.

  In the region where the stacking faults 6 are formed and the region where the stacking faults 7 are formed as illustrated in FIG. 1 or FIG. 2, no current flows, and thus the on-resistance increases.

  FIG. 3 is a plan view schematically illustrating the configuration of the semiconductor element chip according to the present embodiment when the forward current 8 continues to flow through the pn junction 100.

  Further, when the forward current 8 continues to flow through the pn junction 100, the stacking fault 7 has already grown until it reaches the end of the current-carrying portion 2, and therefore does not grow any further. On the other hand, the stacking fault 6 continues to grow until it reaches the end of the current-carrying part 2 as illustrated in FIG.

  The stacking fault 6 and the stacking fault 7 grow as the time for flowing the forward current 8 increases, so that the on-resistance increases. However, the growth of the stacking faults 6 and 7 is limited in the step flow direction of the drift layer 12 by the thickness of the drift layer 12 which is an epitaxial layer, and is orthogonal to the step flow direction of the drift layer 12. The direction is limited by the width of the current flow section 2 in plan view. Therefore, if current is supplied for a certain time or more, the increase in on-resistance is saturated.

  If a forward current that is sufficiently larger than a forward current that may flow during actual use is allowed to flow in advance and the stacking faults in the semiconductor element chip including the defect 5 are grown until they are saturated, during actual use, The on-resistance does not increase. Since the growth rate of stacking faults increases as the temperature during energization increases and the current value increases, the growth of the stacking result can be saturated in a short time if these conditions are satisfied.

  FIG. 4 is a cross-sectional view schematically illustrating a configuration for realizing the conduction inspection apparatus according to the present embodiment. In FIG. 4, some components are arranged with a gap between the components to facilitate understanding of the configurations. However, in practice, the respective configurations are arranged in contact with each other.

  As illustrated in FIG. 4, the conduction inspection device includes a semiconductor wafer 31, a conductive buffer 34 disposed on the lower surface of the semiconductor wafer 31, and a cooling stage 32 disposed on the lower surface of the conductive buffer 34. Is provided.

  Semiconductor wafer 31 is a silicon carbide semiconductor substrate. A plurality of semiconductor element chips 1 are formed on the upper surface of one semiconductor wafer 31.

  The conductive buffer 34 is disposed between the lower surface of the semiconductor wafer 31 and the upper surface of the cooling stage 32. The conductive buffer material 34 is provided in contact with the back surface drain electrode of the semiconductor wafer 31.

  The conductive buffer 34 includes, for example, a thin metal film such as an aluminum foil, a carbon fiber material, or a conductive buffer sheet containing carbon particles.

  The cooling stage 32 is electrically and thermally connected to the back surface drain electrode of the semiconductor wafer 31. Further, cooling stage 32 functions as an energizing mechanism for energizing semiconductor wafer 31. The cooling stage 32 controls the temperature of the semiconductor wafer 31.

  Further, the conduction inspection apparatus includes a conductive buffer 35 disposed on the upper surface of the semiconductor wafer 31 and a conduction electrode 33 disposed on the upper surface of the conductive buffer 35.

  The conductive buffer material 35 is disposed between the upper surface of the semiconductor wafer 31 and the lower surface of the conductive electrode 33. The conductive buffer material 35 is provided across the source electrodes 19 of the plurality of semiconductor element chips 1. The conductive cushioning material 35 covers a region of the semiconductor element chip 1 on the upper surface of the semiconductor wafer 31, including the current conducting portion 2 and the gate pad portion 3.

  The conductive buffer 35 includes, for example, a metal thin film such as an aluminum foil, a carbon fiber material, or a conductive buffer sheet containing carbon particles.

  The energizing electrodes 33 are electrically connected in parallel to the surface electrodes of the plurality of semiconductor element chips 1 formed on the upper surface of the semiconductor wafer 31.

  In the above structure, the semiconductor wafer 31 is pressed against the cooling stage 32 by applying pressure between the cooling stage 32 and the energizing electrode 33, that is, by applying pressure in the direction of the arrow illustrated in FIG. By doing so, the temperature of the semiconductor wafer 31 is controlled by adjusting the temperature of the cooling stage 32 while lowering the thermal resistance between the semiconductor wafer 31 and the cooling stage 32.

  Further, by applying a pressure between the cooling stage 32 and the energizing electrode 33, the electric resistance between the back surface drain electrode of the semiconductor wafer 31 and the cooling stage 32, and the front surface electrode of the semiconductor element chip 1 and the energizing electrode 33 are increased. And the electrical resistance between them can be reduced.

<About the operation of the conduction inspection device>
Next, the operation of the conduction inspection apparatus according to the present embodiment will be described with reference to FIG. FIG. 5 is a flowchart illustrating the operation of the conduction inspection apparatus according to the present embodiment.

  First, the semiconductor element chips 1 are formed on the upper surface of the semiconductor wafer 31 by a wafer process. This is a process corresponding to step ST101 illustrated in FIG.

  Next, after setting the structure formed in step ST101 in the conduction inspection apparatus illustrated in FIG. 4, the conduction electrode 33 and the cooling stage 32 are used to separate the back surface of the semiconductor wafer 31 from the front surface electrode of the semiconductor element chip 1. A current flows toward the drain electrode. This is a process corresponding to step ST102 illustrated in FIG. The energization temperature is determined based on heat generation of the semiconductor element chip 1 by energization and the cooling performance of the cooling stage 32. Then, current is supplied until the stacking fault reaches the end of the current supply section 2 of each semiconductor element chip 1.

  After the energization, the structure formed in step ST101 is taken out of the device, and a dicing process for dividing the structure formed in step ST101 into chip states is performed. This is a process corresponding to step ST103 illustrated in FIG.

  After the dicing process, the semiconductor device chip 1 is subjected to a chip test. This is a process corresponding to step ST104 illustrated in FIG. Before the dicing process, a wafer test for measuring the characteristics of the semiconductor element chip 1 in a wafer state may be performed.

  As a result of measuring the characteristics of the semiconductor element chip 1 in the chip test or the wafer test, the semiconductor element chip 1 that does not satisfy the desired characteristic standard is determined to be defective.

  For example, when the off angle is 4 ° and the thickness of the drift layer 12 is 30 μm, a stacking fault having a width of 429 μm grows. Therefore, when the size of the current-carrying part 2 is, for example, 5 mm square, and when one stacking fault grows from one end of the current-carrying part 2 to the opposite end, the increase in on-resistance is approximately 9%. Further, when five stacking faults grow from the end of the current conducting portion 2 to the end on the opposite side, the increase in on-resistance is about 43%.

  When the standard of the on-resistance in the chip test or the wafer test is, for example, about ± 20% of the center value, at least the semiconductor element chip 1 in which five or more stacking faults have grown is determined to be defective.

  On the other hand, some semiconductor element chips 1 determined to be non-defective have stacking faults. However, if energization is performed for a sufficient time to completely saturate the growth of stacking faults, there is no problem since the on-resistance cannot be increased due to the growth of stacking faults in actual use.

  As disclosed in Patent Literature 2 (International Publication No. WO 2014/148294), in the case of conducting an energization test, that is, an energization screening after dividing into semiconductor element chips, it is necessary to shorten the energization time as much as possible.

  Therefore, in the case exemplified in Patent Document 2 (International Publication No. WO 2014/148294), the on-resistance is measured before and after energization, and a semiconductor element chip having a changed on-resistance is determined to be defective based on the measurement result. The method was used. According to the screening method, a semiconductor element chip including a defect serving as a starting point of a stacking fault is excluded as much as possible, and a semiconductor element chip whose on-resistance increases in actual use is excluded.

  Even when the above method is adopted, it is necessary to supply current for about 5 minutes per chip. That is, it takes about 200 minutes to screen 40 chips.

  On the other hand, in the present embodiment, a plurality of semiconductor element chips 1 on one semiconductor wafer 31, for example, 40 chips can be energized in parallel. Therefore, even when screening a plurality of semiconductor element chips 1, there is no need to increase the energizing time. In addition, it can be reduced to 5/40 minutes when converted into the energizing time per chip.

  In addition, for example, even when energization is performed for a long time of 20 minutes, the energization time converted to one chip is 1/10 as compared with energization in a chip state. Therefore, current can be supplied for a sufficiently long time, so that the growth can be performed until the stacking fault is completely saturated.

  As described above, according to the present embodiment, since a plurality of semiconductor element chips 1 provided on the upper surface of the semiconductor wafer 31 can be energized in parallel, a plurality of semiconductor element chips 1 can be screened. Even if it does, there is no need to increase the energizing time. That is, the energizing time converted per chip can be shortened.

  In addition, since current can be supplied for a sufficiently long time, growth can be performed until stacking faults are completely saturated. Therefore, it is not necessary to measure the on-resistance before and after the energization, and determine that the semiconductor element chip whose on-resistance has changed based on the measurement result is defective.

  As described above, since the conduction test apparatus can be configured with a simple configuration, the chip cost can be reduced.

<Second embodiment>
An energization inspection device and an energization inspection method according to the present embodiment will be described. In the following, the same components as those described in the above-described embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

<About the operation of the conduction inspection device>
The operation of the conduction inspection apparatus according to the present embodiment will be described with reference to FIG. FIG. 6 is a flowchart illustrating the operation of the conduction test apparatus according to the present embodiment.

  In the first embodiment, the energization screening, that is, the step of passing a current from the front surface electrode of the semiconductor element chip 1 to the back surface drain electrode of the semiconductor wafer 31 is performed after the wafer process is completed. On the other hand, in the present embodiment, the energization screening is performed during the wafer process and before the back surface drain electrode is formed.

  First, the semiconductor device chip 1 is formed partway on the upper surface of the semiconductor wafer 31 by a wafer process. Specifically, at least the back surface drain electrode is not formed, and another structure is formed. This is a process corresponding to step ST201 illustrated in FIG.

  Next, after setting the structure formed in step ST <b> 201 in the conduction test apparatus illustrated in FIG. 4, a current is caused to flow from the front surface electrode of the semiconductor element chip 1 to the back surface side of the semiconductor wafer 31. This is a process corresponding to step ST202 illustrated in FIG. The energization temperature is determined based on heat generation of the semiconductor element chip 1 by energization and the cooling performance of the cooling stage 32. Then, current is supplied until the stacking fault reaches the end of the current supply section 2 of each semiconductor element chip 1.

  After energization, a back surface drain electrode is formed on the lower surface of the semiconductor wafer 31. This is a process corresponding to step ST203 illustrated in FIG.

  Next, after taking out the structure formed in step ST201 from the conduction test apparatus, a dicing process for dividing the structure formed in step ST201 into chip states is performed. This is a process corresponding to step ST204 illustrated in FIG.

  After the dicing process, the semiconductor device chip 1 is subjected to a chip test. This is a process corresponding to step ST205 illustrated in FIG. Before the dicing process, a wafer test for measuring the characteristics of the semiconductor element chip 1 in a wafer state may be performed.

  FIG. 7 is a cross-sectional view schematically illustrating a configuration of a conduction inspection apparatus during conduction screening. On the lower surface of silicon carbide semiconductor substrate 11, a back contact electrode 20 made of, for example, nickel silicide is formed.

  In this state, a pressure is applied to the semiconductor wafer 31 including the semiconductor element chip 1 after applying a pressure between the cooling stage 32 and the current-carrying electrode 33.

  After the energization, the process returns to the wafer process. Then, as illustrated in FIG. 8, for example, a back surface drain electrode 21 made of nickel and a back surface drain electrode 22 made of gold are formed as the back surface drain electrode which is a laminated metal film. FIG. 8 is a cross-sectional view schematically illustrating a configuration of a semiconductor element chip on which a back surface drain electrode is formed.

  In the present embodiment, the back surface drain electrode that is thermally degraded during the energization screening is formed after the energization screening. Therefore, the temperature during energization can be increased.

  The heat-resistant temperature of a silicon carbide semiconductor is higher than that of a silicon semiconductor. However, the heat-resistant temperature after the wafer process is determined by the heat-resistant temperature of the constituent members. For example, when aluminum (Al) is used for the surface electrode and a polyimide material is used as the protective film, the heat-resistant temperature is 400 ° C. or less. If there is no problem.

  After forming the back surface drain electrode, which is a laminated metal film made of nickel and gold, the heat resistant temperature is limited to 230 ° C. or less. However, before the formation of the laminated metal film, it is possible to conduct the conduction screening at a high temperature up to 400 ° C.

  The growth rate of stacking faults increases as the temperature during energization increases. Therefore, by raising the temperature at the time of energization, the time until the growth of stacking faults is completely saturated can be shortened. Therefore, inspection costs can be reduced.

<Third embodiment>
An energization inspection device and an energization inspection method according to the present embodiment will be described. In the following, the same components as those described in the above-described embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

<About the operation of the conduction inspection device>
The operation of the conduction inspection apparatus according to the present embodiment will be described with reference to FIG. FIG. 9 is a flowchart illustrating an operation of the conduction inspection apparatus according to the present embodiment.

  In the first embodiment and the second embodiment, a chip test or a wafer test is performed after the energization screening. On the other hand, in the present embodiment, a preliminary test is also performed before the energization screening.

  First, the semiconductor device chip 1 is formed partway on the semiconductor wafer 31 by a wafer process. Specifically, at least the back surface drain electrode is not formed, and another structure is formed. This is a process corresponding to step ST301 illustrated in FIG.

  Next, a preliminary test is performed on the structure formed in step ST301. This is a process corresponding to step ST302 illustrated in FIG. In the preliminary test before the energization screening, at least a test for measuring a voltage value when a forward current 8 is applied to the pn junction 100 of the semiconductor element chip 1 or a forward voltage is applied to the pn junction 100 The test to measure the current value in the case of doing is included.

  If the voltage value is lower than the threshold value or the current value is higher than the threshold value in the preliminary test, it is determined that the chip is defective.

  FIG. 10 is a cross-sectional view schematically illustrating a configuration of the silicon carbide semiconductor device after the preliminary test. As illustrated in FIG. 10, a plurality of semiconductor element chips 1 are formed on the upper surface of one semiconductor wafer 31. The semiconductor element chip 1 includes a source electrode 19 as a front electrode, a back contact electrode 20 as an ohmic electrode, and a protective film 41.

  The protection film 41 includes, for example, a polyimide film. The protective film 41 is a film that protects the upper surface of the semiconductor chip 1. The protective film 41 is an insulating film for preventing discharge on the upper surface of the semiconductor chip 1.

  As illustrated in FIG. 10, a semiconductor chip 1 whose forward voltage is lower than the threshold value or whose forward current is higher than the threshold value is defined as a defective chip 1A.

  Next, as illustrated in FIG. 11, an insulating film 42 is formed on the upper surface of the source electrode 19, which is the surface electrode of the defective chip 1A. This is a process corresponding to step ST303 illustrated in FIG. FIG. 11 is a cross-sectional view schematically illustrating a configuration of the silicon carbide semiconductor device after the preliminary test.

  The insulating film 42 is, for example, an insulating film such as a polyimide film. The insulating film 42 is formed, for example, by the following method.

  A negative photosensitive polyimide film is applied on the upper surface of the semiconductor wafer 31. Then, ultraviolet rays are irradiated to the position of the source electrode 19 of the defective chip 1A to perform development processing. By doing so, the insulating film 42 is selectively formed on the upper surface of the source electrode 19 of the defective chip 1A.

  Alternatively, an insulating material such as polyimide is put in a dispenser and potted on the upper surface of the source electrode 19 of the defective chip 1A. By doing so, the insulating film 42 is selectively formed on the upper surface of the source electrode 19 of the defective chip 1A.

  When the wafer tester used in the preliminary test has a function of marking the defective chip 1A, the ink material of the mark can be used as the insulating film 42.

  The insulating film 42 may be formed so as to cover the entire upper surface of the source electrode 19, but as illustrated in FIG. 11, the conductive buffer 35, the conductive electrode 33, and the defective chip 1A at the time of the current screening. The source electrode 19 may be formed at least at a position that prevents the connection.

  Next, after setting the structure formed in step ST301 in the conduction inspection device, a current is caused to flow from the front surface electrode of the semiconductor element chip 1 toward the back surface of the semiconductor wafer 31. This is a process corresponding to step ST304 illustrated in FIG. The energization temperature is determined based on heat generation of the semiconductor element chip 1 by energization and the cooling performance of the cooling stage 32.

  Next, a back surface drain electrode is formed on the lower surface of the semiconductor wafer 31. This is a process corresponding to step ST305 illustrated in FIG.

  Next, current is supplied until the stacking fault reaches the end of the current supply section 2 of each semiconductor element chip 1. Then, after energization, the structure formed in step ST301 is taken out of the energization inspection device, and a dicing process for dividing the structure formed in step ST301 into chip states is performed. This is a process corresponding to step ST306 illustrated in FIG.

  After the dicing process, the semiconductor device chip 1 is subjected to a chip test. This is a process corresponding to step ST307 illustrated in FIG. Before the dicing process, a wafer test for measuring the characteristics of the semiconductor element chip 1 in a wafer state may be performed.

  In the semiconductor device chip illustrated in FIG. 2, for example, when the formation of the well layer 13 is defective and no pn junction is formed, the build-in voltage of the SiC pn junction is applied to the drift layer 12 of the defective chip. Therefore, a voltage higher than that of the non-defective semiconductor element chip 1, that is, a non-defective chip, is applied to the drift layer 12 by 2.5V.

  When energization screening is performed by energizing in parallel, a larger current flows in the defective chip 1A than in a good chip. Therefore, the temperature of the defective chip becomes higher than the temperature of the good chip.

  When the drift layer 12 is thick and has a high resistance, the difference between the current value flowing through the defective chip and the current value flowing through the non-defective chip becomes small. Heat generation does not lead to good-quality chips being thermally degraded.

  However, when the drift layer 12 is thin and has a low resistance, when the current flowing during the energization screening is low, or when the cooling capacity of the cooling stage 32 is low, the heat generation temperature of the defective chip increases. Therefore, the temperature of the adjacent good chip may rise to a temperature at which the element is deteriorated.

  In the present embodiment, an insulating film 42 is selectively formed on the upper surface of the source electrode 19 of the defective chip 1A before the energization screening. Then, no current flows through the defective chip 1A, so that adjacent non-defective chips are not thermally degraded. Therefore, the yield can be improved and the chip cost can be reduced.

<Fourth embodiment>
An energization inspection device and an energization inspection method according to the present embodiment will be described. In the following, the same components as those described in the above-described embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

<About the configuration of the conduction inspection device>
FIG. 12 is a cross-sectional view schematically illustrating a configuration for realizing the conduction inspection device according to the present embodiment. In FIG. 12, in order to facilitate understanding of the configuration, some components are arranged with a gap between the components. However, in practice, the respective configurations are arranged in contact with each other.

  As illustrated in FIG. 12, the conduction inspection apparatus includes a semiconductor wafer 51, a conductive buffer 34 disposed on a lower surface of the semiconductor wafer 51, and a cooling stage 32 disposed on a lower surface of the conductive buffer 34. Is provided.

  Semiconductor wafer 51 is a silicon carbide semiconductor substrate. A plurality of semiconductor element chips 1 are formed on the upper surface of one semiconductor wafer 51.

  In addition, the conduction inspection device includes a conductive buffer 54 disposed on the upper surface of the semiconductor wafer 51 and a semiconductor wafer 52 disposed on the upper surface of the conductive buffer 54.

  The conductive cushioning material 54 covers a region of the semiconductor device chip 1 on the upper surface of the semiconductor wafer 51, including the current conducting portion 2 and the gate pad portion 3.

  The conductive buffer 54 includes, for example, a thin metal film such as an aluminum foil, a carbon fiber material, or a conductive buffer sheet containing carbon particles.

  Semiconductor wafer 52 is a silicon carbide semiconductor substrate. On the upper surface of one semiconductor wafer 52, a plurality of semiconductor element chips 1 are formed.

  In addition, the conduction inspection device includes a conductive buffer 55 disposed on the upper surface of the semiconductor wafer 52 and a semiconductor wafer 53 disposed on the upper surface of the conductive buffer 55.

  The conductive buffer material 55 covers a region of the semiconductor device chip 1 on the upper surface of the semiconductor wafer 52, the region including the current conducting portion 2 and the gate pad portion 3.

  The conductive buffer material 55 includes, for example, a metal thin film such as an aluminum foil, a carbon fiber material, or a conductive buffer sheet containing carbon particles.

  Semiconductor wafer 53 is a silicon carbide semiconductor substrate. Further, a plurality of semiconductor element chips 1 are formed on the upper surface of one semiconductor wafer 53.

  Further, the conduction inspection device includes a conductive buffer 35 disposed on the upper surface of the semiconductor wafer 53 and a conduction electrode 33 disposed on the upper surface of the conductive buffer 35.

  In the structure as described above, by applying a pressure between the cooling stage 32 and the energizing electrode 33, that is, by applying a pressure in the direction of the arrow illustrated in FIG. The semiconductor wafer 53 is pressed against the cooling stage 32. By doing so, the temperature of the cooling stage 32 is adjusted while lowering the thermal resistance between the semiconductor wafer 51, the semiconductor wafer 52, and the semiconductor wafer 53 and the cooling stage 32, so that the semiconductor wafer 51, the semiconductor wafer 52 , And the temperature of the semiconductor wafer 53 is controlled.

  The forward voltage at the time of energization screening is the sum of 2.5 V, which is the build-in voltage of the SiC semiconductor, and the voltage generated by the resistance of the drift layer 12, and is at most about 5V.

  Therefore, as illustrated in FIG. 12, when three semiconductor wafers are stacked and connected in series, the forward voltage is about 15V. With such a voltage value, it is possible to energize a plurality of semiconductor wafers using one constant current power supply.

  As illustrated in FIG. 12, by stacking a plurality of semiconductor wafers in series, a large number of semiconductor element chips can be energized and screened simultaneously. Therefore, the energization screening time per chip can be reduced, and the cost can be reduced.

  In the present embodiment, a structure in which three semiconductor wafers are stacked is exemplified. However, if the capacity of the power supply permits, a structure in which semiconductor wafers are further stacked can be realized.

<Fifth embodiment>
An energization inspection device and an energization inspection method according to the present embodiment will be described. In the following, the same components as those described in the above-described embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

<About the configuration of the conduction inspection device>
FIG. 13 is a cross-sectional view schematically illustrating a configuration for realizing the conduction inspection device according to the present embodiment. In FIG. 13, some components are arranged with a gap between the components to facilitate understanding of the configurations. However, in practice, the respective configurations are arranged in contact with each other.

  As illustrated in FIG. 13, the conduction inspection apparatus includes a semiconductor wafer 51, a conductive buffer 34 disposed on the lower surface of the semiconductor wafer 51, and a cooling stage 61 disposed on the lower surface of the conductive buffer 34. Is provided.

  The cooling stage 61 is electrically and thermally connected to the back surface drain electrode of the semiconductor wafer 51. The cooling stage 61 functions as an energizing mechanism for energizing the semiconductor wafer 51, the semiconductor wafer 52, and the semiconductor wafer 53. The cooling stage 61 controls the temperatures of the semiconductor wafer 51, the semiconductor wafer 52, and the semiconductor wafer 53.

  In addition, the conduction inspection device includes a conductive buffer 54 disposed on the upper surface of the semiconductor wafer 51 and a semiconductor wafer 52 disposed on the upper surface of the conductive buffer 54.

  In addition, the conduction inspection device includes a conductive buffer 55 disposed on the upper surface of the semiconductor wafer 52 and a semiconductor wafer 53 disposed on the upper surface of the conductive buffer 55.

  Further, the conduction inspection device includes a conductive buffer 35 disposed on the upper surface of the semiconductor wafer 53 and a conduction electrode 62 disposed on the upper surface of the conductive buffer 35.

  The current-carrying electrodes 62 are electrically connected in parallel to the surface electrodes of the plurality of semiconductor element chips 1 formed on the upper surface of the semiconductor wafer 53.

  Further, the power supply inspection device includes a liquid 63 for immersing the above structure and a container 64 for containing the liquid 63. The liquid 63 is an electrically inert liquid.

  Further, the power supply inspection device includes a heat exchanger 65 and a pipe 66 for circulating the liquid 63 between the container 64 and the heat exchanger 65.

  In the structure as described above, by applying a pressure between the cooling stage 61 and the energizing electrode 62, that is, by applying a pressure in a direction of an arrow illustrated in FIG. The semiconductor wafer 53 is pressed against the cooling stage 61.

  The energizing electrode 62 and the semiconductor wafer 51, the semiconductor wafer 52, and the semiconductor wafer 53 are placed in a liquid 63. Then, heat generated at the time of energization propagates to the liquid 63 to be radiated.

  The temperature of the liquid 63 is controlled by the heat exchanger 65. The semiconductor wafer 51, the semiconductor wafer 52, and the semiconductor wafer 53 are cooled to a predetermined temperature by circulating the liquid 63 whose temperature is controlled.

  The liquid 63 is, for example, a fluorine-based inert liquid or a hydrocarbon-based inert liquid. The fluorine-based inert liquid can be used up to a temperature of about 230 ° C. The hydrocarbon-based inert liquid can be used up to a temperature of about 280 ° C.

  In the case where the energization screening is performed in a state where the laminated metal film of nickel and gold is provided as the backside drain electrode, it is desirable that the temperature at the time of energization does not exceed 230 ° C. in order to prevent thermal deterioration of the backside drain electrode.

  Therefore, the semiconductor wafer 51, the semiconductor wafer 52, and the semiconductor wafer 53 can be cooled using the liquid 63 which is a fluorine-based inert liquid or a hydrocarbon-based inert liquid whose temperature is controlled.

  In the case where the energization screening is performed before the formation of the back surface drain electrode, the energization screening can be performed at a high temperature exceeding 300 ° C., for example, by using a silicon oil-based inert liquid as the inert liquid. Therefore, the energization time can be shortened.

  In the case where cooling is performed using the cooling stage 32 in the above-described embodiment, unless the thermal contact with the cooling stage 32 is ensured, a temperature distribution having a different temperature in the semiconductor wafer surface occurs or the semiconductor wafers are stacked. In such a case, the temperature may differ between semiconductor wafers.

  By directly cooling the semiconductor wafer using the liquid 63, the temperature distribution in the semiconductor wafer surface or between the semiconductor wafers can be reduced. Therefore, it is possible to shorten the time of the energization screening and reduce the cost.

  Further, since the semiconductor wafer is directly cooled using the liquid 63, the temperature of the semiconductor wafer depends on the thermal resistance of the conductive buffer 34, the thermal resistance of the conductive buffer 35, the thermal resistance of the conductive buffer 54, and It does not depend on the thermal resistance of the conductive buffer material 55.

  Therefore, the conductive buffering material only needs to be electrically connectable, and the choice of materials increases. Therefore, the cost can be reduced by using a material that can be used a plurality of times and has a low exchange frequency.

  In the present embodiment, a structure in which three semiconductor wafers are stacked is exemplified. However, if the capacity of the power supply permits, a structure in which semiconductor wafers are further stacked can be realized.

<Sixth Embodiment>
An energization inspection device and an energization inspection method according to the present embodiment will be described. In the following, the same components as those described in the above-described embodiments are denoted by the same reference numerals, and detailed descriptions thereof will be omitted as appropriate.

<About the configuration of the conduction inspection device>
FIG. 14 is a cross-sectional view schematically illustrating a configuration for realizing the conduction inspection apparatus according to the present embodiment. In FIG. 14, in order to facilitate understanding of the configuration, some components are arranged with a gap between the components. However, in practice, the respective configurations are arranged in contact with each other.

  As illustrated in FIG. 14, the conduction test apparatus includes a semiconductor wafer 31, a conductive buffer 34 disposed on the lower surface of the semiconductor wafer 31, and a cooling stage 32 disposed on the lower surface of the conductive buffer 34. Is provided.

  Further, the conduction inspection device includes a conductive buffer 74 partially disposed on the upper surface of the semiconductor wafer 31 and a conductive buffer 75 partially disposed on the upper surface of the semiconductor wafer 31.

  That is, the conduction inspection device includes a conductive buffer 74 provided over the source electrodes 19 of the plurality of semiconductor element chips 1 and a source electrode of the plurality of semiconductor element chips 1 in a region where the conductive buffer 74 is not provided. And a conductive cushioning material 75 provided over the 19.

  The conductive buffer material 74 and the conductive buffer material 75 cover a region of the semiconductor device chip 1 on the upper surface of the semiconductor wafer 31, the region including the current conducting portion 2 and the gate pad portion 3.

  The conductive buffer 74 and the conductive buffer 75 include, for example, a metal thin film such as an aluminum foil, a carbon fiber material, or a conductive buffer sheet containing carbon particles.

  In addition, the conduction inspection device includes an upper surface of the conductive buffer 74 and a conduction electrode 33 </ b> A arranged over the upper surface of the conductive buffer 75.

  The conducting electrodes 33A are electrically connected in parallel to the surface electrodes of the plurality of semiconductor element chips 1 formed on the upper surface of the semiconductor wafer 31. The current-carrying electrode 33A includes a conductive portion 71, a conductive portion 72, and an insulating portion 73 interposed between the conductive portions 71 and 72 in plan view.

  The conductive unit 71 is connected to a power supply 77. The conductive portion 71 is provided at a position sandwiching the conductive buffer 74 between the conductive portion 71 and the source electrode 19 of the semiconductor element chip 1.

  Further, the conductive section 72 is connected to a power supply 76. The conductive portion 72 is provided at a position where the conductive buffer 75 is sandwiched between the conductive portion 72 and the source electrode 19 of the semiconductor element chip 1.

  Here, the conductive portion 71 and the conductive portion 72 are electrically separated from each other through the insulating portion 73. However, the conductive portion 71 and the conductive portion 72 are spatially separated from each other. The conductive portion 71 and the conductive portion 72 may be electrically separated.

  To shorten the energization screening time, it is effective to increase the energization current. However, when the power supply capacity is exceeded, as illustrated in the present embodiment, the energizing electrode can be divided into a plurality of regions and energized using a plurality of power supplies.

  According to the present embodiment, power can be supplied using the power supply 77 and the power supply 76, so that the supplied current can be increased. Therefore, the energization time can be shortened, and the cost can be reduced.

  In the present embodiment, the current-carrying electrode is divided into two. However, the current-carrying electrode may be divided into three, four, or more. It may be the case of division.

<About the effect produced by the embodiment described above>
Next, effects produced by the embodiment described above will be exemplified. In the following, the effect is described based on the specific configuration exemplified in the embodiment described above, but other specific examples exemplified in the specification of the present application are provided as long as the same effect is generated. It may be replaced with a general configuration.

  Further, the replacement may be performed over a plurality of embodiments. That is, a case where the same effects are produced by combining the respective configurations exemplified in the different embodiments may be adopted.

  According to the embodiment described above, the conduction inspection device performs the conduction inspection of the plurality of semiconductor element chips 1. Each semiconductor element chip 1 is provided on the upper surface of one semiconductor wafer 31. Each semiconductor element chip 1 includes a pn junction 100 and a surface electrode connected to a first end of the pn junction 100. Here, the source electrode 19 corresponds to the surface electrode. The current-carrying inspection device includes a conductive first buffer, a conductive second buffer, a first current-carrying mechanism, and a second current-carrying mechanism. Here, the conductive buffer material 35 corresponds to the first buffer material. The conductive cushioning material 34 corresponds to the second cushioning material. The energizing electrode 33 corresponds to the first energizing mechanism. Further, the cooling stage 32 corresponds to the second energizing mechanism. The conductive buffer material 35 is provided across the plurality of source electrodes 19. The conductive buffer material 34 contacts a back electrode provided on the lower surface of the semiconductor wafer 31. Here, the back surface drain electrode 21 and the back surface drain electrode 22 correspond to the back surface electrode. The current-carrying electrode 33 is provided at a position sandwiching the conductive buffer material 35 with the source electrode 19. The cooling stage 32 is provided at a position sandwiching the conductive buffer material 34 between the cooling stage 32 and the back surface drain electrode 22. Further, the back surface drain electrode 21 and the back surface drain electrode 22 of the semiconductor wafer 31 are connected to a second end of the pn junction 100 opposite to the first end. Then, the current-carrying electrode 33 and the cooling stage 32 allow a current to flow in the forward direction of the pn junction 100.

  According to such a configuration, since a plurality of semiconductor element chips 1 provided on the upper surface of the semiconductor wafer 31 can be energized in parallel, even when screening the plurality of semiconductor element chips 1, No need to increase time. That is, the energizing time converted per chip can be shortened. Further, by providing the conductive buffer material 34 and the conductive buffer material 35, even when pressure is applied between the cooling stage 32 and the energized electrode 33 to reduce the electric resistance, the semiconductor element chip 1 can be prevented from being damaged.

  Note that other configurations exemplified in the specification of the present application other than these configurations can be omitted as appropriate. That is, the effects described above can be produced only by these configurations.

  However, when at least one of the other configurations exemplified in the specification of the present application is appropriately added to the configuration described above, that is, in the specification of the present application which is not described as the configuration described above. Even when another configuration is added to the configuration described above, the effects described above can be similarly produced.

  Further, according to the embodiment described above, the cooling stage 32 can control the temperature of the semiconductor element chip 1. According to such a configuration, it is possible to control the temperature of the semiconductor element chip 1 during energization.

  Further, according to the embodiment described above, the conduction inspection apparatus includes the insulating liquid 63 for immersing at least the plurality of semiconductor element chips 1 and the container 64 for containing the liquid 63. According to such a configuration, by directly cooling the semiconductor wafer using the liquid 63, the temperature distribution within the semiconductor wafer or between the semiconductor wafers can be reduced. Therefore, it is possible to shorten the time of the energization screening and reduce the cost. Further, since the semiconductor wafer is directly cooled using the liquid 63, the temperature of the semiconductor wafer depends on the thermal resistance of the conductive buffer 34, the thermal resistance of the conductive buffer 35, the thermal resistance of the conductive buffer 54, and It does not depend on the thermal resistance of the conductive buffer material 55. Therefore, the conductive buffering material only needs to be electrically connectable, and the choice of materials increases. Therefore, the cost can be reduced by using a material that can be used a plurality of times and has a low exchange frequency.

  Further, according to the embodiment described above, the conduction inspection device includes a plurality of semiconductor wafers 51, a plurality of semiconductor wafers 52 provided to overlap each other in a plan view, and a plurality of semiconductor elements provided on the upper surface of the semiconductor wafer 53. An energization test of the chip 1 is performed. The conduction test device includes at least one conductive third cushioning material. Here, the conductive buffer 54 and the conductive buffer 55 correspond to a third buffer. The conductive buffer material 54 is provided between the adjacent semiconductor wafers 51 and 52. The conductive buffer material 55 is provided between the adjacent semiconductor wafers 52 and 53. The conductive buffer material 54 is provided across the source electrode 19 of the semiconductor element chip 1 on the semiconductor wafer 51 that is the first semiconductor wafer of the adjacent semiconductor wafers 51 and 52. In addition, the conductive buffer material 54 contacts the back surface drain electrode 22 of the semiconductor wafer 52 that is the second semiconductor wafer adjacent to the semiconductor wafer 51 among the semiconductor wafers 51, 52, and 53. . The conductive buffer material 55 is provided across the source electrode 19 of the semiconductor element chip 1 in the semiconductor wafer 52 that is the first semiconductor wafer among the adjacent semiconductor wafers 52 and 53. In addition, the conductive buffer material 55 contacts the back surface drain electrode 22 of the semiconductor wafer 53, which is the second semiconductor wafer adjacent to the semiconductor wafer 52, of the semiconductor wafer 51, the semiconductor wafer 52, and the semiconductor wafer 53. . According to such a configuration, by laminating a plurality of semiconductor wafers in series, a large number of semiconductor element chips can be energized and screened simultaneously. Therefore, the energization screening time per chip can be reduced, and the cost can be reduced.

  Further, according to the embodiment described above, the first cushioning member includes the conductive fourth cushioning member and the conductive fifth cushioning member. Here, the conductive cushioning material 74 corresponds to the fourth cushioning material. The conductive cushioning material 75 corresponds to the fifth cushioning material. The conductive buffer 74 is provided over the plurality of source electrodes 19. The conductive buffer material 75 is provided over a plurality of source electrodes 19 where the conductive buffer material 74 is not provided. The first energizing mechanism includes a third energizing mechanism and a fourth energizing mechanism. Here, the conductive portion 71 corresponds to the third energizing mechanism. The conductive section 72 corresponds to the fourth energizing mechanism. The conductive portion 71 is provided at a position sandwiching the conductive buffer 74 between the conductive portion 71 and the source electrode 19. The conductive portion 72 is provided at a position sandwiching the conductive buffer 75 between the conductive portion 72 and the source electrode 19. According to such a configuration, power can be supplied using the power supply 77 and the power supply 76, and thus the supplied current can be increased. Therefore, the energization time can be shortened, and the cost can be reduced.

  Further, according to the embodiment described above, the conduction test apparatus performs a conduction test on a plurality of semiconductor element chips 1 provided on the upper surface of semiconductor wafer 31 containing silicon carbide. According to such a configuration, since a plurality of semiconductor element chips 1 provided on the upper surface of one semiconductor wafer 31 can be energized in parallel, even when a plurality of semiconductor element chips 1 are screened. It is not necessary to increase the energizing time.

  Further, according to the embodiment described above, the energization inspection method is an energization inspection method for performing an energization inspection of a plurality of semiconductor element chips 1. Each semiconductor element chip 1 is provided on the upper surface of one semiconductor wafer 31. Each semiconductor element chip 1 has a pn junction 100. Each semiconductor element chip 1 includes a source electrode 19 connected to the first end of the pn junction 100. Then, in the energization inspection method, a conductive conductive buffer material 35 that straddles the plurality of source electrodes 19 is provided. Then, a conductive conductive buffer material 34 is provided to straddle a second end of the plurality of semiconductor element chips 1 which is an end opposite to the first end of the pn junction 100. Then, a current-carrying electrode 33 is provided at a position sandwiching the conductive buffer material 35 with the source electrode 19. Then, the cooling stage 32 is provided at a position sandwiching the conductive buffer material 34 with the second end of the pn junction 100. Then, a current is caused to flow in the forward direction of the pn junction 100 using the current-carrying electrode 33 and the cooling stage 32. Then, after a current flows in the forward direction of the pn junction 100, at least the conductive buffer material 34 and the cooling stage 32 are removed, and the back surface drain connected to the second end of the pn junction 100 is removed. An electrode 21 and a back surface drain electrode 22 are provided.

  According to such a configuration, since a plurality of semiconductor element chips 1 provided on the upper surface of the semiconductor wafer 31 can be energized in parallel, even when screening the plurality of semiconductor element chips 1, No need to increase time. In addition, since the back surface drain electrode that is thermally degraded during the energization screening is formed after the energization screening, the temperature during the energization can be increased. The growth rate of stacking faults increases as the temperature during energization increases. Therefore, by raising the temperature at the time of energization, the time until the growth of stacking faults is completely saturated can be shortened. Therefore, inspection costs can be reduced.

  Note that other configurations exemplified in the specification of the present application other than these configurations can be omitted as appropriate. That is, the effects described above can be produced only by these configurations.

  However, when at least one of the other configurations exemplified in the specification of the present application is appropriately added to the configuration described above, that is, in the specification of the present application which is not described as the configuration described above. Even when another configuration is added to the configuration described above, the effects described above can be similarly produced.

  Also, the order in which the respective processes are performed can be changed unless otherwise specified.

<Modifications of the above-described embodiment>
In the embodiments described above, the materials, materials, dimensions, shapes, relative arrangement relations, or implementation conditions of the respective components may be described, but these are examples in all aspects. Therefore, the present invention is not limited to those described in the specification of the present application.

  Accordingly, innumerable modifications that are not illustrated are envisioned within the scope of the technology disclosed herein. For example, when at least one component is modified, added, or omitted, or when at least one component in at least one embodiment is extracted and combined with components of another embodiment. Shall be included.

  Unless inconsistency arises, "one or more" of the components described as "one" provided in the above-described embodiment may be provided.

  Furthermore, each component in the embodiment described above is a conceptual unit, and one component includes a plurality of structures within the scope of the technology disclosed in this specification. And a case where one component corresponds to a part of a structure, and a case where a plurality of components are provided in one structure.

  In addition, each component in the above-described embodiment includes a structure having another structure or shape as long as the same function is exhibited.

  In addition, the description in the specification of the present application is referred to for all purposes related to the present technology, and none of them is admitted to be prior art.

  In addition, in the embodiments described above, when a material name or the like is described without particular designation, unless there is a contradiction, the material includes other additives, such as an alloy. Shall be included.

  Further, in the above-described embodiment, the semiconductor substrate is of the n-type, but the semiconductor substrate may be of the p-type. In other words, in the above-described embodiments, the MOSFET has been described as an example of the silicon carbide semiconductor device. However, the example of the silicon carbide semiconductor device is an insulated gate bipolar transistor (i.e., IGBT) or a shot transistor. A key barrier diode (Schottky barrier diode, ie, SBD) or a pn diode can be assumed.

  When the example of the silicon carbide semiconductor device is an IGBT, it is assumed that the source electrode corresponds to the emitter electrode and the drain electrode corresponds to the collector electrode. In the case where the example of the silicon carbide semiconductor device is an IGBT, a layer having a conductivity type opposite to that of the drift layer is located on the lower surface of the drift layer. May be a newly formed layer, or a semiconductor substrate on which a drift layer is formed as in the above-described embodiment.

  Further, in the embodiment described above, the planar type MOSFET has been described. However, a case where the present invention is applied to a trench type MOSFET in which a trench is formed on an upper surface of a drift layer can be assumed. . In the case of a trench type MOSFET, a trench, that is, a trench is formed on the upper surface of the drift layer, and a gate electrode is buried via a gate insulating film on the upper surface of the drift layer, that is, on the bottom of the trench.

  REFERENCE SIGNS LIST 1 semiconductor element chip, 1A defective chip, 2 current carrying part, 3 gate pad part, 4 terminal part, 5 defect, 6,7 stacking fault, 8 forward current, 11 silicon carbide semiconductor substrate, 12 drift layer, 13 well layer , 14 source layer, 15 contact injection layer, 16 gate electrode, 17 gate insulating film, 18 interlayer insulating film, 19 source electrode, 20 back contact electrode, 21, 22, back drain electrode, 31, 51, 52, 53 semiconductor wafer, 32, 61 cooling stage, 33, 33A, 62 current-carrying electrode, 34, 35, 54, 55, 74, 75 conductive buffer material, 41 protective film, 42 insulating film, 63 liquid, 64 container, 65 heat exchanger, 66 piping , 71, 72 conductive part, 73 insulating part, 76, 77 power supply, 100 pn junction.

Claims (6)

A semiconductor wafer made of a silicon carbide substrate of the first conductivity type, a drift layer of the first conductivity type formed on the upper surface of the semiconductor wafer, and a well layer of the second conductivity type formed on the surface of the drift layer; And a first conductivity type source layer formed on a surface layer of the well layer.
Each of the semiconductor element chips,
A pn junction comprising the drift layer and the well layer;
A surface electrode connected to a first end of the pn junction;
The energization inspection device,
A first conductive material provided across the plurality of surface electrodes,
A conductive second buffer material that contacts a back electrode provided on the lower surface of the semiconductor wafer;
A first energizing mechanism provided at a position sandwiching the first cushioning material between the first electrode and the surface electrode;
A second energizing mechanism provided at a position sandwiching the second buffer between the back electrode and
The back surface electrode of the semiconductor wafer is connected to a second end of the pn junction opposite to the first end;
The first energizing mechanism and the second energizing mechanism flow a current in a forward direction of the pn junction until the growth of stacking faults of the semiconductor element chip is saturated .
Energization inspection device. The second energization mechanism is capable of controlling the temperature of the semiconductor element chip,
The current inspection device according to claim 1. The energization inspection device further includes:
An insulating liquid for immersing at least a plurality of the semiconductor element chips,
A container for containing the liquid,
The current inspection device according to claim 2. It is a conduction inspection device that performs conduction inspection of a plurality of semiconductor element chips,
Each of the semiconductor element chips,
Provided on the upper surface of one semiconductor wafer,
a pn junction,
A surface electrode connected to a first end of the pn junction;
The energization inspection device,
A first conductive material provided across the plurality of surface electrodes,
A conductive second buffer material that contacts a back electrode provided on the lower surface of the semiconductor wafer;
A first energizing mechanism provided at a position sandwiching the first cushioning material between the first electrode and the surface electrode;
A second energizing mechanism provided at a position sandwiching the second buffer between the back electrode and
The back surface electrode of the semiconductor wafer is connected to a second end of the pn junction opposite to the first end;
The first energizing mechanism and the second energizing mechanism flow a current in a forward direction of the pn junction,
An electrical current inspection apparatus that performs electrical inspection of a plurality of the semiconductor element chips provided on an upper surface of the plurality of semiconductor wafers provided to be overlapped in a plan view,
The energization inspection device further includes:
The semiconductor device according to claim 1, further comprising at least one conductive third cushioning material provided between the adjacent semiconductor wafers,
The third cushioning material is provided across the surface electrode of the semiconductor element chip in the first semiconductor wafer of the adjacent semiconductor wafers, and the first semiconductor of the semiconductor wafer is provided. Contact the back electrode of the second semiconductor wafer adjacent to the wafer;
Energization inspection device. It is a conduction inspection device that performs conduction inspection of a plurality of semiconductor element chips,
Each of the semiconductor element chips,
Provided on the upper surface of one semiconductor wafer,
a pn junction,
A surface electrode connected to a first end of the pn junction;
The energization inspection device,
A first conductive material provided across the plurality of surface electrodes,
A conductive second buffer material that contacts a back electrode provided on the lower surface of the semiconductor wafer;
A first energizing mechanism provided at a position sandwiching the first cushioning material between the first electrode and the surface electrode;
A second energizing mechanism provided at a position sandwiching the second buffer between the back electrode and
The back surface electrode of the semiconductor wafer is connected to a second end of the pn junction opposite to the first end;
The first energizing mechanism and the second energizing mechanism flow a current in a forward direction of the pn junction,
The first cushioning material is
A conductive fourth cushioning material provided over a plurality of the surface electrodes;
A conductive fifth cushioning member provided across the plurality of surface electrodes not provided with the fourth cushioning member,
The first energizing mechanism includes:
A third energizing mechanism provided at a position sandwiching the fourth cushioning material between the fourth electrode and the surface electrode;
A fourth energizing mechanism provided at a position sandwiching the fifth cushioning material with the surface electrode.
Energization inspection device. A conduction test method for conducting a conduction test on a plurality of semiconductor element chips,
Each of the semiconductor element chips is provided on an upper surface of one semiconductor wafer and has a pn junction,
Each of the semiconductor element chips includes a surface electrode connected to a first end of the pn junction,
Providing a conductive first buffer material over a plurality of the surface electrodes,
A conductive second buffer material is provided across a second end of the plurality of semiconductor element chips, the second end being an end opposite to the first end of the pn junction;
A first energizing mechanism is provided at a position sandwiching the first cushioning material between the first electrode and the surface electrode,
A second energizing mechanism is provided at a position sandwiching the second cushioning material between the pn junction and the second end,
Using the first energizing mechanism and the second energizing mechanism, flow a current in a forward direction of the pn junction,
After flowing a current in the forward direction of the pn junction, at least the second buffer and the second energizing mechanism are removed, and the pn junction is connected to the second end of the pn junction. Providing a back electrode,
Energization inspection method.

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