JP7305979B2 - Semiconductor device manufacturing method - Google Patents

Description

The present invention relates to a method of manufacturing a semiconductor device.

Conventionally, silicon (Si) has been used as a constituent material of power semiconductor devices that control high voltages and large currents. Power semiconductor devices include bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors). field effect transistor), etc., and these are used according to the application.

For example, bipolar transistors and IGBTs have higher current densities than MOSFETs and can handle large currents, but cannot be switched at high speed. Specifically, bipolar transistors are limited to use at a switching frequency of about several kHz, and IGBTs are limited to use at a switching frequency of about several tens of kHz. On the other hand, a power MOSFET has a lower current density than a bipolar transistor or an IGBT, making it difficult to increase the current, but it is capable of high-speed switching operation up to several MHz.

Also, unlike an IGBT, a MOSFET can use a parasitic diode formed by a pn junction between a p-type base region and an n ^{− -type} drift region as a freewheeling diode for protecting the MOSFET. For this reason, when the MOSFET is used as an inverter device, it is not necessary to additionally connect an external freewheeling diode to the MOSFET, and attention has also been paid to the economic efficiency.

There is a strong demand in the market for power semiconductor devices that combine large current and high speed, and efforts have been made to improve IGBTs and power MOSFETs. For this reason, from the viewpoint of power semiconductor devices, semiconductor materials that can replace silicon are being investigated. Silicon carbide is a semiconductor material that can be used to fabricate (manufacture) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics. (SiC) is attracting attention.

Silicon carbide is a chemically very stable semiconductor material, has a wide bandgap of 3 eV, and can be used as a semiconductor very stably even at high temperatures. In addition, since silicon carbide has a maximum electric field strength that is one order of magnitude higher than that of silicon, silicon carbide is expected as a semiconductor material capable of sufficiently reducing the on-resistance. Silicon carbide also has such a feature that it has a wider bandgap than other silicon (hereinafter referred to as a wide bandgap semiconductor).

In addition, as the current increases, compared to the planar gate structure in which the channel is formed along the front surface of the semiconductor substrate, the channel ( A trench gate structure in which an inversion layer is formed is advantageous in terms of cost. The reason for this is that the trench gate structure can increase the density of unit cells (components of a device) per unit area, so that the current density per unit area can be increased.

As the current density of the device increases, the rate of temperature rise corresponding to the volume occupied by the unit cell also increases. Furthermore, in consideration of reliability, the same semiconductor substrate as the vertical MOSFET, which is the main semiconductor element, is used as a circuit unit for protecting and controlling the main semiconductor element. It is necessary to have a highly functional structure in which functional units are arranged.

As a conventional semiconductor device having a current sensing portion, there is a silicon carbide device in which the portion of the gate insulating film covering the base region of the current sensing portion is thicker than the portion covering the base region of the main semiconductor element. It has been proposed (for example, see Patent Document 1 below). In the following patent document 1, the gate insulation of the current sensing section is used to reduce the electrostatic breakdown resistance that is reduced when the on-resistance is reduced by making the gate insulation film thinner than when silicon is used as the semiconductor material. It is improved by making the film thicker.

WO2017/002255

However, the film quality of the gate insulating film formed on the surface of the semiconductor substrate made of silicon carbide is weak against electric charges, and the surface area of the active region (hereinafter referred to as the active area) occupying the semiconductor substrate is smaller than that of the main semiconductor element. In some parts, leakage current in the gate insulating film increases due to plasma and static electricity generated during chemical vapor deposition (CVD) and sputtering during the manufacturing process (wafer process). As a result, the current sensing portion has a lower ESD (Electro-Static Discharge) tolerance than the main semiconductor element, and is prone to dielectric breakdown.

In order to solve the above-described problems associated with the prior art, the present invention provides a semiconductor device in which dielectric breakdown is unlikely to occur in the current sensing portion when manufacturing a semiconductor device having a current sensing portion on the same semiconductor substrate as the main semiconductor element. The purpose is to provide a method.

In order to solve the above-described problems and achieve the object of the present invention, a method of manufacturing a semiconductor device according to the present invention provides a semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon, in which first and second insulated gate field effect transistors are formed. A method of manufacturing a semiconductor device having a transistor has the following features. The first and second insulated gate field effect transistors have first and second front surface electrodes and first and second rear surface electrodes, respectively, on both surfaces of the semiconductor substrate. A first step of forming a first insulated gate structure of the first insulated gate field effect transistor on the front surface side of the semiconductor substrate is performed. The second insulated gate field effect transistor occupies a smaller surface area than the first insulated gate field effect transistor on the semiconductor substrate.

A second insulated gate structure of the second insulated gate field effect transistor is formed on the front surface side of the semiconductor substrate in the same structure as the first insulated gate structure but at a position separated from the first insulated gate structure. A second step of forming is performed. A third step of forming the first front surface electrode and the second front surface electrode is performed. A fourth step of forming a gate pad to which the gate electrode forming the first insulating gate structure and the gate electrode forming the second insulating gate structure are electrically connected is performed. After the third step and the fourth step, a fifth step of performing a test for evaluating predetermined characteristics is performed.

After the second step and before the fifth step, a shorting step of forming a shorting electrode for shorting the second insulated gate field effect transistor to the first front surface electrode is performed. After the short-circuiting step, all the predetermined steps up to and including the fifth step are performed with the short-circuit electrode short-circuiting the first front surface electrode and the second insulated gate field effect transistor. conduct. After the predetermined step and before the fifth step, the short-circuit electrode is cut to electrically disconnect the first front surface electrode and the second insulated gate field effect transistor. Further, in the method of manufacturing a semiconductor device according to the present invention, in the invention described above, the short-circuiting step is performed in at least a part of the processing of the third step.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, the step of forming a metal layer on the front surface of the semiconductor substrate is performed in the third step. Then, a step of selectively removing the metal layer to leave a part of the metal layer as the first front surface electrode and the second front surface electrode is performed. In the short-circuiting step, part of the metal layer is left as the short-circuiting electrode in the third step.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, in the third step, the metal layer having a laminated structure in which a plurality of metal films are laminated is formed. In the short-circuiting step, the thinnest metal film among the plurality of metal films is left as the short-circuit electrode.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, in the shorting step, the second front surface electrode is short-circuited to the first front surface electrode by the shorting electrode. Characterized by

Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, the short-circuit electrode is formed between the first front surface electrode and the second front surface electrode in the short-circuiting step. It is characterized by

Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, in the shorting step, the gate electrode of the second insulated gate field effect transistor is connected to the first front surface electrode by the shorting electrode. It is characterized by being short-circuited.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, the short-circuiting step includes forming the short-circuiting electrode between the first front surface electrode and the gate pad, so that the short-circuiting The gate electrode of the second insulated gate field effect transistor and the first front surface electrode are short-circuited via the electrode and the gate pad.

Further, in the method of manufacturing a semiconductor device according to the present invention, in the invention described above, in the shorting step, the shorting electrode having a narrow width in part is formed. After the predetermined step and before the fifth step, the narrow portion of the short-circuit electrode is cut to electrically connect the first front surface electrode and the second insulated gate field effect transistor. It is characterized by separating into

Further, in the method of manufacturing a semiconductor device according to the present invention, in the above-described invention, after the fifth step, the second insulated gate field effect transistor is short-circuited to the first front surface electrode. It is characterized by forming an electrode.

According to the method of manufacturing a semiconductor device according to the present invention, when manufacturing a semiconductor device having a current sensing portion on the same semiconductor substrate as a main semiconductor element, it is possible to increase the ESD tolerance of the current sensing portion during the manufacturing process. Therefore, it is possible to provide a semiconductor device in which dielectric breakdown is unlikely to occur in the current sensing section.

1 is a plan view showing an example of the layout of a semiconductor wafer on which the semiconductor device according to the first embodiment is fabricated (manufactured) viewed from the front side; FIG. 1 is a plan view showing an example of the layout of the semiconductor device according to the first embodiment when viewed from the front surface side of the semiconductor chip; FIG. FIG. 3 is a cross-sectional view showing a cross-sectional structure taken along cutting lines X1-X2, X2-X3, and Y1-Y2 in FIG. 2; 2 is a circuit diagram showing an equivalent circuit of the semiconductor device 20 according to the first embodiment; FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 2 is a plan view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 3 is a cross-sectional view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. FIG. 7 is a cross-sectional view showing another example of the state in the middle of manufacturing the semiconductor device according to the first embodiment; FIG. 12 is a plan view showing a state in the middle of manufacturing the semiconductor device according to the second embodiment; FIG. 11 is a plan view showing a state in the middle of manufacturing a semiconductor device according to a third embodiment; FIG. 11 is a plan view showing a state in the middle of manufacturing a semiconductor device according to a fourth embodiment;

Preferred embodiments of the method for manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p mean that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached, respectively. In the following description of the embodiments and accompanying drawings, the same configurations are denoted by the same reference numerals, and overlapping descriptions are omitted. In this specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after it, and adding "-" before the index indicates a negative index.

(Embodiment 1)
The semiconductor device according to the first embodiment is configured using a semiconductor having a wider bandgap than silicon (Si) (wide bandgap semiconductor) as a semiconductor material. The structure of the semiconductor device according to the first embodiment will be described using, for example, silicon carbide (SiC) as a wide bandgap semiconductor. FIG. 1 is a plan view showing an example layout of a semiconductor wafer on which a semiconductor device according to a first embodiment is fabricated (manufactured), viewed from the front side. FIG. 2 is a plan view showing an example layout of the semiconductor device according to the first embodiment, viewed from the front surface side of the semiconductor chip.

FIG. 2 shows the layout of the electrode pads of each element arranged in a region (hereinafter referred to as a chip region) 10' which will become a semiconductor chip 70 after dicing (cutting) a semiconductor wafer 10 using silicon carbide as a semiconductor material. Here is an example. The chip regions 10 ′ have, for example, a substantially rectangular planar shape, and are arranged in a matrix on the semiconductor wafer 10 . The chip area 10' is surrounded by scribe lines 3 (FIG. 1). The scribe lines 3 are arranged in a grid on the semiconductor wafer 10 . The semiconductor device 20 according to the first embodiment shown in FIG. 2 is formed in all chip regions 10' of the semiconductor wafer 10, respectively.

A semiconductor device 20 according to the first embodiment shown in FIG. have a part. The main semiconductor element 11 is a vertical MOSFET in which a drift current flows in the vertical direction (the depth direction Z of the semiconductor chip 70) in the ON state, and is composed of a plurality of unit cells (element functional units) arranged adjacent to each other. and perform the main action. Circuit units for protecting and controlling the main semiconductor element 11 include, for example, high-performance units such as a current sensing unit 12, a temperature sensing unit 13, an overvoltage protection unit (not shown), and an arithmetic circuit unit (not shown). .

A main semiconductor element 11 is arranged in an effective region 1 a of the active region 1 . The effective region 1a of the active region 1 is a region through which the main current of the main semiconductor element 11 flows when the main semiconductor element 11 is turned on. The effective region 1a of the active region 1 has, for example, a substantially rectangular planar shape. A circuit section for protecting and controlling the main semiconductor element 11 is arranged in the invalid region 1b of the active region 1. FIG. The invalid region 1b of the active region 1 is a region that does not operate as the main semiconductor element 11 when the main semiconductor element 11 is turned on. The invalid region 1b of the active region 1 has, for example, a substantially rectangular planar shape and is adjacent to one side of the valid region 1a of the active region 1. As shown in FIG.

The ineffective area 1b of the active area 1 is arranged, for example, between the effective area 1a of the active area 1 and the edge termination area 2 surrounding the active area 1. FIG. The edge termination region 2 is a region between the active region 1 and the outer periphery of the chip region 10', and relaxes the electric field on the front surface side of the semiconductor chip 70 to maintain the withstand voltage. A breakdown voltage structure (not shown) such as a field limiting ring (FLR) or a junction termination extension (JTE) structure is arranged in the edge termination region 2 . The withstand voltage is the limit voltage at which the element does not malfunction or break down.

A source pad (electrode pad) 21a of the main semiconductor element 11 is arranged on the front surface of the semiconductor chip 70 in the effective region 1a of the active region 1 . In the invalid region 1b of the active region 1, on the front surface of the semiconductor chip 70, electrode pads of the circuit section for protecting and controlling the main semiconductor element 11 are arranged apart from each other. The main semiconductor element 11 has a larger current capability than other circuit sections. Therefore, the source pad 21a of the main semiconductor element 11 has, for example, a substantially rectangular planar shape covering substantially the entire effective region 1a of the active region 1. As shown in FIG. The planar shape of the source pad 21a is determined according to the required specifications such as the current capacity of the main semiconductor element 11, for example.

Electrode pads other than the source pad 21a are arranged in the invalid region 1b of the active region 1. FIG. The electrode pads other than the source pad 21a include the gate pad 21b of the main semiconductor element 11, the electrode pad (hereinafter referred to as OC pad) 22 of the current sensing section 12, and the electrode pad (hereinafter referred to as anode pad and cathode pad) of the temperature sensing section 13. pads) 23a and 23b, electrode pads of the overvoltage protection section (hereinafter referred to as OV pads: not shown), and electrode pads of the arithmetic circuit section (hereinafter referred to as arithmetic section pads: not shown). The electrode pads other than the source pad 21a have, for example, a substantially rectangular planar shape.

All electrode pads are spaced apart from each other. At least the OC pad 22 of the electrode pads other than the source pad 21a faces the source pad 21a. The source pad 21a and the OC pad 22 are arranged between the source pad 21a and the OC pad 22 during the manufacturing process of the semiconductor device 20 according to the first embodiment. They are spaced apart by the length w1 of the electrodes 111 (see FIGS. 11 and 12). A portion where the short-circuit electrode 111 is arranged between the source pad 21a and the OC pad 22 is hereinafter referred to as a short-circuit region 4. FIG.

The short-circuit region 4 may be arranged in either the effective region 1a or the ineffective region 1b of the active region 1, but is a region that does not operate as the main semiconductor element 11 when the main semiconductor element 11 is turned on. In the short-circuit region 4, the front surface of the semiconductor chip 70 is covered with an insulating layer in which a field insulating film 80 and an interlayer insulating film 40 are laminated in order. In the semiconductor device 20 according to the first embodiment as a product, part of the cut short-circuit electrode 111 may remain on the interlayer layer on the front surface of the semiconductor chip 70 in the short-circuit region 4 . A reference numeral 110 denotes a cut portion of the short-circuit electrode 111 .

In FIG. 2, the source pad 21a, gate pad 21b, OC pad 22, anode pad 23a and cathode pad 23b are shown in rectangular plane shapes denoted by S, G, OC, A and K, respectively. FIG. 2 also shows a case where gate pad 21b, anode pad 23a, cathode pad 23b and OC pad 22 all face source pad 21a. The electrode pads arranged in the invalid area 1b of the active area 1 may be arranged in a line along the boundary between the invalid area 1b of the active area 1 and the edge termination area 2, for example.

The current sensing unit 12 has a function of detecting overcurrent (OC) flowing through the main semiconductor element 11 . The current sensing section 12 includes unit cells having the same configuration as the main semiconductor element 11 in a smaller number (for example, about 10 to 20) than the number of unit cells of the main semiconductor element 11 (for example, about 10,000). It is a vertical MOSFET. The current sensing section 12 is arranged apart from the main semiconductor element 11 . The current sensing section 12 operates under the same conditions as the main semiconductor element 11 . The current sensing section 12 may be configured using some unit cells of the main semiconductor element 11 .

The temperature sensing unit 13 has a function of detecting the temperature of the main semiconductor element 11 using the temperature characteristics of the diode. The temperature sensing unit 13 is, for example, a polysilicon diode composed of a polysilicon (poly-Si) layer provided on the field insulating film 80 (see FIG. 3) on the front surface of the semiconductor chip 70 . The overvoltage protector (not shown) is a diode that protects the main semiconductor element 11 from overvoltage (OV: Over Voltage) such as surge. The current sensing section 12, the temperature sensing section 13 and the overvoltage protection section are controlled by the arithmetic circuit section, and the main semiconductor element 11 is controlled based on these output signals.

The arithmetic circuit section is composed of a plurality of semiconductor elements such as CMOS (Complementary MOS) circuits. For this reason, the arithmetic circuit section includes arithmetic section pads in addition to the front surface electrodes (source electrodes and the like: not shown) of the plurality of semiconductor elements forming the arithmetic circuit section. When the arithmetic circuit portion is arranged on the same semiconductor chip 70 as the main semiconductor element 11, the element structure (including the front surface electrode) of the plurality of semiconductor elements constituting the arithmetic circuit portion is placed in the effective region 1a of the active region 1. It is sufficient if it is arranged. The operation part pads may be arranged in either the effective region 1a or the invalid region 1b of the active region 1, or may be arranged in the edge termination region 2. FIG.

Next, cross-sectional structures of the main semiconductor element 11, the current sensing portion 12, and the temperature sensing portion 13 described above will be described. FIG. 3 is a cross-sectional view showing a cross-sectional structure taken along line X1-X2, line X2-X3, and line Y1-Y2 in FIG. FIG. 3 is a cross-sectional structure taken along a cutting line X1-Y2 extending from the source pad 21a of the active region 1a of the active region 1 of FIG. FIG. 3 shows the semiconductor device 20 according to the first embodiment in the state of a semiconductor chip 70 cut from the semiconductor wafer 10. As shown in FIG.

The main semiconductor element 11 and the circuit section that protects and controls the main semiconductor element 11 have the same wiring structure using pin-shaped wiring members (terminal pins 48a to 48d described later). The main semiconductor element 11 is a vertical MOSFET having a trench gate structure MOS gate on the front surface side of the semiconductor chip 70 . Semiconductor chip 70 is a semiconductor substrate obtained by epitaxially growing silicon carbide layers 71, 72 which will be n ^{− -type} drift region 32 and p-type base region 34a in order on n + -type starting substrate 31 made of silicon carbide. Each part constituting the MOS gate of the main semiconductor element 11 is provided in the effective region 1a of the active region 1. As shown in FIG.

Each part constituting the MOS gate of the main semiconductor element 11 is a p-type base region 34a, an n ⁺ -type source region 35a, a p ⁺⁺ -type contact region 36a, a trench 37a, a gate insulating film 38a and a gate electrode 39a. Trench 37 a penetrates p-type silicon carbide layer 72 in depth direction Z from the front surface of semiconductor chip 70 (the surface of p-type silicon carbide layer 72 ) and reaches n ⁻ -type silicon carbide layer 71 . The depth direction Z is the direction from the front surface to the back surface of the semiconductor chip 70 . In the region where main semiconductor element 11 is arranged, p-type base region 34a is provided between adjacent trenches 37a (mesa regions) of p-type silicon carbide layer 72 .

The trenches 37a are formed, for example, in the direction X parallel to the front surface of the semiconductor chip 70 and in which the electrode pads 21b, 23a, 23b, and 22 are arranged (refer to FIG. 2; hereinafter referred to as the first direction), or the first They may be arranged in stripes extending in a direction Y (hereinafter referred to as a second direction) perpendicular to the direction X, or may be arranged in a matrix when viewed from the front surface side of the semiconductor chip 70 . . 2 and 3 show the case where the trenches 37a are arranged in stripes extending in the first direction X. FIG. A gate electrode 39a is provided inside the trench 37a via a gate insulating film 38a. FIG. 3 shows part of the unit cells of the main semiconductor device 11 .

Inside n ⁻ -type silicon carbide layer 71, an n-type region (hereinafter referred to as n-type current diffusion region) 33a may be provided in the mesa region in contact with p-type base region 34a. The n-type current spreading region 33a is a so-called current spreading layer (CSL) that reduces spreading resistance of carriers. The n-type current diffusion region 33a reaches from the interface with the p-type base region 34a to a position closer to the n ⁺ -type drain region (n ⁺ -type starting substrate 31) than the bottom of the trench 37a. Further, first and second p ⁺ -type regions 61a and 62a may be selectively provided inside n ⁻ -type silicon carbide layer 71, respectively.

The first p ⁺ -type region 61a is provided apart from the p-type base region 34a and faces the bottom surface of the trench 37a in the depth direction Z. As shown in FIG. The second p ⁺ -type region 62a is provided between adjacent trenches 37a (mesa regions), separated from the first p ⁺ -type region 61a and the trenches 37a, and in contact with the p-type base region 34a. The first and second p ⁺ -type regions 61a and 62a have the function of relaxing the electric field applied to the gate insulating film 38a at the bottom of the trench 37a. An n - -type drift region 32 is provided between ^the n-type current diffusion region 33a and the first and second p ⁺ -type regions 61a and 62a and the n ⁺ -type drain region in contact with these regions.

Inside the p-type silicon carbide layer 72, a p-type base region 34a, an n ⁺ -type source region 35a and a p ⁺⁺ -type contact region 36a are selectively provided. The n ⁺ -type source region 35a and the p ⁺⁺ -type contact region 36a are provided between the front surface of the semiconductor chip 70 and the p-type base region 34a. The n ⁺ -type source region 35a is in contact with the gate insulating film 38a on the side wall of the trench 37a and faces the gate electrode 39a via the gate insulating film 38a. The interlayer insulating film 40 is provided over the entire front surface of the semiconductor chip 70 so as to cover the gate electrode 39a.

All the gate electrodes 39a of the main semiconductor element 11 are electrically connected to the gate pads 21b (see FIG. 2) through gate runners (not shown) made of polysilicon, for example, at portions not shown. The interlayer insulating film 40 is provided with a first contact hole 40 a that penetrates the interlayer insulating film 40 in the depth direction Z and reaches the front surface of the semiconductor chip 70 . The n ⁺ -type source region 35a and the p ⁺⁺ -type contact region 36a of the main semiconductor element 11 are exposed through the first contact hole 40a.

A nickel silicide (NiSi, Ni ₂ Si or thermally stable NiSi ₂ : hereinafter collectively referred to as NiSi) film 41a is provided on the front surface of the semiconductor chip 70 inside the first contact hole 40a. ing. The NiSi film 41a is in ohmic contact with the semiconductor chip 70 inside the first contact hole 40a, and is electrically connected to the n ⁺ -type source region 35a and the p ^{++ -type} contact region 36a.

In the effective region 1a of the active region 1, a barrier metal 46a is provided over the entire surfaces of the interlayer insulating film 40 and the NiSi film 41a. The barrier metal 46a has a function of preventing mutual reaction between the respective metal films of the barrier metal or between opposing regions with the barrier metal interposed therebetween. The barrier metal 46a may have a laminated structure in which, for example, a first titanium nitride (TiN) film 42a, a first titanium (Ti) film 43a, a second TiN film 44a and a second Ti film 45a are laminated in this order.

The first TiN film 42 a is provided only on the surface of the interlayer insulating film 40 and covers the entire surface of the interlayer insulating film 40 . The first Ti film 43a is provided on the surfaces of the first TiN film 42a and the NiSi film 41a. The second TiN film 44a is provided on the surface of the first Ti film 43a. The second Ti film 45a is provided on the surface of the second TiN film 44a. Barrier metal is not provided, for example, in the temperature sensing section 13 .

The source pad 21a is embedded in the first contact hole 40a and provided over the entire surface of the second Ti film 45a. The source pad 21a is electrically connected to the n ⁺ -type source region 35a and the p ⁺⁺ -type contact region 36a through the barrier metal 46a and the NiSi film 41a, and functions as the source electrode of the main semiconductor element 11. FIG. The source pad 21a is, for example, an aluminum (Al) film or an Al alloy film.

Specifically, when the source pad 21a is an Al alloy film, the source pad 21a may be, for example, an aluminum-silicon (Al--Si) film containing about 5% or less of silicon in its entirety. It may be an aluminum-silicon-copper (Al-Si-Cu) film containing about 5% or less of the whole and copper (Cu) of about 5% or less of the whole, or an aluminum-silicon containing about 5% or less of the whole copper (Cu). A copper (Al—Cu) film may be used.

One end of a terminal pin 48a is joined onto the source pad 21a via a plating film 47a and a solder layer (not shown). The other end of the terminal pin 48 a is joined to a metal bar (not shown) arranged to face the front surface of the semiconductor chip 70 . The other end of the terminal pin 48a is exposed outside the case (not shown) in which the semiconductor chip 70 is mounted, and is electrically connected to an external device (not shown).

The terminal pin 48a is a rod-shaped (cylindrical) wiring member having a predetermined diameter. The terminal pin 48a is soldered to the plating film 47a in a state of standing substantially perpendicular to the front surface of the semiconductor chip 70. As shown in FIG. The terminal pin 48a serves as an external connection terminal for extracting the potential of the source pad 21a to the outside. Source pad 21a is connected to an external ground potential (lowest potential) via terminal pin 48a.

The plated film 47a is formed of a material that has high adhesion to the source pad 21a even under high temperature conditions (for example, 200° C. to 300° C.) and is less likely to peel off than wire bonding. A portion of the surface of the source pad 21a other than the plated film 47a is covered with a first protective film 49a. A boundary between the plated film 47a and the first protective film 49a is covered with a second protective film 50a. The first and second protective films 49a and 50a are polyimide films, for example.

The drain electrode 51 is in ohmic contact with the entire back surface of the semiconductor chip 70 (the back surface of the n ⁺ -type starting substrate 31). A drain pad (electrode pad: not shown) is provided on the drain electrode 51 . The drain pad has a laminated structure in which, for example, a Ti film, a nickel (Ni) film and a gold (Au) film are laminated in order. The thicknesses of the Ni film and the Au film forming the drain pad may be, for example, 20 μm, 100 μm and 2 μm, respectively.

The drain pad is soldered to a metal base plate (not shown) and at least partially contacts the base portion of the cooling fin (not shown) through the metal base plate. The semiconductor chip 70 has a double-sided cooling structure. That is, the heat generated in the semiconductor chip 70 is dissipated from the fin portion of the cooling fin that is in contact with the back surface of the semiconductor chip 70 via the metal base plate, and the terminal pins 48a on the front surface of the semiconductor chip 70 are joined together. heat is dissipated from the metal bar.

A gate pad 21b of the main semiconductor element 11 is provided in the invalid region 1b of the active region 1 . The gate pad 21b is electrically connected to the gate runner. The gate runners are located on a field oxide (not shown) provided over the front surface of semiconductor wafer 10 in edge termination region 2 . Gate runners are provided along the boundary between the active region 1 and the edge termination region 2 and surround the perimeter of the active region 1 .

In the invalid region 1b of the active region 1, the p-type base region 34b of the current sensing section 12 is selectively provided in the surface region of the front surface of the semiconductor chip 70. As shown in FIG. The p-type base region 34 b ^of the current sensing portion 12 is formed by the n − -type region 32 a penetrating the p ^- type silicon carbide layer 72 in the depth direction Z to reach the n − -type silicon carbide layer 71 . It is separated from the base region 34a. That is, the main semiconductor element 11 and the current sensing section 12 are electrically insulated by the n ^- -type region 32a.

The current sensing portion 12 includes a p-type base region 34b, an n ⁺ -type source region 35b, a p ⁺⁺ -type contact region 36b, a trench 37b, a gate insulating film 38b, and a gate electrode 39b, which have the same configuration as the corresponding parts of the main semiconductor element 11. and an interlayer insulating film 40 . Each portion of the MOS gate of the current sensing portion 12 is provided in the formation region of the current sensing portion 12 in the invalid region 1 b of the active region 1 . Like the main semiconductor element 11, the current sensing section 12 may have an n-type current diffusion region 33b and first and second p ⁺ -type regions 61b and 62b.

All the gate electrodes 39b of the current sensing section 12 are electrically connected to the gate pads 21b (see FIG. 2) of the main semiconductor element 11 via gate runners in portions not shown. A second contact hole 40b is provided in the interlayer insulating film 40 in the region where the current sensing portion 12 is formed, and reaches the front surface of the semiconductor chip 70 through the interlayer insulating film 40 in the depth direction Z. As shown in FIG. The n ⁺ -type source region 35b and the p ⁺⁺ -type contact region 36b of the current sensing portion 12 are exposed through the second contact hole 40b.

A NiSi film 41b is provided on the front surface of the semiconductor chip 70 inside the second contact hole 40b. The NiSi film 41b is in ohmic contact with the semiconductor chip 70 inside the second contact hole 40b. In the invalid region 1b of the active region 1, a barrier metal 46b is provided on the entire surface of the interlayer insulating film 40 and the NiSi film 41b in the region where the current sensing portion 12 is formed. The barrier metal 46b has the same lamination structure and function as the barrier metal 46a of the main semiconductor element 11, for example.

That is, the barrier metal 46b has a laminated structure in which a first TiN film 42b, a first Ti film 43b, a second TiN film 44b and a second Ti film 45b are laminated in this order. The first TiN film 42 b is provided only on the surface of the interlayer insulating film 40 and covers the entire surface of the interlayer insulating film 40 . The first Ti film 43b covers the entire surface of the first TiN film 42b and the NiSi film 41b. The second TiN film 44b covers the entire surface of the first Ti film 43b. The second Ti film 45b covers the entire surface of the second TiN film 44b.

The OC pad 22 is embedded in the second contact hole 40b and provided over the entire surface of the second Ti film 45b. The OC pad 22 is electrically connected to the n ⁺ -type source region 35b and the p ⁺⁺ -type contact region 36b through the barrier metal 46b and the NiSi film 41b, and functions as a source electrode of the current sensing section 12. FIG. The OC pad 22 is made of, for example, the same material as the source pad 21a and is formed at the same time as the source pad 21a. Barrier metal 46b and OC pad 22 have the same thickness as barrier metal 46a of main semiconductor element 11 and source pad 21a.

One end of a terminal pin 48b is joined to the OC pad 22 via a plating film 47b and a solder layer (not shown), similarly to the terminal pin 48a on the source pad 21a. The other end of the terminal pin 48b is exposed outside a case (not shown) in which the semiconductor chip 70 is mounted and is electrically connected to an external device (not shown). The terminal pin 48b is a rod-shaped (cylindrical) wiring member having a diameter smaller than that of the terminal pin 48a. The terminal pin 48b serves as an external connection terminal for extracting the potential of the OC pad 22 to the outside, for example. OC pad 22 is connected to the ground potential via terminal pin 48b and external resistor 14 (see FIG. 4).

A portion of the surface of the OC pad 22 other than the plated film 47b is covered with a first protective film 49b like the source pad 21a. A boundary between the plated film 47b and the first protective film 49b is covered with a second protective film 50b. The materials of the plated film 47b and the first and second protective films 49b and 50b are the same as those of the plated film 47a and the first and second protective films 49a and 50a on the source pad 21a, respectively.

The temperature sensing portion 13 is a polysilicon diode formed of a pn junction between a p-type polysilicon layer 81 that is a p-type anode region and an n-type polysilicon layer 82 that is an n-type cathode region. P-type polysilicon layer 81 and n-type polysilicon layer 82 are provided on field insulating film 80 in invalid region 1 b of active region 1 . The temperature sensing section 13 is electrically insulated from the main semiconductor element 11 and the current sensing section 12 by the field insulating film 80 .

Immediately below the p-type polysilicon layer 81 and the n-type polysilicon layer 82, a p-type base region 34c, a p ⁺⁺ -type contact region 36c and a second p ⁺ -type region 62c are selectively provided inside the semiconductor chip 70. It is The p-type base region 34c and the p ^++- type contact region 36c are regions formed by extending the p-type base region 34b and the p ⁺⁺ -type contact region 36b of the current sensing portion 12 to the formation region of the temperature sensing portion 13, respectively. The second p ⁺ -type region 62c is in contact with the p-type base region 34c and provided at a position closer to the n ⁺ -type drain region than the p-type base region 34c.

Instead of the p-type polysilicon layer 81 and the n-type polysilicon layer 82, the temperature sensing section 13 may be composed of a p-type anode region and an n-type cathode region formed adjacent to each other inside the semiconductor chip 70. . Field insulating film 80 , p-type polysilicon layer 81 and n-type polysilicon layer 82 are covered with interlayer insulating film 83 . The interlayer insulating film 83 is provided with third and fourth contact holes 83a and 83b that penetrate the interlayer insulating film 83 in the depth direction Z and expose the p-type polysilicon layer 81 and the n-type polysilicon layer 82, respectively. ing.

Anode pad 23a and cathode pad 23b are in contact with p-type polysilicon layer 81 and n-type polysilicon layer 82 at third and fourth contact holes 83a and 83b, respectively. The anode pad 23a and the cathode pad 23b are, for example, made of the same material as the source pad 21a and formed at the same time as the source pad 21a. Terminal pins 48c and 48d are joined to the anode pad 23a and the cathode pad 23b via plated films 47c and 47d and solder layers (not shown), respectively, similarly to the source pad 21a.

The portions other than the plated films 47c and 47d on the surfaces of the anode pad 23a and the cathode pad 23b are covered with a first protective film 49c like the source pad 21a. A boundary between the plated film 47c and the first protective film 49c is covered with a second protective film 50c. The materials of the plated film 47c and the first and second protective films 49c and 50c are the same as those of the plated film 47a and the first and second protective films 49a and 50a on the source pad 21a, respectively.

The operation of the semiconductor device 20 according to the first embodiment will be explained. FIG. 4 is a circuit diagram showing an equivalent circuit of the semiconductor device 20 according to the first embodiment. As shown in FIG. 4 , the current sensing section 12 is composed of some unit cells among unit cells of a plurality of MOSFETs that constitute the main semiconductor element 11 . The ratio of the sense current flowing through the current sensing section 12 to the main current flowing through the main semiconductor element 11 (hereinafter referred to as the current sensing ratio) is set in advance.

The current sensing ratio can be set by, for example, changing the number of unit cells between the main semiconductor element 11 and the current sensing section 12 . A sense current smaller than the main current flowing through the main semiconductor element 11 flows through the current sensing section 12 according to the current sensing ratio. The source of the main semiconductor element 11 is connected to the ground point GND of the ground potential. A resistor 14, which is an external component, is connected between the source of the current sensing section 12 and the ground point GND.

When the main semiconductor element 11 is turned on, a main current flows from the drain of the main semiconductor element 11 toward the source. At this time, the current sensing section 12 is also turned on at the same time as the main semiconductor element 11, and the sense current of the current sensing section 12 flows from the drain to the source of the current sensing section 12 and passes through the resistor 14 to the ground point GND. and flows. Therefore, a voltage drop occurs in the resistor 14 due to the current sensed by the current sensing section 12 .

When an overcurrent is applied to the main semiconductor element 11, the sense current of the current sensing section 12 increases according to the magnitude of the overcurrent to the main semiconductor element 11, and the voltage drop across the resistor 14 also increases. Therefore, overcurrent in the main semiconductor element 11 can be detected by monitoring the voltage drop across the resistor 14 . When the voltage drop across the resistor 14 exceeds a predetermined value, the gate voltage of the main semiconductor element 11 is cut off by the arithmetic circuit section.

A constant voltage (forward voltage Vf) is always applied between the anode and cathode of the temperature sensing section 13 . By monitoring the amount of change in the forward voltage Vf of the temperature sensing section 13 and utilizing the temperature dependence of the forward voltage Vf of the temperature sensing section 13, the temperature rise of the main semiconductor element 11 can be detected. When the change value of the forward voltage Vf in the temperature sensing section 13 exceeds a predetermined value, the arithmetic circuit section cuts off the gate voltage of the main semiconductor element 11 .

Next, a method for manufacturing the semiconductor device 20 according to the first embodiment will be described. 5 to 10 and 12 are cross-sectional views showing states in the middle of manufacturing the semiconductor device according to the first embodiment. FIG. 11 is a plan view showing a state in the middle of manufacturing the semiconductor device according to the first embodiment. FIG. 13 is a cross-sectional view showing another example of the state in the middle of manufacturing the semiconductor device according to the first embodiment. Although only the main semiconductor element 11 is shown in FIGS. 5 to 10, each part of all the elements fabricated (manufactured) on the same semiconductor wafer 10 as the main semiconductor element 11 is formed at the same time as each part of the main semiconductor element 11. .

FIG. 11 shows one chip area 10' of the semiconductor wafer 10 of FIG. 1 (similar to FIGS. 14 and 15). FIG. 12 is a cross-sectional view showing a cross-sectional structure taken along line X1'-X2', line X2'-X3', and line Y1'-Y2' in FIG. The cutting line X1'-Y2' in FIG. 11 cuts at the same location as the cutting line X1-Y2 in FIG. That is, FIG. 12 shows a main semiconductor element 11, a current sensing section 12 and a temperature sensing section 13. As shown in FIG. Here, the formation of each part of the main semiconductor element 11 will be described with reference to FIGS. 5 to 13, and the formation of each part of the current sensing section 12 and the temperature sensing section 13 will be described with reference to FIGS.

First, as shown in FIG. 5, an n ⁺ -type starting substrate (semiconductor wafer) 31 made of silicon carbide is prepared. The n ⁺ -type starting substrate 31 may be, for example, a nitrogen (N)-doped silicon carbide single crystal substrate. Next, on the front surface of n ⁺ -type starting substrate 31, n ⁻ -type silicon carbide layer 71 doped with nitrogen at a concentration lower than that of n ⁺ -type starting substrate 31 is epitaxially grown. When the main semiconductor element 11 has a withstand voltage of 3300V class, the thickness t1 of the n ⁻ -type silicon carbide layer 71 may be, for example, about 30 μm.

Next, as shown in FIG. 6, by photolithography and ion implantation of a p-type impurity such as Al, n ⁻ -type silicon carbide is formed in the effective region 1a of the active region 1 of each chip region 10′ (see FIG. 1). A first p ⁺ -type region 61a and a p ⁺ -type region 91 are selectively formed in the surface region of layer 71, respectively. This p ⁺ -type region 91 is part of the second p ⁺ -type region 62a. The first p ⁺ -type region 61a and the p ⁺ -type region 91 are alternately arranged in a direction parallel to the front surface of the n ⁺ -type starting substrate 31 (for example, the first direction X or the second direction Y in FIGS. 1 and 2). placed repeatedly.

The first p ⁺ -type regions 61a and the p ⁺ -type regions 91 are arranged in stripes extending, for example, in the second direction Y or the first direction X in FIGS. A distance d2 between the adjacent first p ⁺ -type region 61a and p ⁺ -type region 91 may be, for example, about 1.5 μm. The depth d1 and impurity concentration of the first p ⁺ -type region 61a and p ⁺ -type region 91 may be, for example, about 0.5 μm and about 5.0×10 ¹⁸ /cm ³ , respectively. Then, the ion implantation mask (not shown) used for forming the first p ⁺ -type region 61a and the p ⁺ -type region 91 is removed.

Next, by photolithography and ion implantation of an n-type impurity such as nitrogen, an n-type impurity is formed in the surface region of the n ^{− -type} silicon carbide layer 71 over the entire effective region 1a of the active region 1 in each of the chip regions 10′. A region 92 is formed. The n-type region 92 is formed, for example, between the first p ⁺ -type region 61a and the p ⁺ -type region 91 and in contact with these regions. The depth d3 and impurity concentration of n-type region 92 may be, for example, approximately 0.4 μm and approximately 1.0×10 ¹⁷ /cm ³ , respectively.

This n-type region 92 is part of the n-type current diffusion region 33a. A portion of n ⁻ -type silicon carbide layer 71 sandwiched between n-type region 92 , first p ⁺ -type region 61 a and p ⁺ -type region 91 and n ⁺ -type starting substrate 31 serves as n ⁻ -type drift region 32 . . Then, the ion implantation mask (not shown) used for forming the n-type region 92 is removed. The formation order of the n-type region 92, the first p ⁺ -type region 61a and the p ⁺ -type region 91 may be changed.

Next, as shown in FIG. 7, an n ⁻ -type silicon carbide layer doped with an n-type impurity such as nitrogen is epitaxially grown on the n ⁻ -type silicon carbide layer 71 to a thickness t2 of 0.5 μm, for example. The thickness of n ⁻ -type silicon carbide layer 71 is increased. The impurity concentration of the thickened portion 71 a of the n ⁻ -type silicon carbide layer 71 is sandwiched between the thickened portion 71 a of the n ⁻ -type silicon carbide layer 71 and the n ⁺ -type starting substrate 31 . It may be the same as the impurity concentration of the part.

Then, by photolithography and ion ^implantation of a p ^- type impurity such as Al, a p A p ⁺ -type region 93 is selectively formed with a depth reaching the ⁺ -type region 91 . The second p ⁺ -type region 62a is formed by connecting the p ⁺ -type regions 91 and 93 in the depth direction. The width and impurity concentration of the p ⁺ -type region 93 are substantially the same as those of the p ⁺ -type region 91, for example. Then, the ion implantation mask (not shown) used for forming the p ⁺ -type region 93 is removed.

Next, by photolithography and ion implantation of an n ^- type impurity such as nitrogen, the adjacent p ^{+ -type} region 93 in the effective region 1a of the active region 1 is formed in the thickened portion 71a of the n − -type silicon carbide layer 71 . In between, an n-type region 94 is formed with a depth reaching the n-type region 92 . The impurity concentration of the n-type region 94 is substantially the same as that of the n-type region 92, for example. By connecting the n-type regions 92 and 94 in the depth direction, the n-type current diffusion region 33a is formed. The formation order of the p ⁺ -type region 93 and the n-type region 94 may be exchanged. Then, the ion implantation mask (not shown) used for forming the n-type region 94 is removed.

Next, as shown in FIG. 8, a p-type silicon carbide layer 72 doped with a p-type impurity such as Al is epitaxially grown on the n ⁻ -type silicon carbide layer 71 . The thickness t3 and impurity concentration of p-type silicon carbide layer 72 may be, for example, approximately 1.3 μm and approximately 4.0×10 ¹⁷ /cm ³ , respectively. As a result, semiconductor wafer 10 is formed in which n ⁻ -type silicon carbide layer 71 and p-type silicon carbide layer 72 are sequentially laminated on n ⁺ -type starting substrate 31 by epitaxial growth.

Next, by photolithography and ion implantation of an n-type impurity such as phosphorus (P), an n ⁺ -type impurity is formed in the surface region of the p-type silicon carbide layer 72 in the effective region 1a of the active region 1 of each chip region 10′. A source region 35a is selectively formed. Then, the ion implantation mask used for forming the n ⁺ -type source region 35a is removed.

Next, by photolithography and ion implantation of p-type impurities such as Al, p ⁺⁺ -type contact regions 36a are formed in the surface region of the p-type silicon carbide layer 72 in the effective region 1a of the active region 1 of each chip region 10'. is selectively formed. Then, the ion implantation mask used for forming the p ⁺⁺ type contact region 36a is removed.

Next, by photolithography and ion implantation of an n-type impurity such as phosphorus, the p-type silicon carbide layer 72 is penetrated in the depth direction Z in the vicinity of the boundary between the effective region 1a and the ineffective region 1b of the active region 1. N ^- -type region 32a (see FIG. 12) reaching n ^- -type silicon carbide layer 71 is formed. Effective region 1a and ineffective region 1b of active region 1 are separated by n ^- -type region 32a. Then, the ion implantation mask used for forming the n ^- -type region 32a is removed.

The order of formation of the n ⁺ -type source region 35a, the p ⁺⁺ -type contact region 36a and the n ^- -type region 32a may be changed. In effective region 1a of active region 1, a portion sandwiched between n ⁺ -type source region 35a and p ⁺⁺ -type contact region 36a and n ⁻ -type silicon carbide layer 71 serves as p-type base region 34a. In each ion implantation described above, for example, a resist film or an oxide film may be used as an ion implantation mask.

Next, all diffusion regions formed by ion implantation (first and second p ⁺ -type regions 61a and 62a, n-type current diffusion region 33a, n ⁺ -type source region 35a, p ⁺⁺ -type contact region 36a and n ^- -type region For 32a), a heat treatment (activation annealing) is performed at a temperature of, for example, about 1700° C. for about 2 minutes to activate the impurities. Activation annealing may be performed once after all diffusion regions are formed, or may be performed each time a diffusion region is formed by ion implantation.

Next, as shown in FIG. 9, by photolithography and, for example, dry etching, a first p ⁺ -type region 61a inside the n-type current diffusion region 33a is formed through the n + -type source region 35a and the p- ^type base region 34a. trenches 37a are formed. For example, a resist film or an oxide film may be used as an etching mask for forming the trench 37a.

Next, as shown in FIG. 10, a gate insulating film 38a is formed along the surface of the semiconductor wafer 10 and the inner wall of the trench 37a. The gate insulating film 38a may be formed, for example, by thermal oxidation at a temperature of about 1000° C. in an oxygen (O ₂ ) atmosphere. Also, the gate insulating film 38a may be a film deposited by a chemical reaction of high temperature oxidation (HTO).

Next, for example, a phosphorus-doped polysilicon (poly-Si) layer is deposited on the gate insulating film 38a so as to be embedded in the trench 37a and patterned to leave a portion that will become the gate electrode 39a only inside the trench 37a (the first layer). 1 step). At this time, the portion of the polysilicon layer that will become the gate electrode 39a may be left so as to protrude outward from the front surface of the semiconductor wafer 10, or be lower than the front surface of the semiconductor wafer 10. You can leave it.

All the elements other than the main semiconductor element 11 (for example, the current sensing section 12, the overvoltage protection section such as the diffusion diode, and the CMOS (Complementary MOS) constituting the arithmetic circuit section) are the main semiconductor element 11 described above. are formed in the invalid regions 1b of the active regions 1 of the chip regions 10' of the semiconductor wafer 10 at the same time as the corresponding portions of the main semiconductor element 11 are formed.

For example, the diffusion region of each element arranged on the semiconductor wafer 10 may be formed at the same time as the diffusion region having the same conductivity type, impurity concentration and diffusion depth among the diffusion regions forming the main semiconductor element 11 . Further, the gate trench, gate insulating film and gate electrode of the elements arranged on the semiconductor wafer 10 may be formed at the same time as the trench 37a, the gate insulating film 38a and the gate electrode 39a of the main semiconductor element 11 respectively (second step). .

Next, a field insulating film 80 is formed on the front surface of the semiconductor wafer 10 in the formation region of the temperature sensing portion 13 . At this time, the field insulating film 80 is also formed on the front surface of the semiconductor wafer 10 in the short-circuit region 4 . Next, a phosphorus-doped polysilicon layer, for example, which will become an n-type polysilicon layer 82 is deposited on the field insulating film 80 , and a part of the polysilicon layer is made a p-type region to form a p-type polysilicon layer 81 . Next, the polysilicon layer is patterned to leave only the p-type polysilicon layer 81 and the n-type polysilicon layer 82 .

A polysilicon layer deposited to form the p-type polysilicon layer 81 and the n-type polysilicon layer 82 forms a gate runner (not shown) at the same time as the p-type polysilicon layer 81 and the n-type polysilicon layer 82 are formed. may be formed. In this case, the field insulating film 80 is also formed on the front surface of the semiconductor wafer 10 in the edge termination region 2 . Then, the portion of the polysilicon layer that will become the gate runner should be left in the edge termination region 2 .

Next, interlayer insulating films 40 and 83 are formed all over the front surface of semiconductor wafer 10 so as to cover gate electrodes 39a and 39b, p-type polysilicon layer 81 and n-type polysilicon layer . Further, the interlayer insulating film 40 is also formed on the field insulating film 80 in the short-circuit region 4 . The interlayer insulating films 40 and 83 may be PSG (Phospho Silicate Glass), for example. The thickness of the interlayer insulating films 40 and 83 may be, for example, about 1 μm. Next, the interlayer insulating film 40 and the gate insulating films 38a and 38b are selectively removed by photolithography and etching to form contact holes at predetermined locations.

Specifically, first and second contact holes 40a and 40b are formed in the interlayer insulating film 40 to expose the n ⁺ -type source regions 35a and 35b and the p ⁺⁺ -type contact regions 36a and 36b. A fifth contact hole 40d is formed in the interlayer insulating film 40 near the boundary between the effective region 1a and the ineffective region 1b of the active region 1 to expose the short-circuit region 4 (see FIGS. 11 and 12). Next, the interlayer insulating films 40 and 83 are flattened (reflowed) by heat treatment.

Next, a first TiN film 102 serving as a barrier metal is formed on the entire front surface of the semiconductor wafer 10 by sputtering, for example. The first TiN film 102 covers the entire surfaces of the interlayer insulating films 40 and 83, and the portions (n ⁺ It covers the type source regions 35a, 35b, the p ⁺⁺ type contact regions 36a, 36b and the shorting region 4).

Next, by photolithography and etching, the portions of the first TiN film 102 covering the semiconductor wafer 10 inside the first and second contact holes 40a and 40b are removed to form the n ⁺ -type source regions 35a, 35b and p ⁺⁺ . The mold contact regions 36a, 36b are again exposed. The first TiN film 102 is left in the short-circuit region 4 . As a result, the first TiN film 102 is left on the entire surfaces of the interlayer insulating films 40 and 83 and on the short circuit region 4 (short circuit process).

The portion of the first TiN film 102 remaining on the interlayer insulating film 40 is the first TiN film 42a forming the barrier metal 46a of the main semiconductor element 11 and the first TiN film 42b forming the barrier metal 46b of the current sensing section 12. Become. A portion (hereinafter referred to as a first TiN film) 42d of the first TiN film 102 remaining in the short-circuit region 4 is a short-circuit electrode 111 (hatched portion in FIG. 11) that short-circuits the first TiN film 42a and the first TiN film 42b. becomes.

Next, a Ni film (not shown) is formed on the semiconductor portion (the front surface of the semiconductor wafer 10) exposed through the first and second contact holes 40a and 40b by, for example, sputtering. At this time, a Ni film is also formed on the first TiN film 102 . Next, a heat treatment at about 970° C., for example, is performed to silicidize the contact portion of the Ni film with the semiconductor portion, thereby forming the NiSi film 101 in ohmic contact with the semiconductor portion.

The NiSi film 101 in the first contact hole 40 a becomes the NiSi film 41 a in ohmic contact with the n ⁺ -type source region 35 a and the p ⁺⁺ -type contact region 36 a of the main semiconductor element 11 . The NiSi film 101 in the second contact hole 40b becomes the NiSi film 41b in ohmic contact with the n ⁺ -type source region 35b and the p ⁺⁺ -type contact region 36b of the current sensing section 12 .

During the heat treatment for silicidation of nickel, since the first TiN film 102 is arranged between the interlayer insulating films 40 and 83 and the Ni film, nickel atoms in the Ni film are can be prevented from spreading to The portions of the Ni film on the interlayer insulating films 40 and 83 are not silicided because they are not in contact with the semiconductor portion. Portions of the Ni film on the interlayer insulating films 40 and 83 are removed to expose the interlayer insulating films 40 and 83 .

Next, a Ni film, for example, is formed on the back surface of the semiconductor wafer 10 . Next, the Ni film is silicided by heat treatment at, for example, about 970° C., and a NiSi film is formed as the drain electrode 51 in ohmic contact with the semiconductor portion (back surface of the semiconductor wafer 10). The heat treatment for silicidation when forming the NiSi film to be the drain electrode 51 may be performed simultaneously with the heat treatment when forming the NiSi film 101 on the front surface of the semiconductor wafer 10 .

Next, by sputtering, a first Ti film 103, a second TiN film 104, and a second Ti film 105 serving as barrier metals, and an Al film or Al alloy film (hereinafter referred to as an Al alloy film) serving as electrode pads are formed on the front surface of the semiconductor wafer 10 by sputtering. collectively referred to as an Al film) 106 are laminated in order. The thickness of the first and second TiN films 102 and 104 is, for example, about 50 nm or more and 200 nm or less, and may be about 100 nm, for example. The thickness of the first and second Ti films 103 and 105 is, for example, about 10 nm or more and 50 nm or less, and may be about 20 nm, for example. The thickness of the Al film 106 is, for example, about 5 μm or less.

Next, the metal films 103 to 106 are patterned by photolithography and etching to leave portions to become barrier metals 46a, 46b and electrode pads 21a, 21b, 22. Next, as shown in FIG. The effective region 1a of the active region 1 of the metal films 103 to 106 becomes the first Ti film 43a, the second TiN film 44a, the second Ti film 45a and the source pad 21a of the main semiconductor element 11, respectively. Parts of the metal films 103 to 106 that constitute the invalid region 1b of the active region 1 become the first Ti film 43b, the second TiN film 44b, the second Ti film 45b and the OC pad 22 of the current sensing section 12 (the third process).

The portions of the metal films 103 to 106 in the short-circuit region 4 are also removed, leaving only the first TiN film 42d which becomes the short-circuit electrode 111 in the short-circuit region 4 (FIG. 12). As a result, the source pad 21a of the main semiconductor element 11 and the OC pad 22 of the current sensing section 12 are short-circuited via the short-circuit electrode 111 and the barrier metals 46a and 46b. Since the short-circuit electrode 111 is composed only of the thin first TiN film 42d, the short-circuit electrode 111 can be easily cut in a later step.

When the short-circuit electrode 111 is formed only of the first TiN film 42d, the portion of the first TiN film 102 that becomes the short-circuit electrode 111 (the first TiN film 111) is etched to leave the first TiN film 102 only on the interlayer insulating films 40 and 83. A membrane 42d) can be left. On the other hand, if one of the metal films 103 to 106 is left as the short-circuit electrode 111, an etching process for patterning the metal film that is not left as the short-circuit electrode 111 is performed during the deposition of the metal films 103 to 106 in this order. . Therefore, when the short-circuit electrode 111 is formed only by the first TiN film 42d, all the metal films 103 to 106 can be continuously deposited without intervening the etching process, thereby simplifying the manufacturing process. be able to.

A short-circuit electrode having a laminated structure in which a first TiN film 42d, a first Ti film 43d, a second TiN film 44d, a second Ti film 45d and an Al film 24 are laminated in this order, leaving the short-circuit region 4 of all the metal films 103-106. 111 (FIG. 13). One or more layers of the metal films 102 to 105 in the short-circuit region 4 may be left as the short-circuit electrode 111 . When only the metal film 102 and the portion of the short-circuit region 4 are left, the configuration shown in FIG. 12 is obtained, and the other configuration is omitted.

These NiSi films 41a and 41b and barrier metals 46a and 46b are formed while the p-type polysilicon layer 81 and the n-type polysilicon layer 82 of the temperature sensing section 13 are entirely covered with the interlayer insulating film 83. As shown in FIG. The gate pad 21b of the main semiconductor element 11 and the OV pad (not shown) of the overvoltage protection part may be formed in the same lamination structure as the source pad 21a and the OC pad 22 (fourth step).

Next, the interlayer insulating film 83 is selectively removed by photolithography and etching to form third and fourth contact holes 83a and 83b. The n-type polysilicon layer 82 is exposed. Next, the interlayer insulating film 83 is flattened by heat treatment. Next, the anode pad 23a and the cathode pad 23b of the temperature sensing section 13 are formed with an Al film or an Al alloy film.

The anode pad 23a and the cathode pad 23b of the temperature sensing portion 13 are part of the Al film 106 deposited to form the source pad 21a, and may be formed simultaneously with the formation of the source pad 21a. In this case, after forming the barrier metals 46a and 46b and before forming the Al film 106, the third and fourth contact holes 83a and 83b are formed in the interlayer insulating film 83, and the p-type polysilicon layer 81 and the n-type polysilicon layer 81 are formed. A portion of layer 82 may be exposed.

Next, for example, a Ti film, a Ni film and a gold (Au) film are sequentially laminated on the surface of the drain electrode 51 by, for example, sputtering to form a drain pad (not shown).

Next, the front surface of the semiconductor wafer 10 is protected with a polyimide film by, for example, CVD. Next, the polyimide film is selectively removed by photolithography and etching to form first protective films 49a to 49c covering the electrode pads, respectively, and openings are formed in the first protective films 49a to 49c. At this time, the short-circuit region 4 of the polyimide film is also opened to expose the short-circuit electrode 111 .

Next, after general plating pretreatment, a plating film 47a is formed on the portions of the electrode pads 21a, 21b, 22, 23a, and 23b exposed to the openings of the first protective films 49a to 49c by general plating. Forming ~47c. At this time, the first protective films 49a to 49c function as masks for suppressing wetting and spreading of the plating films 47a to 47c. The thickness of the plating films 47a to 47c may be, for example, about 5 μm. The plated films 47a to 47c do not have to be formed on the short-circuit electrode 111. FIG.

Next, for example, by CVD, a polyimide film is formed as the second protective films 50a to 50c covering the boundaries between the plated films 47a to 47c and the first protective films 49a to 49c. Next, terminal pins 48a to 48c are joined onto the plated films 47a to 47c by solder layers (not shown), respectively. At this time, the second protective films 50a to 50c function as masks for suppressing wetting and spreading of the solder layer.

After the short-circuit electrode 111 is formed, the steps (predetermined steps) up to this point are performed while the source pad 21 a and the OC pad 22 are short-circuited by the short-circuit electrode 111 . The reason is as follows. Since the source potential of the main semiconductor element 11 and the current sensing section 12 is in a state of floating (floating potential) before the formation of the metal films (the NiSi films 41a and 41b formed first) that serve as the source potential, the current sensing section 12 of the gate insulating film 38b is less susceptible to plasma and static electricity. On the other hand, when the metal film having the source potential is formed, the source potential of both the main semiconductor element 11 and the current sensing section 12 is fixed to some extent.

As described above, the current sensing section 12 has a structure in which the number of unit cells having the same configuration as that of the main semiconductor element 11 is approximately 1/1000 of the number of unit cells of the main semiconductor element 11 . Therefore, in the current sensing section 12, the surface area occupied by the gate electrode 39b is smaller than that of the main semiconductor element 11, and the gate capacitance is extremely small. In particular, when silicon carbide is used as a semiconductor material, the gate insulating film 38b provided along the side wall of the trench 37b has poor film quality and is vulnerable to electric charges. The gate insulating film 38b deteriorates due to plasma or static electricity.

Therefore, when a metal film serving as a source potential is formed on each of the main semiconductor element 11 and the current sensing section 12 and the source potential is fixed, the source potential of the current sensing section 12 is changed by plasma and static electricity generated during the manufacturing process. wobbles. As a result, the gate insulating film 38b of the current sensing portion 12 having a smaller gate capacitance than that of the main semiconductor element 11 is likely to break down. Therefore, as described above, the steps after forming the short-circuit electrode 111 are performed with the source pad 21 a and the OC pad 22 short-circuited by the short-circuit electrode 111 . This is because the source potential of the current sensing section 12 can be stabilized while the source pad 21a and the OC pad 22 are short-circuited.

By stabilizing the source potential of the current sensing section 12, the ESD resistance of the current sensing section 12 during the manufacturing process can be increased. The length w1 (see FIG. 11) of the short-circuit electrode 111 is preferably about 5 μm or more and 10 μm or less, for example. As the length w1 of the short-circuit electrode 111 is shortened, the chip size can be reduced. The length w1 of the short-circuit electrode 111 is the distance (the width in the second direction Y) between the source pad 21a and the OC pad 22 . When the Al film 106 is left as the short-circuit electrode 111, the width (width in the first direction X) w2 of the short-circuit electrode 111 is preferably 5 μm or less. The reason for this is that the thinner the Al film 106 is, the easier it is to cut the short-circuit electrode 111 in a later step.

Next, before conducting a performance test (fifth step) for confirming the electrical characteristics of the semiconductor device 20 according to the first embodiment and whether it is good or bad, the short-circuit electrode 111 is cut off so that the main semiconductor element 11 and the OC pad 22 of the current sensing section 12 are opened (disconnected). The performance test may be performed in the state of the semiconductor wafer 10, or may be performed in a state in which the semiconductor wafer 10 (semiconductor wafer) is diced (cut) into individual chips. The short-circuit electrode 111 may be cut during the assembly process. In particular, when testing the current sensing section 12, a resistor 14 (see FIG. 4) is added between the source of the main semiconductor element 11 and the current sensing section 12 for testing. Therefore, it is preferable that the source pad 21a and the OC pad 22 are short-circuited until immediately before the test as much as possible.

The test of the current sensing section 12 performed in the performance test is, for example, a withstand voltage test (screening) for evaluating the reliability of the gate insulating film 38b. In screening, a predetermined voltage is applied to the gate insulating film 38b while the OC pad 22 of the current sensing section 12 is connected to the ground potential via the external resistor 14 (see FIG. 4). Then, the reliability of the gate insulating film 38b is evaluated by observing the aging breakdown phenomenon of the gate insulating film 38b and confirming the leakage current of the gate insulating film 38b.

Moreover, the performance test may be performed multiple times at predetermined timings from the start of manufacturing to the time of shipment of the product. In this case, after the performance test, a new short-circuit electrode 111 that short-circuits the source pad 21a and the OC pad 22 is formed. At this time, between the source pad 21a and the OC pad 22, the portion other than the portion where the short-circuit electrode 111 has already been formed serves as the short-circuit region 4 where the new short-circuit electrode 111 is formed. Then, while the source pad 21a and the OC pad 22 are short-circuited by the new short-circuit electrode 111, the steps after forming the new short-circuit electrode 111 are performed. After that, a new short-circuit electrode 111 may be cut before performing the next performance test.

Specifically, when the performance test is performed multiple times, for example, the following first to third tests may be performed. A first test is a wafer test performed in the state of the semiconductor wafer 10 . The second test is a test performed on the state of the semiconductor chip 70 after dicing (cutting) the semiconductor wafer 10 . The third test is a test performed in the state of the module after the assembly process of the product. When priority is given to cost reduction as a product of the semiconductor device 20 according to the first embodiment, ease of performance test process, quality, etc. may be appropriately selected. For example, when the first test is performed, it is possible to select not to perform the second and third tests.

When performing all of the first to third tests, first, the short-circuit electrode 111 is cut before performing the first test. Then, a first test is performed, and if the first test determines that the product is non-defective, a conductive film is applied to the front surface of the semiconductor wafer 10 for patterning. A new short-circuit electrode 111 is formed by leaving the conductive film only on a portion other than the portion where the short-circuit electrode 111 has already been formed. Next, while the source pad 21a and the OC pad 22 are short-circuited by the new short-circuit electrode 111, the steps after forming the new short-circuit electrode 111 are performed.

Next, a new short-circuit electrode 111 is cut before performing the second test. Then, a second test is performed, and if the second test determines that the product is non-defective, a conductive film is applied to the front surface of the semiconductor wafer 10 for patterning. A new short-circuit electrode 111 is formed by leaving the conductive film again only on a portion other than the portion where the short-circuit electrode 111 has already been formed. Next, while the source pad 21a and the OC pad 22 are short-circuited by the second new short-circuit electrode 111, the steps after forming the second new short-circuit electrode 111 are performed.

Next, the second new short-circuit electrode 111 is cut before performing the third test. Next, a third test is performed, and if the product is determined to be non-defective in the third test, it is shipped as a product. The formation of the new short-circuit electrode 111 may be manual (manual) or automated (automatic). In this way, the source pad 21a and the OC pad 22 are short-circuited by the new short-circuit electrode 111 to protect the gate insulating film 38b of the current sensing section 12, and a predetermined step can be performed between multiple performance tests. preferable. Thereby, the ESD resistance of the current sensing section 12 can be further improved.

For example, laser or etching can be used to cut the short-circuit electrode 111 regardless of which of the metal films 102 to 106 the short-circuit electrode 111 is composed of. When a laser is used to cut the short-circuit electrode 111, the short-circuit electrode 111 may be cut by one laser irradiation, or may be cut by repeating laser irradiation a plurality of times. For example, if the short-circuit electrode 111 is made of the first and second TiN films 102 and 104 and the first and second Ti films 103 and 105 and the thickness of the short-circuit electrode 111 is thin, the short-circuit electrode 111 can be removed by using a laser. It can be cut in a short time. For example, when the short-circuit electrode 111 is a TiN film, when cutting the short-circuit electrode 111, the laser waveform may be continuously oscillated in steps of 0.1 s and repeatedly irradiated in steps of 10 ms.

When the short-circuit electrode 111 includes the Al film 106, the entire short-circuit electrode 111 may be cut with a laser, but cutting the short-circuit electrode 111 takes time. For example, when the short-circuit electrode 111 is an Al film, when cutting the short-circuit electrode 111, the laser waveform may be repeatedly irradiated with an energy of 0.5 mJ in steps of 100 ms. Therefore, if the short-circuit electrode 111 includes the Al film 106, for example, after removing the Al film 106 by etching, the other metal films 102 to 105 may be cut using a laser. As a result, even when the short-circuit electrode 111 includes the Al film 106, the short-circuit electrode 111 can be cut efficiently.

Further, when the short-circuit electrode 111 includes the Al film 106, when the short-circuit electrode 111 is cut by laser, melted cutting debris may scatter around, and the electrode pads may be short-circuited by the cut debris. . Therefore, it is preferable that the metal films 102 to 105 other than the Al film 106 be used for forming the short-circuit electrode 111 . Further, when the short-circuit electrode 111 includes the Al film 106 , after cutting the short-circuit electrode 111 , a step of removing cutting debris using, for example, a general exhaust treatment device (scrubber) may be performed.

It is sufficient that the source pad 21 a and the OC pad 22 are electrically separated after the short-circuit electrode 111 is cut, and part of the short-circuit electrode 111 may remain on the source pad 21 a and the OC pad 22 . Cutting the short-circuit electrode 111 with a laser causes laser interference fringes on the source pad 21 a and the OC pad 22 , but this does not affect the performance of the semiconductor device 20 .

After that, when the semiconductor wafer 10 is tested, the semiconductor wafer 10 is diced (cut) along the scribe lines 3 into individual chips (semiconductor chips 70). Through the above steps, the semiconductor device 20 shown in FIGS. 1 to 3 is completed.

As described above, according to the first embodiment, the steps after forming the short-circuit electrode are performed while the source pad of the main semiconductor element and the OC pad of the current sensing section are short-circuited by the short-circuit electrode. While the source pad of the main semiconductor element and the OC pad of the current sensing section are short-circuited, the source potential of the current sensing section can be stabilized. As a result, it is possible to increase the ESD resistance of the current sensing portion during the manufacturing process, thereby suppressing deterioration of the gate insulating film in the current sensing portion due to plasma and static electricity generated during CVD and sputtering during the manufacturing process. can be done. Therefore, it is possible to provide a semiconductor device in which dielectric breakdown is unlikely to occur in the current sensing section.

Further, according to the first embodiment, by short-circuiting the source pad of the main semiconductor element and the OC pad of the current sensing section with the short-circuit electrode, the source potential of the main semiconductor element can be stabilized. can increase the ESD resistance of the current sensing section in According to the first embodiment, the short-circuit electrode is formed between the source pad of the main semiconductor element and the OC pad of the current sensing section. Scratches can be prevented. Therefore, it is possible to prevent the gate characteristics of the main semiconductor element and the current sensing section from varying due to disconnection of the short-circuit electrode.

(Embodiment 2)
Next, a method for manufacturing the semiconductor device according to the second embodiment will be described. FIG. 14 is a plan view showing a state in the middle of manufacturing the semiconductor device according to the second embodiment. The method of manufacturing the semiconductor device 120 according to the second embodiment differs from the method of manufacturing the semiconductor device 20 according to the first embodiment (see FIG. 11) in that instead of short-circuiting the source pad 21a and the OC pad 22, 14, the source pad 21a and the gate pad 21b are short-circuited by the short-circuit electrode 112 (the hatched portion in FIG. 14), and the subsequent steps up to the performance test are performed.

The gate electrode 39b of the current sensing section 12 is electrically connected to the gate electrode 39a of the main semiconductor element 11 via a gate runner. Therefore, by short-circuiting the source pad 21a and the gate pad 21b of the main semiconductor element 11, the gate electrode 39b of the current sensing section 12 is connected to the source pad 21a of the main semiconductor element 11 via the gate pad 21b and the gate runner. can be electrically connected. As a result, as in the first embodiment, the ESD tolerance of current sensing portion 12 can be increased during the manufacturing process.

That is, the method of manufacturing the semiconductor device 120 according to the second embodiment is the same as the method of manufacturing the semiconductor device 20 according to the first embodiment, except for the arrangement of the short-circuit electrode 112 . Short-circuit electrode 112 is arranged between source pad 21a and gate pad 21b. The short-circuit electrode 112 may have the same layer structure, the same length w11 and the same width w12 dimensions as the short-circuit electrode 111 of the first embodiment, and may be formed by the same method as the short-circuit electrode 111, for example. In FIG. 14, a portion (short-circuit region) between the source pad 21a and the gate pad 21b where the short-circuit electrode 112 is arranged is denoted by 5. As shown in FIG.

As described above, according to the second embodiment, by electrically connecting the gate electrode of the current sensing portion to the source pad of the main semiconductor element, the gate capacitance of the current sensing portion during the manufacturing process can be simulated. , the same effect as in the first embodiment can be obtained.

(Embodiment 3)
Next, a method for manufacturing the semiconductor device according to the third embodiment will be described. FIG. 15 is a plan view showing a state in the middle of manufacturing the semiconductor device according to the third embodiment. The method for manufacturing the semiconductor device 120′ according to the third embodiment is similar to the method for manufacturing the semiconductor device 20 according to the first embodiment (see FIG. 11) and the method for manufacturing the semiconductor device 120 according to the second embodiment (see FIG. 14). is applied. That is, the OC pad 22 and the gate pad 21b are short-circuited to the source pad 21a.

Specifically, the manufacturing method of the semiconductor device 120' according to the third embodiment differs from the manufacturing method of the semiconductor device 20 according to the first embodiment in that the short-circuit electrode 111 (hatched portion) formed in the short-circuit region 4 The source pad 21a and the OC pad 22 are short-circuited, and the source pad 21a and the gate pad 21b are short-circuited by the short-circuit electrode 112 (hatched portion) formed in the short-circuit region 5, and the subsequent steps up to the performance test. It is a point to perform

When the short-circuit electrodes 111 and 112 are cut before the performance test, the source pad 21a and the OC pad 22 are short-circuited after cutting the high-potential-side short-circuit electrode 112 that short-circuits the source pad 21a and the gate pad 21b. It is preferable to disconnect the short-circuit electrode 111 on the low potential (ground potential) side. The reason for this is that the short-circuit electrode 112 can be cut while the source pad 21a is grounded by the short-circuit electrode 111, thereby preventing a high potential from being applied to the source pad 21a.

As described above, according to the third embodiment, even when the gate pad of the main semiconductor element and the OC pad of the current sensing section are short-circuited to the source pad of the main semiconductor element by different short-circuit electrodes, Effects similar to those of modes 1 and 2 can be obtained.

(Embodiment 4)
Next, a method for manufacturing the semiconductor device according to the fourth embodiment will be described. FIG. 16 is a plan view showing a state in the middle of manufacturing the semiconductor device according to the fourth embodiment. FIG. 16 shows the planar shape of the short-circuit electrode. The manufacturing method of the semiconductor device 20' according to the fourth embodiment differs from the manufacturing method of the semiconductor device 20 according to the first embodiment (see FIG. 11) in that the width w2' of the portion 111c of the short-circuit electrode 111' is narrowed. It is a point.

Specifically, in the fifth embodiment, each connecting portion 111a, 111b between the source pad 21a and the OC pad 22 of the short-circuit electrode 111' is formed of one of the metal films 102 to 106 (see FIGS. 12 and 13). Width such that the short-circuit electrode 111′ is not separated from the source pad 21a and the OC pad 22 during etching for leaving the metal film as the short-circuit electrode 111′ (hereinafter referred to as etching for forming the short-circuit electrode 111′). w2.

A portion 111c of the short-circuit electrode 111' where the width w2' is narrowed (hereinafter referred to as a cut portion) is a cut portion when the short-circuit electrode 111' is cut before the performance test. The cut portion 111c of the short-circuit electrode 111' has a width w2' that is not cut during etching for forming the short-circuit electrode 111'. The short-circuit electrode 111 ′ may have, for example, a substantially I-shaped planar shape in which the cut portion 111 c is narrower than the connection portion 111 a with the source pad 21 a and the connection portion 111 b with the OC pad 22 .

As described above, according to the fourth embodiment, effects similar to those of the first to third embodiments can be obtained. Further, according to Embodiment 4, by narrowing the width of the cut portion of the short-circuit electrode, the short-circuit electrode can be cut more efficiently before the performance test.

As described above, the present invention is not limited to the above-described embodiment, and can be variously modified without departing from the scope of the present invention. For example, in the above-described embodiments, by forming the short-circuit electrode with the thinnest metal film among the metal films forming the barrier metal, the short-circuit electrode can be efficiently cut. The present invention can also be applied when a wide bandgap semiconductor is used as the semiconductor material instead of using silicon carbide as the semiconductor material. Moreover, the present invention is similarly established even if the conductivity type (n-type, p-type) is reversed.

INDUSTRIAL APPLICABILITY As described above, the method of manufacturing a semiconductor device according to the present invention is useful for power semiconductor devices used in power converters and power supply devices for various industrial machines.

REFERENCE SIGNS LIST 1 active region 1a valid region of active region 1b invalid region of active region 2 edge termination region 3 scribe line 4, 5 short-circuit region 10 semiconductor wafer 10' chip region of semiconductor wafer 11 main semiconductor element 12 current sensing section 13 temperature sensing section 14 Resistor 20, 20' 120, 120' Semiconductor device 21a Source pad (electrode pad)
21b gate pad (electrode pad)
22 OC pad (electrode pad)
23a anode pad (electrode pad)
23b cathode pad (electrode pad)
24, 106 Al film 31 n ⁺ type starting substrate 32 n ⁻ type drift region 32a n ⁻ type region 33a, 33b n type current diffusion regions 34a to 34c p type base region 35a, 35b n ⁺ type source region 36a to 36c p ^{+ +} type contact regions 37a, 37b trenches 38a, 38b gate insulating films 39a, 39b gate electrodes 40, 83 interlayer insulating films 40a to 40d, 83a, 83b contact holes 41a, 41b, 101 NiSi films 42a, 42b, 42d, 102 first TiN Films 43a, 43b, 43d, 103 First Ti films 44a, 44b, 44d, 104 Second TiN films 45a, 45b, 45d, 105 Second Ti films 46a, 46b Barrier metals 47a to 47d Plating films 48a to 48d Terminal pins 49a to 49c 1 protective film 50a to 50c second protective film 51 drain electrode 61a, 61b, 62a to 62c, 91 p ⁺ type region 70 semiconductor chip 71 n ⁻ type silicon carbide layer 71a increased thickness of n ⁻ type silicon carbide layer 72 p-type silicon carbide layer 80 field insulating film 81 p-type polysilicon layer 82 n-type polysilicon layer 92, 94 n-type regions 111, 111′, 112 short-circuit electrode GND grounding point X parallel to the front surface of the semiconductor chip and the direction in which the electrode pads of the invalid area are arranged (first direction)
Y direction parallel to the front surface of the semiconductor chip and orthogonal to the first direction (second direction)
Z Depth direction d1 Depth between p ⁺ -type regions d2 Distance between p ⁺ -type regions d3 Depth of n-type regions t1 Thickness of the n ⁻ -type silicon carbide layer initially deposited on the n ⁺ -type starting substrate t2 Thickness of increased thickness of n ⁻ -type silicon carbide layer t3 Thickness of p-type silicon carbide layer w1, w11 Length of short-circuit electrode w2, w2′, w12 Width of short-circuit electrode

Claims (10)

A first insulated gate field effect transistor provided with a first front surface electrode and a first rear surface electrode on both sides of a semiconductor substrate made of a semiconductor having a wider bandgap than silicon, and a second transistor on both sides of the semiconductor substrate. a second insulated gate field effect transistor having a front surface electrode and a second back surface electrode, comprising:
a first step of forming a first insulated gate structure of the first insulated gate field effect transistor on the front surface side of the semiconductor substrate;
A second insulated gate structure of the second insulated gate field effect transistor having a smaller surface area in the semiconductor substrate than the first insulated gate field effect transistor is formed on the front surface side of the semiconductor substrate. a second step of forming the same structure as the insulated gate structure at a position separated from the first insulated gate structure;
a third step of forming the first front electrode and the second front electrode;
a fourth step of forming a gate pad to which the gate electrode forming the first insulating gate structure and the gate electrode forming the second insulating gate structure are electrically connected;
After the third step and the fourth step, a fifth step of performing a test for evaluating predetermined characteristics;
including
After the second step and before the fifth step, a shorting step of forming a shorting electrode for shorting the second insulated gate field effect transistor to the first front surface electrode;
After the short-circuiting step, all the predetermined steps up to and including the fifth step are performed with the short-circuit electrode short-circuiting the first front surface electrode and the second insulated gate field effect transistor. do,
After the predetermined step and before the fifth step, the short-circuit electrode is cut to electrically disconnect the first front surface electrode and the second insulated gate field effect transistor. A manufacturing method of a semiconductor device. 2. The method of manufacturing a semiconductor device according to claim 1, wherein said short-circuiting step is performed in at least a part of said third step. In the third step,
forming a metal layer on the front surface of the semiconductor substrate;
selectively removing the metal layer to leave portions of the metal layer as the first front electrode and the second front electrode, respectively;
3. The method of manufacturing a semiconductor device according to claim 2, wherein in said shorting step, a part of said metal layer is left as said shorting electrode in said third step. In the third step, the metal layer having a laminated structure in which a plurality of metal films are laminated is formed;
4. The method of manufacturing a semiconductor device according to claim 3, wherein in said short-circuiting step, the thinnest metal film among said plurality of metal films is left as said short-circuit electrode. 5. The semiconductor device according to claim 1, wherein in said shorting step, said shorting electrode short-circuits said second front surface electrode to said first front surface electrode. manufacturing method. 6. The method of manufacturing a semiconductor device according to claim 5, wherein in said shorting step, said shorting electrode is formed between said first front surface electrode and said second front surface electrode. 5. The method according to claim 1, wherein in said shorting step, said shorting electrode short-circuits a gate electrode of said second insulated gate field effect transistor to said first front surface electrode. A method of manufacturing the described semiconductor device. In the short-circuiting step, the short-circuit electrode is formed between the first front surface electrode and the gate pad so that the second insulated gate field effect transistor is connected through the short-circuit electrode and the gate pad. 8. The method of manufacturing a semiconductor device according to claim 7, wherein said gate electrode and said first front surface electrode are short-circuited. In the short-circuiting step, a part of the short-circuit electrode having a narrow width is formed,
After the predetermined step and before the fifth step, the narrow portion of the short-circuit electrode is cut to electrically connect the first front surface electrode and the second insulated gate field effect transistor. 9. The method of manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is separated. 10. The method according to any one of claims 1 to 9, wherein after the fifth step, a new short-circuit electrode is formed to short-circuit the second insulated gate field effect transistor to the first front surface electrode. 2. The method of manufacturing the semiconductor device according to 1.

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